/Linux-v6.6/drivers/accel/habanalabs/include/goya/asic_reg/ |
D | dma_nrtr_masks.h | 23 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0 24 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F 26 #define DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00 28 #define DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000 30 #define DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000 33 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0 34 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F 36 #define DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00 38 #define DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000 40 #define DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000 [all …]
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D | pci_nrtr_masks.h | 23 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0 24 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F 26 #define PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00 28 #define PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000 30 #define PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000 33 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0 34 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F 36 #define PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00 38 #define PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000 40 #define PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000 [all …]
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D | tpc0_nrtr_masks.h | 23 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0 24 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F 26 #define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00 28 #define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000 30 #define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000 33 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0 34 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F 36 #define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00 38 #define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000 40 #define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000 [all …]
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/Linux-v6.6/arch/arm/mm/ |
D | proc-arm740.S | 37 mrc p15, 0, r0, c1, c0, 0 38 bic r0, r0, #0x3f000000 @ bank/f/lock/s 39 bic r0, r0, #0x0000000c @ w-buffer/cache 40 mcr p15, 0, r0, c1, c0, 0 @ disable caches 50 mov ip, #0 51 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache 52 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register 53 bic ip, ip, #0x0000000c @ ............wc.. 54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 61 mov r0, #0 [all …]
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/Linux-v6.6/arch/arm/boot/dts/broadcom/ |
D | bcm2837.dtsi | 8 ranges = <0x7e000000 0x3f000000 0x1000000>, 9 <0x40000000 0x40000000 0x00001000>; 10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>; 14 reg = <0x40000000 0x100>; 30 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI 39 #size-cells = <0>; 49 cpu0: cpu@0 { 52 reg = <0>; 54 cpu-release-addr = <0x0 0x000000d8>; 55 d-cache-size = <0x8000>; [all …]
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D | bcm2836.dtsi | 9 ranges = <0x7e000000 0x3f000000 0x1000000>, 10 <0x40000000 0x40000000 0x00001000>; 11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>; 15 reg = <0x40000000 0x100>; 31 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI 40 #size-cells = <0>; 51 v7_cpu0: cpu@0 { 54 reg = <0xf00>; 56 d-cache-size = <0x8000>; 59 i-cache-size = <0x8000>; [all …]
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/Linux-v6.6/drivers/net/wireless/ath/ath9k/ |
D | mac.h | 30 AR_RTSCTSQual##_index : 0)) 34 AR_2040_##_index : 0) \ 36 AR_GI##_index : 0) \ 38 AR_STBC##_index : 0)) 71 #define ATH9K_TXERR_XRETRY 0x01 72 #define ATH9K_TXERR_FILT 0x02 73 #define ATH9K_TXERR_FIFO 0x04 74 #define ATH9K_TXERR_XTXOP 0x08 75 #define ATH9K_TXERR_TIMER_EXPIRED 0x10 76 #define ATH9K_TX_ACKED 0x20 [all …]
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D | reg_aic.h | 20 #define AR_SM_BASE 0xa200 21 #define AR_SM1_BASE 0xb200 22 #define AR_AGC_BASE 0x9e00 24 #define AR_PHY_AIC_CTRL_0_B0 (AR_SM_BASE + 0x4b0) 25 #define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4) 26 #define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8) 27 #define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc) 28 #define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0) 30 #define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + 0x4c4) 31 #define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + 0x4c8) [all …]
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/Linux-v6.6/drivers/cpufreq/ |
D | powernow-k8.h | 43 #define CPUID_XFAM 0x0ff00000 /* extended family */ 44 #define CPUID_XFAM_K8 0 45 #define CPUID_XMOD 0x000f0000 /* extended model */ 46 #define CPUID_XMOD_REV_MASK 0x000c0000 47 #define CPUID_XFAM_10H 0x00100000 /* family 0x10 */ 48 #define CPUID_USE_XFAM_XMOD 0x00000f00 49 #define CPUID_GET_MAX_CAPABILITIES 0x80000000 50 #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007 54 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */ 55 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */ [all …]
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/Linux-v6.6/include/linux/bcma/ |
D | bcma_driver_mips.h | 5 #define BCMA_MIPS_IPSFLAG 0x0F08 7 #define BCMA_MIPS_IPSFLAG_IRQ1 0x0000003F 8 #define BCMA_MIPS_IPSFLAG_IRQ1_SHIFT 0 10 #define BCMA_MIPS_IPSFLAG_IRQ2 0x00003F00 13 #define BCMA_MIPS_IPSFLAG_IRQ3 0x003F0000 16 #define BCMA_MIPS_IPSFLAG_IRQ4 0x3F000000 20 #define BCMA_MIPS_MIPS74K_CORECTL 0x0000 21 #define BCMA_MIPS_MIPS74K_EXCEPTBASE 0x0004 22 #define BCMA_MIPS_MIPS74K_BIST 0x000C 23 #define BCMA_MIPS_MIPS74K_INTMASK_INT0 0x0014 [all …]
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/Linux-v6.6/drivers/staging/rtl8712/ |
D | rtl8712_security_bitdef.h | 14 #define _SECCAM_ADR_MSK 0x000000FF 15 #define _SECCAM_ADR_SHT 0 20 #define _SEC_CONFIG_MSK 0x3F000000 22 #define _SEC_KEYCONTENT_MSK 0x00FFFFFF 23 #define _SEC_KEYCONTENT_SHT 0 31 #define _TXUSEDK BIT(0)
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/Linux-v6.6/arch/arm/nwfpe/ |
D | fpopcode.c | 19 { .high = 0x0000, .low = 0x0000000000000000ULL},/* extended 0.0 */ 20 { .high = 0x3fff, .low = 0x8000000000000000ULL},/* extended 1.0 */ 21 { .high = 0x4000, .low = 0x8000000000000000ULL},/* extended 2.0 */ 22 { .high = 0x4000, .low = 0xc000000000000000ULL},/* extended 3.0 */ 23 { .high = 0x4001, .low = 0x8000000000000000ULL},/* extended 4.0 */ 24 { .high = 0x4001, .low = 0xa000000000000000ULL},/* extended 5.0 */ 25 { .high = 0x3ffe, .low = 0x8000000000000000ULL},/* extended 0.5 */ 26 { .high = 0x4002, .low = 0xa000000000000000ULL},/* extended 10.0 */ 31 0x0000000000000000ULL, /* double 0.0 */ 32 0x3ff0000000000000ULL, /* double 1.0 */ [all …]
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/Linux-v6.6/arch/mips/math-emu/ |
D | sp_sqrt.c | 34 /* sqrt(0) = 0 */ in ieee754sp_sqrt() 60 if (m == 0) { /* subnormal x */ in ieee754sp_sqrt() 61 for (i = 0; (ix & 0x00800000) == 0; i++) in ieee754sp_sqrt() 66 ix = (ix & 0x007fffff) | 0x00800000; in ieee754sp_sqrt() 73 s = 0; in ieee754sp_sqrt() 74 q = 0; /* q = sqrt(x) */ in ieee754sp_sqrt() 75 r = 0x01000000; /* r = moving bit from right to left */ in ieee754sp_sqrt() 77 while (r != 0) { in ieee754sp_sqrt() 88 if (ix != 0) { in ieee754sp_sqrt() 99 ix = (q >> 1) + 0x3f000000; in ieee754sp_sqrt()
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/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/bif/ |
D | bif_5_1_sh_mask.h | 27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff 28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0 29 #define MM_INDEX__MM_APER_MASK 0x80000000 30 #define MM_INDEX__MM_APER__SHIFT 0x1f 31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff 32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 33 #define MM_DATA__MM_DATA_MASK 0xffffffff 34 #define MM_DATA__MM_DATA__SHIFT 0x0 35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2 36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 [all …]
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/Linux-v6.6/drivers/accel/habanalabs/include/gaudi2/asic_reg/ |
D | psoc_global_conf_masks.h | 24 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0 25 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF 28 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0 29 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1 32 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0 33 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1 35 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_MNL_RST_IND_MASK 0x10 37 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_WD_RST_IND_MASK 0x20 39 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SW_RST_IND_MASK 0x40 41 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_SOFT_RST_IND_MASK 0x80 [all …]
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/Linux-v6.6/arch/arm/boot/dts/marvell/ |
D | armada-398-db.dts | 23 reg = <0x00000000 0x80000000>; /* 2 GB */ 27 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 28 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; 32 pinctrl-0 = <&i2c0_pins>; 39 pinctrl-0 = <&uart0_pins>; 45 pinctrl-0 = <&uart1_pins>; 62 pcie@1,0 { 66 pcie@2,0 { 70 pcie@3,0 { 79 pinctrl-0 = <&spi1_pins>; [all …]
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D | armada-390-db.dts | 24 reg = <0x00000000 0x80000000>; /* 2 GB */ 28 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 29 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; 38 reg = <0x50>; 62 pcie@1,0 { 67 pcie@2,0 { 72 pcie@3,0 { 81 pinctrl-0 = <&spi1_pins>; 84 flash@0 { 89 reg = <0>; /* Chip select 0 */ [all …]
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D | armada-375-db.dts | 24 memory@0 { 26 reg = <0x00000000 0x40000000>; /* 1 GB */ 30 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 31 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 32 MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000 33 MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>; 46 /* Port 0, Lane 0 */ 51 /* Port 1, Lane 0 */ 57 pinctrl-0 = <&spi0_pins>; 67 flash@0 { [all …]
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/Linux-v6.6/arch/m68k/fpsp040/ |
D | satanh.S | 38 | atan(X) := sgn / (+0). 41 | 5. (|X| > 1) Generate an invalid operation by 0 * infinity. 71 andil #0x7FFFFFFF,%d0 72 cmpil #0x3FFF8000,%d0 82 fadds #0x3F800000,%fp1 | ...1-Y 85 andil #0x80000000,%d0 86 oril #0x3F000000,%d0 | ...SIGN(X)*HALF 99 fcmps #0x3F800000,%fp0
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/Linux-v6.6/drivers/net/ethernet/renesas/ |
D | ravb.h | 38 #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */ 39 #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */ 41 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */ 42 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */ 43 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002 44 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006 45 #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */ 49 CCC = 0x0000, 50 DBAT = 0x0004, 51 DLR = 0x0008, [all …]
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/Linux-v6.6/drivers/staging/rtl8192u/ |
D | r819xU_phyreg.h | 5 #define RF_DATA 0x1d4 /* FW will write RF data in the register.*/ 8 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ 9 #define rFPGA0_TxGainStage 0x80c 10 #define rFPGA0_XA_HSSIParameter1 0x820 11 #define rFPGA0_XA_HSSIParameter2 0x824 12 #define rFPGA0_XB_HSSIParameter1 0x828 13 #define rFPGA0_XB_HSSIParameter2 0x82c 14 #define rFPGA0_XC_HSSIParameter1 0x830 15 #define rFPGA0_XC_HSSIParameter2 0x834 16 #define rFPGA0_XD_HSSIParameter1 0x838 [all …]
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/Linux-v6.6/drivers/staging/rtl8192e/rtl8192e/ |
D | r8192E_phyreg.h | 10 #define RF_DATA 0x1d4 12 #define rPMAC_Reset 0x100 13 #define rPMAC_TxStart 0x104 14 #define rPMAC_TxLegacySIG 0x108 15 #define rPMAC_TxHTSIG1 0x10c 16 #define rPMAC_TxHTSIG2 0x110 17 #define rPMAC_PHYDebug 0x114 18 #define rPMAC_TxPacketNum 0x118 19 #define rPMAC_TxIdle 0x11c 20 #define rPMAC_TxMACHeader0 0x120 [all …]
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/Linux-v6.6/drivers/media/rc/img-ir/ |
D | img-ir.h | 20 #define IMG_IR_CONTROL 0x00 21 #define IMG_IR_STATUS 0x04 22 #define IMG_IR_DATA_LW 0x08 23 #define IMG_IR_DATA_UP 0x0c 24 #define IMG_IR_LEAD_SYMB_TIMING 0x10 25 #define IMG_IR_S00_SYMB_TIMING 0x14 26 #define IMG_IR_S01_SYMB_TIMING 0x18 27 #define IMG_IR_S10_SYMB_TIMING 0x1c 28 #define IMG_IR_S11_SYMB_TIMING 0x20 29 #define IMG_IR_FREE_SYMB_TIMING 0x24 [all …]
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/Linux-v6.6/include/net/ |
D | ieee80211_radiotap.h | 28 * @it_version: radiotap version, always 0 53 /* version is always 0 */ 54 #define PKTHDR_RADIOTAP_VERSION 0 58 IEEE80211_RADIOTAP_TSFT = 0, 97 IEEE80211_RADIOTAP_F_CFP = 0x01, 98 IEEE80211_RADIOTAP_F_SHORTPRE = 0x02, 99 IEEE80211_RADIOTAP_F_WEP = 0x04, 100 IEEE80211_RADIOTAP_F_FRAG = 0x08, 101 IEEE80211_RADIOTAP_F_FCS = 0x10, 102 IEEE80211_RADIOTAP_F_DATAPAD = 0x20, [all …]
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/Linux-v6.6/drivers/gpu/drm/nouveau/nvkm/subdev/top/ |
D | ga100.c | 31 int i, n, size = nvkm_rd32(device, 0x0224fc) >> 20; in ga100_top_parse() 33 for (i = 0, n = 0; i < size; i++) { in ga100_top_parse() 37 type = ~0; in ga100_top_parse() 38 inst = 0; in ga100_top_parse() 41 data = nvkm_rd32(device, 0x022800 + (i * 0x04)); in ga100_top_parse() 43 if (!data && n == 0) in ga100_top_parse() 47 case 0: in ga100_top_parse() 48 type = (data & 0x3f000000) >> 24; in ga100_top_parse() 49 inst = (data & 0x000f0000) >> 16; in ga100_top_parse() 50 info->fault = (data & 0x0000007f); in ga100_top_parse() [all …]
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