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/Linux-v5.15/drivers/media/usb/gspca/
Dsunplus.c29 #define BRIDGE_SPCA504 0
113 /* {0xa0, 0x0000, 0x0503}, * capture mode */
114 {0x00, 0x0000, 0x2000},
115 {0x00, 0x0013, 0x2301},
116 {0x00, 0x0003, 0x2000},
117 {0x00, 0x0001, 0x21ac},
118 {0x00, 0x0001, 0x21a6},
119 {0x00, 0x0000, 0x21a7}, /* brightness */
120 {0x00, 0x0020, 0x21a8}, /* contrast */
121 {0x00, 0x0001, 0x21ac}, /* sat/hue */
[all …]
Dspca500.c26 #define AgfaCl20 0
55 .priv = 0},
68 .priv = 0},
87 {0x00, 0x0003, 0x816b}, /* SSI not active sync with vsync,
88 * hue (H byte) = 0,
92 {0x00, 0x0000, 0x8167}, /* brightness = 0 */
93 {0x00, 0x0020, 0x8168}, /* contrast = 0 */
94 {0x00, 0x0003, 0x816b}, /* SSI not active sync with vsync,
95 * hue (H byte) = 0, saturation/hue enable,
97 * was 0x0003, now 0x0000.
[all …]
/Linux-v5.15/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/Linux-v5.15/drivers/media/dvb-frontends/
Dstv0900_init.h24 { 0, 11101 }, /*C/N=-0dB*/
83 { -5, 0xCAA1 }, /*-5dBm*/
84 { -10, 0xC229 }, /*-10dBm*/
85 { -15, 0xBB08 }, /*-15dBm*/
86 { -20, 0xB4BC }, /*-20dBm*/
87 { -25, 0xAD5A }, /*-25dBm*/
88 { -30, 0xA298 }, /*-30dBm*/
89 { -35, 0x98A8 }, /*-35dBm*/
90 { -40, 0x8389 }, /*-40dBm*/
91 { -45, 0x59BE }, /*-45dBm*/
[all …]
Dtda18271c2dd_maps.h3 HF_None = 0, HF_B, HF_DK, HF_G, HF_I, HF_L, HF_L1, HF_MN, HF_FM_Radio,
10 { 0, 0, 0x00, 0x00 }, /* HF_None */
11 { 6000000, 7000000, 0x1D, 0x2C }, /* HF_B, */
12 { 6900000, 8000000, 0x1E, 0x2C }, /* HF_DK, */
13 { 7100000, 8000000, 0x1E, 0x2C }, /* HF_G, */
14 { 7250000, 8000000, 0x1E, 0x2C }, /* HF_I, */
15 { 6900000, 8000000, 0x1E, 0x2C }, /* HF_L, */
16 { 1250000, 8000000, 0x1E, 0x2C }, /* HF_L1, */
17 { 5400000, 6000000, 0x1C, 0x2C }, /* HF_MN, */
18 { 1250000, 500000, 0x18, 0x2C }, /* HF_FM_Radio, */
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/athub/
Dathub_1_0_sh_mask.h27 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
28 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
29 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
30 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
31 #define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14
32 #define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15
33 #define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16
34 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
35 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
36 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
[all …]
Dathub_2_0_0_sh_mask.h27 …S_CNTL__DISABLE_ATC__SHIFT 0x0
28 …S_CNTL__DISABLE_PRI__SHIFT 0x1
29 …S_CNTL__DISABLE_PASID__SHIFT 0x2
30 …S_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
31 …_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14
32 …_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15
33 …_CNTL__TRANS_EXE_RETURN__SHIFT 0x16
34 …DISABLE_ATC_MASK 0x00000001L
35 …DISABLE_PRI_MASK 0x00000002L
36 …DISABLE_PASID_MASK 0x00000004L
[all …]
Dathub_2_1_0_sh_mask.h27 …ATS_MODE_CNTL__HOST_TRANS_ENABLE__SHIFT 0x0
28 …ATS_MODE_CNTL__CONSOLE_IOV_ENABLE__SHIFT 0x1
29 …_CNTL__HOST_TRANS_ENABLE_MASK 0x00000001L
30 …_CNTL__CONSOLE_IOV_ENABLE_MASK 0x00000002L
32 …SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
33 …HARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
34 …IRT_RESET_REQ__VF_MASK 0x7FFFFFFFL
35 …IRT_RESET_REQ__PF_MASK 0x80000000L
37 …SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
38 …HARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
[all …]
/Linux-v5.15/drivers/gpu/drm/panel/
Dpanel-feixin-k101-im2ba02.c43 /* Switch to page 0 */
44 { .data = { 0xE0, 0x00 } },
47 { .data = { 0xE1, 0x93} },
48 { .data = { 0xE2, 0x65 } },
49 { .data = { 0xE3, 0xF8 } },
51 /* Lane number, 0x02 - 3 lanes, 0x03 - 4 lanes */
52 { .data = { 0x80, 0x03 } },
55 { .data = { 0x70, 0x02 } },
56 { .data = { 0x71, 0x23 } },
57 { .data = { 0x72, 0x06 } },
[all …]
/Linux-v5.15/drivers/media/tuners/
Dqt1010.c16 .flags = 0, .buf = &reg, .len = 1 }, in qt1010_readreg()
26 return 0; in qt1010_readreg()
34 .flags = 0, .buf = buf, .len = 2 }; in qt1010_writereg()
41 return 0; in qt1010_writereg()
52 { QT1010_WR, 0x01, 0x80 }, in qt1010_set_params()
53 { QT1010_WR, 0x02, 0x3f }, in qt1010_set_params()
54 { QT1010_WR, 0x05, 0xff }, /* 02 c write */ in qt1010_set_params()
55 { QT1010_WR, 0x06, 0x44 }, in qt1010_set_params()
56 { QT1010_WR, 0x07, 0xff }, /* 04 c write */ in qt1010_set_params()
57 { QT1010_WR, 0x08, 0x08 }, in qt1010_set_params()
[all …]
/Linux-v5.15/crypto/
Dtestmgr.h33 * @ksize: Length of @key in bytes (0 if no key)
101 * @crypt_error: When @novrfy=0, the expected error from encrypt(). When
192 "\x9C\xE6\x16\xCE\x62\x4A\x11\xE0\x08\x6D\x34\x1E\xBC\xAC\xA0\xA1"
210 "\x9f\x6e\xbd\x4c\x55\x84\x0c\x9b\xcf\x1a\x4b\x51\x1e\x9e\x0c\x06",
231 "\xF8\x3F\x31\x25\x1E\x06\x68\xB4\x27\x84\x81\x38\x01\x57\x96\x41"
265 "\xC6\x67\xFF\x1D\x1E\x3C\x1D\xC1\xB5\x5F\x6C\xC0\xB2\x07\x3A\x6D"
288 "\x9A\xB8\x81\xE2\xD0\x07\x35\xAA\x05\x41\xC9\x1E\xAF\xE4\x04\x3B"
289 "\x19\xB8\x73\xA2\xAC\x4B\x1E\x66\x48\xD8\x72\x1F\xAC\xF6\xCB\xBC"
295 "\xD6\xBF\x7A\x0B\x64\x21\x6D\x88\x7E\x5B\x45\x12\x1E\x63\x8D\x49"
296 "\xA7\x1D\xD9\x1E\x06\xCD\xE8\xBA\x2C\x8C\x69\x32\xEA\xBE\x60\x71"
[all …]
/Linux-v5.15/drivers/infiniband/hw/qib/
Dqib_6120_regs.h35 #define QIB_6120_Revision_OFFS 0x0
36 #define QIB_6120_Revision_R_Simulator_LSB 0x3F
37 #define QIB_6120_Revision_R_Simulator_RMASK 0x1
38 #define QIB_6120_Revision_Reserved_LSB 0x28
39 #define QIB_6120_Revision_Reserved_RMASK 0x7FFFFF
40 #define QIB_6120_Revision_BoardID_LSB 0x20
41 #define QIB_6120_Revision_BoardID_RMASK 0xFF
42 #define QIB_6120_Revision_R_SW_LSB 0x18
43 #define QIB_6120_Revision_R_SW_RMASK 0xFF
44 #define QIB_6120_Revision_R_Arch_LSB 0x10
[all …]
/Linux-v5.15/arch/powerpc/boot/dts/fsl/
Dt2081qds.dts104 #size-cells = <0>;
105 reg = <0x54 1>;
106 mux-mask = <0xe0>;
108 t2081mdio0: mdio@0 {
110 #size-cells = <0>;
111 reg = <0>;
114 reg = <0x1>;
120 #size-cells = <0>;
121 reg = <0x20>;
124 reg = <0x2>;
[all …]
/Linux-v5.15/sound/soc/amd/include/
Dacp_2_2_sh_mask.h27 #define ACP_DMA_CNTL_0__DMAChRst_MASK 0x1
28 #define ACP_DMA_CNTL_0__DMAChRst__SHIFT 0x0
29 #define ACP_DMA_CNTL_0__DMAChRun_MASK 0x2
30 #define ACP_DMA_CNTL_0__DMAChRun__SHIFT 0x1
31 #define ACP_DMA_CNTL_0__DMAChIOCEn_MASK 0x4
32 #define ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT 0x2
33 #define ACP_DMA_CNTL_0__Circular_DMA_En_MASK 0x8
34 #define ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT 0x3
35 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK 0x10
36 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT 0x4
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
Doss_3_0_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_1_sh_mask.h26 …C_TAG_CNT__DED_COUNT__SHIFT 0x0
27 …C_TAG_CNT__SEC_COUNT__SHIFT 0x2
28 …T__DED_COUNT_MASK 0x00000003L
29 …T__SEC_COUNT_MASK 0x0000000CL
31 …C_ROQ_CNT__DED_COUNT_ME1__SHIFT 0x0
32 …C_ROQ_CNT__SEC_COUNT_ME1__SHIFT 0x2
33 …C_ROQ_CNT__DED_COUNT_ME2__SHIFT 0x4
34 …C_ROQ_CNT__SEC_COUNT_ME2__SHIFT 0x6
35 …T__DED_COUNT_ME1_MASK 0x00000003L
36 …T__SEC_COUNT_ME1_MASK 0x0000000CL
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_0_sh_mask.h27 #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0
28 #define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL
30 #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
31 #define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
33 #define SDMA0_VM_CNTL__CMD__SHIFT 0x0
34 #define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL
36 #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2
37 #define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL
39 #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0
40 #define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/sdma1/
Dsdma1_4_0_sh_mask.h27 #define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0
28 #define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL
30 #define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0
31 #define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
33 #define SDMA1_VM_CNTL__CMD__SHIFT 0x0
34 #define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL
36 #define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2
37 #define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL
39 #define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0
40 #define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL
[all …]

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