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/Linux-v5.15/drivers/staging/rts5208/
Dms.h19 #define MS_EXTRA_SIZE 0x9
21 #define WRT_PRTCT 0x01
24 #define MS_NO_ERROR 0x00
25 #define MS_CRC16_ERROR 0x80
26 #define MS_TO_ERROR 0x40
27 #define MS_NO_CARD 0x20
28 #define MS_NO_MEMORY 0x10
29 #define MS_CMD_NK 0x08
30 #define MS_FLASH_READ_ERROR 0x04
31 #define MS_FLASH_WRITE_ERROR 0x02
[all …]
/Linux-v5.15/arch/mips/mm/
Dcex-sb1.S31 * the L1 and L2) since it is fetched as 0xa0000100.
35 * (0x170-0x17f) are used to preserve k0, k1, and ra.
48 sd k0,0x170($0)
49 sd k1,0x178($0)
69 mtc0 $0,C0_CERR_D
101 andi k0,0x1fe0
108 cache Index_Invalidate_I,(0<<13)(k0)
117 ld k0,0x170($0)
118 ld k1,0x178($0)
140 bnezl $0, 1f
/Linux-v5.15/Documentation/fault-injection/
Dnvme-fault-injection.rst33 name fault_inject, interval 1, probability 100, space 0, times 1
34 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.15.0-rc8+ #2
39 dump_stack+0x5c/0x7d
40 should_fail+0x148/0x170
41 nvme_should_fail+0x2f/0x50 [nvme_core]
42 nvme_process_cq+0xe7/0x1d0 [nvme]
43 nvme_irq+0x1e/0x40 [nvme]
44 __handle_irq_event_percpu+0x3a/0x190
45 handle_irq_event_percpu+0x30/0x70
46 handle_irq_event+0x36/0x60
[all …]
/Linux-v5.15/drivers/phy/qualcomm/
Dphy-qcom-qmp.h11 #define QSERDES_PLL_BG_TIMER 0x00c
12 #define QSERDES_PLL_SSC_PER1 0x01c
13 #define QSERDES_PLL_SSC_PER2 0x020
14 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
15 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
16 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
17 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
18 #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c
19 #define QSERDES_PLL_CLK_ENABLE1 0x040
20 #define QSERDES_PLL_SYS_CLK_CTRL 0x044
[all …]
/Linux-v5.15/arch/sparc/kernel/
Dkprobes.c31 * - Set regs->tpc to point to kprobe->ainsn.insn[0]
52 if ((unsigned long) p->addr & 0x3UL) in arch_prepare_kprobe()
55 p->ainsn.insn[0] = *p->addr; in arch_prepare_kprobe()
56 flushi(&p->ainsn.insn[0]); in arch_prepare_kprobe()
62 return 0; in arch_prepare_kprobe()
111 regs->tpc = (unsigned long) &p->ainsn.insn[0]; in prepare_singlestep()
120 int ret = 0; in kprobe_handler()
207 if (regs->tnpc == regs->tpc + 0x4UL) in relbranch_fixup()
208 return real_pc + 0x8UL; in relbranch_fixup()
213 if ((insn & 0xc0000000) == 0x40000000 || in relbranch_fixup()
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/sound/
Dsprd-mcdt.txt17 reg = <0 0x41490000 0 0x170>;
/Linux-v5.15/tools/testing/selftests/kvm/lib/x86_64/
Dsvm.c73 memset(vmcb, 0, sizeof(*vmcb)); in generic_svm_setup()
74 asm volatile ("vmsave %0\n\t" : : "a" (vmcb_gpa) : "memory"); in generic_svm_setup()
75 vmcb_set_seg(&save->es, get_es(), 0, -1U, data_seg_attr); in generic_svm_setup()
76 vmcb_set_seg(&save->cs, get_cs(), 0, -1U, code_seg_attr); in generic_svm_setup()
77 vmcb_set_seg(&save->ss, get_ss(), 0, -1U, data_seg_attr); in generic_svm_setup()
78 vmcb_set_seg(&save->ds, get_ds(), 0, -1U, data_seg_attr); in generic_svm_setup()
79 vmcb_set_seg(&save->gdtr, 0, get_gdt().address, get_gdt().size, 0); in generic_svm_setup()
80 vmcb_set_seg(&save->idtr, 0, get_idt().address, get_idt().size, 0); in generic_svm_setup()
83 save->cpl = 0; in generic_svm_setup()
85 asm volatile ("mov %%cr4, %0" : "=r"(save->cr4) : : "memory"); in generic_svm_setup()
[all …]
/Linux-v5.15/arch/mips/configs/
Dmpc30x_defconfig53 CONFIG_CMDLINE="mem=32M console=ttyVR0,19200 ide0=0x170,0x376,73"
Dworkpad_defconfig68 CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x170,0x376,49 mem=16M"
/Linux-v5.15/drivers/ata/
Dpata_legacy.c70 module_param(probe_all, int, 0);
74 static int probe_mask = ~0;
75 module_param(probe_mask, int, 0);
79 module_param(autospeed, int, 0);
83 module_param(pio_mask, int, 0);
86 static int iordy_mask = 0xFFFFFFFF;
87 module_param(iordy_mask, int, 0);
91 module_param(ht6560a, int, 0);
95 module_param(ht6560b, int, 0);
99 module_param(opti82c611a, int, 0);
[all …]
/Linux-v5.15/include/dt-bindings/clock/
Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
/Linux-v5.15/drivers/tty/serial/8250/
D8250_boca.c13 SERIAL8250_PORT(0x100, 12),
14 SERIAL8250_PORT(0x108, 12),
15 SERIAL8250_PORT(0x110, 12),
16 SERIAL8250_PORT(0x118, 12),
17 SERIAL8250_PORT(0x120, 12),
18 SERIAL8250_PORT(0x128, 12),
19 SERIAL8250_PORT(0x130, 12),
20 SERIAL8250_PORT(0x138, 12),
21 SERIAL8250_PORT(0x140, 12),
22 SERIAL8250_PORT(0x148, 12),
[all …]
/Linux-v5.15/arch/arm/mach-davinci/
Dclock.h13 #define PLLCTL 0x100
14 #define PLLCTL_PLLEN BIT(0)
21 #define PLLM 0x110
22 #define PLLM_PLLM_MASK 0xff
24 #define PREDIV 0x114
25 #define PLLDIV1 0x118
26 #define PLLDIV2 0x11c
27 #define PLLDIV3 0x120
28 #define POSTDIV 0x128
29 #define BPDIV 0x12c
[all …]
/Linux-v5.15/drivers/input/serio/
Di8042-io.h20 # define I8042_AUX_IRQ (RTC_PORT(0) == 0x170 ? 9 : 12) /* Jensen is special */
39 #define I8042_COMMAND_REG 0x64
40 #define I8042_STATUS_REG 0x64
41 #define I8042_DATA_REG 0x60
79 return 0; in i8042_platform_init()
/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
/Linux-v5.15/drivers/media/platform/mtk-jpeg/
Dmtk_jpeg_enc_hw.h15 #define JPEG_ENC_INT_STATUS_DONE BIT(0)
16 #define JPEG_ENC_INT_STATUS_MASK_ALLIRQ 0x13
18 #define JPEG_ENC_DST_ADDR_OFFSET_MASK GENMASK(3, 0)
20 #define JPEG_ENC_CTRL_YUV_FORMAT_MASK 0x18
24 #define JPEG_ENC_CTRL_ENABLE_BIT BIT(0)
25 #define JPEG_ENC_RESET_BIT BIT(0)
27 #define JPEG_ENC_YUV_FORMAT_YUYV 0
32 #define JPEG_ENC_QUALITY_Q60 0x0
33 #define JPEG_ENC_QUALITY_Q80 0x1
34 #define JPEG_ENC_QUALITY_Q90 0x2
[all …]
/Linux-v5.15/drivers/scsi/
Dfdomain_isa.c10 static int io[MAXBOARDS_PARAM] = { 0, 0, 0, 0 };
11 module_param_hw_array(io, int, ioport, NULL, 0);
12 MODULE_PARM_DESC(io, "base I/O address of controller (0x140, 0x150, 0x160, 0x170)");
14 static int irq[MAXBOARDS_PARAM] = { 0, 0, 0, 0 };
15 module_param_hw_array(irq, int, irq, NULL, 0);
16 MODULE_PARM_DESC(irq, "IRQ of controller (0=auto [default])");
18 static int scsi_id[MAXBOARDS_PARAM] = { 0, 0, 0, 0 };
19 module_param_hw_array(scsi_id, int, other, NULL, 0);
23 0xc8000,
24 0xca000,
[all …]
/Linux-v5.15/drivers/usb/host/
Dehci-fsl.h9 #define FSL_SOC_USB_SBUSCFG 0x90
10 #define SBUSCFG_INCR8 0x02 /* INCR8, specified */
11 #define FSL_SOC_USB_ULPIVP 0x170
12 #define FSL_SOC_USB_PORTSC1 0x184
14 #define PORT_PTS_UTMI (0<<30)
18 #define FSL_SOC_USB_PORTSC2 0x188
19 #define FSL_SOC_USB_USBMODE 0x1a8
20 #define USBMODE_CM_MASK (3 << 0) /* controller mode mask */
21 #define USBMODE_CM_HOST (3 << 0) /* controller mode: host */
24 #define FSL_SOC_USB_USBGENCTRL 0x200
[all …]
/Linux-v5.15/drivers/mmc/host/
Dsdhci-esdhc.h27 #define ESDHC_HOST_CONTROL_LE 0x20
34 #define ESDHC_PRSSTAT 0x24
35 #define ESDHC_CLOCK_GATE_OFF 0x00000080
36 #define ESDHC_CLOCK_STABLE 0x00000008
39 #define ESDHC_PROCTL 0x28
40 #define ESDHC_VOLT_SEL 0x00000400
41 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
42 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
43 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
44 #define ESDHC_HOST_CONTROL_RES 0x01
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
/Linux-v5.15/arch/arm/mach-mmp/
Dregs-icu.h11 #define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x82000)
14 #define ICU2_VIRT_BASE (AXI_VIRT_BASE + 0x84000)
18 #define ICU_INT_CONF_MASK (0xf)
25 #define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */
26 #define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */
27 #define ICU_AP_GBL_IRQ_MSK ICU_REG(0x114) /* AP Global Interrupt Mask */
28 #define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */
29 #define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */
41 #define MMP2_ICU_PJ4_IRQ_STATUS0 ICU_REG(0x138)
42 #define MMP2_ICU_PJ4_IRQ_STATUS1 ICU_REG(0x13c)
[all …]
/Linux-v5.15/arch/mips/include/asm/mach-lantiq/xway/
Dlantiq_soc.h15 #define SOC_ID_DANUBE1 0x129
16 #define SOC_ID_DANUBE2 0x12B
17 #define SOC_ID_TWINPASS 0x12D
18 #define SOC_ID_AMAZON_SE_1 0x152 /* 50601 */
19 #define SOC_ID_AMAZON_SE_2 0x153 /* 50600 */
20 #define SOC_ID_ARX188 0x16C
21 #define SOC_ID_ARX168_1 0x16D
22 #define SOC_ID_ARX168_2 0x16E
23 #define SOC_ID_ARX182 0x16F
24 #define SOC_ID_GRX188 0x170
[all …]
/Linux-v5.15/drivers/crypto/caam/
Ddpseci_cmd.h29 #define DPSECI_CMDID_CLOSE DPSECI_CMD_V1(0x800)
30 #define DPSECI_CMDID_OPEN DPSECI_CMD_V1(0x809)
31 #define DPSECI_CMDID_GET_API_VERSION DPSECI_CMD_V1(0xa09)
33 #define DPSECI_CMDID_ENABLE DPSECI_CMD_V1(0x002)
34 #define DPSECI_CMDID_DISABLE DPSECI_CMD_V1(0x003)
35 #define DPSECI_CMDID_GET_ATTR DPSECI_CMD_V1(0x004)
36 #define DPSECI_CMDID_RESET DPSECI_CMD_V1(0x005)
37 #define DPSECI_CMDID_IS_ENABLED DPSECI_CMD_V1(0x006)
39 #define DPSECI_CMDID_SET_RX_QUEUE DPSECI_CMD_V1(0x194)
40 #define DPSECI_CMDID_GET_RX_QUEUE DPSECI_CMD_V1(0x196)
[all …]
/Linux-v5.15/arch/sh/include/mach-common/mach/
Dsdk7780.h16 #define PA_ROM 0xa0000000 /* EPROM */
17 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
18 #define PA_FROM 0xa0800000 /* Flash-ROM */
19 #define PA_FROM_SIZE 0x00400000 /* Flash-ROM size 4M byte */
20 #define PA_EXT1 0xa4000000
21 #define PA_EXT1_SIZE 0x04000000
22 #define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */
23 #define PA_SDRAM_SIZE 0x08000000
25 #define PA_EXT4 0xb0000000
26 #define PA_EXT4_SIZE 0x04000000
[all …]

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