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/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dimx8mn-var-som-symphony.dts18 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
53 gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
66 pinctrl-0 = <&pinctrl_i2c2>;
71 reg = <0x20>;
74 pinctrl-0 = <&pinctrl_pca9534>;
105 reg = <0x3d>;
109 pinctrl-0 = <&pinctrl_ptn5150>;
118 reg = <0x38>;
120 pinctrl-0 = <&pinctrl_captouch>;
132 reg = <0x68>;
[all …]
Dimx8mn-var-som.dtsi20 reg = <0x0 0x40000000 0 0x40000000>;
26 pinctrl-0 = <&pinctrl_reg_eth_phy>;
53 pinctrl-0 = <&pinctrl_ecspi1>;
55 <&gpio1 0 GPIO_ACTIVE_LOW>;
61 touchscreen@0 {
62 reg = <0>;
65 pinctrl-0 = <&pinctrl_restouch>;
89 pinctrl-0 = <&pinctrl_fec1>;
99 #size-cells = <0>;
113 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
/Linux-v5.15/Documentation/dev-tools/
Dubsan.rst22 CPU: 0 PID: 0 Comm: swapper Not tainted 4.4.0-rc1+ #26
27 [<ffffffff815e6cd6>] dump_stack+0x45/0x5f
28 [<ffffffff8163a5ed>] ubsan_epilogue+0xd/0x40
29 [<ffffffff8163ac2b>] __ubsan_handle_shift_out_of_bounds+0xeb/0x130
30 [<ffffffff815f0001>] ? radix_tree_gang_lookup_slot+0x51/0x150
31 [<ffffffff8173c586>] _mix_pool_bytes+0x1e6/0x480
32 [<ffffffff83105653>] ? dmi_walk_early+0x48/0x5c
33 [<ffffffff8173c881>] add_device_randomness+0x61/0x130
34 [<ffffffff83105b35>] ? dmi_save_one_device+0xaa/0xaa
35 [<ffffffff83105653>] dmi_walk_early+0x48/0x5c
[all …]
/Linux-v5.15/drivers/clk/renesas/
Dr8a774a1-cpg-mssr.c82 DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
103 DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, CLK_SDSRC, 0x074),
104 DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078),
105 DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268),
106 DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c),
112 DEF_DIV6P1("canfd", R8A774A1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
113 DEF_DIV6P1("csi0", R8A774A1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
114 DEF_DIV6P1("mso", R8A774A1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
115 DEF_DIV6P1("hdmi", R8A774A1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
128 DEF_MOD("fdp1-0", 119, R8A774A1_CLK_S0D1),
[all …]
Dr8a774e1-cpg-mssr.c82 DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
103 DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, CLK_SDSRC, 0x074),
104 DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, CLK_SDSRC, 0x078),
105 DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, CLK_SDSRC, 0x268),
106 DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, CLK_SDSRC, 0x26c),
113 DEF_DIV6P1("canfd", R8A774E1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
114 DEF_DIV6P1("csi0", R8A774E1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
115 DEF_DIV6P1("mso", R8A774E1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
116 DEF_DIV6P1("hdmi", R8A774E1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
125 DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
[all …]
Dr8a7796-cpg-mssr.c87 DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
109 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
110 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
111 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
112 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
119 DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
120 DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
121 DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014),
122 DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
130 DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
[all …]
Dr8a7795-cpg-mssr.c85 DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
107 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
108 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
109 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
110 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
117 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
118 DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
119 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
120 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
130 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
[all …]
Dr8a774b1-cpg-mssr.c100 DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, CLK_SDSRC, 0x074),
101 DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, CLK_SDSRC, 0x078),
102 DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, CLK_SDSRC, 0x268),
103 DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, CLK_SDSRC, 0x26c),
109 DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
110 DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
111 DEF_DIV6P1("mso", R8A774B1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
112 DEF_DIV6P1("hdmi", R8A774B1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
125 DEF_MOD("fdp1-0", 119, R8A774B1_CLK_S0D1),
256 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
[all …]
Dr8a77965-cpg-mssr.c104 DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, CLK_SDSRC, 0x074),
105 DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, CLK_SDSRC, 0x078),
106 DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268),
107 DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
114 DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
115 DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
116 DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),
117 DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
125 DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
284 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
[all …]
/Linux-v5.15/drivers/clk/mediatek/
Dclk-mt7622.c295 .set_ofs = 0x8,
296 .clr_ofs = 0x8,
297 .sta_ofs = 0x8,
301 .set_ofs = 0x40,
302 .clr_ofs = 0x44,
303 .sta_ofs = 0x48,
307 .set_ofs = 0x120,
308 .clr_ofs = 0x120,
309 .sta_ofs = 0x120,
313 .set_ofs = 0x128,
[all …]
/Linux-v5.15/arch/arm/mach-mmp/
Dmmp2.c32 #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
36 MFP_ADDR_X(GPIO0, GPIO58, 0x54),
37 MFP_ADDR_X(GPIO59, GPIO73, 0x280),
38 MFP_ADDR_X(GPIO74, GPIO101, 0x170),
40 MFP_ADDR(GPIO102, 0x0),
41 MFP_ADDR(GPIO103, 0x4),
42 MFP_ADDR(GPIO104, 0x1fc),
43 MFP_ADDR(GPIO105, 0x1f8),
44 MFP_ADDR(GPIO106, 0x1f4),
45 MFP_ADDR(GPIO107, 0x1f0),
[all …]
/Linux-v5.15/include/linux/mfd/syscon/
Datmel-matrix.h11 #define AT91SAM9260_MATRIX_MCFG 0x00
12 #define AT91SAM9260_MATRIX_SCFG 0x40
13 #define AT91SAM9260_MATRIX_PRS 0x80
14 #define AT91SAM9260_MATRIX_MRCR 0x100
15 #define AT91SAM9260_MATRIX_EBICSA 0x11c
17 #define AT91SAM9261_MATRIX_MRCR 0x0
18 #define AT91SAM9261_MATRIX_SCFG 0x4
19 #define AT91SAM9261_MATRIX_TCR 0x24
20 #define AT91SAM9261_MATRIX_EBICSA 0x30
21 #define AT91SAM9261_MATRIX_USBPUCR 0x34
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-mediatek-hw.yaml47 #size-cells = <0>;
49 cpu0: cpu@0 {
53 performance-domains = <&performance 0>;
54 reg = <0x000>;
66 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
/Linux-v5.15/drivers/media/usb/gspca/
Dkonica.c29 #define WHITEBAL_REG 0x01
30 #define BRIGHTNESS_REG 0x02
31 #define SHARPNESS_REG 0x03
32 #define CONTRAST_REG 0x04
33 #define SATURATION_REG 0x05
44 0x00 -> 176x144, cropped
45 0x01 -> 176x144, cropped
46 0x02 -> 176x144, cropped
47 0x03 -> 176x144, cropped
48 0x04 -> 176x144, binned
[all …]
/Linux-v5.15/include/dt-bindings/clock/
Dam3.h8 #define AM3_CLKCTRL_OFFSET 0x0
14 #define AM3_L4_PER_CLKCTRL_OFFSET 0x14
16 #define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14)
17 #define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18)
18 #define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c)
19 #define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24)
20 #define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28)
21 #define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c)
22 #define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30)
23 #define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34)
[all …]
Dam4.h8 #define AM4_CLKCTRL_OFFSET 0x20
14 #define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120)
15 #define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
16 #define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228)
17 #define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230)
18 #define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328)
19 #define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338)
20 #define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340)
21 #define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348)
22 #define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350)
[all …]
/Linux-v5.15/drivers/phy/qualcomm/
Dphy-qcom-qmp.h11 #define QSERDES_PLL_BG_TIMER 0x00c
12 #define QSERDES_PLL_SSC_PER1 0x01c
13 #define QSERDES_PLL_SSC_PER2 0x020
14 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
15 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
16 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
17 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
18 #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c
19 #define QSERDES_PLL_CLK_ENABLE1 0x040
20 #define QSERDES_PLL_SYS_CLK_CTRL 0x044
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/soc/ti/
Dkeystone-navigator-dma.txt17 |-> DMA instance #0
64 knav_dmas: knav_dmas@0 {
70 ti,navigator-cloud-address = <0x23a80000 0x23a90000
71 0x23aa0000 0x23ab0000>;
73 dma_gbe: dma_gbe@0 {
74 reg = <0x2004000 0x100>,
75 <0x2004400 0x120>,
76 <0x2004800 0x300>,
77 <0x2004c00 0x120>,
78 <0x2005000 0x400>;
[all …]
/Linux-v5.15/drivers/pinctrl/samsung/
Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
73 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
93 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
94 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
95 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
96 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
97 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
98 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dmmp3.dtsi16 #size-cells = <0>;
19 cpu@0 {
23 reg = <0>;
45 reg = <0xd4200000 0x00200000>;
52 reg = <0xd4282000 0x1000>,
53 <0xd4284000 0x100>;
62 reg = <0x150 0x4>, <0x168 0x4>;
72 reg = <0x154 0x4>, <0x16c 0x4>;
82 reg = <0x1bc 0x4>, <0x1a4 0x4>;
92 reg = <0x1c0 0x4>, <0x1a8 0x4>;
[all …]
Dmmp2.dtsi33 marvell,tauros2-cache-features = <0x3>;
40 reg = <0xd4200000 0x00200000>;
45 reg = <0xd420d000 0x4000>;
58 reg = <0xd4282000 0x1000>;
67 reg = <0x150 0x4>, <0x168 0x4>;
77 reg = <0x154 0x4>, <0x16c 0x4>;
88 reg = <0x180 0x4>, <0x17c 0x4>;
98 reg = <0x158 0x4>, <0x170 0x4>;
108 reg = <0x15c 0x4>, <0x174 0x4>;
118 reg = <0x160 0x4>, <0x178 0x4>;
[all …]
Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/watchdog/
Drt2880-wdt.txt14 reg = <0x120 0x10>;
/Linux-v5.15/arch/arm64/boot/dts/mediatek/
Dmt8183-kukui-kodama-sku288.dts5 * SKU: 0x120 => 288
7 * - bits 7..4: Panel ID: 0x2 (BOE)
/Linux-v5.15/drivers/clk/hisilicon/
Dclk-hix5hd2.c14 { HIX5HD2_FIXED_1200M, "1200m", NULL, 0, 1200000000, },
15 { HIX5HD2_FIXED_400M, "400m", NULL, 0, 400000000, },
16 { HIX5HD2_FIXED_48M, "48m", NULL, 0, 48000000, },
17 { HIX5HD2_FIXED_24M, "24m", NULL, 0, 24000000, },
18 { HIX5HD2_FIXED_600M, "600m", NULL, 0, 600000000, },
19 { HIX5HD2_FIXED_300M, "300m", NULL, 0, 300000000, },
20 { HIX5HD2_FIXED_75M, "75m", NULL, 0, 75000000, },
21 { HIX5HD2_FIXED_200M, "200m", NULL, 0, 200000000, },
22 { HIX5HD2_FIXED_100M, "100m", NULL, 0, 100000000, },
23 { HIX5HD2_FIXED_40M, "40m", NULL, 0, 40000000, },
[all …]

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