Searched +full:0 +full:x01c2bc00 (Results 1 – 4 of 4) sorted by relevance
46 reg = <0x01c2bc00 0x400>;
67 /* Registers address (physical base address 0x01C2BC00) */68 #define SUN4I_REG_MSEL_ADDR 0x0000 /* CAN Mode Select */69 #define SUN4I_REG_CMD_ADDR 0x0004 /* CAN Command */70 #define SUN4I_REG_STA_ADDR 0x0008 /* CAN Status */71 #define SUN4I_REG_INT_ADDR 0x000c /* CAN Interrupt Flag */72 #define SUN4I_REG_INTEN_ADDR 0x0010 /* CAN Interrupt Enable */73 #define SUN4I_REG_BTIME_ADDR 0x0014 /* CAN Bus Timing 0 */74 #define SUN4I_REG_TEWL_ADDR 0x0018 /* CAN Tx Error Warning Limit */75 #define SUN4I_REG_ERRC_ADDR 0x001c /* CAN Error Counter */76 #define SUN4I_REG_RMCNT_ADDR 0x0020 /* CAN Receive Message Counter */[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;167 #clock-cells = <0>;174 #clock-cells = <0>;200 size = <0x6000000>;201 alloc-ranges = <0x40000000 0x10000000>;215 reg = <0x01c00000 0x30>;220 sram_a: sram@0 {222 reg = <0x00000000 0xc000>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;183 size = <0x6000000>;184 alloc-ranges = <0x40000000 0x10000000>;210 #clock-cells = <0>;217 #clock-cells = <0>;233 #clock-cells = <0>;240 #clock-cells = <0>;247 #clock-cells = <0>;[all …]
