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/Linux-v6.1/arch/arm/boot/dts/
Dtegra30-asus-tf201.dts67 reg = <0x4d>;
82 mount-matrix = "-1", "0", "0",
83 "0", "-1", "0",
84 "0", "0", "-1";
88 mount-matrix = "0", "-1", "0",
89 "-1", "0", "0",
90 "0", "0", "-1";
95 mount-matrix = "1", "0", "0",
96 "0", "-1", "0",
97 "0", "0", "1";
[all …]
Dtegra30-asus-tf300tg.dts22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
171 reg = <0x10>;
190 mount-matrix = "1", "0", "0",
191 "0", "-1", "0",
192 "0", "0", "-1";
196 mount-matrix = "-1", "0", "0",
197 "0", "1", "0",
198 "0", "0", "-1";
203 mount-matrix = "0", "-1", "0",
204 "-1", "0", "0",
[all …]
Dtegra30-asus-tf300t.dts75 reg = <0x10>;
94 mount-matrix = "0", "-1", "0",
95 "-1", "0", "0",
96 "0", "0", "-1";
100 mount-matrix = "-1", "0", "0",
101 "0", "1", "0",
102 "0", "0", "-1";
107 mount-matrix = "0", "-1", "0",
108 "-1", "0", "0",
109 "0", "0", "1";
[all …]
Dtegra30-asus-tf700t.dts18 port@0 {
92 reg = <0x10>;
111 mount-matrix = "1", "0", "0",
112 "0", "-1", "0",
113 "0", "0", "-1";
117 mount-matrix = "0", "1", "0",
118 "1", "0", "0",
119 "0", "0", "-1";
124 mount-matrix = "0", "-1", "0",
125 "-1", "0", "0",
[all …]
Dtegra124-nyan-blaze-emc.dtsi89 0x40040001
90 0x8000000a
91 0x00000001
92 0x00000001
93 0x00000002
94 0x00000000
95 0x00000002
96 0x00000001
97 0x00000002
98 0x00000008
[all …]
Dtegra20-acer-a500-picasso.dts37 memory@0 {
38 reg = <0x00000000 0x40000000>;
48 reg = <0x2ffe0000 0x10000>; /* 64kB */
49 console-size = <0x8000>; /* 32kB */
50 record-size = <0x400>; /* 1kB */
56 alloc-ranges = <0x30000000 0x10000000>;
57 size = <0x10000000>; /* 256MiB */
68 port@0 {
92 pinctrl-0 = <&state_default>;
420 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
[all …]
Dtegra124-apalis-emc.dtsi106 0x40040001 0x8000000a
107 0x00000001 0x00000001
108 0x00000002 0x00000000
109 0x00000002 0x00000001
110 0x00000003 0x00000008
111 0x00000003 0x00000002
112 0x00000003 0x00000006
113 0x06030203 0x000a0502
114 0x77e30303 0x70000f03
115 0x001f0000
[all …]
Dtegra124-jetson-tk1-emc.dtsi101 0x40040001
102 0x8000000a
103 0x00000001
104 0x00000001
105 0x00000002
106 0x00000000
107 0x00000002
108 0x00000001
109 0x00000003
110 0x00000008
[all …]
Dtegra30-pegatron-chagall.dts41 reg = <0x80000000 0x40000000>;
51 alloc-ranges = <0x80000000 0x30000000>;
52 size = <0x10000000>; /* 256MiB */
59 reg = <0xbeb00000 0x10000>; /* 64kB */
60 console-size = <0x8000>; /* 32kB */
61 record-size = <0x400>; /* 1kB */
66 reg = <0xbfe00000 0x200000>; /* 2MB */
92 pinctrl-0 = <&state_default>;
136 nvidia,lock = <0>;
137 nvidia,ioreset = <0>;
[all …]
Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
[all …]
Dtegra124-nyan-big-emc.dtsi260 0x40040001 /* MC_EMEM_ARB_CFG */
261 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
262 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
263 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
264 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
265 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
266 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
267 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
268 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
269 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
[all …]
/Linux-v6.1/drivers/soc/atmel/
Dsoc.h36 #define AT91RM9200_CIDR_MATCH 0x09290780
38 #define AT91SAM9260_CIDR_MATCH 0x019803a0
39 #define AT91SAM9261_CIDR_MATCH 0x019703a0
40 #define AT91SAM9263_CIDR_MATCH 0x019607a0
41 #define AT91SAM9G20_CIDR_MATCH 0x019905a0
42 #define AT91SAM9RL64_CIDR_MATCH 0x019b03a0
43 #define AT91SAM9G45_CIDR_MATCH 0x019b05a0
44 #define AT91SAM9X5_CIDR_MATCH 0x019a05a0
45 #define AT91SAM9N12_CIDR_MATCH 0x019a07a0
46 #define SAM9X60_CIDR_MATCH 0x019b35a0
[all …]
/Linux-v6.1/tools/testing/selftests/powerpc/vphn/
Dtest-vphn.c29 0xffffffffffffffff,
30 0xffffffffffffffff,
31 0xffffffffffffffff,
32 0xffffffffffffffff,
33 0xffffffffffffffff,
34 0xffffffffffffffff,
37 0x00000000
43 0x8001ffffffffffff,
44 0xffffffffffffffff,
45 0xffffffffffffffff,
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/include/
Dvega10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 NO_FORCE_REQUEST = 0x00000000,
185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
187 FORCE_SHUT_DOWN_REQUEST = 0x00000003,
195 NO_FORCE_REQ = 0x00000000,
196 FORCE_LIGHT_SLEEP_REQ = 0x00000001,
204 ENABLE_MEM_PWR_CTRL = 0x00000000,
205 DISABLE_MEM_PWR_CTRL = 0x00000001,
213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
[all …]
Dsoc21_enum.h55 DSM_DATA_SEL_DISABLE = 0x00000000,
56 DSM_DATA_SEL_0 = 0x00000001,
57 DSM_DATA_SEL_1 = 0x00000002,
58 DSM_DATA_SEL_BOTH = 0x00000003,
66 DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000,
67 DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001,
68 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 0x00000002,
69 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003,
77 DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000,
78 DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001,
[all …]
Dnavi10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 GATCL1_TYPE_NORMAL = 0x00000000,
185 GATCL1_TYPE_SHOOTDOWN = 0x00000001,
186 GATCL1_TYPE_BYPASS = 0x00000002,
194 UTCL1_TYPE_NORMAL = 0x00000000,
195 UTCL1_TYPE_SHOOTDOWN = 0x00000001,
196 UTCL1_TYPE_BYPASS = 0x00000002,
204 UTCL1_XNACK_SUCCESS = 0x00000000,
205 UTCL1_XNACK_RETRY = 0x00000001,
206 UTCL1_XNACK_PRT = 0x00000002,
[all …]
/Linux-v6.1/sound/soc/tegra/
Dtegra210_sfc.c28 { TEGRA210_SFC_RX_INT_MASK, 0x00000001},
29 { TEGRA210_SFC_RX_CIF_CTRL, 0x00007700},
30 { TEGRA210_SFC_TX_INT_MASK, 0x00000001},
31 { TEGRA210_SFC_TX_CIF_CTRL, 0x00007700},
32 { TEGRA210_SFC_CG, 0x1},
33 { TEGRA210_SFC_CFG_RAM_CTRL, 0x00004000},
53 0x000c6102,//header
54 0x0001d727,//input gain
55 0x00fc2fc7, 0xff9bb27b, 0x001c564c,
56 0x00e55557, 0xffcadd5b, 0x003d80ba,
[all …]
/Linux-v6.1/drivers/gpu/drm/nouveau/include/nvhw/class/
Dcla0b5.h27 #define NVA0B5_SET_SRC_PHYS_MODE (0x00000260)
28 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET 1:0
29 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
30 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
31 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
32 #define NVA0B5_SET_DST_PHYS_MODE (0x00000264)
33 #define NVA0B5_SET_DST_PHYS_MODE_TARGET 1:0
34 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
35 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
36 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
[all …]
Dcl917d.h28 #define NV917D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0…
29 #define NV917D_SOR_SET_CONTROL_OWNER_MASK 3:0
30 #define NV917D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000)
31 #define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001)
32 #define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002)
33 #define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004)
34 #define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008)
36 #define NV917D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
37 #define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001)
38 #define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002)
[all …]
Dcl507d.h27 #define NV_DISP_CORE_NOTIFIER_1 0x00000000
28 #define NV_DISP_CORE_NOTIFIER_1_SIZEOF 0x00000054
29 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0 0x00000000
30 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE 0:0
31 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_FALSE 0x00000000
32 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE 0x00000001
35 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1 0x00000001
36 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE 0:0
37 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_FALSE 0x00000000
38 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_TRUE 0x00000001
[all …]
Dclc37d.h27 #define NV_DISP_NOTIFIER 0x00000000
28 #define NV_DISP_NOTIFIER_SIZEOF 0x00000010
29 #define NV_DISP_NOTIFIER__0 0x00000000
30 #define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0
33 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000
34 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001
39 #define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000
40 #define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001
41 #define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002
42 #define NV_DISP_NOTIFIER__1 0x00000001
[all …]
/Linux-v6.1/sound/pci/cs46xx/
Dcs46xx.h25 #define BA0_HISR 0x00000000
26 #define BA0_HSR0 0x00000004
27 #define BA0_HICR 0x00000008
28 #define BA0_DMSR 0x00000100
29 #define BA0_HSAR 0x00000110
30 #define BA0_HDAR 0x00000114
31 #define BA0_HDMR 0x00000118
32 #define BA0_HDCR 0x0000011C
33 #define BA0_PFMC 0x00000200
34 #define BA0_PFCV1 0x00000204
[all …]
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_3_0_sh_mask.h26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L
27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007
28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L
29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001
30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L
31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000
32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L
33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005
34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L
35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002
[all …]
/Linux-v6.1/include/uapi/sound/
Dcompress_params.h30 #define SND_AUDIOCODEC_PCM ((__u32) 0x00000001)
31 #define SND_AUDIOCODEC_MP3 ((__u32) 0x00000002)
32 #define SND_AUDIOCODEC_AMR ((__u32) 0x00000003)
33 #define SND_AUDIOCODEC_AMRWB ((__u32) 0x00000004)
34 #define SND_AUDIOCODEC_AMRWBPLUS ((__u32) 0x00000005)
35 #define SND_AUDIOCODEC_AAC ((__u32) 0x00000006)
36 #define SND_AUDIOCODEC_WMA ((__u32) 0x00000007)
37 #define SND_AUDIOCODEC_REAL ((__u32) 0x00000008)
38 #define SND_AUDIOCODEC_VORBIS ((__u32) 0x00000009)
39 #define SND_AUDIOCODEC_FLAC ((__u32) 0x0000000A)
[all …]
/Linux-v6.1/drivers/net/ethernet/renesas/
Dravb.h38 #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */
39 #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */
41 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
42 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
43 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
44 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
45 #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */
49 CCC = 0x0000,
50 DBAT = 0x0004,
51 DLR = 0x0008,
[all …]

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