1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/fb.h>
26 
27 #include "vega10_processpptables.h"
28 #include "ppatomfwctrl.h"
29 #include "atomfirmware.h"
30 #include "pp_debug.h"
31 #include "cgs_common.h"
32 #include "vega10_pptable.h"
33 
34 #define NUM_DSPCLK_LEVELS 8
35 
set_hw_cap(struct pp_hwmgr * hwmgr,bool enable,enum phm_platform_caps cap)36 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
37 		enum phm_platform_caps cap)
38 {
39 	if (enable)
40 		phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
41 	else
42 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
43 }
44 
get_powerplay_table(struct pp_hwmgr * hwmgr)45 static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
46 {
47 	int index = GetIndexIntoMasterDataTable(powerplayinfo);
48 
49 	u16 size;
50 	u8 frev, crev;
51 	const void *table_address = hwmgr->soft_pp_table;
52 
53 	if (!table_address) {
54 		table_address = (ATOM_Vega10_POWERPLAYTABLE *)
55 				smu_atom_get_data_table(hwmgr->adev, index,
56 						&size, &frev, &crev);
57 
58 		hwmgr->soft_pp_table = table_address;	/*Cache the result in RAM.*/
59 		hwmgr->soft_pp_table_size = size;
60 	}
61 
62 	return table_address;
63 }
64 
check_powerplay_tables(struct pp_hwmgr * hwmgr,const ATOM_Vega10_POWERPLAYTABLE * powerplay_table)65 static int check_powerplay_tables(
66 		struct pp_hwmgr *hwmgr,
67 		const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
68 {
69 	const ATOM_Vega10_State_Array *state_arrays;
70 
71 	state_arrays = (ATOM_Vega10_State_Array *)(((unsigned long)powerplay_table) +
72 		le16_to_cpu(powerplay_table->usStateArrayOffset));
73 
74 	PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
75 			ATOM_Vega10_TABLE_REVISION_VEGA10),
76 		"Unsupported PPTable format!", return -1);
77 	PP_ASSERT_WITH_CODE(powerplay_table->usStateArrayOffset,
78 		"State table is not set!", return -1);
79 	PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
80 		"Invalid PowerPlay Table!", return -1);
81 	PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,
82 		"Invalid PowerPlay Table!", return -1);
83 
84 	return 0;
85 }
86 
set_platform_caps(struct pp_hwmgr * hwmgr,uint32_t powerplay_caps)87 static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
88 {
89 	set_hw_cap(
90 			hwmgr,
91 			0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_POWERPLAY),
92 			PHM_PlatformCaps_PowerPlaySupport);
93 
94 	set_hw_cap(
95 			hwmgr,
96 			0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_SBIOSPOWERSOURCE),
97 			PHM_PlatformCaps_BiosPowerSourceControl);
98 
99 	set_hw_cap(
100 			hwmgr,
101 			0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_HARDWAREDC),
102 			PHM_PlatformCaps_AutomaticDCTransition);
103 
104 	set_hw_cap(
105 			hwmgr,
106 			0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_BACO),
107 			PHM_PlatformCaps_BACO);
108 
109 	set_hw_cap(
110 			hwmgr,
111 			0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL),
112 			PHM_PlatformCaps_CombinePCCWithThermalSignal);
113 
114 	return 0;
115 }
116 
init_thermal_controller(struct pp_hwmgr * hwmgr,const ATOM_Vega10_POWERPLAYTABLE * powerplay_table)117 static int init_thermal_controller(
118 		struct pp_hwmgr *hwmgr,
119 		const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
120 {
121 	const ATOM_Vega10_Thermal_Controller *thermal_controller;
122 	const Vega10_PPTable_Generic_SubTable_Header *header;
123 	const ATOM_Vega10_Fan_Table *fan_table_v1;
124 	const ATOM_Vega10_Fan_Table_V2 *fan_table_v2;
125 
126 	thermal_controller = (ATOM_Vega10_Thermal_Controller *)
127 			(((unsigned long)powerplay_table) +
128 			le16_to_cpu(powerplay_table->usThermalControllerOffset));
129 
130 	PP_ASSERT_WITH_CODE((powerplay_table->usThermalControllerOffset != 0),
131 			"Thermal controller table not set!", return -EINVAL);
132 
133 	hwmgr->thermal_controller.ucType = thermal_controller->ucType;
134 	hwmgr->thermal_controller.ucI2cLine = thermal_controller->ucI2cLine;
135 	hwmgr->thermal_controller.ucI2cAddress = thermal_controller->ucI2cAddress;
136 
137 	hwmgr->thermal_controller.fanInfo.bNoFan =
138 			(0 != (thermal_controller->ucFanParameters &
139 			ATOM_VEGA10_PP_FANPARAMETERS_NOFAN));
140 
141 	hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
142 			thermal_controller->ucFanParameters &
143 			ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
144 
145 	hwmgr->thermal_controller.fanInfo.ulMinRPM =
146 			thermal_controller->ucFanMinRPM * 100UL;
147 	hwmgr->thermal_controller.fanInfo.ulMaxRPM =
148 			thermal_controller->ucFanMaxRPM * 100UL;
149 
150 	hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay
151 			= 100000;
152 
153 	set_hw_cap(
154 			hwmgr,
155 			ATOM_VEGA10_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
156 			PHM_PlatformCaps_ThermalController);
157 
158 	if (!powerplay_table->usFanTableOffset)
159 		return 0;
160 
161 	header = (const Vega10_PPTable_Generic_SubTable_Header *)
162 			(((unsigned long)powerplay_table) +
163 			le16_to_cpu(powerplay_table->usFanTableOffset));
164 
165 	if (header->ucRevId == 10) {
166 		fan_table_v1 = (ATOM_Vega10_Fan_Table *)header;
167 
168 		PP_ASSERT_WITH_CODE((fan_table_v1->ucRevId >= 8),
169 				"Invalid Input Fan Table!", return -EINVAL);
170 
171 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
172 				PHM_PlatformCaps_MicrocodeFanControl);
173 
174 		hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
175 				le16_to_cpu(fan_table_v1->usFanOutputSensitivity);
176 		hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
177 				le16_to_cpu(fan_table_v1->usFanRPMMax);
178 		hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
179 				le16_to_cpu(fan_table_v1->usThrottlingRPM);
180 		hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit =
181 				le16_to_cpu(fan_table_v1->usFanAcousticLimit);
182 		hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
183 				le16_to_cpu(fan_table_v1->usTargetTemperature);
184 		hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
185 				le16_to_cpu(fan_table_v1->usMinimumPWMLimit);
186 		hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk =
187 				le16_to_cpu(fan_table_v1->usTargetGfxClk);
188 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge =
189 				le16_to_cpu(fan_table_v1->usFanGainEdge);
190 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot =
191 				le16_to_cpu(fan_table_v1->usFanGainHotspot);
192 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid =
193 				le16_to_cpu(fan_table_v1->usFanGainLiquid);
194 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc =
195 				le16_to_cpu(fan_table_v1->usFanGainVrVddc);
196 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd =
197 				le16_to_cpu(fan_table_v1->usFanGainVrMvdd);
198 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx =
199 				le16_to_cpu(fan_table_v1->usFanGainPlx);
200 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm =
201 				le16_to_cpu(fan_table_v1->usFanGainHbm);
202 
203 		hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM =
204 				fan_table_v1->ucEnableZeroRPM;
205 		hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature =
206 				le16_to_cpu(fan_table_v1->usFanStopTemperature);
207 		hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
208 				le16_to_cpu(fan_table_v1->usFanStartTemperature);
209 	} else if (header->ucRevId > 10) {
210 		fan_table_v2 = (ATOM_Vega10_Fan_Table_V2 *)header;
211 
212 		hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
213 				fan_table_v2->ucFanParameters & ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
214 		hwmgr->thermal_controller.fanInfo.ulMinRPM = fan_table_v2->ucFanMinRPM * 100UL;
215 		hwmgr->thermal_controller.fanInfo.ulMaxRPM = fan_table_v2->ucFanMaxRPM * 100UL;
216 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
217 				PHM_PlatformCaps_MicrocodeFanControl);
218 		hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
219 				le16_to_cpu(fan_table_v2->usFanOutputSensitivity);
220 		hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
221 				fan_table_v2->ucFanMaxRPM * 100UL;
222 		hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
223 				le16_to_cpu(fan_table_v2->usThrottlingRPM);
224 		hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit =
225 				le16_to_cpu(fan_table_v2->usFanAcousticLimitRpm);
226 		hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
227 				le16_to_cpu(fan_table_v2->usTargetTemperature);
228 		hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
229 				le16_to_cpu(fan_table_v2->usMinimumPWMLimit);
230 		hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk =
231 				le16_to_cpu(fan_table_v2->usTargetGfxClk);
232 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge =
233 				le16_to_cpu(fan_table_v2->usFanGainEdge);
234 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot =
235 				le16_to_cpu(fan_table_v2->usFanGainHotspot);
236 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid =
237 				le16_to_cpu(fan_table_v2->usFanGainLiquid);
238 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc =
239 				le16_to_cpu(fan_table_v2->usFanGainVrVddc);
240 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd =
241 				le16_to_cpu(fan_table_v2->usFanGainVrMvdd);
242 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx =
243 				le16_to_cpu(fan_table_v2->usFanGainPlx);
244 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm =
245 				le16_to_cpu(fan_table_v2->usFanGainHbm);
246 
247 		hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM =
248 				fan_table_v2->ucEnableZeroRPM;
249 		hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature =
250 				le16_to_cpu(fan_table_v2->usFanStopTemperature);
251 		hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
252 				le16_to_cpu(fan_table_v2->usFanStartTemperature);
253 	}
254 	return 0;
255 }
256 
init_over_drive_limits(struct pp_hwmgr * hwmgr,const ATOM_Vega10_POWERPLAYTABLE * powerplay_table)257 static int init_over_drive_limits(
258 		struct pp_hwmgr *hwmgr,
259 		const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
260 {
261 	hwmgr->platform_descriptor.overdriveLimit.engineClock =
262 			le32_to_cpu(powerplay_table->ulMaxODEngineClock);
263 	hwmgr->platform_descriptor.overdriveLimit.memoryClock =
264 			le32_to_cpu(powerplay_table->ulMaxODMemoryClock);
265 
266 	hwmgr->platform_descriptor.minOverdriveVDDC = 0;
267 	hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
268 	hwmgr->platform_descriptor.overdriveVDDCStep = 0;
269 
270 	return 0;
271 }
272 
get_mm_clock_voltage_table(struct pp_hwmgr * hwmgr,phm_ppt_v1_mm_clock_voltage_dependency_table ** vega10_mm_table,const ATOM_Vega10_MM_Dependency_Table * mm_dependency_table)273 static int get_mm_clock_voltage_table(
274 		struct pp_hwmgr *hwmgr,
275 		phm_ppt_v1_mm_clock_voltage_dependency_table **vega10_mm_table,
276 		const ATOM_Vega10_MM_Dependency_Table *mm_dependency_table)
277 {
278 	uint32_t table_size, i;
279 	const ATOM_Vega10_MM_Dependency_Record *mm_dependency_record;
280 	phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table;
281 
282 	PP_ASSERT_WITH_CODE((mm_dependency_table->ucNumEntries != 0),
283 			"Invalid PowerPlay Table!", return -1);
284 
285 	table_size = sizeof(uint32_t) +
286 			sizeof(phm_ppt_v1_mm_clock_voltage_dependency_record) *
287 			mm_dependency_table->ucNumEntries;
288 	mm_table = kzalloc(table_size, GFP_KERNEL);
289 
290 	if (!mm_table)
291 		return -ENOMEM;
292 
293 	mm_table->count = mm_dependency_table->ucNumEntries;
294 
295 	for (i = 0; i < mm_dependency_table->ucNumEntries; i++) {
296 		mm_dependency_record = &mm_dependency_table->entries[i];
297 		mm_table->entries[i].vddcInd = mm_dependency_record->ucVddcInd;
298 		mm_table->entries[i].samclock =
299 				le32_to_cpu(mm_dependency_record->ulPSPClk);
300 		mm_table->entries[i].eclk = le32_to_cpu(mm_dependency_record->ulEClk);
301 		mm_table->entries[i].vclk = le32_to_cpu(mm_dependency_record->ulVClk);
302 		mm_table->entries[i].dclk = le32_to_cpu(mm_dependency_record->ulDClk);
303 	}
304 
305 	*vega10_mm_table = mm_table;
306 
307 	return 0;
308 }
309 
get_scl_sda_value(uint8_t line,uint8_t * scl,uint8_t * sda)310 static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t* sda)
311 {
312 	switch(line){
313 	case Vega10_I2CLineID_DDC1:
314 		*scl = Vega10_I2C_DDC1CLK;
315 		*sda = Vega10_I2C_DDC1DATA;
316 		break;
317 	case Vega10_I2CLineID_DDC2:
318 		*scl = Vega10_I2C_DDC2CLK;
319 		*sda = Vega10_I2C_DDC2DATA;
320 		break;
321 	case Vega10_I2CLineID_DDC3:
322 		*scl = Vega10_I2C_DDC3CLK;
323 		*sda = Vega10_I2C_DDC3DATA;
324 		break;
325 	case Vega10_I2CLineID_DDC4:
326 		*scl = Vega10_I2C_DDC4CLK;
327 		*sda = Vega10_I2C_DDC4DATA;
328 		break;
329 	case Vega10_I2CLineID_DDC5:
330 		*scl = Vega10_I2C_DDC5CLK;
331 		*sda = Vega10_I2C_DDC5DATA;
332 		break;
333 	case Vega10_I2CLineID_DDC6:
334 		*scl = Vega10_I2C_DDC6CLK;
335 		*sda = Vega10_I2C_DDC6DATA;
336 		break;
337 	case Vega10_I2CLineID_SCLSDA:
338 		*scl = Vega10_I2C_SCL;
339 		*sda = Vega10_I2C_SDA;
340 		break;
341 	case Vega10_I2CLineID_DDCVGA:
342 		*scl = Vega10_I2C_DDCVGACLK;
343 		*sda = Vega10_I2C_DDCVGADATA;
344 		break;
345 	default:
346 		*scl = 0;
347 		*sda = 0;
348 		break;
349 	}
350 }
351 
get_tdp_table(struct pp_hwmgr * hwmgr,struct phm_tdp_table ** info_tdp_table,const Vega10_PPTable_Generic_SubTable_Header * table)352 static int get_tdp_table(
353 		struct pp_hwmgr *hwmgr,
354 		struct phm_tdp_table **info_tdp_table,
355 		const Vega10_PPTable_Generic_SubTable_Header *table)
356 {
357 	uint32_t table_size;
358 	struct phm_tdp_table *tdp_table;
359 	uint8_t scl;
360 	uint8_t sda;
361 	const ATOM_Vega10_PowerTune_Table *power_tune_table;
362 	const ATOM_Vega10_PowerTune_Table_V2 *power_tune_table_v2;
363 	const ATOM_Vega10_PowerTune_Table_V3 *power_tune_table_v3;
364 
365 	table_size = sizeof(uint32_t) + sizeof(struct phm_tdp_table);
366 
367 	tdp_table = kzalloc(table_size, GFP_KERNEL);
368 
369 	if (!tdp_table)
370 		return -ENOMEM;
371 
372 	if (table->ucRevId == 5) {
373 		power_tune_table = (ATOM_Vega10_PowerTune_Table *)table;
374 		tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table->usSocketPowerLimit);
375 		tdp_table->usTDC = le16_to_cpu(power_tune_table->usTdcLimit);
376 		tdp_table->usEDCLimit = le16_to_cpu(power_tune_table->usEdcLimit);
377 		tdp_table->usSoftwareShutdownTemp =
378 				le16_to_cpu(power_tune_table->usSoftwareShutdownTemp);
379 		tdp_table->usTemperatureLimitTedge =
380 				le16_to_cpu(power_tune_table->usTemperatureLimitTedge);
381 		tdp_table->usTemperatureLimitHotspot =
382 				le16_to_cpu(power_tune_table->usTemperatureLimitHotSpot);
383 		tdp_table->usTemperatureLimitLiquid1 =
384 				le16_to_cpu(power_tune_table->usTemperatureLimitLiquid1);
385 		tdp_table->usTemperatureLimitLiquid2 =
386 				le16_to_cpu(power_tune_table->usTemperatureLimitLiquid2);
387 		tdp_table->usTemperatureLimitHBM =
388 				le16_to_cpu(power_tune_table->usTemperatureLimitHBM);
389 		tdp_table->usTemperatureLimitVrVddc =
390 				le16_to_cpu(power_tune_table->usTemperatureLimitVrSoc);
391 		tdp_table->usTemperatureLimitVrMvdd =
392 				le16_to_cpu(power_tune_table->usTemperatureLimitVrMem);
393 		tdp_table->usTemperatureLimitPlx =
394 				le16_to_cpu(power_tune_table->usTemperatureLimitPlx);
395 		tdp_table->ucLiquid1_I2C_address = power_tune_table->ucLiquid1_I2C_address;
396 		tdp_table->ucLiquid2_I2C_address = power_tune_table->ucLiquid2_I2C_address;
397 		tdp_table->ucLiquid_I2C_Line = power_tune_table->ucLiquid_I2C_LineSCL;
398 		tdp_table->ucLiquid_I2C_LineSDA = power_tune_table->ucLiquid_I2C_LineSDA;
399 		tdp_table->ucVr_I2C_address = power_tune_table->ucVr_I2C_address;
400 		tdp_table->ucVr_I2C_Line = power_tune_table->ucVr_I2C_LineSCL;
401 		tdp_table->ucVr_I2C_LineSDA = power_tune_table->ucVr_I2C_LineSDA;
402 		tdp_table->ucPlx_I2C_address = power_tune_table->ucPlx_I2C_address;
403 		tdp_table->ucPlx_I2C_Line = power_tune_table->ucPlx_I2C_LineSCL;
404 		tdp_table->ucPlx_I2C_LineSDA = power_tune_table->ucPlx_I2C_LineSDA;
405 		hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(power_tune_table->usLoadLineResistance);
406 	} else if (table->ucRevId == 6) {
407 		power_tune_table_v2 = (ATOM_Vega10_PowerTune_Table_V2 *)table;
408 		tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table_v2->usSocketPowerLimit);
409 		tdp_table->usTDC = le16_to_cpu(power_tune_table_v2->usTdcLimit);
410 		tdp_table->usEDCLimit = le16_to_cpu(power_tune_table_v2->usEdcLimit);
411 		tdp_table->usSoftwareShutdownTemp =
412 				le16_to_cpu(power_tune_table_v2->usSoftwareShutdownTemp);
413 		tdp_table->usTemperatureLimitTedge =
414 				le16_to_cpu(power_tune_table_v2->usTemperatureLimitTedge);
415 		tdp_table->usTemperatureLimitHotspot =
416 				le16_to_cpu(power_tune_table_v2->usTemperatureLimitHotSpot);
417 		tdp_table->usTemperatureLimitLiquid1 =
418 				le16_to_cpu(power_tune_table_v2->usTemperatureLimitLiquid1);
419 		tdp_table->usTemperatureLimitLiquid2 =
420 				le16_to_cpu(power_tune_table_v2->usTemperatureLimitLiquid2);
421 		tdp_table->usTemperatureLimitHBM =
422 				le16_to_cpu(power_tune_table_v2->usTemperatureLimitHBM);
423 		tdp_table->usTemperatureLimitVrVddc =
424 				le16_to_cpu(power_tune_table_v2->usTemperatureLimitVrSoc);
425 		tdp_table->usTemperatureLimitVrMvdd =
426 				le16_to_cpu(power_tune_table_v2->usTemperatureLimitVrMem);
427 		tdp_table->usTemperatureLimitPlx =
428 				le16_to_cpu(power_tune_table_v2->usTemperatureLimitPlx);
429 		tdp_table->ucLiquid1_I2C_address = power_tune_table_v2->ucLiquid1_I2C_address;
430 		tdp_table->ucLiquid2_I2C_address = power_tune_table_v2->ucLiquid2_I2C_address;
431 
432 		get_scl_sda_value(power_tune_table_v2->ucLiquid_I2C_Line, &scl, &sda);
433 
434 		tdp_table->ucLiquid_I2C_Line = scl;
435 		tdp_table->ucLiquid_I2C_LineSDA = sda;
436 
437 		tdp_table->ucVr_I2C_address = power_tune_table_v2->ucVr_I2C_address;
438 
439 		get_scl_sda_value(power_tune_table_v2->ucVr_I2C_Line, &scl, &sda);
440 
441 		tdp_table->ucVr_I2C_Line = scl;
442 		tdp_table->ucVr_I2C_LineSDA = sda;
443 		tdp_table->ucPlx_I2C_address = power_tune_table_v2->ucPlx_I2C_address;
444 
445 		get_scl_sda_value(power_tune_table_v2->ucPlx_I2C_Line, &scl, &sda);
446 
447 		tdp_table->ucPlx_I2C_Line = scl;
448 		tdp_table->ucPlx_I2C_LineSDA = sda;
449 
450 		hwmgr->platform_descriptor.LoadLineSlope =
451 					le16_to_cpu(power_tune_table_v2->usLoadLineResistance);
452 	} else {
453 		power_tune_table_v3 = (ATOM_Vega10_PowerTune_Table_V3 *)table;
454 		tdp_table->usMaximumPowerDeliveryLimit   = power_tune_table_v3->usSocketPowerLimit;
455 		tdp_table->usTDC                         = power_tune_table_v3->usTdcLimit;
456 		tdp_table->usEDCLimit                    = power_tune_table_v3->usEdcLimit;
457 		tdp_table->usSoftwareShutdownTemp        = power_tune_table_v3->usSoftwareShutdownTemp;
458 		tdp_table->usTemperatureLimitTedge       = power_tune_table_v3->usTemperatureLimitTedge;
459 		tdp_table->usTemperatureLimitHotspot     = power_tune_table_v3->usTemperatureLimitHotSpot;
460 		tdp_table->usTemperatureLimitLiquid1     = power_tune_table_v3->usTemperatureLimitLiquid1;
461 		tdp_table->usTemperatureLimitLiquid2     = power_tune_table_v3->usTemperatureLimitLiquid2;
462 		tdp_table->usTemperatureLimitHBM         = power_tune_table_v3->usTemperatureLimitHBM;
463 		tdp_table->usTemperatureLimitVrVddc      = power_tune_table_v3->usTemperatureLimitVrSoc;
464 		tdp_table->usTemperatureLimitVrMvdd      = power_tune_table_v3->usTemperatureLimitVrMem;
465 		tdp_table->usTemperatureLimitPlx         = power_tune_table_v3->usTemperatureLimitPlx;
466 		tdp_table->ucLiquid1_I2C_address         = power_tune_table_v3->ucLiquid1_I2C_address;
467 		tdp_table->ucLiquid2_I2C_address         = power_tune_table_v3->ucLiquid2_I2C_address;
468 		tdp_table->usBoostStartTemperature       = power_tune_table_v3->usBoostStartTemperature;
469 		tdp_table->usBoostStopTemperature        = power_tune_table_v3->usBoostStopTemperature;
470 		tdp_table->ulBoostClock                  = power_tune_table_v3->ulBoostClock;
471 
472 		get_scl_sda_value(power_tune_table_v3->ucLiquid_I2C_Line, &scl, &sda);
473 
474 		tdp_table->ucLiquid_I2C_Line             = scl;
475 		tdp_table->ucLiquid_I2C_LineSDA          = sda;
476 
477 		tdp_table->ucVr_I2C_address              = power_tune_table_v3->ucVr_I2C_address;
478 
479 		get_scl_sda_value(power_tune_table_v3->ucVr_I2C_Line, &scl, &sda);
480 
481 		tdp_table->ucVr_I2C_Line                 = scl;
482 		tdp_table->ucVr_I2C_LineSDA              = sda;
483 
484 		tdp_table->ucPlx_I2C_address             = power_tune_table_v3->ucPlx_I2C_address;
485 
486 		get_scl_sda_value(power_tune_table_v3->ucPlx_I2C_Line, &scl, &sda);
487 
488 		tdp_table->ucPlx_I2C_Line                = scl;
489 		tdp_table->ucPlx_I2C_LineSDA             = sda;
490 
491 		hwmgr->platform_descriptor.LoadLineSlope =
492 					le16_to_cpu(power_tune_table_v3->usLoadLineResistance);
493 	}
494 
495 	*info_tdp_table = tdp_table;
496 
497 	return 0;
498 }
499 
get_socclk_voltage_dependency_table(struct pp_hwmgr * hwmgr,phm_ppt_v1_clock_voltage_dependency_table ** pp_vega10_clk_dep_table,const ATOM_Vega10_SOCCLK_Dependency_Table * clk_dep_table)500 static int get_socclk_voltage_dependency_table(
501 		struct pp_hwmgr *hwmgr,
502 		phm_ppt_v1_clock_voltage_dependency_table **pp_vega10_clk_dep_table,
503 		const ATOM_Vega10_SOCCLK_Dependency_Table *clk_dep_table)
504 {
505 	uint32_t table_size, i;
506 	phm_ppt_v1_clock_voltage_dependency_table *clk_table;
507 
508 	PP_ASSERT_WITH_CODE(clk_dep_table->ucNumEntries,
509 		"Invalid PowerPlay Table!", return -1);
510 
511 	table_size = sizeof(uint32_t) +
512 			sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
513 			clk_dep_table->ucNumEntries;
514 
515 	clk_table = kzalloc(table_size, GFP_KERNEL);
516 
517 	if (!clk_table)
518 		return -ENOMEM;
519 
520 	clk_table->count = (uint32_t)clk_dep_table->ucNumEntries;
521 
522 	for (i = 0; i < clk_dep_table->ucNumEntries; i++) {
523 		clk_table->entries[i].vddInd =
524 				clk_dep_table->entries[i].ucVddInd;
525 		clk_table->entries[i].clk =
526 				le32_to_cpu(clk_dep_table->entries[i].ulClk);
527 	}
528 
529 	*pp_vega10_clk_dep_table = clk_table;
530 
531 	return 0;
532 }
533 
get_mclk_voltage_dependency_table(struct pp_hwmgr * hwmgr,phm_ppt_v1_clock_voltage_dependency_table ** pp_vega10_mclk_dep_table,const ATOM_Vega10_MCLK_Dependency_Table * mclk_dep_table)534 static int get_mclk_voltage_dependency_table(
535 		struct pp_hwmgr *hwmgr,
536 		phm_ppt_v1_clock_voltage_dependency_table **pp_vega10_mclk_dep_table,
537 		const ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table)
538 {
539 	uint32_t table_size, i;
540 	phm_ppt_v1_clock_voltage_dependency_table *mclk_table;
541 
542 	PP_ASSERT_WITH_CODE(mclk_dep_table->ucNumEntries,
543 		"Invalid PowerPlay Table!", return -1);
544 
545 	table_size = sizeof(uint32_t) +
546 			sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
547 			mclk_dep_table->ucNumEntries;
548 
549 	mclk_table = kzalloc(table_size, GFP_KERNEL);
550 
551 	if (!mclk_table)
552 		return -ENOMEM;
553 
554 	mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries;
555 
556 	for (i = 0; i < mclk_dep_table->ucNumEntries; i++) {
557 		mclk_table->entries[i].vddInd =
558 				mclk_dep_table->entries[i].ucVddInd;
559 		mclk_table->entries[i].vddciInd =
560 				mclk_dep_table->entries[i].ucVddciInd;
561 		mclk_table->entries[i].mvddInd =
562 				mclk_dep_table->entries[i].ucVddMemInd;
563 		mclk_table->entries[i].clk =
564 				le32_to_cpu(mclk_dep_table->entries[i].ulMemClk);
565 	}
566 
567 	*pp_vega10_mclk_dep_table = mclk_table;
568 
569 	return 0;
570 }
571 
get_gfxclk_voltage_dependency_table(struct pp_hwmgr * hwmgr,struct phm_ppt_v1_clock_voltage_dependency_table ** pp_vega10_clk_dep_table,const ATOM_Vega10_GFXCLK_Dependency_Table * clk_dep_table)572 static int get_gfxclk_voltage_dependency_table(
573 		struct pp_hwmgr *hwmgr,
574 		struct phm_ppt_v1_clock_voltage_dependency_table
575 			**pp_vega10_clk_dep_table,
576 		const ATOM_Vega10_GFXCLK_Dependency_Table *clk_dep_table)
577 {
578 	uint32_t table_size, i;
579 	struct phm_ppt_v1_clock_voltage_dependency_table
580 				*clk_table;
581 	ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_v2;
582 
583 	PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
584 			"Invalid PowerPlay Table!", return -1);
585 
586 	table_size = sizeof(uint32_t) +
587 			sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
588 			clk_dep_table->ucNumEntries;
589 
590 	clk_table = kzalloc(table_size, GFP_KERNEL);
591 
592 	if (!clk_table)
593 		return -ENOMEM;
594 
595 	clk_table->count = clk_dep_table->ucNumEntries;
596 
597 	if (clk_dep_table->ucRevId == 0) {
598 		for (i = 0; i < clk_table->count; i++) {
599 			clk_table->entries[i].vddInd =
600 				clk_dep_table->entries[i].ucVddInd;
601 			clk_table->entries[i].clk =
602 				le32_to_cpu(clk_dep_table->entries[i].ulClk);
603 			clk_table->entries[i].cks_enable =
604 				(((le16_to_cpu(clk_dep_table->entries[i].usCKSVOffsetandDisable) & 0x8000)
605 						>> 15) == 0) ? 1 : 0;
606 			clk_table->entries[i].cks_voffset =
607 				le16_to_cpu(clk_dep_table->entries[i].usCKSVOffsetandDisable) & 0x7F;
608 			clk_table->entries[i].sclk_offset =
609 				le16_to_cpu(clk_dep_table->entries[i].usAVFSOffset);
610 		}
611 	} else if (clk_dep_table->ucRevId == 1) {
612 		patom_record_v2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)clk_dep_table->entries;
613 		for (i = 0; i < clk_table->count; i++) {
614 			clk_table->entries[i].vddInd =
615 					patom_record_v2->ucVddInd;
616 			clk_table->entries[i].clk =
617 					le32_to_cpu(patom_record_v2->ulClk);
618 			clk_table->entries[i].cks_enable =
619 					(((le16_to_cpu(patom_record_v2->usCKSVOffsetandDisable) & 0x8000)
620 							>> 15) == 0) ? 1 : 0;
621 			clk_table->entries[i].cks_voffset =
622 					le16_to_cpu(patom_record_v2->usCKSVOffsetandDisable) & 0x7F;
623 			clk_table->entries[i].sclk_offset =
624 					le16_to_cpu(patom_record_v2->usAVFSOffset);
625 			patom_record_v2++;
626 		}
627 	} else {
628 		kfree(clk_table);
629 		PP_ASSERT_WITH_CODE(false,
630 			"Unsupported GFXClockDependencyTable Revision!",
631 			return -EINVAL);
632 	}
633 
634 	*pp_vega10_clk_dep_table = clk_table;
635 
636 	return 0;
637 }
638 
get_pix_clk_voltage_dependency_table(struct pp_hwmgr * hwmgr,struct phm_ppt_v1_clock_voltage_dependency_table ** pp_vega10_clk_dep_table,const ATOM_Vega10_PIXCLK_Dependency_Table * clk_dep_table)639 static int get_pix_clk_voltage_dependency_table(
640 		struct pp_hwmgr *hwmgr,
641 		struct phm_ppt_v1_clock_voltage_dependency_table
642 			**pp_vega10_clk_dep_table,
643 		const  ATOM_Vega10_PIXCLK_Dependency_Table *clk_dep_table)
644 {
645 	uint32_t table_size, i;
646 	struct phm_ppt_v1_clock_voltage_dependency_table
647 				*clk_table;
648 
649 	PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
650 			"Invalid PowerPlay Table!", return -1);
651 
652 	table_size = sizeof(uint32_t) +
653 			sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
654 			clk_dep_table->ucNumEntries;
655 
656 	clk_table = kzalloc(table_size, GFP_KERNEL);
657 
658 	if (!clk_table)
659 		return -ENOMEM;
660 
661 	clk_table->count = clk_dep_table->ucNumEntries;
662 
663 	for (i = 0; i < clk_table->count; i++) {
664 		clk_table->entries[i].vddInd =
665 				clk_dep_table->entries[i].ucVddInd;
666 		clk_table->entries[i].clk =
667 				le32_to_cpu(clk_dep_table->entries[i].ulClk);
668 	}
669 
670 	*pp_vega10_clk_dep_table = clk_table;
671 
672 	return 0;
673 }
674 
get_dcefclk_voltage_dependency_table(struct pp_hwmgr * hwmgr,struct phm_ppt_v1_clock_voltage_dependency_table ** pp_vega10_clk_dep_table,const ATOM_Vega10_DCEFCLK_Dependency_Table * clk_dep_table)675 static int get_dcefclk_voltage_dependency_table(
676 		struct pp_hwmgr *hwmgr,
677 		struct phm_ppt_v1_clock_voltage_dependency_table
678 			**pp_vega10_clk_dep_table,
679 		const ATOM_Vega10_DCEFCLK_Dependency_Table *clk_dep_table)
680 {
681 	uint32_t table_size, i;
682 	uint8_t num_entries;
683 	struct phm_ppt_v1_clock_voltage_dependency_table
684 				*clk_table;
685 	uint32_t dev_id;
686 	uint32_t rev_id;
687 	struct amdgpu_device *adev = hwmgr->adev;
688 
689 	PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
690 			"Invalid PowerPlay Table!", return -1);
691 
692 /*
693  * workaround needed to add another DPM level for pioneer cards
694  * as VBIOS is locked down.
695  * This DPM level was added to support 3DPM monitors @ 4K120Hz
696  *
697  */
698 	dev_id = adev->pdev->device;
699 	rev_id = adev->pdev->revision;
700 
701 	if (dev_id == 0x6863 && rev_id == 0 &&
702 		clk_dep_table->entries[clk_dep_table->ucNumEntries - 1].ulClk < 90000)
703 		num_entries = clk_dep_table->ucNumEntries + 1 > NUM_DSPCLK_LEVELS ?
704 				NUM_DSPCLK_LEVELS : clk_dep_table->ucNumEntries + 1;
705 	else
706 		num_entries = clk_dep_table->ucNumEntries;
707 
708 
709 	table_size = sizeof(uint32_t) +
710 			sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
711 			num_entries;
712 
713 	clk_table = kzalloc(table_size, GFP_KERNEL);
714 
715 	if (!clk_table)
716 		return -ENOMEM;
717 
718 	clk_table->count = (uint32_t)num_entries;
719 
720 	for (i = 0; i < clk_dep_table->ucNumEntries; i++) {
721 		clk_table->entries[i].vddInd =
722 				clk_dep_table->entries[i].ucVddInd;
723 		clk_table->entries[i].clk =
724 				le32_to_cpu(clk_dep_table->entries[i].ulClk);
725 	}
726 
727 	if (i < num_entries) {
728 		clk_table->entries[i].vddInd = clk_dep_table->entries[i-1].ucVddInd;
729 		clk_table->entries[i].clk = 90000;
730 	}
731 
732 	*pp_vega10_clk_dep_table = clk_table;
733 
734 	return 0;
735 }
736 
get_pcie_table(struct pp_hwmgr * hwmgr,struct phm_ppt_v1_pcie_table ** vega10_pcie_table,const Vega10_PPTable_Generic_SubTable_Header * table)737 static int get_pcie_table(struct pp_hwmgr *hwmgr,
738 		struct phm_ppt_v1_pcie_table **vega10_pcie_table,
739 		const Vega10_PPTable_Generic_SubTable_Header *table)
740 {
741 	uint32_t table_size, i, pcie_count;
742 	struct phm_ppt_v1_pcie_table *pcie_table;
743 	struct phm_ppt_v2_information *table_info =
744 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
745 	const ATOM_Vega10_PCIE_Table *atom_pcie_table =
746 			(ATOM_Vega10_PCIE_Table *)table;
747 
748 	PP_ASSERT_WITH_CODE(atom_pcie_table->ucNumEntries,
749 			"Invalid PowerPlay Table!",
750 			return 0);
751 
752 	table_size = sizeof(uint32_t) +
753 			sizeof(struct phm_ppt_v1_pcie_record) *
754 			atom_pcie_table->ucNumEntries;
755 
756 	pcie_table = kzalloc(table_size, GFP_KERNEL);
757 
758 	if (!pcie_table)
759 		return -ENOMEM;
760 
761 	pcie_count = table_info->vdd_dep_on_sclk->count;
762 	if (atom_pcie_table->ucNumEntries <= pcie_count)
763 		pcie_count = atom_pcie_table->ucNumEntries;
764 	else
765 		pr_info("Number of Pcie Entries exceed the number of"
766 				" GFXCLK Dpm Levels!"
767 				" Disregarding the excess entries...\n");
768 
769 	pcie_table->count = pcie_count;
770 
771 	for (i = 0; i < pcie_count; i++) {
772 		pcie_table->entries[i].gen_speed =
773 				atom_pcie_table->entries[i].ucPCIEGenSpeed;
774 		pcie_table->entries[i].lane_width =
775 				atom_pcie_table->entries[i].ucPCIELaneWidth;
776 		pcie_table->entries[i].pcie_sclk =
777 				atom_pcie_table->entries[i].ulLCLK;
778 	}
779 
780 	*vega10_pcie_table = pcie_table;
781 
782 	return 0;
783 }
784 
get_hard_limits(struct pp_hwmgr * hwmgr,struct phm_clock_and_voltage_limits * limits,const ATOM_Vega10_Hard_Limit_Table * limit_table)785 static int get_hard_limits(
786 		struct pp_hwmgr *hwmgr,
787 		struct phm_clock_and_voltage_limits *limits,
788 		const ATOM_Vega10_Hard_Limit_Table *limit_table)
789 {
790 	PP_ASSERT_WITH_CODE(limit_table->ucNumEntries,
791 			"Invalid PowerPlay Table!", return -1);
792 
793 	/* currently we always take entries[0] parameters */
794 	limits->sclk = le32_to_cpu(limit_table->entries[0].ulSOCCLKLimit);
795 	limits->mclk = le32_to_cpu(limit_table->entries[0].ulMCLKLimit);
796 	limits->gfxclk = le32_to_cpu(limit_table->entries[0].ulGFXCLKLimit);
797 	limits->vddc = le16_to_cpu(limit_table->entries[0].usVddcLimit);
798 	limits->vddci = le16_to_cpu(limit_table->entries[0].usVddciLimit);
799 	limits->vddmem = le16_to_cpu(limit_table->entries[0].usVddMemLimit);
800 
801 	return 0;
802 }
803 
get_valid_clk(struct pp_hwmgr * hwmgr,struct phm_clock_array ** clk_table,const phm_ppt_v1_clock_voltage_dependency_table * clk_volt_pp_table)804 static int get_valid_clk(
805 		struct pp_hwmgr *hwmgr,
806 		struct phm_clock_array **clk_table,
807 		const phm_ppt_v1_clock_voltage_dependency_table *clk_volt_pp_table)
808 {
809 	uint32_t table_size, i;
810 	struct phm_clock_array *table;
811 
812 	PP_ASSERT_WITH_CODE(clk_volt_pp_table->count,
813 			"Invalid PowerPlay Table!", return -1);
814 
815 	table_size = sizeof(uint32_t) +
816 			sizeof(uint32_t) * clk_volt_pp_table->count;
817 
818 	table = kzalloc(table_size, GFP_KERNEL);
819 
820 	if (!table)
821 		return -ENOMEM;
822 
823 	table->count = (uint32_t)clk_volt_pp_table->count;
824 
825 	for (i = 0; i < table->count; i++)
826 		table->values[i] = (uint32_t)clk_volt_pp_table->entries[i].clk;
827 
828 	*clk_table = table;
829 
830 	return 0;
831 }
832 
init_powerplay_extended_tables(struct pp_hwmgr * hwmgr,const ATOM_Vega10_POWERPLAYTABLE * powerplay_table)833 static int init_powerplay_extended_tables(
834 		struct pp_hwmgr *hwmgr,
835 		const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
836 {
837 	int result = 0;
838 	struct phm_ppt_v2_information *pp_table_info =
839 		(struct phm_ppt_v2_information *)(hwmgr->pptable);
840 
841 	const ATOM_Vega10_MM_Dependency_Table *mm_dependency_table =
842 			(const ATOM_Vega10_MM_Dependency_Table *)
843 			(((unsigned long) powerplay_table) +
844 			le16_to_cpu(powerplay_table->usMMDependencyTableOffset));
845 	const Vega10_PPTable_Generic_SubTable_Header *power_tune_table =
846 			(const Vega10_PPTable_Generic_SubTable_Header *)
847 			(((unsigned long) powerplay_table) +
848 			le16_to_cpu(powerplay_table->usPowerTuneTableOffset));
849 	const ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table =
850 			(const ATOM_Vega10_SOCCLK_Dependency_Table *)
851 			(((unsigned long) powerplay_table) +
852 			le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset));
853 	const ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
854 			(const ATOM_Vega10_GFXCLK_Dependency_Table *)
855 			(((unsigned long) powerplay_table) +
856 			le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
857 	const ATOM_Vega10_DCEFCLK_Dependency_Table *dcefclk_dep_table =
858 			(const ATOM_Vega10_DCEFCLK_Dependency_Table *)
859 			(((unsigned long) powerplay_table) +
860 			le16_to_cpu(powerplay_table->usDcefclkDependencyTableOffset));
861 	const ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table =
862 			(const ATOM_Vega10_MCLK_Dependency_Table *)
863 			(((unsigned long) powerplay_table) +
864 			le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
865 	const ATOM_Vega10_Hard_Limit_Table *hard_limits =
866 			(const ATOM_Vega10_Hard_Limit_Table *)
867 			(((unsigned long) powerplay_table) +
868 			le16_to_cpu(powerplay_table->usHardLimitTableOffset));
869 	const Vega10_PPTable_Generic_SubTable_Header *pcie_table =
870 			(const Vega10_PPTable_Generic_SubTable_Header *)
871 			(((unsigned long) powerplay_table) +
872 			le16_to_cpu(powerplay_table->usPCIETableOffset));
873 	const ATOM_Vega10_PIXCLK_Dependency_Table *pixclk_dep_table =
874 			(const ATOM_Vega10_PIXCLK_Dependency_Table *)
875 			(((unsigned long) powerplay_table) +
876 			le16_to_cpu(powerplay_table->usPixclkDependencyTableOffset));
877 	const ATOM_Vega10_PHYCLK_Dependency_Table *phyclk_dep_table =
878 			(const ATOM_Vega10_PHYCLK_Dependency_Table *)
879 			(((unsigned long) powerplay_table) +
880 			le16_to_cpu(powerplay_table->usPhyClkDependencyTableOffset));
881 	const ATOM_Vega10_DISPCLK_Dependency_Table *dispclk_dep_table =
882 			(const ATOM_Vega10_DISPCLK_Dependency_Table *)
883 			(((unsigned long) powerplay_table) +
884 			le16_to_cpu(powerplay_table->usDispClkDependencyTableOffset));
885 
886 	pp_table_info->vdd_dep_on_socclk = NULL;
887 	pp_table_info->vdd_dep_on_sclk = NULL;
888 	pp_table_info->vdd_dep_on_mclk = NULL;
889 	pp_table_info->vdd_dep_on_dcefclk = NULL;
890 	pp_table_info->mm_dep_table = NULL;
891 	pp_table_info->tdp_table = NULL;
892 	pp_table_info->vdd_dep_on_pixclk = NULL;
893 	pp_table_info->vdd_dep_on_phyclk = NULL;
894 	pp_table_info->vdd_dep_on_dispclk = NULL;
895 
896 	if (powerplay_table->usMMDependencyTableOffset)
897 		result = get_mm_clock_voltage_table(hwmgr,
898 				&pp_table_info->mm_dep_table,
899 				mm_dependency_table);
900 
901 	if (!result && powerplay_table->usPowerTuneTableOffset)
902 		result = get_tdp_table(hwmgr,
903 				&pp_table_info->tdp_table,
904 				power_tune_table);
905 
906 	if (!result && powerplay_table->usSocclkDependencyTableOffset)
907 		result = get_socclk_voltage_dependency_table(hwmgr,
908 				&pp_table_info->vdd_dep_on_socclk,
909 				socclk_dep_table);
910 
911 	if (!result && powerplay_table->usGfxclkDependencyTableOffset)
912 		result = get_gfxclk_voltage_dependency_table(hwmgr,
913 				&pp_table_info->vdd_dep_on_sclk,
914 				gfxclk_dep_table);
915 
916 	if (!result && powerplay_table->usPixclkDependencyTableOffset)
917 		result = get_pix_clk_voltage_dependency_table(hwmgr,
918 				&pp_table_info->vdd_dep_on_pixclk,
919 				(const ATOM_Vega10_PIXCLK_Dependency_Table*)
920 				pixclk_dep_table);
921 
922 	if (!result && powerplay_table->usPhyClkDependencyTableOffset)
923 		result = get_pix_clk_voltage_dependency_table(hwmgr,
924 				&pp_table_info->vdd_dep_on_phyclk,
925 				(const ATOM_Vega10_PIXCLK_Dependency_Table *)
926 				phyclk_dep_table);
927 
928 	if (!result && powerplay_table->usDispClkDependencyTableOffset)
929 		result = get_pix_clk_voltage_dependency_table(hwmgr,
930 				&pp_table_info->vdd_dep_on_dispclk,
931 				(const ATOM_Vega10_PIXCLK_Dependency_Table *)
932 				dispclk_dep_table);
933 
934 	if (!result && powerplay_table->usDcefclkDependencyTableOffset)
935 		result = get_dcefclk_voltage_dependency_table(hwmgr,
936 				&pp_table_info->vdd_dep_on_dcefclk,
937 				dcefclk_dep_table);
938 
939 	if (!result && powerplay_table->usMclkDependencyTableOffset)
940 		result = get_mclk_voltage_dependency_table(hwmgr,
941 				&pp_table_info->vdd_dep_on_mclk,
942 				mclk_dep_table);
943 
944 	if (!result && powerplay_table->usPCIETableOffset)
945 		result = get_pcie_table(hwmgr,
946 				&pp_table_info->pcie_table,
947 				pcie_table);
948 
949 	if (!result && powerplay_table->usHardLimitTableOffset)
950 		result = get_hard_limits(hwmgr,
951 				&pp_table_info->max_clock_voltage_on_dc,
952 				hard_limits);
953 
954 	hwmgr->dyn_state.max_clock_voltage_on_dc.sclk =
955 			pp_table_info->max_clock_voltage_on_dc.sclk;
956 	hwmgr->dyn_state.max_clock_voltage_on_dc.mclk =
957 			pp_table_info->max_clock_voltage_on_dc.mclk;
958 	hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
959 			pp_table_info->max_clock_voltage_on_dc.vddc;
960 	hwmgr->dyn_state.max_clock_voltage_on_dc.vddci =
961 			pp_table_info->max_clock_voltage_on_dc.vddci;
962 
963 	if (!result &&
964 		pp_table_info->vdd_dep_on_socclk &&
965 		pp_table_info->vdd_dep_on_socclk->count)
966 		result = get_valid_clk(hwmgr,
967 				&pp_table_info->valid_socclk_values,
968 				pp_table_info->vdd_dep_on_socclk);
969 
970 	if (!result &&
971 		pp_table_info->vdd_dep_on_sclk &&
972 		pp_table_info->vdd_dep_on_sclk->count)
973 		result = get_valid_clk(hwmgr,
974 				&pp_table_info->valid_sclk_values,
975 				pp_table_info->vdd_dep_on_sclk);
976 
977 	if (!result &&
978 		pp_table_info->vdd_dep_on_dcefclk &&
979 		pp_table_info->vdd_dep_on_dcefclk->count)
980 		result = get_valid_clk(hwmgr,
981 				&pp_table_info->valid_dcefclk_values,
982 				pp_table_info->vdd_dep_on_dcefclk);
983 
984 	if (!result &&
985 		pp_table_info->vdd_dep_on_mclk &&
986 		pp_table_info->vdd_dep_on_mclk->count)
987 		result = get_valid_clk(hwmgr,
988 				&pp_table_info->valid_mclk_values,
989 				pp_table_info->vdd_dep_on_mclk);
990 
991 	return result;
992 }
993 
get_vddc_lookup_table(struct pp_hwmgr * hwmgr,phm_ppt_v1_voltage_lookup_table ** lookup_table,const ATOM_Vega10_Voltage_Lookup_Table * vddc_lookup_pp_tables,uint32_t max_levels)994 static int get_vddc_lookup_table(
995 		struct pp_hwmgr	*hwmgr,
996 		phm_ppt_v1_voltage_lookup_table	**lookup_table,
997 		const ATOM_Vega10_Voltage_Lookup_Table *vddc_lookup_pp_tables,
998 		uint32_t max_levels)
999 {
1000 	uint32_t table_size, i;
1001 	phm_ppt_v1_voltage_lookup_table *table;
1002 
1003 	PP_ASSERT_WITH_CODE((vddc_lookup_pp_tables->ucNumEntries != 0),
1004 			"Invalid SOC_VDDD Lookup Table!", return 1);
1005 
1006 	table_size = sizeof(uint32_t) +
1007 			sizeof(phm_ppt_v1_voltage_lookup_record) * max_levels;
1008 
1009 	table = kzalloc(table_size, GFP_KERNEL);
1010 
1011 	if (table == NULL)
1012 		return -ENOMEM;
1013 
1014 	table->count = vddc_lookup_pp_tables->ucNumEntries;
1015 
1016 	for (i = 0; i < vddc_lookup_pp_tables->ucNumEntries; i++)
1017 		table->entries[i].us_vdd =
1018 				le16_to_cpu(vddc_lookup_pp_tables->entries[i].usVdd);
1019 
1020 	*lookup_table = table;
1021 
1022 	return 0;
1023 }
1024 
init_dpm_2_parameters(struct pp_hwmgr * hwmgr,const ATOM_Vega10_POWERPLAYTABLE * powerplay_table)1025 static int init_dpm_2_parameters(
1026 		struct pp_hwmgr *hwmgr,
1027 		const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
1028 {
1029 	int result = 0;
1030 	struct phm_ppt_v2_information *pp_table_info =
1031 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
1032 	uint32_t disable_power_control = 0;
1033 
1034 	pp_table_info->us_ulv_voltage_offset =
1035 		le16_to_cpu(powerplay_table->usUlvVoltageOffset);
1036 
1037 	pp_table_info->us_ulv_smnclk_did =
1038 			le16_to_cpu(powerplay_table->usUlvSmnclkDid);
1039 	pp_table_info->us_ulv_mp1clk_did =
1040 			le16_to_cpu(powerplay_table->usUlvMp1clkDid);
1041 	pp_table_info->us_ulv_gfxclk_bypass =
1042 			le16_to_cpu(powerplay_table->usUlvGfxclkBypass);
1043 	pp_table_info->us_gfxclk_slew_rate =
1044 			le16_to_cpu(powerplay_table->usGfxclkSlewRate);
1045 	pp_table_info->uc_gfx_dpm_voltage_mode  =
1046 			le16_to_cpu(powerplay_table->ucGfxVoltageMode);
1047 	pp_table_info->uc_soc_dpm_voltage_mode  =
1048 			le16_to_cpu(powerplay_table->ucSocVoltageMode);
1049 	pp_table_info->uc_uclk_dpm_voltage_mode =
1050 			le16_to_cpu(powerplay_table->ucUclkVoltageMode);
1051 	pp_table_info->uc_uvd_dpm_voltage_mode  =
1052 			le16_to_cpu(powerplay_table->ucUvdVoltageMode);
1053 	pp_table_info->uc_vce_dpm_voltage_mode  =
1054 			le16_to_cpu(powerplay_table->ucVceVoltageMode);
1055 	pp_table_info->uc_mp0_dpm_voltage_mode  =
1056 			le16_to_cpu(powerplay_table->ucMp0VoltageMode);
1057 	pp_table_info->uc_dcef_dpm_voltage_mode =
1058 			le16_to_cpu(powerplay_table->ucDcefVoltageMode);
1059 
1060 	pp_table_info->ppm_parameter_table = NULL;
1061 	pp_table_info->vddc_lookup_table = NULL;
1062 	pp_table_info->vddmem_lookup_table = NULL;
1063 	pp_table_info->vddci_lookup_table = NULL;
1064 
1065 	/* TDP limits */
1066 	hwmgr->platform_descriptor.TDPODLimit =
1067 		le16_to_cpu(powerplay_table->usPowerControlLimit);
1068 	hwmgr->platform_descriptor.TDPAdjustment = 0;
1069 	hwmgr->platform_descriptor.VidAdjustment = 0;
1070 	hwmgr->platform_descriptor.VidAdjustmentPolarity = 0;
1071 	hwmgr->platform_descriptor.VidMinLimit = 0;
1072 	hwmgr->platform_descriptor.VidMaxLimit = 1500000;
1073 	hwmgr->platform_descriptor.VidStep = 6250;
1074 
1075 	disable_power_control = 0;
1076 	if (!disable_power_control) {
1077 		/* enable TDP overdrive (PowerControl) feature as well if supported */
1078 		if (hwmgr->platform_descriptor.TDPODLimit)
1079 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1080 			PHM_PlatformCaps_PowerControl);
1081 	}
1082 
1083 	if (powerplay_table->usVddcLookupTableOffset) {
1084 		const ATOM_Vega10_Voltage_Lookup_Table *vddc_table =
1085 				(ATOM_Vega10_Voltage_Lookup_Table *)
1086 				(((unsigned long)powerplay_table) +
1087 				le16_to_cpu(powerplay_table->usVddcLookupTableOffset));
1088 		result = get_vddc_lookup_table(hwmgr,
1089 				&pp_table_info->vddc_lookup_table, vddc_table, 8);
1090 	}
1091 
1092 	if (powerplay_table->usVddmemLookupTableOffset) {
1093 		const ATOM_Vega10_Voltage_Lookup_Table *vdd_mem_table =
1094 				(ATOM_Vega10_Voltage_Lookup_Table *)
1095 				(((unsigned long)powerplay_table) +
1096 				le16_to_cpu(powerplay_table->usVddmemLookupTableOffset));
1097 		result = get_vddc_lookup_table(hwmgr,
1098 				&pp_table_info->vddmem_lookup_table, vdd_mem_table, 4);
1099 	}
1100 
1101 	if (powerplay_table->usVddciLookupTableOffset) {
1102 		const ATOM_Vega10_Voltage_Lookup_Table *vddci_table =
1103 				(ATOM_Vega10_Voltage_Lookup_Table *)
1104 				(((unsigned long)powerplay_table) +
1105 				le16_to_cpu(powerplay_table->usVddciLookupTableOffset));
1106 		result = get_vddc_lookup_table(hwmgr,
1107 				&pp_table_info->vddci_lookup_table, vddci_table, 4);
1108 	}
1109 
1110 	return result;
1111 }
1112 
vega10_pp_tables_initialize(struct pp_hwmgr * hwmgr)1113 int vega10_pp_tables_initialize(struct pp_hwmgr *hwmgr)
1114 {
1115 	int result = 0;
1116 	const ATOM_Vega10_POWERPLAYTABLE *powerplay_table;
1117 
1118 	hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v2_information), GFP_KERNEL);
1119 
1120 	PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
1121 			    "Failed to allocate hwmgr->pptable!", return -ENOMEM);
1122 
1123 	powerplay_table = get_powerplay_table(hwmgr);
1124 
1125 	PP_ASSERT_WITH_CODE((powerplay_table != NULL),
1126 		"Missing PowerPlay Table!", return -1);
1127 
1128 	result = check_powerplay_tables(hwmgr, powerplay_table);
1129 
1130 	PP_ASSERT_WITH_CODE((result == 0),
1131 			    "check_powerplay_tables failed", return result);
1132 
1133 	result = set_platform_caps(hwmgr,
1134 				   le32_to_cpu(powerplay_table->ulPlatformCaps));
1135 
1136 	PP_ASSERT_WITH_CODE((result == 0),
1137 			    "set_platform_caps failed", return result);
1138 
1139 	result = init_thermal_controller(hwmgr, powerplay_table);
1140 
1141 	PP_ASSERT_WITH_CODE((result == 0),
1142 			    "init_thermal_controller failed", return result);
1143 
1144 	result = init_over_drive_limits(hwmgr, powerplay_table);
1145 
1146 	PP_ASSERT_WITH_CODE((result == 0),
1147 			    "init_over_drive_limits failed", return result);
1148 
1149 	result = init_powerplay_extended_tables(hwmgr, powerplay_table);
1150 
1151 	PP_ASSERT_WITH_CODE((result == 0),
1152 			    "init_powerplay_extended_tables failed", return result);
1153 
1154 	result = init_dpm_2_parameters(hwmgr, powerplay_table);
1155 
1156 	PP_ASSERT_WITH_CODE((result == 0),
1157 			    "init_dpm_2_parameters failed", return result);
1158 
1159 	return result;
1160 }
1161 
vega10_pp_tables_uninitialize(struct pp_hwmgr * hwmgr)1162 static int vega10_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
1163 {
1164 	struct phm_ppt_v2_information *pp_table_info =
1165 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
1166 
1167 	kfree(pp_table_info->vdd_dep_on_sclk);
1168 	pp_table_info->vdd_dep_on_sclk = NULL;
1169 
1170 	kfree(pp_table_info->vdd_dep_on_mclk);
1171 	pp_table_info->vdd_dep_on_mclk = NULL;
1172 
1173 	kfree(pp_table_info->valid_mclk_values);
1174 	pp_table_info->valid_mclk_values = NULL;
1175 
1176 	kfree(pp_table_info->valid_sclk_values);
1177 	pp_table_info->valid_sclk_values = NULL;
1178 
1179 	kfree(pp_table_info->vddc_lookup_table);
1180 	pp_table_info->vddc_lookup_table = NULL;
1181 
1182 	kfree(pp_table_info->vddmem_lookup_table);
1183 	pp_table_info->vddmem_lookup_table = NULL;
1184 
1185 	kfree(pp_table_info->vddci_lookup_table);
1186 	pp_table_info->vddci_lookup_table = NULL;
1187 
1188 	kfree(pp_table_info->ppm_parameter_table);
1189 	pp_table_info->ppm_parameter_table = NULL;
1190 
1191 	kfree(pp_table_info->mm_dep_table);
1192 	pp_table_info->mm_dep_table = NULL;
1193 
1194 	kfree(pp_table_info->cac_dtp_table);
1195 	pp_table_info->cac_dtp_table = NULL;
1196 
1197 	kfree(hwmgr->dyn_state.cac_dtp_table);
1198 	hwmgr->dyn_state.cac_dtp_table = NULL;
1199 
1200 	kfree(pp_table_info->tdp_table);
1201 	pp_table_info->tdp_table = NULL;
1202 
1203 	kfree(hwmgr->pptable);
1204 	hwmgr->pptable = NULL;
1205 
1206 	return 0;
1207 }
1208 
1209 const struct pp_table_func vega10_pptable_funcs = {
1210 	.pptable_init = vega10_pp_tables_initialize,
1211 	.pptable_fini = vega10_pp_tables_uninitialize,
1212 };
1213 
vega10_get_number_of_powerplay_table_entries(struct pp_hwmgr * hwmgr)1214 int vega10_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr)
1215 {
1216 	const ATOM_Vega10_State_Array *state_arrays;
1217 	const ATOM_Vega10_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
1218 
1219 	PP_ASSERT_WITH_CODE((pp_table != NULL),
1220 			"Missing PowerPlay Table!", return -1);
1221 	PP_ASSERT_WITH_CODE((pp_table->sHeader.format_revision >=
1222 			ATOM_Vega10_TABLE_REVISION_VEGA10),
1223 			"Incorrect PowerPlay table revision!", return -1);
1224 
1225 	state_arrays = (ATOM_Vega10_State_Array *)(((unsigned long)pp_table) +
1226 			le16_to_cpu(pp_table->usStateArrayOffset));
1227 
1228 	return (uint32_t)(state_arrays->ucNumEntries);
1229 }
1230 
make_classification_flags(struct pp_hwmgr * hwmgr,uint16_t classification,uint16_t classification2)1231 static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,
1232 		uint16_t classification, uint16_t classification2)
1233 {
1234 	uint32_t result = 0;
1235 
1236 	if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT)
1237 		result |= PP_StateClassificationFlag_Boot;
1238 
1239 	if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1240 		result |= PP_StateClassificationFlag_Thermal;
1241 
1242 	if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
1243 		result |= PP_StateClassificationFlag_LimitedPowerSource;
1244 
1245 	if (classification & ATOM_PPLIB_CLASSIFICATION_REST)
1246 		result |= PP_StateClassificationFlag_Rest;
1247 
1248 	if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED)
1249 		result |= PP_StateClassificationFlag_Forced;
1250 
1251 	if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI)
1252 		result |= PP_StateClassificationFlag_ACPI;
1253 
1254 	if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
1255 		result |= PP_StateClassificationFlag_LimitedPowerSource_2;
1256 
1257 	return result;
1258 }
1259 
vega10_get_powerplay_table_entry(struct pp_hwmgr * hwmgr,uint32_t entry_index,struct pp_power_state * power_state,int (* call_back_func)(struct pp_hwmgr *,void *,struct pp_power_state *,void *,uint32_t))1260 int vega10_get_powerplay_table_entry(struct pp_hwmgr *hwmgr,
1261 		uint32_t entry_index, struct pp_power_state *power_state,
1262 		int (*call_back_func)(struct pp_hwmgr *, void *,
1263 				struct pp_power_state *, void *, uint32_t))
1264 {
1265 	int result = 0;
1266 	const ATOM_Vega10_State_Array *state_arrays;
1267 	const ATOM_Vega10_State *state_entry;
1268 	const ATOM_Vega10_POWERPLAYTABLE *pp_table =
1269 			get_powerplay_table(hwmgr);
1270 
1271 	PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!",
1272 			return -1;);
1273 	power_state->classification.bios_index = entry_index;
1274 
1275 	if (pp_table->sHeader.format_revision >=
1276 			ATOM_Vega10_TABLE_REVISION_VEGA10) {
1277 		state_arrays = (ATOM_Vega10_State_Array *)
1278 				(((unsigned long)pp_table) +
1279 				le16_to_cpu(pp_table->usStateArrayOffset));
1280 
1281 		PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0,
1282 				"Invalid PowerPlay Table State Array Offset.",
1283 				return -1);
1284 		PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,
1285 				"Invalid PowerPlay Table State Array.",
1286 				return -1);
1287 		PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),
1288 				"Invalid PowerPlay Table State Array Entry.",
1289 				return -1);
1290 
1291 		state_entry = &(state_arrays->states[entry_index]);
1292 
1293 		result = call_back_func(hwmgr, (void *)state_entry, power_state,
1294 				(void *)pp_table,
1295 				make_classification_flags(hwmgr,
1296 					le16_to_cpu(state_entry->usClassification),
1297 					le16_to_cpu(state_entry->usClassification2)));
1298 	}
1299 
1300 	if (!result && (power_state->classification.flags &
1301 			PP_StateClassificationFlag_Boot))
1302 		result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
1303 
1304 	return result;
1305 }
1306