1 /*
2 * Copyright © 2006-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 *
27 */
28
29 /** @file
30 * Integrated TV-out support for the 915GM and 945GM.
31 */
32
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36
37 #include "i915_drv.h"
38 #include "i915_reg.h"
39 #include "intel_connector.h"
40 #include "intel_crtc.h"
41 #include "intel_de.h"
42 #include "intel_display_irq.h"
43 #include "intel_display_types.h"
44 #include "intel_dpll.h"
45 #include "intel_hotplug.h"
46 #include "intel_load_detect.h"
47 #include "intel_tv.h"
48 #include "intel_tv_regs.h"
49
50 enum tv_margin {
51 TV_MARGIN_LEFT, TV_MARGIN_TOP,
52 TV_MARGIN_RIGHT, TV_MARGIN_BOTTOM
53 };
54
55 struct intel_tv {
56 struct intel_encoder base;
57
58 int type;
59 };
60
61 struct video_levels {
62 u16 blank, black;
63 u8 burst;
64 };
65
66 struct color_conversion {
67 u16 ry, gy, by, ay;
68 u16 ru, gu, bu, au;
69 u16 rv, gv, bv, av;
70 };
71
72 static const u32 filter_table[] = {
73 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
74 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
75 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
76 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
77 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
78 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
79 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
80 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
81 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
82 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
83 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
84 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
85 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
86 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
87 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
88 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
89 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
90 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
91 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
92 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
93 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
94 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
95 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
96 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
97 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
98 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
99 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
100 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
101 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
102 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
103 0x36403000, 0x2D002CC0, 0x30003640, 0x2D0036C0,
104 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
105 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
106 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
107 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
108 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
109 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
110 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
111 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
112 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
113 0x28003100, 0x28002F00, 0x00003100, 0x36403000,
114 0x2D002CC0, 0x30003640, 0x2D0036C0,
115 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
116 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
117 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
118 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
119 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
120 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
121 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
122 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
123 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
124 0x28003100, 0x28002F00, 0x00003100,
125 };
126
127 /*
128 * Color conversion values have 3 separate fixed point formats:
129 *
130 * 10 bit fields (ay, au)
131 * 1.9 fixed point (b.bbbbbbbbb)
132 * 11 bit fields (ry, by, ru, gu, gv)
133 * exp.mantissa (ee.mmmmmmmmm)
134 * ee = 00 = 10^-1 (0.mmmmmmmmm)
135 * ee = 01 = 10^-2 (0.0mmmmmmmmm)
136 * ee = 10 = 10^-3 (0.00mmmmmmmmm)
137 * ee = 11 = 10^-4 (0.000mmmmmmmmm)
138 * 12 bit fields (gy, rv, bu)
139 * exp.mantissa (eee.mmmmmmmmm)
140 * eee = 000 = 10^-1 (0.mmmmmmmmm)
141 * eee = 001 = 10^-2 (0.0mmmmmmmmm)
142 * eee = 010 = 10^-3 (0.00mmmmmmmmm)
143 * eee = 011 = 10^-4 (0.000mmmmmmmmm)
144 * eee = 100 = reserved
145 * eee = 101 = reserved
146 * eee = 110 = reserved
147 * eee = 111 = 10^0 (m.mmmmmmmm) (only usable for 1.0 representation)
148 *
149 * Saturation and contrast are 8 bits, with their own representation:
150 * 8 bit field (saturation, contrast)
151 * exp.mantissa (ee.mmmmmm)
152 * ee = 00 = 10^-1 (0.mmmmmm)
153 * ee = 01 = 10^0 (m.mmmmm)
154 * ee = 10 = 10^1 (mm.mmmm)
155 * ee = 11 = 10^2 (mmm.mmm)
156 *
157 * Simple conversion function:
158 *
159 * static u32
160 * float_to_csc_11(float f)
161 * {
162 * u32 exp;
163 * u32 mant;
164 * u32 ret;
165 *
166 * if (f < 0)
167 * f = -f;
168 *
169 * if (f >= 1) {
170 * exp = 0x7;
171 * mant = 1 << 8;
172 * } else {
173 * for (exp = 0; exp < 3 && f < 0.5; exp++)
174 * f *= 2.0;
175 * mant = (f * (1 << 9) + 0.5);
176 * if (mant >= (1 << 9))
177 * mant = (1 << 9) - 1;
178 * }
179 * ret = (exp << 9) | mant;
180 * return ret;
181 * }
182 */
183
184 /*
185 * Behold, magic numbers! If we plant them they might grow a big
186 * s-video cable to the sky... or something.
187 *
188 * Pre-converted to appropriate hex value.
189 */
190
191 /*
192 * PAL & NTSC values for composite & s-video connections
193 */
194 static const struct color_conversion ntsc_m_csc_composite = {
195 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
196 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
197 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
198 };
199
200 static const struct video_levels ntsc_m_levels_composite = {
201 .blank = 225, .black = 267, .burst = 113,
202 };
203
204 static const struct color_conversion ntsc_m_csc_svideo = {
205 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
206 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
207 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
208 };
209
210 static const struct video_levels ntsc_m_levels_svideo = {
211 .blank = 266, .black = 316, .burst = 133,
212 };
213
214 static const struct color_conversion ntsc_j_csc_composite = {
215 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0119,
216 .ru = 0x074c, .gu = 0x0546, .bu = 0x05ec, .au = 0x0200,
217 .rv = 0x035a, .gv = 0x0322, .bv = 0x06e1, .av = 0x0200,
218 };
219
220 static const struct video_levels ntsc_j_levels_composite = {
221 .blank = 225, .black = 225, .burst = 113,
222 };
223
224 static const struct color_conversion ntsc_j_csc_svideo = {
225 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x014c,
226 .ru = 0x0788, .gu = 0x0581, .bu = 0x0322, .au = 0x0200,
227 .rv = 0x0399, .gv = 0x0356, .bv = 0x070a, .av = 0x0200,
228 };
229
230 static const struct video_levels ntsc_j_levels_svideo = {
231 .blank = 266, .black = 266, .burst = 133,
232 };
233
234 static const struct color_conversion pal_csc_composite = {
235 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0113,
236 .ru = 0x0745, .gu = 0x053f, .bu = 0x05e1, .au = 0x0200,
237 .rv = 0x0353, .gv = 0x031c, .bv = 0x06dc, .av = 0x0200,
238 };
239
240 static const struct video_levels pal_levels_composite = {
241 .blank = 237, .black = 237, .burst = 118,
242 };
243
244 static const struct color_conversion pal_csc_svideo = {
245 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
246 .ru = 0x0780, .gu = 0x0579, .bu = 0x031c, .au = 0x0200,
247 .rv = 0x0390, .gv = 0x034f, .bv = 0x0705, .av = 0x0200,
248 };
249
250 static const struct video_levels pal_levels_svideo = {
251 .blank = 280, .black = 280, .burst = 139,
252 };
253
254 static const struct color_conversion pal_m_csc_composite = {
255 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
256 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
257 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
258 };
259
260 static const struct video_levels pal_m_levels_composite = {
261 .blank = 225, .black = 267, .burst = 113,
262 };
263
264 static const struct color_conversion pal_m_csc_svideo = {
265 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
266 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
267 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
268 };
269
270 static const struct video_levels pal_m_levels_svideo = {
271 .blank = 266, .black = 316, .burst = 133,
272 };
273
274 static const struct color_conversion pal_n_csc_composite = {
275 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
276 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
277 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
278 };
279
280 static const struct video_levels pal_n_levels_composite = {
281 .blank = 225, .black = 267, .burst = 118,
282 };
283
284 static const struct color_conversion pal_n_csc_svideo = {
285 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
286 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
287 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
288 };
289
290 static const struct video_levels pal_n_levels_svideo = {
291 .blank = 266, .black = 316, .burst = 139,
292 };
293
294 /*
295 * Component connections
296 */
297 static const struct color_conversion sdtv_csc_yprpb = {
298 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
299 .ru = 0x0559, .gu = 0x0353, .bu = 0x0100, .au = 0x0200,
300 .rv = 0x0100, .gv = 0x03ad, .bv = 0x074d, .av = 0x0200,
301 };
302
303 static const struct color_conversion hdtv_csc_yprpb = {
304 .ry = 0x05b3, .gy = 0x016e, .by = 0x0728, .ay = 0x0145,
305 .ru = 0x07d5, .gu = 0x038b, .bu = 0x0100, .au = 0x0200,
306 .rv = 0x0100, .gv = 0x03d1, .bv = 0x06bc, .av = 0x0200,
307 };
308
309 static const struct video_levels component_levels = {
310 .blank = 279, .black = 279, .burst = 0,
311 };
312
313
314 struct tv_mode {
315 const char *name;
316
317 u32 clock;
318 u16 refresh; /* in millihertz (for precision) */
319 u8 oversample;
320 u8 hsync_end;
321 u16 hblank_start, hblank_end, htotal;
322 bool progressive : 1, trilevel_sync : 1, component_only : 1;
323 u8 vsync_start_f1, vsync_start_f2, vsync_len;
324 bool veq_ena : 1;
325 u8 veq_start_f1, veq_start_f2, veq_len;
326 u8 vi_end_f1, vi_end_f2;
327 u16 nbr_end;
328 bool burst_ena : 1;
329 u8 hburst_start, hburst_len;
330 u8 vburst_start_f1;
331 u16 vburst_end_f1;
332 u8 vburst_start_f2;
333 u16 vburst_end_f2;
334 u8 vburst_start_f3;
335 u16 vburst_end_f3;
336 u8 vburst_start_f4;
337 u16 vburst_end_f4;
338 /*
339 * subcarrier programming
340 */
341 u16 dda2_size, dda3_size;
342 u8 dda1_inc;
343 u16 dda2_inc, dda3_inc;
344 u32 sc_reset;
345 bool pal_burst : 1;
346 /*
347 * blank/black levels
348 */
349 const struct video_levels *composite_levels, *svideo_levels;
350 const struct color_conversion *composite_color, *svideo_color;
351 const u32 *filter_table;
352 };
353
354
355 /*
356 * Sub carrier DDA
357 *
358 * I think this works as follows:
359 *
360 * subcarrier freq = pixel_clock * (dda1_inc + dda2_inc / dda2_size) / 4096
361 *
362 * Presumably, when dda3 is added in, it gets to adjust the dda2_inc value
363 *
364 * So,
365 * dda1_ideal = subcarrier/pixel * 4096
366 * dda1_inc = floor (dda1_ideal)
367 * dda2 = dda1_ideal - dda1_inc
368 *
369 * then pick a ratio for dda2 that gives the closest approximation. If
370 * you can't get close enough, you can play with dda3 as well. This
371 * seems likely to happen when dda2 is small as the jumps would be larger
372 *
373 * To invert this,
374 *
375 * pixel_clock = subcarrier * 4096 / (dda1_inc + dda2_inc / dda2_size)
376 *
377 * The constants below were all computed using a 107.520MHz clock
378 */
379
380 /*
381 * Register programming values for TV modes.
382 *
383 * These values account for -1s required.
384 */
385 static const struct tv_mode tv_modes[] = {
386 {
387 .name = "NTSC-M",
388 .clock = 108000,
389 .refresh = 59940,
390 .oversample = 8,
391 .component_only = false,
392 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
393
394 .hsync_end = 64, .hblank_end = 124,
395 .hblank_start = 836, .htotal = 857,
396
397 .progressive = false, .trilevel_sync = false,
398
399 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
400 .vsync_len = 6,
401
402 .veq_ena = true, .veq_start_f1 = 0,
403 .veq_start_f2 = 1, .veq_len = 18,
404
405 .vi_end_f1 = 20, .vi_end_f2 = 21,
406 .nbr_end = 240,
407
408 .burst_ena = true,
409 .hburst_start = 72, .hburst_len = 34,
410 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
411 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
412 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
413 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
414
415 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
416 .dda1_inc = 135,
417 .dda2_inc = 20800, .dda2_size = 27456,
418 .dda3_inc = 0, .dda3_size = 0,
419 .sc_reset = TV_SC_RESET_EVERY_4,
420 .pal_burst = false,
421
422 .composite_levels = &ntsc_m_levels_composite,
423 .composite_color = &ntsc_m_csc_composite,
424 .svideo_levels = &ntsc_m_levels_svideo,
425 .svideo_color = &ntsc_m_csc_svideo,
426
427 .filter_table = filter_table,
428 },
429 {
430 .name = "NTSC-443",
431 .clock = 108000,
432 .refresh = 59940,
433 .oversample = 8,
434 .component_only = false,
435 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */
436 .hsync_end = 64, .hblank_end = 124,
437 .hblank_start = 836, .htotal = 857,
438
439 .progressive = false, .trilevel_sync = false,
440
441 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
442 .vsync_len = 6,
443
444 .veq_ena = true, .veq_start_f1 = 0,
445 .veq_start_f2 = 1, .veq_len = 18,
446
447 .vi_end_f1 = 20, .vi_end_f2 = 21,
448 .nbr_end = 240,
449
450 .burst_ena = true,
451 .hburst_start = 72, .hburst_len = 34,
452 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
453 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
454 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
455 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
456
457 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
458 .dda1_inc = 168,
459 .dda2_inc = 4093, .dda2_size = 27456,
460 .dda3_inc = 310, .dda3_size = 525,
461 .sc_reset = TV_SC_RESET_NEVER,
462 .pal_burst = false,
463
464 .composite_levels = &ntsc_m_levels_composite,
465 .composite_color = &ntsc_m_csc_composite,
466 .svideo_levels = &ntsc_m_levels_svideo,
467 .svideo_color = &ntsc_m_csc_svideo,
468
469 .filter_table = filter_table,
470 },
471 {
472 .name = "NTSC-J",
473 .clock = 108000,
474 .refresh = 59940,
475 .oversample = 8,
476 .component_only = false,
477
478 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
479 .hsync_end = 64, .hblank_end = 124,
480 .hblank_start = 836, .htotal = 857,
481
482 .progressive = false, .trilevel_sync = false,
483
484 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
485 .vsync_len = 6,
486
487 .veq_ena = true, .veq_start_f1 = 0,
488 .veq_start_f2 = 1, .veq_len = 18,
489
490 .vi_end_f1 = 20, .vi_end_f2 = 21,
491 .nbr_end = 240,
492
493 .burst_ena = true,
494 .hburst_start = 72, .hburst_len = 34,
495 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
496 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
497 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
498 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
499
500 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
501 .dda1_inc = 135,
502 .dda2_inc = 20800, .dda2_size = 27456,
503 .dda3_inc = 0, .dda3_size = 0,
504 .sc_reset = TV_SC_RESET_EVERY_4,
505 .pal_burst = false,
506
507 .composite_levels = &ntsc_j_levels_composite,
508 .composite_color = &ntsc_j_csc_composite,
509 .svideo_levels = &ntsc_j_levels_svideo,
510 .svideo_color = &ntsc_j_csc_svideo,
511
512 .filter_table = filter_table,
513 },
514 {
515 .name = "PAL-M",
516 .clock = 108000,
517 .refresh = 59940,
518 .oversample = 8,
519 .component_only = false,
520
521 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
522 .hsync_end = 64, .hblank_end = 124,
523 .hblank_start = 836, .htotal = 857,
524
525 .progressive = false, .trilevel_sync = false,
526
527 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
528 .vsync_len = 6,
529
530 .veq_ena = true, .veq_start_f1 = 0,
531 .veq_start_f2 = 1, .veq_len = 18,
532
533 .vi_end_f1 = 20, .vi_end_f2 = 21,
534 .nbr_end = 240,
535
536 .burst_ena = true,
537 .hburst_start = 72, .hburst_len = 34,
538 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
539 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
540 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
541 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
542
543 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
544 .dda1_inc = 135,
545 .dda2_inc = 16704, .dda2_size = 27456,
546 .dda3_inc = 0, .dda3_size = 0,
547 .sc_reset = TV_SC_RESET_EVERY_8,
548 .pal_burst = true,
549
550 .composite_levels = &pal_m_levels_composite,
551 .composite_color = &pal_m_csc_composite,
552 .svideo_levels = &pal_m_levels_svideo,
553 .svideo_color = &pal_m_csc_svideo,
554
555 .filter_table = filter_table,
556 },
557 {
558 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
559 .name = "PAL-N",
560 .clock = 108000,
561 .refresh = 50000,
562 .oversample = 8,
563 .component_only = false,
564
565 .hsync_end = 64, .hblank_end = 128,
566 .hblank_start = 844, .htotal = 863,
567
568 .progressive = false, .trilevel_sync = false,
569
570
571 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
572 .vsync_len = 6,
573
574 .veq_ena = true, .veq_start_f1 = 0,
575 .veq_start_f2 = 1, .veq_len = 18,
576
577 .vi_end_f1 = 24, .vi_end_f2 = 25,
578 .nbr_end = 286,
579
580 .burst_ena = true,
581 .hburst_start = 73, .hburst_len = 34,
582 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
583 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
584 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
585 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
586
587
588 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
589 .dda1_inc = 135,
590 .dda2_inc = 23578, .dda2_size = 27648,
591 .dda3_inc = 134, .dda3_size = 625,
592 .sc_reset = TV_SC_RESET_EVERY_8,
593 .pal_burst = true,
594
595 .composite_levels = &pal_n_levels_composite,
596 .composite_color = &pal_n_csc_composite,
597 .svideo_levels = &pal_n_levels_svideo,
598 .svideo_color = &pal_n_csc_svideo,
599
600 .filter_table = filter_table,
601 },
602 {
603 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
604 .name = "PAL",
605 .clock = 108000,
606 .refresh = 50000,
607 .oversample = 8,
608 .component_only = false,
609
610 .hsync_end = 64, .hblank_end = 142,
611 .hblank_start = 844, .htotal = 863,
612
613 .progressive = false, .trilevel_sync = false,
614
615 .vsync_start_f1 = 5, .vsync_start_f2 = 6,
616 .vsync_len = 5,
617
618 .veq_ena = true, .veq_start_f1 = 0,
619 .veq_start_f2 = 1, .veq_len = 15,
620
621 .vi_end_f1 = 24, .vi_end_f2 = 25,
622 .nbr_end = 286,
623
624 .burst_ena = true,
625 .hburst_start = 73, .hburst_len = 32,
626 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
627 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
628 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
629 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
630
631 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
632 .dda1_inc = 168,
633 .dda2_inc = 4122, .dda2_size = 27648,
634 .dda3_inc = 67, .dda3_size = 625,
635 .sc_reset = TV_SC_RESET_EVERY_8,
636 .pal_burst = true,
637
638 .composite_levels = &pal_levels_composite,
639 .composite_color = &pal_csc_composite,
640 .svideo_levels = &pal_levels_svideo,
641 .svideo_color = &pal_csc_svideo,
642
643 .filter_table = filter_table,
644 },
645 {
646 .name = "480p",
647 .clock = 108000,
648 .refresh = 59940,
649 .oversample = 4,
650 .component_only = true,
651
652 .hsync_end = 64, .hblank_end = 122,
653 .hblank_start = 842, .htotal = 857,
654
655 .progressive = true, .trilevel_sync = false,
656
657 .vsync_start_f1 = 12, .vsync_start_f2 = 12,
658 .vsync_len = 12,
659
660 .veq_ena = false,
661
662 .vi_end_f1 = 44, .vi_end_f2 = 44,
663 .nbr_end = 479,
664
665 .burst_ena = false,
666
667 .filter_table = filter_table,
668 },
669 {
670 .name = "576p",
671 .clock = 108000,
672 .refresh = 50000,
673 .oversample = 4,
674 .component_only = true,
675
676 .hsync_end = 64, .hblank_end = 139,
677 .hblank_start = 859, .htotal = 863,
678
679 .progressive = true, .trilevel_sync = false,
680
681 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
682 .vsync_len = 10,
683
684 .veq_ena = false,
685
686 .vi_end_f1 = 48, .vi_end_f2 = 48,
687 .nbr_end = 575,
688
689 .burst_ena = false,
690
691 .filter_table = filter_table,
692 },
693 {
694 .name = "720p@60Hz",
695 .clock = 148500,
696 .refresh = 60000,
697 .oversample = 2,
698 .component_only = true,
699
700 .hsync_end = 80, .hblank_end = 300,
701 .hblank_start = 1580, .htotal = 1649,
702
703 .progressive = true, .trilevel_sync = true,
704
705 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
706 .vsync_len = 10,
707
708 .veq_ena = false,
709
710 .vi_end_f1 = 29, .vi_end_f2 = 29,
711 .nbr_end = 719,
712
713 .burst_ena = false,
714
715 .filter_table = filter_table,
716 },
717 {
718 .name = "720p@50Hz",
719 .clock = 148500,
720 .refresh = 50000,
721 .oversample = 2,
722 .component_only = true,
723
724 .hsync_end = 80, .hblank_end = 300,
725 .hblank_start = 1580, .htotal = 1979,
726
727 .progressive = true, .trilevel_sync = true,
728
729 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
730 .vsync_len = 10,
731
732 .veq_ena = false,
733
734 .vi_end_f1 = 29, .vi_end_f2 = 29,
735 .nbr_end = 719,
736
737 .burst_ena = false,
738
739 .filter_table = filter_table,
740 },
741 {
742 .name = "1080i@50Hz",
743 .clock = 148500,
744 .refresh = 50000,
745 .oversample = 2,
746 .component_only = true,
747
748 .hsync_end = 88, .hblank_end = 235,
749 .hblank_start = 2155, .htotal = 2639,
750
751 .progressive = false, .trilevel_sync = true,
752
753 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
754 .vsync_len = 10,
755
756 .veq_ena = true, .veq_start_f1 = 4,
757 .veq_start_f2 = 4, .veq_len = 10,
758
759
760 .vi_end_f1 = 21, .vi_end_f2 = 22,
761 .nbr_end = 539,
762
763 .burst_ena = false,
764
765 .filter_table = filter_table,
766 },
767 {
768 .name = "1080i@60Hz",
769 .clock = 148500,
770 .refresh = 60000,
771 .oversample = 2,
772 .component_only = true,
773
774 .hsync_end = 88, .hblank_end = 235,
775 .hblank_start = 2155, .htotal = 2199,
776
777 .progressive = false, .trilevel_sync = true,
778
779 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
780 .vsync_len = 10,
781
782 .veq_ena = true, .veq_start_f1 = 4,
783 .veq_start_f2 = 4, .veq_len = 10,
784
785
786 .vi_end_f1 = 21, .vi_end_f2 = 22,
787 .nbr_end = 539,
788
789 .burst_ena = false,
790
791 .filter_table = filter_table,
792 },
793
794 {
795 .name = "1080p@30Hz",
796 .clock = 148500,
797 .refresh = 30000,
798 .oversample = 2,
799 .component_only = true,
800
801 .hsync_end = 88, .hblank_end = 235,
802 .hblank_start = 2155, .htotal = 2199,
803
804 .progressive = true, .trilevel_sync = true,
805
806 .vsync_start_f1 = 8, .vsync_start_f2 = 8,
807 .vsync_len = 10,
808
809 .veq_ena = false, .veq_start_f1 = 0,
810 .veq_start_f2 = 0, .veq_len = 0,
811
812 .vi_end_f1 = 44, .vi_end_f2 = 44,
813 .nbr_end = 1079,
814
815 .burst_ena = false,
816
817 .filter_table = filter_table,
818 },
819
820 {
821 .name = "1080p@50Hz",
822 .clock = 148500,
823 .refresh = 50000,
824 .oversample = 1,
825 .component_only = true,
826
827 .hsync_end = 88, .hblank_end = 235,
828 .hblank_start = 2155, .htotal = 2639,
829
830 .progressive = true, .trilevel_sync = true,
831
832 .vsync_start_f1 = 8, .vsync_start_f2 = 8,
833 .vsync_len = 10,
834
835 .veq_ena = false, .veq_start_f1 = 0,
836 .veq_start_f2 = 0, .veq_len = 0,
837
838 .vi_end_f1 = 44, .vi_end_f2 = 44,
839 .nbr_end = 1079,
840
841 .burst_ena = false,
842
843 .filter_table = filter_table,
844 },
845
846 {
847 .name = "1080p@60Hz",
848 .clock = 148500,
849 .refresh = 60000,
850 .oversample = 1,
851 .component_only = true,
852
853 .hsync_end = 88, .hblank_end = 235,
854 .hblank_start = 2155, .htotal = 2199,
855
856 .progressive = true, .trilevel_sync = true,
857
858 .vsync_start_f1 = 8, .vsync_start_f2 = 8,
859 .vsync_len = 10,
860
861 .veq_ena = false, .veq_start_f1 = 0,
862 .veq_start_f2 = 0, .veq_len = 0,
863
864 .vi_end_f1 = 44, .vi_end_f2 = 44,
865 .nbr_end = 1079,
866
867 .burst_ena = false,
868
869 .filter_table = filter_table,
870 },
871 };
872
873 struct intel_tv_connector_state {
874 struct drm_connector_state base;
875
876 /*
877 * May need to override the user margins for
878 * gen3 >1024 wide source vertical centering.
879 */
880 struct {
881 u16 top, bottom;
882 } margins;
883
884 bool bypass_vfilter;
885 };
886
887 #define to_intel_tv_connector_state(x) container_of(x, struct intel_tv_connector_state, base)
888
889 static struct drm_connector_state *
intel_tv_connector_duplicate_state(struct drm_connector * connector)890 intel_tv_connector_duplicate_state(struct drm_connector *connector)
891 {
892 struct intel_tv_connector_state *state;
893
894 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
895 if (!state)
896 return NULL;
897
898 __drm_atomic_helper_connector_duplicate_state(connector, &state->base);
899 return &state->base;
900 }
901
enc_to_tv(struct intel_encoder * encoder)902 static struct intel_tv *enc_to_tv(struct intel_encoder *encoder)
903 {
904 return container_of(encoder, struct intel_tv, base);
905 }
906
intel_attached_tv(struct intel_connector * connector)907 static struct intel_tv *intel_attached_tv(struct intel_connector *connector)
908 {
909 return enc_to_tv(intel_attached_encoder(connector));
910 }
911
912 static bool
intel_tv_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)913 intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe)
914 {
915 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
916 u32 tmp = intel_de_read(dev_priv, TV_CTL);
917
918 *pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT;
919
920 return tmp & TV_ENC_ENABLE;
921 }
922
923 static void
intel_enable_tv(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)924 intel_enable_tv(struct intel_atomic_state *state,
925 struct intel_encoder *encoder,
926 const struct intel_crtc_state *pipe_config,
927 const struct drm_connector_state *conn_state)
928 {
929 struct drm_device *dev = encoder->base.dev;
930 struct drm_i915_private *dev_priv = to_i915(dev);
931
932 /* Prevents vblank waits from timing out in intel_tv_detect_type() */
933 intel_crtc_wait_for_next_vblank(to_intel_crtc(pipe_config->uapi.crtc));
934
935 intel_de_rmw(dev_priv, TV_CTL, 0, TV_ENC_ENABLE);
936 }
937
938 static void
intel_disable_tv(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)939 intel_disable_tv(struct intel_atomic_state *state,
940 struct intel_encoder *encoder,
941 const struct intel_crtc_state *old_crtc_state,
942 const struct drm_connector_state *old_conn_state)
943 {
944 struct drm_device *dev = encoder->base.dev;
945 struct drm_i915_private *dev_priv = to_i915(dev);
946
947 intel_de_rmw(dev_priv, TV_CTL, TV_ENC_ENABLE, 0);
948 }
949
intel_tv_mode_find(const struct drm_connector_state * conn_state)950 static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state)
951 {
952 int format = conn_state->tv.mode;
953
954 return &tv_modes[format];
955 }
956
957 static enum drm_mode_status
intel_tv_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)958 intel_tv_mode_valid(struct drm_connector *connector,
959 struct drm_display_mode *mode)
960 {
961 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
962 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
963
964 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
965 return MODE_NO_DBLESCAN;
966
967 if (mode->clock > max_dotclk)
968 return MODE_CLOCK_HIGH;
969
970 /* Ensure TV refresh is close to desired refresh */
971 if (abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000) >= 1000)
972 return MODE_CLOCK_RANGE;
973
974 return MODE_OK;
975 }
976
977 static int
intel_tv_mode_vdisplay(const struct tv_mode * tv_mode)978 intel_tv_mode_vdisplay(const struct tv_mode *tv_mode)
979 {
980 if (tv_mode->progressive)
981 return tv_mode->nbr_end + 1;
982 else
983 return 2 * (tv_mode->nbr_end + 1);
984 }
985
986 static void
intel_tv_mode_to_mode(struct drm_display_mode * mode,const struct tv_mode * tv_mode,int clock)987 intel_tv_mode_to_mode(struct drm_display_mode *mode,
988 const struct tv_mode *tv_mode,
989 int clock)
990 {
991 mode->clock = clock / (tv_mode->oversample >> !tv_mode->progressive);
992
993 /*
994 * tv_mode horizontal timings:
995 *
996 * hsync_end
997 * | hblank_end
998 * | | hblank_start
999 * | | | htotal
1000 * | _______ |
1001 * ____/ \___
1002 * \__/ \
1003 */
1004 mode->hdisplay =
1005 tv_mode->hblank_start - tv_mode->hblank_end;
1006 mode->hsync_start = mode->hdisplay +
1007 tv_mode->htotal - tv_mode->hblank_start;
1008 mode->hsync_end = mode->hsync_start +
1009 tv_mode->hsync_end;
1010 mode->htotal = tv_mode->htotal + 1;
1011
1012 /*
1013 * tv_mode vertical timings:
1014 *
1015 * vsync_start
1016 * | vsync_end
1017 * | | vi_end nbr_end
1018 * | | | |
1019 * | | _______
1020 * \__ ____/ \
1021 * \__/
1022 */
1023 mode->vdisplay = intel_tv_mode_vdisplay(tv_mode);
1024 if (tv_mode->progressive) {
1025 mode->vsync_start = mode->vdisplay +
1026 tv_mode->vsync_start_f1 + 1;
1027 mode->vsync_end = mode->vsync_start +
1028 tv_mode->vsync_len;
1029 mode->vtotal = mode->vdisplay +
1030 tv_mode->vi_end_f1 + 1;
1031 } else {
1032 mode->vsync_start = mode->vdisplay +
1033 tv_mode->vsync_start_f1 + 1 +
1034 tv_mode->vsync_start_f2 + 1;
1035 mode->vsync_end = mode->vsync_start +
1036 2 * tv_mode->vsync_len;
1037 mode->vtotal = mode->vdisplay +
1038 tv_mode->vi_end_f1 + 1 +
1039 tv_mode->vi_end_f2 + 1;
1040 }
1041
1042 /* TV has it's own notion of sync and other mode flags, so clear them. */
1043 mode->flags = 0;
1044
1045 snprintf(mode->name, sizeof(mode->name),
1046 "%dx%d%c (%s)",
1047 mode->hdisplay, mode->vdisplay,
1048 tv_mode->progressive ? 'p' : 'i',
1049 tv_mode->name);
1050 }
1051
intel_tv_scale_mode_horiz(struct drm_display_mode * mode,int hdisplay,int left_margin,int right_margin)1052 static void intel_tv_scale_mode_horiz(struct drm_display_mode *mode,
1053 int hdisplay, int left_margin,
1054 int right_margin)
1055 {
1056 int hsync_start = mode->hsync_start - mode->hdisplay + right_margin;
1057 int hsync_end = mode->hsync_end - mode->hdisplay + right_margin;
1058 int new_htotal = mode->htotal * hdisplay /
1059 (mode->hdisplay - left_margin - right_margin);
1060
1061 mode->clock = mode->clock * new_htotal / mode->htotal;
1062
1063 mode->hdisplay = hdisplay;
1064 mode->hsync_start = hdisplay + hsync_start * new_htotal / mode->htotal;
1065 mode->hsync_end = hdisplay + hsync_end * new_htotal / mode->htotal;
1066 mode->htotal = new_htotal;
1067 }
1068
intel_tv_scale_mode_vert(struct drm_display_mode * mode,int vdisplay,int top_margin,int bottom_margin)1069 static void intel_tv_scale_mode_vert(struct drm_display_mode *mode,
1070 int vdisplay, int top_margin,
1071 int bottom_margin)
1072 {
1073 int vsync_start = mode->vsync_start - mode->vdisplay + bottom_margin;
1074 int vsync_end = mode->vsync_end - mode->vdisplay + bottom_margin;
1075 int new_vtotal = mode->vtotal * vdisplay /
1076 (mode->vdisplay - top_margin - bottom_margin);
1077
1078 mode->clock = mode->clock * new_vtotal / mode->vtotal;
1079
1080 mode->vdisplay = vdisplay;
1081 mode->vsync_start = vdisplay + vsync_start * new_vtotal / mode->vtotal;
1082 mode->vsync_end = vdisplay + vsync_end * new_vtotal / mode->vtotal;
1083 mode->vtotal = new_vtotal;
1084 }
1085
1086 static void
intel_tv_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1087 intel_tv_get_config(struct intel_encoder *encoder,
1088 struct intel_crtc_state *pipe_config)
1089 {
1090 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1091 struct drm_display_mode *adjusted_mode =
1092 &pipe_config->hw.adjusted_mode;
1093 struct drm_display_mode mode = {};
1094 u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp;
1095 struct tv_mode tv_mode = {};
1096 int hdisplay = adjusted_mode->crtc_hdisplay;
1097 int vdisplay = adjusted_mode->crtc_vdisplay;
1098 int xsize, ysize, xpos, ypos;
1099
1100 pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT);
1101
1102 tv_ctl = intel_de_read(dev_priv, TV_CTL);
1103 hctl1 = intel_de_read(dev_priv, TV_H_CTL_1);
1104 hctl3 = intel_de_read(dev_priv, TV_H_CTL_3);
1105 vctl1 = intel_de_read(dev_priv, TV_V_CTL_1);
1106 vctl2 = intel_de_read(dev_priv, TV_V_CTL_2);
1107
1108 tv_mode.htotal = (hctl1 & TV_HTOTAL_MASK) >> TV_HTOTAL_SHIFT;
1109 tv_mode.hsync_end = (hctl1 & TV_HSYNC_END_MASK) >> TV_HSYNC_END_SHIFT;
1110
1111 tv_mode.hblank_start = (hctl3 & TV_HBLANK_START_MASK) >> TV_HBLANK_START_SHIFT;
1112 tv_mode.hblank_end = (hctl3 & TV_HSYNC_END_MASK) >> TV_HBLANK_END_SHIFT;
1113
1114 tv_mode.nbr_end = (vctl1 & TV_NBR_END_MASK) >> TV_NBR_END_SHIFT;
1115 tv_mode.vi_end_f1 = (vctl1 & TV_VI_END_F1_MASK) >> TV_VI_END_F1_SHIFT;
1116 tv_mode.vi_end_f2 = (vctl1 & TV_VI_END_F2_MASK) >> TV_VI_END_F2_SHIFT;
1117
1118 tv_mode.vsync_len = (vctl2 & TV_VSYNC_LEN_MASK) >> TV_VSYNC_LEN_SHIFT;
1119 tv_mode.vsync_start_f1 = (vctl2 & TV_VSYNC_START_F1_MASK) >> TV_VSYNC_START_F1_SHIFT;
1120 tv_mode.vsync_start_f2 = (vctl2 & TV_VSYNC_START_F2_MASK) >> TV_VSYNC_START_F2_SHIFT;
1121
1122 tv_mode.clock = pipe_config->port_clock;
1123
1124 tv_mode.progressive = tv_ctl & TV_PROGRESSIVE;
1125
1126 switch (tv_ctl & TV_OVERSAMPLE_MASK) {
1127 case TV_OVERSAMPLE_8X:
1128 tv_mode.oversample = 8;
1129 break;
1130 case TV_OVERSAMPLE_4X:
1131 tv_mode.oversample = 4;
1132 break;
1133 case TV_OVERSAMPLE_2X:
1134 tv_mode.oversample = 2;
1135 break;
1136 default:
1137 tv_mode.oversample = 1;
1138 break;
1139 }
1140
1141 tmp = intel_de_read(dev_priv, TV_WIN_POS);
1142 xpos = tmp >> 16;
1143 ypos = tmp & 0xffff;
1144
1145 tmp = intel_de_read(dev_priv, TV_WIN_SIZE);
1146 xsize = tmp >> 16;
1147 ysize = tmp & 0xffff;
1148
1149 intel_tv_mode_to_mode(&mode, &tv_mode, pipe_config->port_clock);
1150
1151 drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n",
1152 DRM_MODE_ARG(&mode));
1153
1154 intel_tv_scale_mode_horiz(&mode, hdisplay,
1155 xpos, mode.hdisplay - xsize - xpos);
1156 intel_tv_scale_mode_vert(&mode, vdisplay,
1157 ypos, mode.vdisplay - ysize - ypos);
1158
1159 adjusted_mode->crtc_clock = mode.clock;
1160 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1161 adjusted_mode->crtc_clock /= 2;
1162
1163 /* pixel counter doesn't work on i965gm TV output */
1164 if (IS_I965GM(dev_priv))
1165 pipe_config->mode_flags |=
1166 I915_MODE_FLAG_USE_SCANLINE_COUNTER;
1167 }
1168
intel_tv_source_too_wide(struct drm_i915_private * dev_priv,int hdisplay)1169 static bool intel_tv_source_too_wide(struct drm_i915_private *dev_priv,
1170 int hdisplay)
1171 {
1172 return DISPLAY_VER(dev_priv) == 3 && hdisplay > 1024;
1173 }
1174
intel_tv_vert_scaling(const struct drm_display_mode * tv_mode,const struct drm_connector_state * conn_state,int vdisplay)1175 static bool intel_tv_vert_scaling(const struct drm_display_mode *tv_mode,
1176 const struct drm_connector_state *conn_state,
1177 int vdisplay)
1178 {
1179 return tv_mode->crtc_vdisplay -
1180 conn_state->tv.margins.top -
1181 conn_state->tv.margins.bottom !=
1182 vdisplay;
1183 }
1184
1185 static int
intel_tv_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)1186 intel_tv_compute_config(struct intel_encoder *encoder,
1187 struct intel_crtc_state *pipe_config,
1188 struct drm_connector_state *conn_state)
1189 {
1190 struct intel_atomic_state *state =
1191 to_intel_atomic_state(pipe_config->uapi.state);
1192 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1193 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1194 struct intel_tv_connector_state *tv_conn_state =
1195 to_intel_tv_connector_state(conn_state);
1196 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
1197 struct drm_display_mode *adjusted_mode =
1198 &pipe_config->hw.adjusted_mode;
1199 int hdisplay = adjusted_mode->crtc_hdisplay;
1200 int vdisplay = adjusted_mode->crtc_vdisplay;
1201 int ret;
1202
1203 if (!tv_mode)
1204 return -EINVAL;
1205
1206 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1207 return -EINVAL;
1208
1209 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
1210 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1211
1212 drm_dbg_kms(&dev_priv->drm, "forcing bpc to 8 for TV\n");
1213 pipe_config->pipe_bpp = 8*3;
1214
1215 pipe_config->port_clock = tv_mode->clock;
1216
1217 ret = intel_dpll_crtc_compute_clock(state, crtc);
1218 if (ret)
1219 return ret;
1220
1221 pipe_config->clock_set = true;
1222
1223 intel_tv_mode_to_mode(adjusted_mode, tv_mode, pipe_config->port_clock);
1224 drm_mode_set_crtcinfo(adjusted_mode, 0);
1225
1226 if (intel_tv_source_too_wide(dev_priv, hdisplay) ||
1227 !intel_tv_vert_scaling(adjusted_mode, conn_state, vdisplay)) {
1228 int extra, top, bottom;
1229
1230 extra = adjusted_mode->crtc_vdisplay - vdisplay;
1231
1232 if (extra < 0) {
1233 drm_dbg_kms(&dev_priv->drm,
1234 "No vertical scaling for >1024 pixel wide modes\n");
1235 return -EINVAL;
1236 }
1237
1238 /* Need to turn off the vertical filter and center the image */
1239
1240 /* Attempt to maintain the relative sizes of the margins */
1241 top = conn_state->tv.margins.top;
1242 bottom = conn_state->tv.margins.bottom;
1243
1244 if (top + bottom)
1245 top = extra * top / (top + bottom);
1246 else
1247 top = extra / 2;
1248 bottom = extra - top;
1249
1250 tv_conn_state->margins.top = top;
1251 tv_conn_state->margins.bottom = bottom;
1252
1253 tv_conn_state->bypass_vfilter = true;
1254
1255 if (!tv_mode->progressive) {
1256 adjusted_mode->clock /= 2;
1257 adjusted_mode->crtc_clock /= 2;
1258 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
1259 }
1260 } else {
1261 tv_conn_state->margins.top = conn_state->tv.margins.top;
1262 tv_conn_state->margins.bottom = conn_state->tv.margins.bottom;
1263
1264 tv_conn_state->bypass_vfilter = false;
1265 }
1266
1267 drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n",
1268 DRM_MODE_ARG(adjusted_mode));
1269
1270 /*
1271 * The pipe scanline counter behaviour looks as follows when
1272 * using the TV encoder:
1273 *
1274 * time ->
1275 *
1276 * dsl=vtotal-1 | |
1277 * || ||
1278 * ___| | ___| |
1279 * / | / |
1280 * / | / |
1281 * dsl=0 ___/ |_____/ |
1282 * | | | | | |
1283 * ^ ^ ^ ^ ^
1284 * | | | | pipe vblank/first part of tv vblank
1285 * | | | bottom margin
1286 * | | active
1287 * | top margin
1288 * remainder of tv vblank
1289 *
1290 * When the TV encoder is used the pipe wants to run faster
1291 * than expected rate. During the active portion the TV
1292 * encoder stalls the pipe every few lines to keep it in
1293 * check. When the TV encoder reaches the bottom margin the
1294 * pipe simply stops. Once we reach the TV vblank the pipe is
1295 * no longer stalled and it runs at the max rate (apparently
1296 * oversample clock on gen3, cdclk on gen4). Once the pipe
1297 * reaches the pipe vtotal the pipe stops for the remainder
1298 * of the TV vblank/top margin. The pipe starts up again when
1299 * the TV encoder exits the top margin.
1300 *
1301 * To avoid huge hassles for vblank timestamping we scale
1302 * the pipe timings as if the pipe always runs at the average
1303 * rate it maintains during the active period. This also
1304 * gives us a reasonable guesstimate as to the pixel rate.
1305 * Due to the variation in the actual pipe speed the scanline
1306 * counter will give us slightly erroneous results during the
1307 * TV vblank/margins. But since vtotal was selected such that
1308 * it matches the average rate of the pipe during the active
1309 * portion the error shouldn't cause any serious grief to
1310 * vblank timestamps.
1311 *
1312 * For posterity here is the empirically derived formula
1313 * that gives us the maximum length of the pipe vblank
1314 * we can use without causing display corruption. Following
1315 * this would allow us to have a ticking scanline counter
1316 * everywhere except during the bottom margin (there the
1317 * pipe always stops). Ie. this would eliminate the second
1318 * flat portion of the above graph. However this would also
1319 * complicate vblank timestamping as the pipe vtotal would
1320 * no longer match the average rate the pipe runs at during
1321 * the active portion. Hence following this formula seems
1322 * more trouble that it's worth.
1323 *
1324 * if (GRAPHICS_VER(dev_priv) == 4) {
1325 * num = cdclk * (tv_mode->oversample >> !tv_mode->progressive);
1326 * den = tv_mode->clock;
1327 * } else {
1328 * num = tv_mode->oversample >> !tv_mode->progressive;
1329 * den = 1;
1330 * }
1331 * max_pipe_vblank_len ~=
1332 * (num * tv_htotal * (tv_vblank_len + top_margin)) /
1333 * (den * pipe_htotal);
1334 */
1335 intel_tv_scale_mode_horiz(adjusted_mode, hdisplay,
1336 conn_state->tv.margins.left,
1337 conn_state->tv.margins.right);
1338 intel_tv_scale_mode_vert(adjusted_mode, vdisplay,
1339 tv_conn_state->margins.top,
1340 tv_conn_state->margins.bottom);
1341 drm_mode_set_crtcinfo(adjusted_mode, 0);
1342 adjusted_mode->name[0] = '\0';
1343
1344 /* pixel counter doesn't work on i965gm TV output */
1345 if (IS_I965GM(dev_priv))
1346 pipe_config->mode_flags |=
1347 I915_MODE_FLAG_USE_SCANLINE_COUNTER;
1348
1349 return 0;
1350 }
1351
1352 static void
set_tv_mode_timings(struct drm_i915_private * dev_priv,const struct tv_mode * tv_mode,bool burst_ena)1353 set_tv_mode_timings(struct drm_i915_private *dev_priv,
1354 const struct tv_mode *tv_mode,
1355 bool burst_ena)
1356 {
1357 u32 hctl1, hctl2, hctl3;
1358 u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;
1359
1360 hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) |
1361 (tv_mode->htotal << TV_HTOTAL_SHIFT);
1362
1363 hctl2 = (tv_mode->hburst_start << 16) |
1364 (tv_mode->hburst_len << TV_HBURST_LEN_SHIFT);
1365
1366 if (burst_ena)
1367 hctl2 |= TV_BURST_ENA;
1368
1369 hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) |
1370 (tv_mode->hblank_end << TV_HBLANK_END_SHIFT);
1371
1372 vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) |
1373 (tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) |
1374 (tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT);
1375
1376 vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) |
1377 (tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) |
1378 (tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT);
1379
1380 vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) |
1381 (tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) |
1382 (tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT);
1383
1384 if (tv_mode->veq_ena)
1385 vctl3 |= TV_EQUAL_ENA;
1386
1387 vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) |
1388 (tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT);
1389
1390 vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) |
1391 (tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT);
1392
1393 vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) |
1394 (tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT);
1395
1396 vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
1397 (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
1398
1399 intel_de_write(dev_priv, TV_H_CTL_1, hctl1);
1400 intel_de_write(dev_priv, TV_H_CTL_2, hctl2);
1401 intel_de_write(dev_priv, TV_H_CTL_3, hctl3);
1402 intel_de_write(dev_priv, TV_V_CTL_1, vctl1);
1403 intel_de_write(dev_priv, TV_V_CTL_2, vctl2);
1404 intel_de_write(dev_priv, TV_V_CTL_3, vctl3);
1405 intel_de_write(dev_priv, TV_V_CTL_4, vctl4);
1406 intel_de_write(dev_priv, TV_V_CTL_5, vctl5);
1407 intel_de_write(dev_priv, TV_V_CTL_6, vctl6);
1408 intel_de_write(dev_priv, TV_V_CTL_7, vctl7);
1409 }
1410
set_color_conversion(struct drm_i915_private * dev_priv,const struct color_conversion * color_conversion)1411 static void set_color_conversion(struct drm_i915_private *dev_priv,
1412 const struct color_conversion *color_conversion)
1413 {
1414 if (!color_conversion)
1415 return;
1416
1417 intel_de_write(dev_priv, TV_CSC_Y,
1418 (color_conversion->ry << 16) | color_conversion->gy);
1419 intel_de_write(dev_priv, TV_CSC_Y2,
1420 (color_conversion->by << 16) | color_conversion->ay);
1421 intel_de_write(dev_priv, TV_CSC_U,
1422 (color_conversion->ru << 16) | color_conversion->gu);
1423 intel_de_write(dev_priv, TV_CSC_U2,
1424 (color_conversion->bu << 16) | color_conversion->au);
1425 intel_de_write(dev_priv, TV_CSC_V,
1426 (color_conversion->rv << 16) | color_conversion->gv);
1427 intel_de_write(dev_priv, TV_CSC_V2,
1428 (color_conversion->bv << 16) | color_conversion->av);
1429 }
1430
intel_tv_pre_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)1431 static void intel_tv_pre_enable(struct intel_atomic_state *state,
1432 struct intel_encoder *encoder,
1433 const struct intel_crtc_state *pipe_config,
1434 const struct drm_connector_state *conn_state)
1435 {
1436 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1437 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1438 struct intel_tv *intel_tv = enc_to_tv(encoder);
1439 const struct intel_tv_connector_state *tv_conn_state =
1440 to_intel_tv_connector_state(conn_state);
1441 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
1442 u32 tv_ctl, tv_filter_ctl;
1443 u32 scctl1, scctl2, scctl3;
1444 int i, j;
1445 const struct video_levels *video_levels;
1446 const struct color_conversion *color_conversion;
1447 bool burst_ena;
1448 int xpos, ypos;
1449 unsigned int xsize, ysize;
1450
1451 if (!tv_mode)
1452 return; /* can't happen (mode_prepare prevents this) */
1453
1454 tv_ctl = intel_de_read(dev_priv, TV_CTL);
1455 tv_ctl &= TV_CTL_SAVE;
1456
1457 switch (intel_tv->type) {
1458 default:
1459 case DRM_MODE_CONNECTOR_Unknown:
1460 case DRM_MODE_CONNECTOR_Composite:
1461 tv_ctl |= TV_ENC_OUTPUT_COMPOSITE;
1462 video_levels = tv_mode->composite_levels;
1463 color_conversion = tv_mode->composite_color;
1464 burst_ena = tv_mode->burst_ena;
1465 break;
1466 case DRM_MODE_CONNECTOR_Component:
1467 tv_ctl |= TV_ENC_OUTPUT_COMPONENT;
1468 video_levels = &component_levels;
1469 if (tv_mode->burst_ena)
1470 color_conversion = &sdtv_csc_yprpb;
1471 else
1472 color_conversion = &hdtv_csc_yprpb;
1473 burst_ena = false;
1474 break;
1475 case DRM_MODE_CONNECTOR_SVIDEO:
1476 tv_ctl |= TV_ENC_OUTPUT_SVIDEO;
1477 video_levels = tv_mode->svideo_levels;
1478 color_conversion = tv_mode->svideo_color;
1479 burst_ena = tv_mode->burst_ena;
1480 break;
1481 }
1482
1483 tv_ctl |= TV_ENC_PIPE_SEL(crtc->pipe);
1484
1485 switch (tv_mode->oversample) {
1486 case 8:
1487 tv_ctl |= TV_OVERSAMPLE_8X;
1488 break;
1489 case 4:
1490 tv_ctl |= TV_OVERSAMPLE_4X;
1491 break;
1492 case 2:
1493 tv_ctl |= TV_OVERSAMPLE_2X;
1494 break;
1495 default:
1496 tv_ctl |= TV_OVERSAMPLE_NONE;
1497 break;
1498 }
1499
1500 if (tv_mode->progressive)
1501 tv_ctl |= TV_PROGRESSIVE;
1502 if (tv_mode->trilevel_sync)
1503 tv_ctl |= TV_TRILEVEL_SYNC;
1504 if (tv_mode->pal_burst)
1505 tv_ctl |= TV_PAL_BURST;
1506
1507 scctl1 = 0;
1508 if (tv_mode->dda1_inc)
1509 scctl1 |= TV_SC_DDA1_EN;
1510 if (tv_mode->dda2_inc)
1511 scctl1 |= TV_SC_DDA2_EN;
1512 if (tv_mode->dda3_inc)
1513 scctl1 |= TV_SC_DDA3_EN;
1514 scctl1 |= tv_mode->sc_reset;
1515 if (video_levels)
1516 scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT;
1517 scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT;
1518
1519 scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT |
1520 tv_mode->dda2_inc << TV_SCDDA2_INC_SHIFT;
1521
1522 scctl3 = tv_mode->dda3_size << TV_SCDDA3_SIZE_SHIFT |
1523 tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT;
1524
1525 /* Enable two fixes for the chips that need them. */
1526 if (IS_I915GM(dev_priv))
1527 tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
1528
1529 set_tv_mode_timings(dev_priv, tv_mode, burst_ena);
1530
1531 intel_de_write(dev_priv, TV_SC_CTL_1, scctl1);
1532 intel_de_write(dev_priv, TV_SC_CTL_2, scctl2);
1533 intel_de_write(dev_priv, TV_SC_CTL_3, scctl3);
1534
1535 set_color_conversion(dev_priv, color_conversion);
1536
1537 if (DISPLAY_VER(dev_priv) >= 4)
1538 intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00404000);
1539 else
1540 intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00606000);
1541
1542 if (video_levels)
1543 intel_de_write(dev_priv, TV_CLR_LEVEL,
1544 ((video_levels->black << TV_BLACK_LEVEL_SHIFT) | (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
1545
1546 assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);
1547
1548 /* Filter ctl must be set before TV_WIN_SIZE */
1549 tv_filter_ctl = TV_AUTO_SCALE;
1550 if (tv_conn_state->bypass_vfilter)
1551 tv_filter_ctl |= TV_V_FILTER_BYPASS;
1552 intel_de_write(dev_priv, TV_FILTER_CTL_1, tv_filter_ctl);
1553
1554 xsize = tv_mode->hblank_start - tv_mode->hblank_end;
1555 ysize = intel_tv_mode_vdisplay(tv_mode);
1556
1557 xpos = conn_state->tv.margins.left;
1558 ypos = tv_conn_state->margins.top;
1559 xsize -= (conn_state->tv.margins.left +
1560 conn_state->tv.margins.right);
1561 ysize -= (tv_conn_state->margins.top +
1562 tv_conn_state->margins.bottom);
1563 intel_de_write(dev_priv, TV_WIN_POS, (xpos << 16) | ypos);
1564 intel_de_write(dev_priv, TV_WIN_SIZE, (xsize << 16) | ysize);
1565
1566 j = 0;
1567 for (i = 0; i < 60; i++)
1568 intel_de_write(dev_priv, TV_H_LUMA(i),
1569 tv_mode->filter_table[j++]);
1570 for (i = 0; i < 60; i++)
1571 intel_de_write(dev_priv, TV_H_CHROMA(i),
1572 tv_mode->filter_table[j++]);
1573 for (i = 0; i < 43; i++)
1574 intel_de_write(dev_priv, TV_V_LUMA(i),
1575 tv_mode->filter_table[j++]);
1576 for (i = 0; i < 43; i++)
1577 intel_de_write(dev_priv, TV_V_CHROMA(i),
1578 tv_mode->filter_table[j++]);
1579 intel_de_write(dev_priv, TV_DAC,
1580 intel_de_read(dev_priv, TV_DAC) & TV_DAC_SAVE);
1581 intel_de_write(dev_priv, TV_CTL, tv_ctl);
1582 }
1583
1584 static int
intel_tv_detect_type(struct intel_tv * intel_tv,struct drm_connector * connector)1585 intel_tv_detect_type(struct intel_tv *intel_tv,
1586 struct drm_connector *connector)
1587 {
1588 struct intel_crtc *crtc = to_intel_crtc(connector->state->crtc);
1589 struct drm_device *dev = connector->dev;
1590 struct drm_i915_private *dev_priv = to_i915(dev);
1591 u32 tv_ctl, save_tv_ctl;
1592 u32 tv_dac, save_tv_dac;
1593 int type;
1594
1595 /* Disable TV interrupts around load detect or we'll recurse */
1596 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
1597 spin_lock_irq(&dev_priv->irq_lock);
1598 i915_disable_pipestat(dev_priv, 0,
1599 PIPE_HOTPLUG_INTERRUPT_STATUS |
1600 PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
1601 spin_unlock_irq(&dev_priv->irq_lock);
1602 }
1603
1604 save_tv_dac = tv_dac = intel_de_read(dev_priv, TV_DAC);
1605 save_tv_ctl = tv_ctl = intel_de_read(dev_priv, TV_CTL);
1606
1607 /* Poll for TV detection */
1608 tv_ctl &= ~(TV_ENC_ENABLE | TV_ENC_PIPE_SEL_MASK | TV_TEST_MODE_MASK);
1609 tv_ctl |= TV_TEST_MODE_MONITOR_DETECT;
1610 tv_ctl |= TV_ENC_PIPE_SEL(crtc->pipe);
1611
1612 tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK);
1613 tv_dac |= (TVDAC_STATE_CHG_EN |
1614 TVDAC_A_SENSE_CTL |
1615 TVDAC_B_SENSE_CTL |
1616 TVDAC_C_SENSE_CTL |
1617 DAC_CTL_OVERRIDE |
1618 DAC_A_0_7_V |
1619 DAC_B_0_7_V |
1620 DAC_C_0_7_V);
1621
1622
1623 /*
1624 * The TV sense state should be cleared to zero on cantiga platform. Otherwise
1625 * the TV is misdetected. This is hardware requirement.
1626 */
1627 if (IS_GM45(dev_priv))
1628 tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL |
1629 TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);
1630
1631 intel_de_write(dev_priv, TV_CTL, tv_ctl);
1632 intel_de_write(dev_priv, TV_DAC, tv_dac);
1633 intel_de_posting_read(dev_priv, TV_DAC);
1634
1635 intel_crtc_wait_for_next_vblank(crtc);
1636
1637 type = -1;
1638 tv_dac = intel_de_read(dev_priv, TV_DAC);
1639 drm_dbg_kms(&dev_priv->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac);
1640 /*
1641 * A B C
1642 * 0 1 1 Composite
1643 * 1 0 X svideo
1644 * 0 0 0 Component
1645 */
1646 if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) {
1647 drm_dbg_kms(&dev_priv->drm,
1648 "Detected Composite TV connection\n");
1649 type = DRM_MODE_CONNECTOR_Composite;
1650 } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) {
1651 drm_dbg_kms(&dev_priv->drm,
1652 "Detected S-Video TV connection\n");
1653 type = DRM_MODE_CONNECTOR_SVIDEO;
1654 } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) {
1655 drm_dbg_kms(&dev_priv->drm,
1656 "Detected Component TV connection\n");
1657 type = DRM_MODE_CONNECTOR_Component;
1658 } else {
1659 drm_dbg_kms(&dev_priv->drm, "Unrecognised TV connection\n");
1660 type = -1;
1661 }
1662
1663 intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1664 intel_de_write(dev_priv, TV_CTL, save_tv_ctl);
1665 intel_de_posting_read(dev_priv, TV_CTL);
1666
1667 /* For unknown reasons the hw barfs if we don't do this vblank wait. */
1668 intel_crtc_wait_for_next_vblank(crtc);
1669
1670 /* Restore interrupt config */
1671 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
1672 spin_lock_irq(&dev_priv->irq_lock);
1673 i915_enable_pipestat(dev_priv, 0,
1674 PIPE_HOTPLUG_INTERRUPT_STATUS |
1675 PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
1676 spin_unlock_irq(&dev_priv->irq_lock);
1677 }
1678
1679 return type;
1680 }
1681
1682 /*
1683 * Here we set accurate tv format according to connector type
1684 * i.e Component TV should not be assigned by NTSC or PAL
1685 */
intel_tv_find_better_format(struct drm_connector * connector)1686 static void intel_tv_find_better_format(struct drm_connector *connector)
1687 {
1688 struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector));
1689 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
1690 int i;
1691
1692 /* Component supports everything so we can keep the current mode */
1693 if (intel_tv->type == DRM_MODE_CONNECTOR_Component)
1694 return;
1695
1696 /* If the current mode is fine don't change it */
1697 if (!tv_mode->component_only)
1698 return;
1699
1700 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
1701 tv_mode = &tv_modes[i];
1702
1703 if (!tv_mode->component_only)
1704 break;
1705 }
1706
1707 connector->state->tv.mode = i;
1708 }
1709
1710 static int
intel_tv_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)1711 intel_tv_detect(struct drm_connector *connector,
1712 struct drm_modeset_acquire_ctx *ctx,
1713 bool force)
1714 {
1715 struct drm_i915_private *i915 = to_i915(connector->dev);
1716 struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector));
1717 enum drm_connector_status status;
1718 int type;
1719
1720 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] force=%d\n",
1721 connector->base.id, connector->name, force);
1722
1723 if (!INTEL_DISPLAY_ENABLED(i915))
1724 return connector_status_disconnected;
1725
1726 if (force) {
1727 struct drm_atomic_state *state;
1728
1729 state = intel_load_detect_get_pipe(connector, ctx);
1730 if (IS_ERR(state))
1731 return PTR_ERR(state);
1732
1733 if (state) {
1734 type = intel_tv_detect_type(intel_tv, connector);
1735 intel_load_detect_release_pipe(connector, state, ctx);
1736 status = type < 0 ?
1737 connector_status_disconnected :
1738 connector_status_connected;
1739 } else {
1740 status = connector_status_unknown;
1741 }
1742
1743 if (status == connector_status_connected) {
1744 intel_tv->type = type;
1745 intel_tv_find_better_format(connector);
1746 }
1747
1748 return status;
1749 } else
1750 return connector->status;
1751 }
1752
1753 static const struct input_res {
1754 u16 w, h;
1755 } input_res_table[] = {
1756 { 640, 480 },
1757 { 800, 600 },
1758 { 1024, 768 },
1759 { 1280, 1024 },
1760 { 848, 480 },
1761 { 1280, 720 },
1762 { 1920, 1080 },
1763 };
1764
1765 /* Choose preferred mode according to line number of TV format */
1766 static bool
intel_tv_is_preferred_mode(const struct drm_display_mode * mode,const struct tv_mode * tv_mode)1767 intel_tv_is_preferred_mode(const struct drm_display_mode *mode,
1768 const struct tv_mode *tv_mode)
1769 {
1770 int vdisplay = intel_tv_mode_vdisplay(tv_mode);
1771
1772 /* prefer 480 line modes for all SD TV modes */
1773 if (vdisplay <= 576)
1774 vdisplay = 480;
1775
1776 return vdisplay == mode->vdisplay;
1777 }
1778
1779 static void
intel_tv_set_mode_type(struct drm_display_mode * mode,const struct tv_mode * tv_mode)1780 intel_tv_set_mode_type(struct drm_display_mode *mode,
1781 const struct tv_mode *tv_mode)
1782 {
1783 mode->type = DRM_MODE_TYPE_DRIVER;
1784
1785 if (intel_tv_is_preferred_mode(mode, tv_mode))
1786 mode->type |= DRM_MODE_TYPE_PREFERRED;
1787 }
1788
1789 static int
intel_tv_get_modes(struct drm_connector * connector)1790 intel_tv_get_modes(struct drm_connector *connector)
1791 {
1792 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1793 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
1794 int i, count = 0;
1795
1796 for (i = 0; i < ARRAY_SIZE(input_res_table); i++) {
1797 const struct input_res *input = &input_res_table[i];
1798 struct drm_display_mode *mode;
1799
1800 if (input->w > 1024 &&
1801 !tv_mode->progressive &&
1802 !tv_mode->component_only)
1803 continue;
1804
1805 /* no vertical scaling with wide sources on gen3 */
1806 if (DISPLAY_VER(dev_priv) == 3 && input->w > 1024 &&
1807 input->h > intel_tv_mode_vdisplay(tv_mode))
1808 continue;
1809
1810 mode = drm_mode_create(connector->dev);
1811 if (!mode)
1812 continue;
1813
1814 /*
1815 * We take the TV mode and scale it to look
1816 * like it had the expected h/vdisplay. This
1817 * provides the most information to userspace
1818 * about the actual timings of the mode. We
1819 * do ignore the margins though.
1820 */
1821 intel_tv_mode_to_mode(mode, tv_mode, tv_mode->clock);
1822 if (count == 0) {
1823 drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n",
1824 DRM_MODE_ARG(mode));
1825 }
1826 intel_tv_scale_mode_horiz(mode, input->w, 0, 0);
1827 intel_tv_scale_mode_vert(mode, input->h, 0, 0);
1828 intel_tv_set_mode_type(mode, tv_mode);
1829
1830 drm_mode_set_name(mode);
1831
1832 drm_mode_probed_add(connector, mode);
1833 count++;
1834 }
1835
1836 return count;
1837 }
1838
1839 static const struct drm_connector_funcs intel_tv_connector_funcs = {
1840 .late_register = intel_connector_register,
1841 .early_unregister = intel_connector_unregister,
1842 .destroy = intel_connector_destroy,
1843 .fill_modes = drm_helper_probe_single_connector_modes,
1844 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1845 .atomic_duplicate_state = intel_tv_connector_duplicate_state,
1846 };
1847
intel_tv_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)1848 static int intel_tv_atomic_check(struct drm_connector *connector,
1849 struct drm_atomic_state *state)
1850 {
1851 struct drm_connector_state *new_state;
1852 struct drm_crtc_state *new_crtc_state;
1853 struct drm_connector_state *old_state;
1854
1855 new_state = drm_atomic_get_new_connector_state(state, connector);
1856 if (!new_state->crtc)
1857 return 0;
1858
1859 old_state = drm_atomic_get_old_connector_state(state, connector);
1860 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);
1861
1862 if (old_state->tv.mode != new_state->tv.mode ||
1863 old_state->tv.margins.left != new_state->tv.margins.left ||
1864 old_state->tv.margins.right != new_state->tv.margins.right ||
1865 old_state->tv.margins.top != new_state->tv.margins.top ||
1866 old_state->tv.margins.bottom != new_state->tv.margins.bottom) {
1867 /* Force a modeset. */
1868
1869 new_crtc_state->connectors_changed = true;
1870 }
1871
1872 return 0;
1873 }
1874
1875 static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = {
1876 .detect_ctx = intel_tv_detect,
1877 .mode_valid = intel_tv_mode_valid,
1878 .get_modes = intel_tv_get_modes,
1879 .atomic_check = intel_tv_atomic_check,
1880 };
1881
1882 static const struct drm_encoder_funcs intel_tv_enc_funcs = {
1883 .destroy = intel_encoder_destroy,
1884 };
1885
intel_tv_add_properties(struct drm_connector * connector)1886 static void intel_tv_add_properties(struct drm_connector *connector)
1887 {
1888 struct drm_i915_private *i915 = to_i915(connector->dev);
1889 struct drm_connector_state *conn_state = connector->state;
1890 const char *tv_format_names[ARRAY_SIZE(tv_modes)];
1891 int i;
1892
1893 /* BIOS margin values */
1894 conn_state->tv.margins.left = 54;
1895 conn_state->tv.margins.top = 36;
1896 conn_state->tv.margins.right = 46;
1897 conn_state->tv.margins.bottom = 37;
1898
1899 conn_state->tv.mode = 0;
1900
1901 /* Create TV properties then attach current values */
1902 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
1903 /* 1080p50/1080p60 not supported on gen3 */
1904 if (DISPLAY_VER(i915) == 3 && tv_modes[i].oversample == 1)
1905 break;
1906
1907 tv_format_names[i] = tv_modes[i].name;
1908 }
1909 drm_mode_create_tv_properties_legacy(&i915->drm, i, tv_format_names);
1910
1911 drm_object_attach_property(&connector->base,
1912 i915->drm.mode_config.legacy_tv_mode_property,
1913 conn_state->tv.mode);
1914 drm_object_attach_property(&connector->base,
1915 i915->drm.mode_config.tv_left_margin_property,
1916 conn_state->tv.margins.left);
1917 drm_object_attach_property(&connector->base,
1918 i915->drm.mode_config.tv_top_margin_property,
1919 conn_state->tv.margins.top);
1920 drm_object_attach_property(&connector->base,
1921 i915->drm.mode_config.tv_right_margin_property,
1922 conn_state->tv.margins.right);
1923 drm_object_attach_property(&connector->base,
1924 i915->drm.mode_config.tv_bottom_margin_property,
1925 conn_state->tv.margins.bottom);
1926 }
1927
1928 void
intel_tv_init(struct drm_i915_private * dev_priv)1929 intel_tv_init(struct drm_i915_private *dev_priv)
1930 {
1931 struct drm_connector *connector;
1932 struct intel_tv *intel_tv;
1933 struct intel_encoder *intel_encoder;
1934 struct intel_connector *intel_connector;
1935 u32 tv_dac_on, tv_dac_off, save_tv_dac;
1936
1937 if ((intel_de_read(dev_priv, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
1938 return;
1939
1940 if (!intel_bios_is_tv_present(dev_priv)) {
1941 drm_dbg_kms(&dev_priv->drm, "Integrated TV is not present.\n");
1942 return;
1943 }
1944
1945 /*
1946 * Sanity check the TV output by checking to see if the
1947 * DAC register holds a value
1948 */
1949 save_tv_dac = intel_de_read(dev_priv, TV_DAC);
1950
1951 intel_de_write(dev_priv, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
1952 tv_dac_on = intel_de_read(dev_priv, TV_DAC);
1953
1954 intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1955 tv_dac_off = intel_de_read(dev_priv, TV_DAC);
1956
1957 intel_de_write(dev_priv, TV_DAC, save_tv_dac);
1958
1959 /*
1960 * If the register does not hold the state change enable
1961 * bit, (either as a 0 or a 1), assume it doesn't really
1962 * exist
1963 */
1964 if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 ||
1965 (tv_dac_off & TVDAC_STATE_CHG_EN) != 0)
1966 return;
1967
1968 intel_tv = kzalloc(sizeof(*intel_tv), GFP_KERNEL);
1969 if (!intel_tv) {
1970 return;
1971 }
1972
1973 intel_connector = intel_connector_alloc();
1974 if (!intel_connector) {
1975 kfree(intel_tv);
1976 return;
1977 }
1978
1979 intel_encoder = &intel_tv->base;
1980 connector = &intel_connector->base;
1981
1982 /*
1983 * The documentation, for the older chipsets at least, recommend
1984 * using a polling method rather than hotplug detection for TVs.
1985 * This is because in order to perform the hotplug detection, the PLLs
1986 * for the TV must be kept alive increasing power drain and starving
1987 * bandwidth from other encoders. Notably for instance, it causes
1988 * pipe underruns on Crestline when this encoder is supposedly idle.
1989 *
1990 * More recent chipsets favour HDMI rather than integrated S-Video.
1991 */
1992 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1993
1994 drm_connector_init(&dev_priv->drm, connector, &intel_tv_connector_funcs,
1995 DRM_MODE_CONNECTOR_SVIDEO);
1996
1997 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, &intel_tv_enc_funcs,
1998 DRM_MODE_ENCODER_TVDAC, "TV");
1999
2000 intel_encoder->compute_config = intel_tv_compute_config;
2001 intel_encoder->get_config = intel_tv_get_config;
2002 intel_encoder->pre_enable = intel_tv_pre_enable;
2003 intel_encoder->enable = intel_enable_tv;
2004 intel_encoder->disable = intel_disable_tv;
2005 intel_encoder->get_hw_state = intel_tv_get_hw_state;
2006 intel_connector->get_hw_state = intel_connector_get_hw_state;
2007
2008 intel_connector_attach_encoder(intel_connector, intel_encoder);
2009
2010 intel_encoder->type = INTEL_OUTPUT_TVOUT;
2011 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
2012 intel_encoder->port = PORT_NONE;
2013 intel_encoder->pipe_mask = ~0;
2014 intel_encoder->cloneable = 0;
2015 intel_tv->type = DRM_MODE_CONNECTOR_Unknown;
2016
2017 drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs);
2018
2019 intel_tv_add_properties(connector);
2020 }
2021
