1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef MBOX_H 9 #define MBOX_H 10 11 #include <linux/etherdevice.h> 12 #include <linux/sizes.h> 13 14 #include "rvu_struct.h" 15 #include "common.h" 16 17 #define MBOX_SIZE SZ_64K 18 19 /* AF/PF: PF initiated, PF/VF VF initiated */ 20 #define MBOX_DOWN_RX_START 0 21 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 22 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 23 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 24 /* AF/PF: AF initiated, PF/VF PF initiated */ 25 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 26 #define MBOX_UP_RX_SIZE SZ_1K 27 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 28 #define MBOX_UP_TX_SIZE SZ_1K 29 30 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 31 # error "incorrect mailbox area sizes" 32 #endif 33 34 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 35 36 #define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */ 37 38 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 39 40 /* Mailbox directions */ 41 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 42 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 43 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 44 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 45 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 46 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 47 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 48 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 49 50 struct otx2_mbox_dev { 51 void *mbase; /* This dev's mbox region */ 52 void *hwbase; 53 spinlock_t mbox_lock; 54 u16 msg_size; /* Total msg size to be sent */ 55 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 56 u16 num_msgs; /* No of msgs sent or waiting for response */ 57 u16 msgs_acked; /* No of msgs for which response is received */ 58 }; 59 60 struct otx2_mbox { 61 struct pci_dev *pdev; 62 void *hwbase; /* Mbox region advertised by HW */ 63 void *reg_base;/* CSR base for this dev */ 64 u64 trigger; /* Trigger mbox notification */ 65 u16 tr_shift; /* Mbox trigger shift */ 66 u64 rx_start; /* Offset of Rx region in mbox memory */ 67 u64 tx_start; /* Offset of Tx region in mbox memory */ 68 u16 rx_size; /* Size of Rx region */ 69 u16 tx_size; /* Size of Tx region */ 70 u16 ndevs; /* The number of peers */ 71 struct otx2_mbox_dev *dev; 72 }; 73 74 /* Header which precedes all mbox messages */ 75 struct mbox_hdr { 76 u64 msg_size; /* Total msgs size embedded */ 77 u16 num_msgs; /* No of msgs embedded */ 78 }; 79 80 /* Header which precedes every msg and is also part of it */ 81 struct mbox_msghdr { 82 u16 pcifunc; /* Who's sending this msg */ 83 u16 id; /* Mbox message ID */ 84 #define OTX2_MBOX_REQ_SIG (0xdead) 85 #define OTX2_MBOX_RSP_SIG (0xbeef) 86 u16 sig; /* Signature, for validating corrupted msgs */ 87 #define OTX2_MBOX_VERSION (0x000a) 88 u16 ver; /* Version of msg's structure for this ID */ 89 u16 next_msgoff; /* Offset of next msg within mailbox region */ 90 int rc; /* Msg process'ed response code */ 91 }; 92 93 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 94 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 95 void otx2_mbox_destroy(struct otx2_mbox *mbox); 96 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 97 struct pci_dev *pdev, void __force *reg_base, 98 int direction, int ndevs); 99 100 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 101 struct pci_dev *pdev, void __force *reg_base, 102 int direction, int ndevs, unsigned long *bmap); 103 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 104 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 105 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 106 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 107 int size, int size_rsp); 108 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 109 struct mbox_msghdr *msg); 110 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 111 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 112 u16 pcifunc, u16 id); 113 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 114 const char *otx2_mbox_id2name(u16 id); otx2_mbox_alloc_msg(struct otx2_mbox * mbox,int devid,int size)115 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 116 int devid, int size) 117 { 118 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 119 } 120 121 /* Mailbox message types */ 122 #define MBOX_MSG_MASK 0xFFFF 123 #define MBOX_MSG_INVALID 0xFFFE 124 #define MBOX_MSG_MAX 0xFFFF 125 126 #define MBOX_MESSAGES \ 127 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 128 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 129 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 130 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 131 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \ 132 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 133 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 134 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 135 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 136 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \ 137 msg_rsp) \ 138 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ 139 M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \ 140 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 141 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 142 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 143 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 144 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 145 cgx_mac_addr_set_or_get) \ 146 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 147 cgx_mac_addr_set_or_get) \ 148 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 149 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 150 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 151 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 152 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 153 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 154 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 155 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 156 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 157 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 158 cgx_pause_frm_cfg) \ 159 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 160 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 161 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \ 162 cgx_mac_addr_add_rsp) \ 163 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \ 164 msg_rsp) \ 165 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \ 166 cgx_max_dmac_entries_get_rsp) \ 167 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 168 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\ 169 cgx_set_link_mode_rsp) \ 170 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 171 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \ 172 cgx_features_info_msg) \ 173 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \ 174 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \ 175 msg_rsp) \ 176 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \ 177 cgx_mac_addr_update_rsp) \ 178 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \ 179 cgx_pfc_rsp) \ 180 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 181 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 182 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 183 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 184 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 185 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 186 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 187 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 188 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 189 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 190 msg_rsp) \ 191 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 192 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 193 cpt_rd_wr_reg_msg) \ 194 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \ 195 cpt_inline_ipsec_cfg_msg, msg_rsp) \ 196 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \ 197 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ 198 msg_rsp) \ 199 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \ 200 M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \ 201 M(CPT_FLT_ENG_INFO, 0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req, \ 202 cpt_flt_eng_info_rsp) \ 203 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \ 204 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \ 205 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \ 206 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 207 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 208 npc_mcam_alloc_entry_rsp) \ 209 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 210 npc_mcam_free_entry_req, msg_rsp) \ 211 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 212 npc_mcam_write_entry_req, msg_rsp) \ 213 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 214 npc_mcam_ena_dis_entry_req, msg_rsp) \ 215 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 216 npc_mcam_ena_dis_entry_req, msg_rsp) \ 217 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 218 npc_mcam_shift_entry_rsp) \ 219 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 220 npc_mcam_alloc_counter_req, \ 221 npc_mcam_alloc_counter_rsp) \ 222 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 223 npc_mcam_oper_counter_req, msg_rsp) \ 224 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 225 npc_mcam_unmap_counter_req, msg_rsp) \ 226 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 227 npc_mcam_oper_counter_req, msg_rsp) \ 228 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 229 npc_mcam_oper_counter_req, \ 230 npc_mcam_oper_counter_rsp) \ 231 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 232 npc_mcam_alloc_and_write_entry_req, \ 233 npc_mcam_alloc_and_write_entry_rsp) \ 234 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 235 msg_req, npc_get_kex_cfg_rsp) \ 236 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 237 npc_install_flow_req, npc_install_flow_rsp) \ 238 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 239 npc_delete_flow_req, npc_delete_flow_rsp) \ 240 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 241 npc_mcam_read_entry_req, \ 242 npc_mcam_read_entry_rsp) \ 243 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \ 244 npc_set_pkind, msg_rsp) \ 245 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 246 msg_req, npc_mcam_read_base_rule_rsp) \ 247 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 248 npc_mcam_get_stats_req, \ 249 npc_mcam_get_stats_rsp) \ 250 M(NPC_GET_FIELD_HASH_INFO, 0x6013, npc_get_field_hash_info, \ 251 npc_get_field_hash_info_req, \ 252 npc_get_field_hash_info_rsp) \ 253 M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \ 254 npc_get_field_status_req, \ 255 npc_get_field_status_rsp) \ 256 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 257 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 258 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 259 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 260 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 261 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 262 hwctx_disable_req, msg_rsp) \ 263 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 264 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 265 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 266 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \ 267 nix_txschq_config) \ 268 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 269 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 270 nix_vtag_config_rsp) \ 271 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 272 nix_rss_flowkey_cfg, \ 273 nix_rss_flowkey_cfg_rsp) \ 274 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 275 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 276 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 277 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 278 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 279 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 280 nix_mark_format_cfg, \ 281 nix_mark_format_cfg_rsp) \ 282 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 283 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 284 nix_lso_format_cfg, \ 285 nix_lso_format_cfg_rsp) \ 286 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 287 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 288 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 289 nix_bp_cfg_rsp) \ 290 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 291 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 292 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \ 293 nix_inline_ipsec_cfg, msg_rsp) \ 294 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \ 295 nix_inline_ipsec_lf_cfg, msg_rsp) \ 296 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 297 nix_cn10k_aq_enq_rsp) \ 298 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ 299 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \ 300 nix_bandprof_alloc_rsp) \ 301 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ 302 msg_rsp) \ 303 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \ 304 nix_bandprof_get_hwinfo_rsp) \ 305 M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \ 306 msg_req, nix_inline_ipsec_cfg) \ 307 /* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \ 308 M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ 309 mcs_alloc_rsrc_rsp) \ 310 M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \ 311 M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \ 312 msg_rsp) \ 313 M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \ 314 msg_rsp) \ 315 M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \ 316 msg_rsp) \ 317 M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \ 318 msg_rsp) \ 319 M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \ 320 msg_rsp) \ 321 M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \ 322 msg_rsp) \ 323 M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \ 324 msg_rsp) \ 325 M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \ 326 msg_rsp) \ 327 M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \ 328 msg_rsp) \ 329 M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ 330 M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \ 331 mcs_flowid_stats) \ 332 M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \ 333 mcs_secy_stats) \ 334 M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \ 335 M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \ 336 M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \ 337 mcs_port_stats) \ 338 M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \ 339 M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \ 340 M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \ 341 M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \ 342 msg_rsp) \ 343 M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \ 344 mcs_alloc_ctrl_pkt_rule_req, \ 345 mcs_alloc_ctrl_pkt_rule_rsp) \ 346 M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \ 347 mcs_free_ctrl_pkt_rule_req, msg_rsp) \ 348 M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \ 349 mcs_ctrl_pkt_rule_write_req, msg_rsp) \ 350 M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \ 351 M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\ 352 M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \ 353 mcs_port_cfg_get_rsp) \ 354 M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \ 355 mcs_custom_tag_cfg_get_req, \ 356 mcs_custom_tag_cfg_get_rsp) 357 358 /* Messages initiated by AF (range 0xC00 - 0xEFF) */ 359 #define MBOX_UP_CGX_MESSAGES \ 360 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 361 362 #define MBOX_UP_CPT_MESSAGES \ 363 M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp) 364 365 #define MBOX_UP_MCS_MESSAGES \ 366 M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp) 367 368 enum { 369 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 370 MBOX_MESSAGES 371 MBOX_UP_CGX_MESSAGES 372 MBOX_UP_CPT_MESSAGES 373 MBOX_UP_MCS_MESSAGES 374 #undef M 375 }; 376 377 /* Mailbox message formats */ 378 379 #define RVU_DEFAULT_PF_FUNC 0xFFFF 380 381 /* Generic request msg used for those mbox messages which 382 * don't send any data in the request. 383 */ 384 struct msg_req { 385 struct mbox_msghdr hdr; 386 }; 387 388 /* Generic response msg used an ack or response for those mbox 389 * messages which don't have a specific rsp msg format. 390 */ 391 struct msg_rsp { 392 struct mbox_msghdr hdr; 393 }; 394 395 /* RVU mailbox error codes 396 * Range 256 - 300. 397 */ 398 enum rvu_af_status { 399 RVU_INVALID_VF_ID = -256, 400 }; 401 402 struct ready_msg_rsp { 403 struct mbox_msghdr hdr; 404 u16 sclk_freq; /* SCLK frequency (in MHz) */ 405 u16 rclk_freq; /* RCLK frequency (in MHz) */ 406 }; 407 408 /* Structure for requesting resource provisioning. 409 * 'modify' flag to be used when either requesting more 410 * or to detach partial of a certain resource type. 411 * Rest of the fields specify how many of what type to 412 * be attached. 413 * To request LFs from two blocks of same type this mailbox 414 * can be sent twice as below: 415 * struct rsrc_attach *attach; 416 * .. Allocate memory for message .. 417 * attach->cptlfs = 3; <3 LFs from CPT0> 418 * .. Send message .. 419 * .. Allocate memory for message .. 420 * attach->modify = 1; 421 * attach->cpt_blkaddr = BLKADDR_CPT1; 422 * attach->cptlfs = 2; <2 LFs from CPT1> 423 * .. Send message .. 424 */ 425 struct rsrc_attach { 426 struct mbox_msghdr hdr; 427 u8 modify:1; 428 u8 npalf:1; 429 u8 nixlf:1; 430 u16 sso; 431 u16 ssow; 432 u16 timlfs; 433 u16 cptlfs; 434 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 435 }; 436 437 /* Structure for relinquishing resources. 438 * 'partial' flag to be used when relinquishing all resources 439 * but only of a certain type. If not set, all resources of all 440 * types provisioned to the RVU function will be detached. 441 */ 442 struct rsrc_detach { 443 struct mbox_msghdr hdr; 444 u8 partial:1; 445 u8 npalf:1; 446 u8 nixlf:1; 447 u8 sso:1; 448 u8 ssow:1; 449 u8 timlfs:1; 450 u8 cptlfs:1; 451 }; 452 453 /* Number of resources available to the caller. 454 * In reply to MBOX_MSG_FREE_RSRC_CNT. 455 */ 456 struct free_rsrcs_rsp { 457 struct mbox_msghdr hdr; 458 u16 schq[NIX_TXSCH_LVL_CNT]; 459 u16 sso; 460 u16 tim; 461 u16 ssow; 462 u16 cpt; 463 u8 npa; 464 u8 nix; 465 u16 schq_nix1[NIX_TXSCH_LVL_CNT]; 466 u8 nix1; 467 u8 cpt1; 468 u8 ree0; 469 u8 ree1; 470 }; 471 472 #define MSIX_VECTOR_INVALID 0xFFFF 473 #define MAX_RVU_BLKLF_CNT 256 474 475 struct msix_offset_rsp { 476 struct mbox_msghdr hdr; 477 u16 npa_msixoff; 478 u16 nix_msixoff; 479 u16 sso; 480 u16 ssow; 481 u16 timlfs; 482 u16 cptlfs; 483 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 484 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 485 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 486 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 487 u16 cpt1_lfs; 488 u16 ree0_lfs; 489 u16 ree1_lfs; 490 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 491 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT]; 492 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 493 }; 494 495 struct get_hw_cap_rsp { 496 struct mbox_msghdr hdr; 497 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 498 u8 nix_shaping; /* Is shaping and coloring supported */ 499 u8 npc_hash_extract; /* Is hash extract supported */ 500 }; 501 502 /* CGX mbox message formats */ 503 504 struct cgx_stats_rsp { 505 struct mbox_msghdr hdr; 506 #define CGX_RX_STATS_COUNT 9 507 #define CGX_TX_STATS_COUNT 18 508 u64 rx_stats[CGX_RX_STATS_COUNT]; 509 u64 tx_stats[CGX_TX_STATS_COUNT]; 510 }; 511 512 struct cgx_fec_stats_rsp { 513 struct mbox_msghdr hdr; 514 u64 fec_corr_blks; 515 u64 fec_uncorr_blks; 516 }; 517 /* Structure for requesting the operation for 518 * setting/getting mac address in the CGX interface 519 */ 520 struct cgx_mac_addr_set_or_get { 521 struct mbox_msghdr hdr; 522 u8 mac_addr[ETH_ALEN]; 523 u32 index; 524 }; 525 526 /* Structure for requesting the operation to 527 * add DMAC filter entry into CGX interface 528 */ 529 struct cgx_mac_addr_add_req { 530 struct mbox_msghdr hdr; 531 u8 mac_addr[ETH_ALEN]; 532 }; 533 534 /* Structure for response against the operation to 535 * add DMAC filter entry into CGX interface 536 */ 537 struct cgx_mac_addr_add_rsp { 538 struct mbox_msghdr hdr; 539 u32 index; 540 }; 541 542 /* Structure for requesting the operation to 543 * delete DMAC filter entry from CGX interface 544 */ 545 struct cgx_mac_addr_del_req { 546 struct mbox_msghdr hdr; 547 u32 index; 548 }; 549 550 /* Structure for response against the operation to 551 * get maximum supported DMAC filter entries 552 */ 553 struct cgx_max_dmac_entries_get_rsp { 554 struct mbox_msghdr hdr; 555 u32 max_dmac_filters; 556 }; 557 558 struct cgx_link_user_info { 559 uint64_t link_up:1; 560 uint64_t full_duplex:1; 561 uint64_t lmac_type_id:4; 562 uint64_t speed:20; /* speed in Mbps */ 563 uint64_t an:1; /* AN supported or not */ 564 uint64_t fec:2; /* FEC type if enabled else 0 */ 565 #define LMACTYPE_STR_LEN 16 566 char lmac_type[LMACTYPE_STR_LEN]; 567 }; 568 569 struct cgx_link_info_msg { 570 struct mbox_msghdr hdr; 571 struct cgx_link_user_info link_info; 572 }; 573 574 struct cgx_pause_frm_cfg { 575 struct mbox_msghdr hdr; 576 u8 set; 577 /* set = 1 if the request is to config pause frames */ 578 /* set = 0 if the request is to fetch pause frames config */ 579 u8 rx_pause; 580 u8 tx_pause; 581 }; 582 583 enum fec_type { 584 OTX2_FEC_NONE, 585 OTX2_FEC_BASER, 586 OTX2_FEC_RS, 587 OTX2_FEC_STATS_CNT = 2, 588 OTX2_FEC_OFF, 589 }; 590 591 struct fec_mode { 592 struct mbox_msghdr hdr; 593 int fec; 594 }; 595 596 struct sfp_eeprom_s { 597 #define SFP_EEPROM_SIZE 256 598 u16 sff_id; 599 u8 buf[SFP_EEPROM_SIZE]; 600 u64 reserved; 601 }; 602 603 struct phy_s { 604 struct { 605 u64 can_change_mod_type:1; 606 u64 mod_type:1; 607 u64 has_fec_stats:1; 608 } misc; 609 struct fec_stats_s { 610 u32 rsfec_corr_cws; 611 u32 rsfec_uncorr_cws; 612 u32 brfec_corr_blks; 613 u32 brfec_uncorr_blks; 614 } fec_stats; 615 }; 616 617 struct cgx_lmac_fwdata_s { 618 u16 rw_valid; 619 u64 supported_fec; 620 u64 supported_an; 621 u64 supported_link_modes; 622 /* only applicable if AN is supported */ 623 u64 advertised_fec; 624 u64 advertised_link_modes; 625 /* Only applicable if SFP/QSFP slot is present */ 626 struct sfp_eeprom_s sfp_eeprom; 627 struct phy_s phy; 628 #define LMAC_FWDATA_RESERVED_MEM 1021 629 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 630 }; 631 632 struct cgx_fw_data { 633 struct mbox_msghdr hdr; 634 struct cgx_lmac_fwdata_s fwdata; 635 }; 636 637 struct cgx_set_link_mode_args { 638 u32 speed; 639 u8 duplex; 640 u8 an; 641 u8 ports; 642 u64 mode; 643 }; 644 645 struct cgx_set_link_mode_req { 646 #define AUTONEG_UNKNOWN 0xff 647 struct mbox_msghdr hdr; 648 struct cgx_set_link_mode_args args; 649 }; 650 651 struct cgx_set_link_mode_rsp { 652 struct mbox_msghdr hdr; 653 int status; 654 }; 655 656 struct cgx_mac_addr_reset_req { 657 struct mbox_msghdr hdr; 658 u32 index; 659 }; 660 661 struct cgx_mac_addr_update_req { 662 struct mbox_msghdr hdr; 663 u8 mac_addr[ETH_ALEN]; 664 u32 index; 665 }; 666 667 struct cgx_mac_addr_update_rsp { 668 struct mbox_msghdr hdr; 669 u32 index; 670 }; 671 672 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 673 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1) 674 /* flow control from physical link higig2 messages */ 675 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */ 676 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */ 677 #define RVU_MAC_VERSION BIT_ULL(4) 678 #define RVU_MAC_CGX BIT_ULL(5) 679 #define RVU_MAC_RPM BIT_ULL(6) 680 681 struct cgx_features_info_msg { 682 struct mbox_msghdr hdr; 683 u64 lmac_features; 684 }; 685 686 struct rpm_stats_rsp { 687 struct mbox_msghdr hdr; 688 #define RPM_RX_STATS_COUNT 43 689 #define RPM_TX_STATS_COUNT 34 690 u64 rx_stats[RPM_RX_STATS_COUNT]; 691 u64 tx_stats[RPM_TX_STATS_COUNT]; 692 }; 693 694 struct cgx_pfc_cfg { 695 struct mbox_msghdr hdr; 696 u8 rx_pause; 697 u8 tx_pause; 698 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */ 699 }; 700 701 struct cgx_pfc_rsp { 702 struct mbox_msghdr hdr; 703 u8 rx_pause; 704 u8 tx_pause; 705 }; 706 707 /* NPA mbox message formats */ 708 709 struct npc_set_pkind { 710 struct mbox_msghdr hdr; 711 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0) 712 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63) 713 u64 mode; 714 #define PKIND_TX BIT_ULL(0) 715 #define PKIND_RX BIT_ULL(1) 716 u8 dir; 717 u8 pkind; /* valid only in case custom flag */ 718 u8 var_len_off; /* Offset of custom header length field. 719 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND 720 */ 721 u8 var_len_off_mask; /* Mask for length with in offset */ 722 u8 shift_dir; /* shift direction to get length of the header at var_len_off */ 723 }; 724 725 /* NPA mbox message formats */ 726 727 /* NPA mailbox error codes 728 * Range 301 - 400. 729 */ 730 enum npa_af_status { 731 NPA_AF_ERR_PARAM = -301, 732 NPA_AF_ERR_AQ_FULL = -302, 733 NPA_AF_ERR_AQ_ENQUEUE = -303, 734 NPA_AF_ERR_AF_LF_INVALID = -304, 735 NPA_AF_ERR_AF_LF_ALLOC = -305, 736 NPA_AF_ERR_LF_RESET = -306, 737 }; 738 739 /* For NPA LF context alloc and init */ 740 struct npa_lf_alloc_req { 741 struct mbox_msghdr hdr; 742 int node; 743 int aura_sz; /* No of auras */ 744 u32 nr_pools; /* No of pools */ 745 u64 way_mask; 746 }; 747 748 struct npa_lf_alloc_rsp { 749 struct mbox_msghdr hdr; 750 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 751 u32 stack_pg_bytes; /* Size of stack page */ 752 u16 qints; /* NPA_AF_CONST::QINTS */ 753 u8 cache_lines; /*BATCH ALLOC DMA */ 754 }; 755 756 /* NPA AQ enqueue msg */ 757 struct npa_aq_enq_req { 758 struct mbox_msghdr hdr; 759 u32 aura_id; 760 u8 ctype; 761 u8 op; 762 union { 763 /* Valid when op == WRITE/INIT and ctype == AURA. 764 * LF fills the pool_id in aura.pool_addr. AF will translate 765 * the pool_id to pool context pointer. 766 */ 767 struct npa_aura_s aura; 768 /* Valid when op == WRITE/INIT and ctype == POOL */ 769 struct npa_pool_s pool; 770 }; 771 /* Mask data when op == WRITE (1=write, 0=don't write) */ 772 union { 773 /* Valid when op == WRITE and ctype == AURA */ 774 struct npa_aura_s aura_mask; 775 /* Valid when op == WRITE and ctype == POOL */ 776 struct npa_pool_s pool_mask; 777 }; 778 }; 779 780 struct npa_aq_enq_rsp { 781 struct mbox_msghdr hdr; 782 union { 783 /* Valid when op == READ and ctype == AURA */ 784 struct npa_aura_s aura; 785 /* Valid when op == READ and ctype == POOL */ 786 struct npa_pool_s pool; 787 }; 788 }; 789 790 /* Disable all contexts of type 'ctype' */ 791 struct hwctx_disable_req { 792 struct mbox_msghdr hdr; 793 u8 ctype; 794 }; 795 796 /* NIX mbox message formats */ 797 798 /* NIX mailbox error codes 799 * Range 401 - 500. 800 */ 801 enum nix_af_status { 802 NIX_AF_ERR_PARAM = -401, 803 NIX_AF_ERR_AQ_FULL = -402, 804 NIX_AF_ERR_AQ_ENQUEUE = -403, 805 NIX_AF_ERR_AF_LF_INVALID = -404, 806 NIX_AF_ERR_AF_LF_ALLOC = -405, 807 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 808 NIX_AF_ERR_TLX_INVALID = -407, 809 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 810 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 811 NIX_AF_ERR_FRS_INVALID = -410, 812 NIX_AF_ERR_RX_LINK_INVALID = -411, 813 NIX_AF_INVAL_TXSCHQ_CFG = -412, 814 NIX_AF_SMQ_FLUSH_FAILED = -413, 815 NIX_AF_ERR_LF_RESET = -414, 816 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 817 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 818 NIX_AF_ERR_MARK_CFG_FAIL = -417, 819 NIX_AF_ERR_LSO_CFG_FAIL = -418, 820 NIX_AF_INVAL_NPA_PF_FUNC = -419, 821 NIX_AF_INVAL_SSO_PF_FUNC = -420, 822 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 823 NIX_AF_ERR_RX_VTAG_INUSE = -422, 824 NIX_AF_ERR_PTP_CONFIG_FAIL = -423, 825 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424, 826 NIX_AF_ERR_INVALID_NIXBLK = -425, 827 NIX_AF_ERR_INVALID_BANDPROF = -426, 828 NIX_AF_ERR_IPOLICER_NOTSUPP = -427, 829 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428, 830 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429, 831 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430, 832 NIX_AF_ERR_LINK_CREDITS = -431, 833 }; 834 835 /* For NIX RX vtag action */ 836 enum nix_rx_vtag0_type { 837 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 838 NIX_AF_LFX_RX_VTAG_TYPE1, 839 NIX_AF_LFX_RX_VTAG_TYPE2, 840 NIX_AF_LFX_RX_VTAG_TYPE3, 841 NIX_AF_LFX_RX_VTAG_TYPE4, 842 NIX_AF_LFX_RX_VTAG_TYPE5, 843 NIX_AF_LFX_RX_VTAG_TYPE6, 844 NIX_AF_LFX_RX_VTAG_TYPE7, 845 }; 846 847 /* For NIX LF context alloc and init */ 848 struct nix_lf_alloc_req { 849 struct mbox_msghdr hdr; 850 int node; 851 u32 rq_cnt; /* No of receive queues */ 852 u32 sq_cnt; /* No of send queues */ 853 u32 cq_cnt; /* No of completion queues */ 854 u8 xqe_sz; 855 u16 rss_sz; 856 u8 rss_grps; 857 u16 npa_func; 858 u16 sso_func; 859 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 860 u64 way_mask; 861 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0) 862 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1) 863 u64 flags; 864 }; 865 866 struct nix_lf_alloc_rsp { 867 struct mbox_msghdr hdr; 868 u16 sqb_size; 869 u16 rx_chan_base; 870 u16 tx_chan_base; 871 u8 rx_chan_cnt; /* total number of RX channels */ 872 u8 tx_chan_cnt; /* total number of TX channels */ 873 u8 lso_tsov4_idx; 874 u8 lso_tsov6_idx; 875 u8 mac_addr[ETH_ALEN]; 876 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 877 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 878 u16 cints; /* NIX_AF_CONST2::CINTS */ 879 u16 qints; /* NIX_AF_CONST2::QINTS */ 880 u8 cgx_links; /* No. of CGX links present in HW */ 881 u8 lbk_links; /* No. of LBK links present in HW */ 882 u8 sdp_links; /* No. of SDP links present in HW */ 883 u8 tx_link; /* Transmit channel link number */ 884 }; 885 886 struct nix_lf_free_req { 887 struct mbox_msghdr hdr; 888 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 889 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 890 u64 flags; 891 }; 892 893 /* CN10K NIX AQ enqueue msg */ 894 struct nix_cn10k_aq_enq_req { 895 struct mbox_msghdr hdr; 896 u32 qidx; 897 u8 ctype; 898 u8 op; 899 union { 900 struct nix_cn10k_rq_ctx_s rq; 901 struct nix_cn10k_sq_ctx_s sq; 902 struct nix_cq_ctx_s cq; 903 struct nix_rsse_s rss; 904 struct nix_rx_mce_s mce; 905 struct nix_bandprof_s prof; 906 }; 907 union { 908 struct nix_cn10k_rq_ctx_s rq_mask; 909 struct nix_cn10k_sq_ctx_s sq_mask; 910 struct nix_cq_ctx_s cq_mask; 911 struct nix_rsse_s rss_mask; 912 struct nix_rx_mce_s mce_mask; 913 struct nix_bandprof_s prof_mask; 914 }; 915 }; 916 917 struct nix_cn10k_aq_enq_rsp { 918 struct mbox_msghdr hdr; 919 union { 920 struct nix_cn10k_rq_ctx_s rq; 921 struct nix_cn10k_sq_ctx_s sq; 922 struct nix_cq_ctx_s cq; 923 struct nix_rsse_s rss; 924 struct nix_rx_mce_s mce; 925 struct nix_bandprof_s prof; 926 }; 927 }; 928 929 /* NIX AQ enqueue msg */ 930 struct nix_aq_enq_req { 931 struct mbox_msghdr hdr; 932 u32 qidx; 933 u8 ctype; 934 u8 op; 935 union { 936 struct nix_rq_ctx_s rq; 937 struct nix_sq_ctx_s sq; 938 struct nix_cq_ctx_s cq; 939 struct nix_rsse_s rss; 940 struct nix_rx_mce_s mce; 941 struct nix_bandprof_s prof; 942 }; 943 union { 944 struct nix_rq_ctx_s rq_mask; 945 struct nix_sq_ctx_s sq_mask; 946 struct nix_cq_ctx_s cq_mask; 947 struct nix_rsse_s rss_mask; 948 struct nix_rx_mce_s mce_mask; 949 struct nix_bandprof_s prof_mask; 950 }; 951 }; 952 953 struct nix_aq_enq_rsp { 954 struct mbox_msghdr hdr; 955 union { 956 struct nix_rq_ctx_s rq; 957 struct nix_sq_ctx_s sq; 958 struct nix_cq_ctx_s cq; 959 struct nix_rsse_s rss; 960 struct nix_rx_mce_s mce; 961 struct nix_bandprof_s prof; 962 }; 963 }; 964 965 /* Tx scheduler/shaper mailbox messages */ 966 967 #define MAX_TXSCHQ_PER_FUNC 128 968 969 struct nix_txsch_alloc_req { 970 struct mbox_msghdr hdr; 971 /* Scheduler queue count request at each level */ 972 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 973 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 974 }; 975 976 struct nix_txsch_alloc_rsp { 977 struct mbox_msghdr hdr; 978 /* Scheduler queue count allocated at each level */ 979 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 980 u16 schq[NIX_TXSCH_LVL_CNT]; 981 /* Scheduler queue list allocated at each level */ 982 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 983 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 984 u8 aggr_level; /* Traffic aggregation scheduler level */ 985 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 986 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 987 }; 988 989 struct nix_txsch_free_req { 990 struct mbox_msghdr hdr; 991 #define TXSCHQ_FREE_ALL BIT_ULL(0) 992 u16 flags; 993 /* Scheduler queue level to be freed */ 994 u16 schq_lvl; 995 /* List of scheduler queues to be freed */ 996 u16 schq; 997 }; 998 999 struct nix_txschq_config { 1000 struct mbox_msghdr hdr; 1001 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 1002 u8 read; 1003 #define TXSCHQ_IDX_SHIFT 16 1004 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 1005 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 1006 u8 num_regs; 1007 #define MAX_REGS_PER_MBOX_MSG 20 1008 u64 reg[MAX_REGS_PER_MBOX_MSG]; 1009 u64 regval[MAX_REGS_PER_MBOX_MSG]; 1010 /* All 0's => overwrite with new value */ 1011 u64 regval_mask[MAX_REGS_PER_MBOX_MSG]; 1012 }; 1013 1014 struct nix_vtag_config { 1015 struct mbox_msghdr hdr; 1016 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 1017 u8 vtag_size; 1018 /* cfg_type is '0' for tx vlan cfg 1019 * cfg_type is '1' for rx vlan cfg 1020 */ 1021 u8 cfg_type; 1022 union { 1023 /* valid when cfg_type is '0' */ 1024 struct { 1025 u64 vtag0; 1026 u64 vtag1; 1027 1028 /* cfg_vtag0 & cfg_vtag1 fields are valid 1029 * when free_vtag0 & free_vtag1 are '0's. 1030 */ 1031 /* cfg_vtag0 = 1 to configure vtag0 */ 1032 u8 cfg_vtag0 :1; 1033 /* cfg_vtag1 = 1 to configure vtag1 */ 1034 u8 cfg_vtag1 :1; 1035 1036 /* vtag0_idx & vtag1_idx are only valid when 1037 * both cfg_vtag0 & cfg_vtag1 are '0's, 1038 * these fields are used along with free_vtag0 1039 * & free_vtag1 to free the nix lf's tx_vlan 1040 * configuration. 1041 * 1042 * Denotes the indices of tx_vtag def registers 1043 * that needs to be cleared and freed. 1044 */ 1045 int vtag0_idx; 1046 int vtag1_idx; 1047 1048 /* free_vtag0 & free_vtag1 fields are valid 1049 * when cfg_vtag0 & cfg_vtag1 are '0's. 1050 */ 1051 /* free_vtag0 = 1 clears vtag0 configuration 1052 * vtag0_idx denotes the index to be cleared. 1053 */ 1054 u8 free_vtag0 :1; 1055 /* free_vtag1 = 1 clears vtag1 configuration 1056 * vtag1_idx denotes the index to be cleared. 1057 */ 1058 u8 free_vtag1 :1; 1059 } tx; 1060 1061 /* valid when cfg_type is '1' */ 1062 struct { 1063 /* rx vtag type index, valid values are in 0..7 range */ 1064 u8 vtag_type; 1065 /* rx vtag strip */ 1066 u8 strip_vtag :1; 1067 /* rx vtag capture */ 1068 u8 capture_vtag :1; 1069 } rx; 1070 }; 1071 }; 1072 1073 struct nix_vtag_config_rsp { 1074 struct mbox_msghdr hdr; 1075 int vtag0_idx; 1076 int vtag1_idx; 1077 /* Indices of tx_vtag def registers used to configure 1078 * tx vtag0 & vtag1 headers, these indices are valid 1079 * when nix_vtag_config mbox requested for vtag0 and/ 1080 * or vtag1 configuration. 1081 */ 1082 }; 1083 1084 #define NIX_FLOW_KEY_TYPE_L3_L4_MASK (~(0xf << 28)) 1085 1086 struct nix_rss_flowkey_cfg { 1087 struct mbox_msghdr hdr; 1088 int mcam_index; /* MCAM entry index to modify */ 1089 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 1090 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 1091 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 1092 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 1093 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 1094 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 1095 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 1096 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 1097 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 1098 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 1099 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 1100 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 1101 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 1102 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 1103 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 1104 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 1105 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 1106 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 1107 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 1108 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 1109 #define NIX_FLOW_KEY_TYPE_AH BIT(22) 1110 #define NIX_FLOW_KEY_TYPE_ESP BIT(23) 1111 #define NIX_FLOW_KEY_TYPE_L4_DST_ONLY BIT(28) 1112 #define NIX_FLOW_KEY_TYPE_L4_SRC_ONLY BIT(29) 1113 #define NIX_FLOW_KEY_TYPE_L3_DST_ONLY BIT(30) 1114 #define NIX_FLOW_KEY_TYPE_L3_SRC_ONLY BIT(31) 1115 u32 flowkey_cfg; /* Flowkey types selected */ 1116 u8 group; /* RSS context or group */ 1117 }; 1118 1119 struct nix_rss_flowkey_cfg_rsp { 1120 struct mbox_msghdr hdr; 1121 u8 alg_idx; /* Selected algo index */ 1122 }; 1123 1124 struct nix_set_mac_addr { 1125 struct mbox_msghdr hdr; 1126 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 1127 }; 1128 1129 struct nix_get_mac_addr_rsp { 1130 struct mbox_msghdr hdr; 1131 u8 mac_addr[ETH_ALEN]; 1132 }; 1133 1134 struct nix_mark_format_cfg { 1135 struct mbox_msghdr hdr; 1136 u8 offset; 1137 u8 y_mask; 1138 u8 y_val; 1139 u8 r_mask; 1140 u8 r_val; 1141 }; 1142 1143 struct nix_mark_format_cfg_rsp { 1144 struct mbox_msghdr hdr; 1145 u8 mark_format_idx; 1146 }; 1147 1148 struct nix_rx_mode { 1149 struct mbox_msghdr hdr; 1150 #define NIX_RX_MODE_UCAST BIT(0) 1151 #define NIX_RX_MODE_PROMISC BIT(1) 1152 #define NIX_RX_MODE_ALLMULTI BIT(2) 1153 #define NIX_RX_MODE_USE_MCE BIT(3) 1154 u16 mode; 1155 }; 1156 1157 struct nix_rx_cfg { 1158 struct mbox_msghdr hdr; 1159 #define NIX_RX_OL3_VERIFY BIT(0) 1160 #define NIX_RX_OL4_VERIFY BIT(1) 1161 #define NIX_RX_DROP_RE BIT(2) 1162 u8 len_verify; /* Outer L3/L4 len check */ 1163 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 1164 u8 csum_verify; /* Outer L4 checksum verification */ 1165 }; 1166 1167 struct nix_frs_cfg { 1168 struct mbox_msghdr hdr; 1169 u8 update_smq; /* Update SMQ's min/max lens */ 1170 u8 update_minlen; /* Set minlen also */ 1171 u8 sdp_link; /* Set SDP RX link */ 1172 u16 maxlen; 1173 u16 minlen; 1174 }; 1175 1176 struct nix_lso_format_cfg { 1177 struct mbox_msghdr hdr; 1178 u64 field_mask; 1179 #define NIX_LSO_FIELD_MAX 8 1180 u64 fields[NIX_LSO_FIELD_MAX]; 1181 }; 1182 1183 struct nix_lso_format_cfg_rsp { 1184 struct mbox_msghdr hdr; 1185 u8 lso_format_idx; 1186 }; 1187 1188 struct nix_bp_cfg_req { 1189 struct mbox_msghdr hdr; 1190 u16 chan_base; /* Starting channel number */ 1191 u8 chan_cnt; /* Number of channels */ 1192 u8 bpid_per_chan; 1193 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 1194 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 1195 }; 1196 1197 /* PF can be mapped to either CGX or LBK interface, 1198 * so maximum 64 channels are possible. 1199 */ 1200 #define NIX_MAX_BPID_CHAN 64 1201 struct nix_bp_cfg_rsp { 1202 struct mbox_msghdr hdr; 1203 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 1204 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 1205 }; 1206 1207 /* Global NIX inline IPSec configuration */ 1208 struct nix_inline_ipsec_cfg { 1209 struct mbox_msghdr hdr; 1210 u32 cpt_credit; 1211 struct { 1212 u8 egrp; 1213 u16 opcode; 1214 u16 param1; 1215 u16 param2; 1216 } gen_cfg; 1217 struct { 1218 u16 cpt_pf_func; 1219 u8 cpt_slot; 1220 } inst_qsel; 1221 u8 enable; 1222 u16 bpid; 1223 u32 credit_th; 1224 }; 1225 1226 /* Per NIX LF inline IPSec configuration */ 1227 struct nix_inline_ipsec_lf_cfg { 1228 struct mbox_msghdr hdr; 1229 u64 sa_base_addr; 1230 struct { 1231 u32 tag_const; 1232 u16 lenm1_max; 1233 u8 sa_pow2_size; 1234 u8 tt; 1235 } ipsec_cfg0; 1236 struct { 1237 u32 sa_idx_max; 1238 u8 sa_idx_w; 1239 } ipsec_cfg1; 1240 u8 enable; 1241 }; 1242 1243 struct nix_hw_info { 1244 struct mbox_msghdr hdr; 1245 u16 rsvs16; 1246 u16 max_mtu; 1247 u16 min_mtu; 1248 u32 rpm_dwrr_mtu; 1249 u32 sdp_dwrr_mtu; 1250 u32 lbk_dwrr_mtu; 1251 u32 rsvd32[1]; 1252 u64 rsvd[15]; /* Add reserved fields for future expansion */ 1253 }; 1254 1255 struct nix_bandprof_alloc_req { 1256 struct mbox_msghdr hdr; 1257 /* Count of profiles needed per layer */ 1258 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1259 }; 1260 1261 struct nix_bandprof_alloc_rsp { 1262 struct mbox_msghdr hdr; 1263 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1264 1265 /* There is no need to allocate morethan 1 bandwidth profile 1266 * per RQ of a PF_FUNC's NIXLF. So limit the maximum 1267 * profiles to 64 per PF_FUNC. 1268 */ 1269 #define MAX_BANDPROF_PER_PFFUNC 64 1270 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1271 }; 1272 1273 struct nix_bandprof_free_req { 1274 struct mbox_msghdr hdr; 1275 u8 free_all; 1276 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1277 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1278 }; 1279 1280 struct nix_bandprof_get_hwinfo_rsp { 1281 struct mbox_msghdr hdr; 1282 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1283 u32 policer_timeunit; 1284 }; 1285 1286 /* NPC mbox message structs */ 1287 1288 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 1289 #define NPC_MCAM_INVALID_MAP 0xFFFF 1290 1291 /* NPC mailbox error codes 1292 * Range 701 - 800. 1293 */ 1294 enum npc_af_status { 1295 NPC_MCAM_INVALID_REQ = -701, 1296 NPC_MCAM_ALLOC_DENIED = -702, 1297 NPC_MCAM_ALLOC_FAILED = -703, 1298 NPC_MCAM_PERM_DENIED = -704, 1299 NPC_FLOW_INTF_INVALID = -707, 1300 NPC_FLOW_CHAN_INVALID = -708, 1301 NPC_FLOW_NO_NIXLF = -709, 1302 NPC_FLOW_NOT_SUPPORTED = -710, 1303 NPC_FLOW_VF_PERM_DENIED = -711, 1304 NPC_FLOW_VF_NOT_INIT = -712, 1305 NPC_FLOW_VF_OVERLAP = -713, 1306 }; 1307 1308 struct npc_mcam_alloc_entry_req { 1309 struct mbox_msghdr hdr; 1310 #define NPC_MAX_NONCONTIG_ENTRIES 256 1311 u8 contig; /* Contiguous entries ? */ 1312 #define NPC_MCAM_ANY_PRIO 0 1313 #define NPC_MCAM_LOWER_PRIO 1 1314 #define NPC_MCAM_HIGHER_PRIO 2 1315 u8 priority; /* Lower or higher w.r.t ref_entry */ 1316 u16 ref_entry; 1317 u16 count; /* Number of entries requested */ 1318 }; 1319 1320 struct npc_mcam_alloc_entry_rsp { 1321 struct mbox_msghdr hdr; 1322 u16 entry; /* Entry allocated or start index if contiguous. 1323 * Invalid incase of non-contiguous. 1324 */ 1325 u16 count; /* Number of entries allocated */ 1326 u16 free_count; /* Number of entries available */ 1327 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1328 }; 1329 1330 struct npc_mcam_free_entry_req { 1331 struct mbox_msghdr hdr; 1332 u16 entry; /* Entry index to be freed */ 1333 u8 all; /* If all entries allocated to this PFVF to be freed */ 1334 }; 1335 1336 struct mcam_entry { 1337 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1338 u64 kw[NPC_MAX_KWS_IN_KEY]; 1339 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1340 u64 action; 1341 u64 vtag_action; 1342 }; 1343 1344 struct npc_mcam_write_entry_req { 1345 struct mbox_msghdr hdr; 1346 struct mcam_entry entry_data; 1347 u16 entry; /* MCAM entry to write this match key */ 1348 u16 cntr; /* Counter for this MCAM entry */ 1349 u8 intf; /* Rx or Tx interface */ 1350 u8 enable_entry;/* Enable this MCAM entry ? */ 1351 u8 set_cntr; /* Set counter for this entry ? */ 1352 }; 1353 1354 /* Enable/Disable a given entry */ 1355 struct npc_mcam_ena_dis_entry_req { 1356 struct mbox_msghdr hdr; 1357 u16 entry; 1358 }; 1359 1360 struct npc_mcam_shift_entry_req { 1361 struct mbox_msghdr hdr; 1362 #define NPC_MCAM_MAX_SHIFTS 64 1363 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1364 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1365 u16 shift_count; /* Number of entries to shift */ 1366 }; 1367 1368 struct npc_mcam_shift_entry_rsp { 1369 struct mbox_msghdr hdr; 1370 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1371 }; 1372 1373 struct npc_mcam_alloc_counter_req { 1374 struct mbox_msghdr hdr; 1375 u8 contig; /* Contiguous counters ? */ 1376 #define NPC_MAX_NONCONTIG_COUNTERS 64 1377 u16 count; /* Number of counters requested */ 1378 }; 1379 1380 struct npc_mcam_alloc_counter_rsp { 1381 struct mbox_msghdr hdr; 1382 u16 cntr; /* Counter allocated or start index if contiguous. 1383 * Invalid incase of non-contiguous. 1384 */ 1385 u16 count; /* Number of counters allocated */ 1386 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1387 }; 1388 1389 struct npc_mcam_oper_counter_req { 1390 struct mbox_msghdr hdr; 1391 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1392 }; 1393 1394 struct npc_mcam_oper_counter_rsp { 1395 struct mbox_msghdr hdr; 1396 u64 stat; /* valid only while fetching counter's stats */ 1397 }; 1398 1399 struct npc_mcam_unmap_counter_req { 1400 struct mbox_msghdr hdr; 1401 u16 cntr; 1402 u16 entry; /* Entry and counter to be unmapped */ 1403 u8 all; /* Unmap all entries using this counter ? */ 1404 }; 1405 1406 struct npc_mcam_alloc_and_write_entry_req { 1407 struct mbox_msghdr hdr; 1408 struct mcam_entry entry_data; 1409 u16 ref_entry; 1410 u8 priority; /* Lower or higher w.r.t ref_entry */ 1411 u8 intf; /* Rx or Tx interface */ 1412 u8 enable_entry;/* Enable this MCAM entry ? */ 1413 u8 alloc_cntr; /* Allocate counter and map ? */ 1414 }; 1415 1416 struct npc_mcam_alloc_and_write_entry_rsp { 1417 struct mbox_msghdr hdr; 1418 u16 entry; 1419 u16 cntr; 1420 }; 1421 1422 struct npc_get_kex_cfg_rsp { 1423 struct mbox_msghdr hdr; 1424 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1425 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1426 #define NPC_MAX_INTF 2 1427 #define NPC_MAX_LID 8 1428 #define NPC_MAX_LT 16 1429 #define NPC_MAX_LD 2 1430 #define NPC_MAX_LFL 16 1431 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1432 u64 kex_ld_flags[NPC_MAX_LD]; 1433 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1434 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1435 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1436 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1437 #define MKEX_NAME_LEN 128 1438 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1439 }; 1440 1441 struct ptp_get_cap_rsp { 1442 struct mbox_msghdr hdr; 1443 #define PTP_CAP_HW_ATOMIC_UPDATE BIT_ULL(0) 1444 u64 cap; 1445 }; 1446 1447 struct flow_msg { 1448 unsigned char dmac[6]; 1449 unsigned char smac[6]; 1450 __be16 etype; 1451 __be16 vlan_etype; 1452 __be16 vlan_tci; 1453 union { 1454 __be32 ip4src; 1455 __be32 ip6src[4]; 1456 }; 1457 union { 1458 __be32 ip4dst; 1459 __be32 ip6dst[4]; 1460 }; 1461 union { 1462 __be32 spi; 1463 }; 1464 1465 u8 tos; 1466 u8 ip_ver; 1467 u8 ip_proto; 1468 u8 tc; 1469 __be16 sport; 1470 __be16 dport; 1471 union { 1472 u8 ip_flag; 1473 u8 next_header; 1474 }; 1475 __be16 vlan_itci; 1476 }; 1477 1478 struct npc_install_flow_req { 1479 struct mbox_msghdr hdr; 1480 struct flow_msg packet; 1481 struct flow_msg mask; 1482 u64 features; 1483 u16 entry; 1484 u16 channel; 1485 u16 chan_mask; 1486 u8 intf; 1487 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1488 u8 default_rule; 1489 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1490 u16 vf; 1491 /* action */ 1492 u32 index; 1493 u16 match_id; 1494 u8 flow_key_alg; 1495 u8 op; 1496 /* vtag rx action */ 1497 u8 vtag0_type; 1498 u8 vtag0_valid; 1499 u8 vtag1_type; 1500 u8 vtag1_valid; 1501 /* vtag tx action */ 1502 u16 vtag0_def; 1503 u8 vtag0_op; 1504 u16 vtag1_def; 1505 u8 vtag1_op; 1506 /* old counter value */ 1507 u16 cntr_val; 1508 }; 1509 1510 struct npc_install_flow_rsp { 1511 struct mbox_msghdr hdr; 1512 int counter; /* negative if no counter else counter number */ 1513 }; 1514 1515 struct npc_delete_flow_req { 1516 struct mbox_msghdr hdr; 1517 u16 entry; 1518 u16 start;/*Disable range of entries */ 1519 u16 end; 1520 u8 all; /* PF + VFs */ 1521 }; 1522 1523 struct npc_delete_flow_rsp { 1524 struct mbox_msghdr hdr; 1525 u16 cntr_val; 1526 }; 1527 1528 struct npc_mcam_read_entry_req { 1529 struct mbox_msghdr hdr; 1530 u16 entry; /* MCAM entry to read */ 1531 }; 1532 1533 struct npc_mcam_read_entry_rsp { 1534 struct mbox_msghdr hdr; 1535 struct mcam_entry entry_data; 1536 u8 intf; 1537 u8 enable; 1538 }; 1539 1540 struct npc_mcam_read_base_rule_rsp { 1541 struct mbox_msghdr hdr; 1542 struct mcam_entry entry; 1543 }; 1544 1545 struct npc_mcam_get_stats_req { 1546 struct mbox_msghdr hdr; 1547 u16 entry; /* mcam entry */ 1548 }; 1549 1550 struct npc_mcam_get_stats_rsp { 1551 struct mbox_msghdr hdr; 1552 u64 stat; /* counter stats */ 1553 u8 stat_ena; /* enabled */ 1554 }; 1555 1556 struct npc_get_field_hash_info_req { 1557 struct mbox_msghdr hdr; 1558 u8 intf; 1559 }; 1560 1561 struct npc_get_field_hash_info_rsp { 1562 struct mbox_msghdr hdr; 1563 u64 secret_key[3]; 1564 #define NPC_MAX_HASH 2 1565 #define NPC_MAX_HASH_MASK 2 1566 /* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */ 1567 u64 hash_mask[NPC_MAX_INTF][NPC_MAX_HASH][NPC_MAX_HASH_MASK]; 1568 /* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */ 1569 u64 hash_ctrl[NPC_MAX_INTF][NPC_MAX_HASH]; 1570 }; 1571 1572 enum ptp_op { 1573 PTP_OP_ADJFINE = 0, 1574 PTP_OP_GET_CLOCK = 1, 1575 PTP_OP_GET_TSTMP = 2, 1576 PTP_OP_SET_THRESH = 3, 1577 PTP_OP_EXTTS_ON = 4, 1578 PTP_OP_ADJTIME = 5, 1579 PTP_OP_SET_CLOCK = 6, 1580 }; 1581 1582 struct ptp_req { 1583 struct mbox_msghdr hdr; 1584 u8 op; 1585 s64 scaled_ppm; 1586 u64 thresh; 1587 int extts_on; 1588 s64 delta; 1589 u64 clk; 1590 }; 1591 1592 struct ptp_rsp { 1593 struct mbox_msghdr hdr; 1594 u64 clk; 1595 u64 tsc; 1596 }; 1597 1598 struct npc_get_field_status_req { 1599 struct mbox_msghdr hdr; 1600 u8 intf; 1601 u8 field; 1602 }; 1603 1604 struct npc_get_field_status_rsp { 1605 struct mbox_msghdr hdr; 1606 u8 enable; 1607 }; 1608 1609 struct set_vf_perm { 1610 struct mbox_msghdr hdr; 1611 u16 vf; 1612 #define RESET_VF_PERM BIT_ULL(0) 1613 #define VF_TRUSTED BIT_ULL(1) 1614 u64 flags; 1615 }; 1616 1617 struct lmtst_tbl_setup_req { 1618 struct mbox_msghdr hdr; 1619 u64 dis_sched_early_comp :1; 1620 u64 sch_ena :1; 1621 u64 dis_line_pref :1; 1622 u64 ssow_pf_func :13; 1623 u16 base_pcifunc; 1624 u8 use_local_lmt_region; 1625 u64 lmt_iova; 1626 u64 rsvd[4]; 1627 }; 1628 1629 /* CPT mailbox error codes 1630 * Range 901 - 1000. 1631 */ 1632 enum cpt_af_status { 1633 CPT_AF_ERR_PARAM = -901, 1634 CPT_AF_ERR_GRP_INVALID = -902, 1635 CPT_AF_ERR_LF_INVALID = -903, 1636 CPT_AF_ERR_ACCESS_DENIED = -904, 1637 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1638 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906, 1639 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907, 1640 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908 1641 }; 1642 1643 /* CPT mbox message formats */ 1644 struct cpt_rd_wr_reg_msg { 1645 struct mbox_msghdr hdr; 1646 u64 reg_offset; 1647 u64 *ret_val; 1648 u64 val; 1649 u8 is_write; 1650 int blkaddr; 1651 }; 1652 1653 struct cpt_lf_alloc_req_msg { 1654 struct mbox_msghdr hdr; 1655 u16 nix_pf_func; 1656 u16 sso_pf_func; 1657 u16 eng_grpmsk; 1658 int blkaddr; 1659 u8 ctx_ilen_valid : 1; 1660 u8 ctx_ilen : 7; 1661 }; 1662 1663 #define CPT_INLINE_INBOUND 0 1664 #define CPT_INLINE_OUTBOUND 1 1665 1666 /* Mailbox message request format for CPT IPsec 1667 * inline inbound and outbound configuration. 1668 */ 1669 struct cpt_inline_ipsec_cfg_msg { 1670 struct mbox_msghdr hdr; 1671 u8 enable; 1672 u8 slot; 1673 u8 dir; 1674 u8 sso_pf_func_ovrd; 1675 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */ 1676 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */ 1677 }; 1678 1679 /* Mailbox message request and response format for CPT stats. */ 1680 struct cpt_sts_req { 1681 struct mbox_msghdr hdr; 1682 u8 blkaddr; 1683 }; 1684 1685 struct cpt_sts_rsp { 1686 struct mbox_msghdr hdr; 1687 u64 inst_req_pc; 1688 u64 inst_lat_pc; 1689 u64 rd_req_pc; 1690 u64 rd_lat_pc; 1691 u64 rd_uc_pc; 1692 u64 active_cycles_pc; 1693 u64 ctx_mis_pc; 1694 u64 ctx_hit_pc; 1695 u64 ctx_aop_pc; 1696 u64 ctx_aop_lat_pc; 1697 u64 ctx_ifetch_pc; 1698 u64 ctx_ifetch_lat_pc; 1699 u64 ctx_ffetch_pc; 1700 u64 ctx_ffetch_lat_pc; 1701 u64 ctx_wback_pc; 1702 u64 ctx_wback_lat_pc; 1703 u64 ctx_psh_pc; 1704 u64 ctx_psh_lat_pc; 1705 u64 ctx_err; 1706 u64 ctx_enc_id; 1707 u64 ctx_flush_timer; 1708 u64 rxc_time; 1709 u64 rxc_time_cfg; 1710 u64 rxc_active_sts; 1711 u64 rxc_zombie_sts; 1712 u64 busy_sts_ae; 1713 u64 free_sts_ae; 1714 u64 busy_sts_se; 1715 u64 free_sts_se; 1716 u64 busy_sts_ie; 1717 u64 free_sts_ie; 1718 u64 exe_err_info; 1719 u64 cptclk_cnt; 1720 u64 diag; 1721 u64 rxc_dfrg; 1722 u64 x2p_link_cfg0; 1723 u64 x2p_link_cfg1; 1724 }; 1725 1726 /* Mailbox message request format to configure reassembly timeout. */ 1727 struct cpt_rxc_time_cfg_req { 1728 struct mbox_msghdr hdr; 1729 int blkaddr; 1730 u32 step; 1731 u16 zombie_thres; 1732 u16 zombie_limit; 1733 u16 active_thres; 1734 u16 active_limit; 1735 }; 1736 1737 /* Mailbox message request format to request for CPT_INST_S lmtst. */ 1738 struct cpt_inst_lmtst_req { 1739 struct mbox_msghdr hdr; 1740 u64 inst[8]; 1741 u64 rsvd; 1742 }; 1743 1744 /* Mailbox message format to request for CPT LF reset */ 1745 struct cpt_lf_rst_req { 1746 struct mbox_msghdr hdr; 1747 u32 slot; 1748 u32 rsvd; 1749 }; 1750 1751 /* Mailbox message format to request for CPT faulted engines */ 1752 struct cpt_flt_eng_info_req { 1753 struct mbox_msghdr hdr; 1754 int blkaddr; 1755 bool reset; 1756 u32 rsvd; 1757 }; 1758 1759 struct cpt_flt_eng_info_rsp { 1760 struct mbox_msghdr hdr; 1761 u64 flt_eng_map[CPT_10K_AF_INT_VEC_RVU]; 1762 u64 rcvrd_eng_map[CPT_10K_AF_INT_VEC_RVU]; 1763 u64 rsvd; 1764 }; 1765 1766 struct sdp_node_info { 1767 /* Node to which this PF belons to */ 1768 u8 node_id; 1769 u8 max_vfs; 1770 u8 num_pf_rings; 1771 u8 pf_srn; 1772 #define SDP_MAX_VFS 128 1773 u8 vf_rings[SDP_MAX_VFS]; 1774 }; 1775 1776 struct sdp_chan_info_msg { 1777 struct mbox_msghdr hdr; 1778 struct sdp_node_info info; 1779 }; 1780 1781 struct sdp_get_chan_info_msg { 1782 struct mbox_msghdr hdr; 1783 u16 chan_base; 1784 u16 num_chan; 1785 }; 1786 1787 /* CGX mailbox error codes 1788 * Range 1101 - 1200. 1789 */ 1790 enum cgx_af_status { 1791 LMAC_AF_ERR_INVALID_PARAM = -1101, 1792 LMAC_AF_ERR_PF_NOT_MAPPED = -1102, 1793 LMAC_AF_ERR_PERM_DENIED = -1103, 1794 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104, 1795 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105, 1796 LMAC_AF_ERR_CMD_TIMEOUT = -1106, 1797 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107, 1798 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108, 1799 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109, 1800 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110, 1801 }; 1802 1803 enum mcs_direction { 1804 MCS_RX, 1805 MCS_TX, 1806 }; 1807 1808 enum mcs_rsrc_type { 1809 MCS_RSRC_TYPE_FLOWID, 1810 MCS_RSRC_TYPE_SECY, 1811 MCS_RSRC_TYPE_SC, 1812 MCS_RSRC_TYPE_SA, 1813 }; 1814 1815 struct mcs_alloc_rsrc_req { 1816 struct mbox_msghdr hdr; 1817 u8 rsrc_type; 1818 u8 rsrc_cnt; /* Resources count */ 1819 u8 mcs_id; /* MCS block ID */ 1820 u8 dir; /* Macsec ingress or egress side */ 1821 u8 all; /* Allocate all resource type one each */ 1822 u64 rsvd; 1823 }; 1824 1825 struct mcs_alloc_rsrc_rsp { 1826 struct mbox_msghdr hdr; 1827 u8 flow_ids[128]; /* Index of reserved entries */ 1828 u8 secy_ids[128]; 1829 u8 sc_ids[128]; 1830 u8 sa_ids[256]; 1831 u8 rsrc_type; 1832 u8 rsrc_cnt; /* No of entries reserved */ 1833 u8 mcs_id; 1834 u8 dir; 1835 u8 all; 1836 u8 rsvd[256]; /* reserved fields for future expansion */ 1837 }; 1838 1839 struct mcs_free_rsrc_req { 1840 struct mbox_msghdr hdr; 1841 u8 rsrc_id; /* Index of the entry to be freed */ 1842 u8 rsrc_type; 1843 u8 mcs_id; 1844 u8 dir; 1845 u8 all; /* Free all the cam resources */ 1846 u64 rsvd; 1847 }; 1848 1849 struct mcs_flowid_entry_write_req { 1850 struct mbox_msghdr hdr; 1851 u64 data[4]; 1852 u64 mask[4]; 1853 u64 sci; /* CNF10K-B for tx_secy_mem_map */ 1854 u8 flow_id; 1855 u8 secy_id; /* secyid for which flowid is mapped */ 1856 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */ 1857 u8 ena; /* Enable tcam entry */ 1858 u8 ctrl_pkt; 1859 u8 mcs_id; 1860 u8 dir; 1861 u64 rsvd; 1862 }; 1863 1864 struct mcs_secy_plcy_write_req { 1865 struct mbox_msghdr hdr; 1866 u64 plcy; 1867 u8 secy_id; 1868 u8 mcs_id; 1869 u8 dir; 1870 u64 rsvd; 1871 }; 1872 1873 /* RX SC_CAM mapping */ 1874 struct mcs_rx_sc_cam_write_req { 1875 struct mbox_msghdr hdr; 1876 u64 sci; /* SCI */ 1877 u64 secy_id; /* secy index mapped to SC */ 1878 u8 sc_id; /* SC CAM entry index */ 1879 u8 mcs_id; 1880 u64 rsvd; 1881 }; 1882 1883 struct mcs_sa_plcy_write_req { 1884 struct mbox_msghdr hdr; 1885 u64 plcy[2][9]; /* Support 2 SA policy */ 1886 u8 sa_index[2]; 1887 u8 sa_cnt; 1888 u8 mcs_id; 1889 u8 dir; 1890 u64 rsvd; 1891 }; 1892 1893 struct mcs_tx_sc_sa_map { 1894 struct mbox_msghdr hdr; 1895 u8 sa_index0; 1896 u8 sa_index1; 1897 u8 rekey_ena; 1898 u8 sa_index0_vld; 1899 u8 sa_index1_vld; 1900 u8 tx_sa_active; 1901 u64 sectag_sci; 1902 u8 sc_id; /* used as index for SA_MEM_MAP */ 1903 u8 mcs_id; 1904 u64 rsvd; 1905 }; 1906 1907 struct mcs_rx_sc_sa_map { 1908 struct mbox_msghdr hdr; 1909 u8 sa_index; 1910 u8 sa_in_use; 1911 u8 sc_id; 1912 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */ 1913 u8 mcs_id; 1914 u64 rsvd; 1915 }; 1916 1917 struct mcs_flowid_ena_dis_entry { 1918 struct mbox_msghdr hdr; 1919 u8 flow_id; 1920 u8 ena; 1921 u8 mcs_id; 1922 u8 dir; 1923 u64 rsvd; 1924 }; 1925 1926 struct mcs_pn_table_write_req { 1927 struct mbox_msghdr hdr; 1928 u64 next_pn; 1929 u8 pn_id; 1930 u8 mcs_id; 1931 u8 dir; 1932 u64 rsvd; 1933 }; 1934 1935 struct mcs_hw_info { 1936 struct mbox_msghdr hdr; 1937 u8 num_mcs_blks; /* Number of MCS blocks */ 1938 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */ 1939 u8 secy_entries; /* RX/TX SECY entries per mcs block */ 1940 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */ 1941 u8 sa_entries; /* PN table entries = SA entries */ 1942 u64 rsvd[16]; 1943 }; 1944 1945 struct mcs_set_active_lmac { 1946 struct mbox_msghdr hdr; 1947 u32 lmac_bmap; /* bitmap of active lmac per mcs block */ 1948 u8 mcs_id; 1949 u16 chan_base; /* MCS channel base */ 1950 u64 rsvd; 1951 }; 1952 1953 struct mcs_set_lmac_mode { 1954 struct mbox_msghdr hdr; 1955 u8 mode; /* 1:Bypass 0:Operational */ 1956 u8 lmac_id; 1957 u8 mcs_id; 1958 u64 rsvd; 1959 }; 1960 1961 struct mcs_port_reset_req { 1962 struct mbox_msghdr hdr; 1963 u8 reset; 1964 u8 mcs_id; 1965 u8 port_id; 1966 u64 rsvd; 1967 }; 1968 1969 struct mcs_port_cfg_set_req { 1970 struct mbox_msghdr hdr; 1971 u8 cstm_tag_rel_mode_sel; 1972 u8 custom_hdr_enb; 1973 u8 fifo_skid; 1974 u8 port_mode; 1975 u8 port_id; 1976 u8 mcs_id; 1977 u64 rsvd; 1978 }; 1979 1980 struct mcs_port_cfg_get_req { 1981 struct mbox_msghdr hdr; 1982 u8 port_id; 1983 u8 mcs_id; 1984 u64 rsvd; 1985 }; 1986 1987 struct mcs_port_cfg_get_rsp { 1988 struct mbox_msghdr hdr; 1989 u8 cstm_tag_rel_mode_sel; 1990 u8 custom_hdr_enb; 1991 u8 fifo_skid; 1992 u8 port_mode; 1993 u8 port_id; 1994 u8 mcs_id; 1995 u64 rsvd; 1996 }; 1997 1998 struct mcs_custom_tag_cfg_get_req { 1999 struct mbox_msghdr hdr; 2000 u8 mcs_id; 2001 u8 dir; 2002 u64 rsvd; 2003 }; 2004 2005 struct mcs_custom_tag_cfg_get_rsp { 2006 struct mbox_msghdr hdr; 2007 u16 cstm_etype[8]; 2008 u8 cstm_indx[8]; 2009 u8 cstm_etype_en; 2010 u8 mcs_id; 2011 u8 dir; 2012 u64 rsvd; 2013 }; 2014 2015 /* MCS mailbox error codes 2016 * Range 1201 - 1300. 2017 */ 2018 enum mcs_af_status { 2019 MCS_AF_ERR_INVALID_MCSID = -1201, 2020 MCS_AF_ERR_NOT_MAPPED = -1202, 2021 }; 2022 2023 struct mcs_set_pn_threshold { 2024 struct mbox_msghdr hdr; 2025 u64 threshold; 2026 u8 xpn; /* '1' for setting xpn threshold */ 2027 u8 mcs_id; 2028 u8 dir; 2029 u64 rsvd; 2030 }; 2031 2032 enum mcs_ctrl_pkt_rulew_type { 2033 MCS_CTRL_PKT_RULE_TYPE_ETH, 2034 MCS_CTRL_PKT_RULE_TYPE_DA, 2035 MCS_CTRL_PKT_RULE_TYPE_RANGE, 2036 MCS_CTRL_PKT_RULE_TYPE_COMBO, 2037 MCS_CTRL_PKT_RULE_TYPE_MAC, 2038 }; 2039 2040 struct mcs_alloc_ctrl_pkt_rule_req { 2041 struct mbox_msghdr hdr; 2042 u8 rule_type; 2043 u8 mcs_id; /* MCS block ID */ 2044 u8 dir; /* Macsec ingress or egress side */ 2045 u64 rsvd; 2046 }; 2047 2048 struct mcs_alloc_ctrl_pkt_rule_rsp { 2049 struct mbox_msghdr hdr; 2050 u8 rule_idx; 2051 u8 rule_type; 2052 u8 mcs_id; 2053 u8 dir; 2054 u64 rsvd; 2055 }; 2056 2057 struct mcs_free_ctrl_pkt_rule_req { 2058 struct mbox_msghdr hdr; 2059 u8 rule_idx; 2060 u8 rule_type; 2061 u8 mcs_id; 2062 u8 dir; 2063 u8 all; 2064 u64 rsvd; 2065 }; 2066 2067 struct mcs_ctrl_pkt_rule_write_req { 2068 struct mbox_msghdr hdr; 2069 u64 data0; 2070 u64 data1; 2071 u64 data2; 2072 u8 rule_idx; 2073 u8 rule_type; 2074 u8 mcs_id; 2075 u8 dir; 2076 u64 rsvd; 2077 }; 2078 2079 struct mcs_stats_req { 2080 struct mbox_msghdr hdr; 2081 u8 id; 2082 u8 mcs_id; 2083 u8 dir; 2084 u64 rsvd; 2085 }; 2086 2087 struct mcs_flowid_stats { 2088 struct mbox_msghdr hdr; 2089 u64 tcam_hit_cnt; 2090 u64 rsvd; 2091 }; 2092 2093 struct mcs_secy_stats { 2094 struct mbox_msghdr hdr; 2095 u64 ctl_pkt_bcast_cnt; 2096 u64 ctl_pkt_mcast_cnt; 2097 u64 ctl_pkt_ucast_cnt; 2098 u64 ctl_octet_cnt; 2099 u64 unctl_pkt_bcast_cnt; 2100 u64 unctl_pkt_mcast_cnt; 2101 u64 unctl_pkt_ucast_cnt; 2102 u64 unctl_octet_cnt; 2103 /* Valid only for RX */ 2104 u64 octet_decrypted_cnt; 2105 u64 octet_validated_cnt; 2106 u64 pkt_port_disabled_cnt; 2107 u64 pkt_badtag_cnt; 2108 u64 pkt_nosa_cnt; 2109 u64 pkt_nosaerror_cnt; 2110 u64 pkt_tagged_ctl_cnt; 2111 u64 pkt_untaged_cnt; 2112 u64 pkt_ctl_cnt; /* CN10K-B */ 2113 u64 pkt_notag_cnt; /* CNF10K-B */ 2114 /* Valid only for TX */ 2115 u64 octet_encrypted_cnt; 2116 u64 octet_protected_cnt; 2117 u64 pkt_noactivesa_cnt; 2118 u64 pkt_toolong_cnt; 2119 u64 pkt_untagged_cnt; 2120 u64 rsvd[4]; 2121 }; 2122 2123 struct mcs_port_stats { 2124 struct mbox_msghdr hdr; 2125 u64 tcam_miss_cnt; 2126 u64 parser_err_cnt; 2127 u64 preempt_err_cnt; /* CNF10K-B */ 2128 u64 sectag_insert_err_cnt; 2129 u64 rsvd[4]; 2130 }; 2131 2132 /* Only for CN10K-B */ 2133 struct mcs_sa_stats { 2134 struct mbox_msghdr hdr; 2135 /* RX */ 2136 u64 pkt_invalid_cnt; 2137 u64 pkt_nosaerror_cnt; 2138 u64 pkt_notvalid_cnt; 2139 u64 pkt_ok_cnt; 2140 u64 pkt_nosa_cnt; 2141 /* TX */ 2142 u64 pkt_encrypt_cnt; 2143 u64 pkt_protected_cnt; 2144 u64 rsvd[4]; 2145 }; 2146 2147 struct mcs_sc_stats { 2148 struct mbox_msghdr hdr; 2149 /* RX */ 2150 u64 hit_cnt; 2151 u64 pkt_invalid_cnt; 2152 u64 pkt_late_cnt; 2153 u64 pkt_notvalid_cnt; 2154 u64 pkt_unchecked_cnt; 2155 u64 pkt_delay_cnt; /* CNF10K-B */ 2156 u64 pkt_ok_cnt; /* CNF10K-B */ 2157 u64 octet_decrypt_cnt; /* CN10K-B */ 2158 u64 octet_validate_cnt; /* CN10K-B */ 2159 /* TX */ 2160 u64 pkt_encrypt_cnt; 2161 u64 pkt_protected_cnt; 2162 u64 octet_encrypt_cnt; /* CN10K-B */ 2163 u64 octet_protected_cnt; /* CN10K-B */ 2164 u64 rsvd[4]; 2165 }; 2166 2167 struct mcs_clear_stats { 2168 struct mbox_msghdr hdr; 2169 #define MCS_FLOWID_STATS 0 2170 #define MCS_SECY_STATS 1 2171 #define MCS_SC_STATS 2 2172 #define MCS_SA_STATS 3 2173 #define MCS_PORT_STATS 4 2174 u8 type; /* FLOWID, SECY, SC, SA, PORT */ 2175 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */ 2176 u8 mcs_id; 2177 u8 dir; 2178 u8 all; /* All resources stats mapped to PF are cleared */ 2179 }; 2180 2181 struct mcs_intr_cfg { 2182 struct mbox_msghdr hdr; 2183 #define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0) 2184 #define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1) 2185 #define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2) 2186 #define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3) 2187 #define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4) 2188 #define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5) 2189 #define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6) 2190 #define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7) 2191 #define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8) 2192 #define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9) 2193 #define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10) 2194 #define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11) 2195 #define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12) 2196 #define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13) 2197 #define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14) 2198 #define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15) 2199 u64 intr_mask; /* Interrupt enable mask */ 2200 u8 mcs_id; 2201 u8 lmac_id; 2202 u64 rsvd; 2203 }; 2204 2205 struct mcs_intr_info { 2206 struct mbox_msghdr hdr; 2207 u64 intr_mask; 2208 int sa_id; 2209 u8 mcs_id; 2210 u8 lmac_id; 2211 u64 rsvd; 2212 }; 2213 2214 #endif /* MBOX_H */ 2215
