1 /*
2 * Support for configuration of IO Delay module found on Texas Instruments SoCs
3 * such as DRA7
4 *
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/err.h>
13 #include <linux/init.h>
14 #include <linux/io.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_device.h>
18 #include <linux/regmap.h>
19 #include <linux/seq_file.h>
20 #include <linux/slab.h>
21
22 #include <linux/pinctrl/pinconf-generic.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinctrl.h>
25
26 #include "../core.h"
27 #include "../devicetree.h"
28
29 #define DRIVER_NAME "ti-iodelay"
30
31 /**
32 * struct ti_iodelay_reg_data - Describes the registers for the iodelay instance
33 * @signature_mask: CONFIG_REG mask for the signature bits (see TRM)
34 * @signature_value: CONFIG_REG signature value to be written (see TRM)
35 * @lock_mask: CONFIG_REG mask for the lock bits (see TRM)
36 * @lock_val: CONFIG_REG lock value for the lock bits (see TRM)
37 * @unlock_val:CONFIG_REG unlock value for the lock bits (see TRM)
38 * @binary_data_coarse_mask: CONFIG_REG coarse mask (see TRM)
39 * @binary_data_fine_mask: CONFIG_REG fine mask (see TRM)
40 * @reg_refclk_offset: Refclk register offset
41 * @refclk_period_mask: Refclk mask
42 * @reg_coarse_offset: Coarse register configuration offset
43 * @coarse_delay_count_mask: Coarse delay count mask
44 * @coarse_ref_count_mask: Coarse ref count mask
45 * @reg_fine_offset: Fine register configuration offset
46 * @fine_delay_count_mask: Fine delay count mask
47 * @fine_ref_count_mask: Fine ref count mask
48 * @reg_global_lock_offset: Global iodelay module lock register offset
49 * @global_lock_mask: Lock mask
50 * @global_unlock_val: Unlock value
51 * @global_lock_val: Lock value
52 * @reg_start_offset: Offset to iodelay registers after the CONFIG_REG_0 to 8
53 * @reg_nr_per_pin: Number of iodelay registers for each pin
54 * @regmap_config: Regmap configuration for the IODelay region
55 */
56 struct ti_iodelay_reg_data {
57 u32 signature_mask;
58 u32 signature_value;
59 u32 lock_mask;
60 u32 lock_val;
61 u32 unlock_val;
62 u32 binary_data_coarse_mask;
63 u32 binary_data_fine_mask;
64
65 u32 reg_refclk_offset;
66 u32 refclk_period_mask;
67
68 u32 reg_coarse_offset;
69 u32 coarse_delay_count_mask;
70 u32 coarse_ref_count_mask;
71
72 u32 reg_fine_offset;
73 u32 fine_delay_count_mask;
74 u32 fine_ref_count_mask;
75
76 u32 reg_global_lock_offset;
77 u32 global_lock_mask;
78 u32 global_unlock_val;
79 u32 global_lock_val;
80
81 u32 reg_start_offset;
82 u32 reg_nr_per_pin;
83
84 struct regmap_config *regmap_config;
85 };
86
87 /**
88 * struct ti_iodelay_reg_values - Computed io_reg configuration values (see TRM)
89 * @coarse_ref_count: Coarse reference count
90 * @coarse_delay_count: Coarse delay count
91 * @fine_ref_count: Fine reference count
92 * @fine_delay_count: Fine Delay count
93 * @ref_clk_period: Reference Clock period
94 * @cdpe: Coarse delay parameter
95 * @fdpe: Fine delay parameter
96 */
97 struct ti_iodelay_reg_values {
98 u16 coarse_ref_count;
99 u16 coarse_delay_count;
100
101 u16 fine_ref_count;
102 u16 fine_delay_count;
103
104 u16 ref_clk_period;
105
106 u32 cdpe;
107 u32 fdpe;
108 };
109
110 /**
111 * struct ti_iodelay_cfg - Description of each configuration parameters
112 * @offset: Configuration register offset
113 * @a_delay: Agnostic Delay (in ps)
114 * @g_delay: Gnostic Delay (in ps)
115 */
116 struct ti_iodelay_cfg {
117 u16 offset;
118 u16 a_delay;
119 u16 g_delay;
120 };
121
122 /**
123 * struct ti_iodelay_pingroup - Structure that describes one group
124 * @cfg: configuration array for the pin (from dt)
125 * @ncfg: number of configuration values allocated
126 * @config: pinconf "Config" - currently a dummy value
127 */
128 struct ti_iodelay_pingroup {
129 struct ti_iodelay_cfg *cfg;
130 int ncfg;
131 unsigned long config;
132 };
133
134 /**
135 * struct ti_iodelay_device - Represents information for a iodelay instance
136 * @dev: Device pointer
137 * @phys_base: Physical address base of the iodelay device
138 * @reg_base: Virtual address base of the iodelay device
139 * @regmap: Regmap for this iodelay instance
140 * @pctl: Pinctrl device
141 * @desc: pinctrl descriptor for pctl
142 * @pa: pinctrl pin wise description
143 * @reg_data: Register definition data for the IODelay instance
144 * @reg_init_conf_values: Initial configuration values.
145 */
146 struct ti_iodelay_device {
147 struct device *dev;
148 unsigned long phys_base;
149 void __iomem *reg_base;
150 struct regmap *regmap;
151
152 struct pinctrl_dev *pctl;
153 struct pinctrl_desc desc;
154 struct pinctrl_pin_desc *pa;
155
156 const struct ti_iodelay_reg_data *reg_data;
157 struct ti_iodelay_reg_values reg_init_conf_values;
158 };
159
160 /**
161 * ti_iodelay_extract() - extract bits for a field
162 * @val: Register value
163 * @mask: Mask
164 *
165 * Return: extracted value which is appropriately shifted
166 */
ti_iodelay_extract(u32 val,u32 mask)167 static inline u32 ti_iodelay_extract(u32 val, u32 mask)
168 {
169 return (val & mask) >> __ffs(mask);
170 }
171
172 /**
173 * ti_iodelay_compute_dpe() - Compute equation for delay parameter
174 * @period: Period to use
175 * @ref: Reference Count
176 * @delay: Delay count
177 * @delay_m: Delay multiplier
178 *
179 * Return: Computed delay parameter
180 */
ti_iodelay_compute_dpe(u16 period,u16 ref,u16 delay,u16 delay_m)181 static inline u32 ti_iodelay_compute_dpe(u16 period, u16 ref, u16 delay,
182 u16 delay_m)
183 {
184 u64 m, d;
185
186 /* Handle overflow conditions */
187 m = 10 * (u64)period * (u64)ref;
188 d = 2 * (u64)delay * (u64)delay_m;
189
190 /* Truncate result back to 32 bits */
191 return div64_u64(m, d);
192 }
193
194 /**
195 * ti_iodelay_pinconf_set() - Configure the pin configuration
196 * @iod: iodelay device
197 * @cfg: Configuration
198 *
199 * Update the configuration register as per TRM and lockup once done.
200 * *IMPORTANT NOTE* SoC TRM does recommend doing iodelay programmation only
201 * while in Isolation. But, then, isolation also implies that every pin
202 * on the SoC (including DDR) will be isolated out. The only benefit being
203 * a glitchless configuration, However, the intent of this driver is purely
204 * to support a "glitchy" configuration where applicable.
205 *
206 * Return: 0 in case of success, else appropriate error value
207 */
ti_iodelay_pinconf_set(struct ti_iodelay_device * iod,struct ti_iodelay_cfg * cfg)208 static int ti_iodelay_pinconf_set(struct ti_iodelay_device *iod,
209 struct ti_iodelay_cfg *cfg)
210 {
211 const struct ti_iodelay_reg_data *reg = iod->reg_data;
212 struct ti_iodelay_reg_values *ival = &iod->reg_init_conf_values;
213 struct device *dev = iod->dev;
214 u32 g_delay_coarse, g_delay_fine;
215 u32 a_delay_coarse, a_delay_fine;
216 u32 c_elements, f_elements;
217 u32 total_delay;
218 u32 reg_mask, reg_val, tmp_val;
219 int r;
220
221 /* NOTE: Truncation is expected in all division below */
222 g_delay_coarse = cfg->g_delay / 920;
223 g_delay_fine = ((cfg->g_delay % 920) * 10) / 60;
224
225 a_delay_coarse = cfg->a_delay / ival->cdpe;
226 a_delay_fine = ((cfg->a_delay % ival->cdpe) * 10) / ival->fdpe;
227
228 c_elements = g_delay_coarse + a_delay_coarse;
229 f_elements = (g_delay_fine + a_delay_fine) / 10;
230
231 if (f_elements > 22) {
232 total_delay = c_elements * ival->cdpe + f_elements * ival->fdpe;
233 c_elements = total_delay / ival->cdpe;
234 f_elements = (total_delay % ival->cdpe) / ival->fdpe;
235 }
236
237 reg_mask = reg->signature_mask;
238 reg_val = reg->signature_value << __ffs(reg->signature_mask);
239
240 reg_mask |= reg->binary_data_coarse_mask;
241 tmp_val = c_elements << __ffs(reg->binary_data_coarse_mask);
242 if (tmp_val & ~reg->binary_data_coarse_mask) {
243 dev_err(dev, "Masking overflow of coarse elements %08x\n",
244 tmp_val);
245 tmp_val &= reg->binary_data_coarse_mask;
246 }
247 reg_val |= tmp_val;
248
249 reg_mask |= reg->binary_data_fine_mask;
250 tmp_val = f_elements << __ffs(reg->binary_data_fine_mask);
251 if (tmp_val & ~reg->binary_data_fine_mask) {
252 dev_err(dev, "Masking overflow of fine elements %08x\n",
253 tmp_val);
254 tmp_val &= reg->binary_data_fine_mask;
255 }
256 reg_val |= tmp_val;
257
258 /*
259 * NOTE: we leave the iodelay values unlocked - this is to work around
260 * situations such as those found with mmc mode change.
261 * However, this leaves open any unwarranted changes to padconf register
262 * impacting iodelay configuration. Use with care!
263 */
264 reg_mask |= reg->lock_mask;
265 reg_val |= reg->unlock_val << __ffs(reg->lock_mask);
266 r = regmap_update_bits(iod->regmap, cfg->offset, reg_mask, reg_val);
267
268 dev_dbg(dev, "Set reg 0x%x Delay(a: %d g: %d), Elements(C=%d F=%d)0x%x\n",
269 cfg->offset, cfg->a_delay, cfg->g_delay, c_elements,
270 f_elements, reg_val);
271
272 return r;
273 }
274
275 /**
276 * ti_iodelay_pinconf_init_dev() - Initialize IODelay device
277 * @iod: iodelay device
278 *
279 * Unlocks the iodelay region, computes the common parameters
280 *
281 * Return: 0 in case of success, else appropriate error value
282 */
ti_iodelay_pinconf_init_dev(struct ti_iodelay_device * iod)283 static int ti_iodelay_pinconf_init_dev(struct ti_iodelay_device *iod)
284 {
285 const struct ti_iodelay_reg_data *reg = iod->reg_data;
286 struct device *dev = iod->dev;
287 struct ti_iodelay_reg_values *ival = &iod->reg_init_conf_values;
288 u32 val;
289 int r;
290
291 /* unlock the iodelay region */
292 r = regmap_update_bits(iod->regmap, reg->reg_global_lock_offset,
293 reg->global_lock_mask, reg->global_unlock_val);
294 if (r)
295 return r;
296
297 /* Read up Recalibration sequence done by bootloader */
298 r = regmap_read(iod->regmap, reg->reg_refclk_offset, &val);
299 if (r)
300 return r;
301 ival->ref_clk_period = ti_iodelay_extract(val, reg->refclk_period_mask);
302 dev_dbg(dev, "refclk_period=0x%04x\n", ival->ref_clk_period);
303
304 r = regmap_read(iod->regmap, reg->reg_coarse_offset, &val);
305 if (r)
306 return r;
307 ival->coarse_ref_count =
308 ti_iodelay_extract(val, reg->coarse_ref_count_mask);
309 ival->coarse_delay_count =
310 ti_iodelay_extract(val, reg->coarse_delay_count_mask);
311 if (!ival->coarse_delay_count) {
312 dev_err(dev, "Invalid Coarse delay count (0) (reg=0x%08x)\n",
313 val);
314 return -EINVAL;
315 }
316 ival->cdpe = ti_iodelay_compute_dpe(ival->ref_clk_period,
317 ival->coarse_ref_count,
318 ival->coarse_delay_count, 88);
319 if (!ival->cdpe) {
320 dev_err(dev, "Invalid cdpe computed params = %d %d %d\n",
321 ival->ref_clk_period, ival->coarse_ref_count,
322 ival->coarse_delay_count);
323 return -EINVAL;
324 }
325 dev_dbg(iod->dev, "coarse: ref=0x%04x delay=0x%04x cdpe=0x%08x\n",
326 ival->coarse_ref_count, ival->coarse_delay_count, ival->cdpe);
327
328 r = regmap_read(iod->regmap, reg->reg_fine_offset, &val);
329 if (r)
330 return r;
331 ival->fine_ref_count =
332 ti_iodelay_extract(val, reg->fine_ref_count_mask);
333 ival->fine_delay_count =
334 ti_iodelay_extract(val, reg->fine_delay_count_mask);
335 if (!ival->fine_delay_count) {
336 dev_err(dev, "Invalid Fine delay count (0) (reg=0x%08x)\n",
337 val);
338 return -EINVAL;
339 }
340 ival->fdpe = ti_iodelay_compute_dpe(ival->ref_clk_period,
341 ival->fine_ref_count,
342 ival->fine_delay_count, 264);
343 if (!ival->fdpe) {
344 dev_err(dev, "Invalid fdpe(0) computed params = %d %d %d\n",
345 ival->ref_clk_period, ival->fine_ref_count,
346 ival->fine_delay_count);
347 return -EINVAL;
348 }
349 dev_dbg(iod->dev, "fine: ref=0x%04x delay=0x%04x fdpe=0x%08x\n",
350 ival->fine_ref_count, ival->fine_delay_count, ival->fdpe);
351
352 return 0;
353 }
354
355 /**
356 * ti_iodelay_pinconf_deinit_dev() - deinit the iodelay device
357 * @iod: IODelay device
358 *
359 * Deinitialize the IODelay device (basically just lock the region back up.
360 */
ti_iodelay_pinconf_deinit_dev(struct ti_iodelay_device * iod)361 static void ti_iodelay_pinconf_deinit_dev(struct ti_iodelay_device *iod)
362 {
363 const struct ti_iodelay_reg_data *reg = iod->reg_data;
364
365 /* lock the iodelay region back again */
366 regmap_update_bits(iod->regmap, reg->reg_global_lock_offset,
367 reg->global_lock_mask, reg->global_lock_val);
368 }
369
370 /**
371 * ti_iodelay_get_pingroup() - Find the group mapped by a group selector
372 * @iod: iodelay device
373 * @selector: Group Selector
374 *
375 * Return: Corresponding group representing group selector
376 */
377 static struct ti_iodelay_pingroup *
ti_iodelay_get_pingroup(struct ti_iodelay_device * iod,unsigned int selector)378 ti_iodelay_get_pingroup(struct ti_iodelay_device *iod, unsigned int selector)
379 {
380 struct group_desc *g;
381
382 g = pinctrl_generic_get_group(iod->pctl, selector);
383 if (!g) {
384 dev_err(iod->dev, "%s could not find pingroup %i\n", __func__,
385 selector);
386
387 return NULL;
388 }
389
390 return g->data;
391 }
392
393 /**
394 * ti_iodelay_offset_to_pin() - get a pin index based on the register offset
395 * @iod: iodelay driver instance
396 * @offset: register offset from the base
397 */
ti_iodelay_offset_to_pin(struct ti_iodelay_device * iod,unsigned int offset)398 static int ti_iodelay_offset_to_pin(struct ti_iodelay_device *iod,
399 unsigned int offset)
400 {
401 const struct ti_iodelay_reg_data *r = iod->reg_data;
402 unsigned int index;
403
404 if (offset > r->regmap_config->max_register) {
405 dev_err(iod->dev, "mux offset out of range: 0x%x (0x%x)\n",
406 offset, r->regmap_config->max_register);
407 return -EINVAL;
408 }
409
410 index = (offset - r->reg_start_offset) / r->regmap_config->reg_stride;
411 index /= r->reg_nr_per_pin;
412
413 return index;
414 }
415
416 /**
417 * ti_iodelay_node_iterator() - Iterate iodelay node
418 * @pctldev: Pin controller driver
419 * @np: Device node
420 * @pinctrl_spec: Parsed arguments from device tree
421 * @pins: Array of pins in the pin group
422 * @pin_index: Pin index in the pin array
423 * @data: Pin controller driver specific data
424 *
425 */
ti_iodelay_node_iterator(struct pinctrl_dev * pctldev,struct device_node * np,const struct of_phandle_args * pinctrl_spec,int * pins,int pin_index,void * data)426 static int ti_iodelay_node_iterator(struct pinctrl_dev *pctldev,
427 struct device_node *np,
428 const struct of_phandle_args *pinctrl_spec,
429 int *pins, int pin_index, void *data)
430 {
431 struct ti_iodelay_device *iod;
432 struct ti_iodelay_cfg *cfg = data;
433 const struct ti_iodelay_reg_data *r;
434 struct pinctrl_pin_desc *pd;
435 int pin;
436
437 iod = pinctrl_dev_get_drvdata(pctldev);
438 if (!iod)
439 return -EINVAL;
440
441 r = iod->reg_data;
442
443 if (pinctrl_spec->args_count < r->reg_nr_per_pin) {
444 dev_err(iod->dev, "invalid args_count for spec: %i\n",
445 pinctrl_spec->args_count);
446
447 return -EINVAL;
448 }
449
450 /* Index plus two value cells */
451 cfg[pin_index].offset = pinctrl_spec->args[0];
452 cfg[pin_index].a_delay = pinctrl_spec->args[1] & 0xffff;
453 cfg[pin_index].g_delay = pinctrl_spec->args[2] & 0xffff;
454
455 pin = ti_iodelay_offset_to_pin(iod, cfg[pin_index].offset);
456 if (pin < 0) {
457 dev_err(iod->dev, "could not add functions for %pOFn %ux\n",
458 np, cfg[pin_index].offset);
459 return -ENODEV;
460 }
461 pins[pin_index] = pin;
462
463 pd = &iod->pa[pin];
464 pd->drv_data = &cfg[pin_index];
465
466 dev_dbg(iod->dev, "%pOFn offset=%x a_delay = %d g_delay = %d\n",
467 np, cfg[pin_index].offset, cfg[pin_index].a_delay,
468 cfg[pin_index].g_delay);
469
470 return 0;
471 }
472
473 /**
474 * ti_iodelay_dt_node_to_map() - Map a device tree node to appropriate group
475 * @pctldev: pinctrl device representing IODelay device
476 * @np: Node Pointer (device tree)
477 * @map: Pinctrl Map returned back to pinctrl framework
478 * @num_maps: Number of maps (1)
479 *
480 * Maps the device tree description into a group of configuration parameters
481 * for iodelay block entry.
482 *
483 * Return: 0 in case of success, else appropriate error value
484 */
ti_iodelay_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned int * num_maps)485 static int ti_iodelay_dt_node_to_map(struct pinctrl_dev *pctldev,
486 struct device_node *np,
487 struct pinctrl_map **map,
488 unsigned int *num_maps)
489 {
490 struct ti_iodelay_device *iod;
491 struct ti_iodelay_cfg *cfg;
492 struct ti_iodelay_pingroup *g;
493 const char *name = "pinctrl-pin-array";
494 int rows, *pins, error = -EINVAL, i;
495
496 iod = pinctrl_dev_get_drvdata(pctldev);
497 if (!iod)
498 return -EINVAL;
499
500 rows = pinctrl_count_index_with_args(np, name);
501 if (rows < 0)
502 return rows;
503
504 *map = devm_kzalloc(iod->dev, sizeof(**map), GFP_KERNEL);
505 if (!*map)
506 return -ENOMEM;
507 *num_maps = 0;
508
509 g = devm_kzalloc(iod->dev, sizeof(*g), GFP_KERNEL);
510 if (!g) {
511 error = -ENOMEM;
512 goto free_map;
513 }
514
515 pins = devm_kcalloc(iod->dev, rows, sizeof(*pins), GFP_KERNEL);
516 if (!pins) {
517 error = -ENOMEM;
518 goto free_group;
519 }
520
521 cfg = devm_kcalloc(iod->dev, rows, sizeof(*cfg), GFP_KERNEL);
522 if (!cfg) {
523 error = -ENOMEM;
524 goto free_pins;
525 }
526
527 for (i = 0; i < rows; i++) {
528 struct of_phandle_args pinctrl_spec;
529
530 error = pinctrl_parse_index_with_args(np, name, i,
531 &pinctrl_spec);
532 if (error)
533 goto free_data;
534
535 error = ti_iodelay_node_iterator(pctldev, np, &pinctrl_spec,
536 pins, i, cfg);
537 if (error)
538 goto free_data;
539 }
540
541 g->cfg = cfg;
542 g->ncfg = i;
543 g->config = PIN_CONFIG_END;
544
545 error = pinctrl_generic_add_group(iod->pctl, np->name, pins, i, g);
546 if (error < 0)
547 goto free_data;
548
549 (*map)->type = PIN_MAP_TYPE_CONFIGS_GROUP;
550 (*map)->data.configs.group_or_pin = np->name;
551 (*map)->data.configs.configs = &g->config;
552 (*map)->data.configs.num_configs = 1;
553 *num_maps = 1;
554
555 return 0;
556
557 free_data:
558 devm_kfree(iod->dev, cfg);
559 free_pins:
560 devm_kfree(iod->dev, pins);
561 free_group:
562 devm_kfree(iod->dev, g);
563 free_map:
564 devm_kfree(iod->dev, *map);
565
566 return error;
567 }
568
569 /**
570 * ti_iodelay_pinconf_group_get() - Get the group configuration
571 * @pctldev: pinctrl device representing IODelay device
572 * @selector: Group selector
573 * @config: Configuration returned
574 *
575 * Return: The configuration if the group is valid, else returns -EINVAL
576 */
ti_iodelay_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int selector,unsigned long * config)577 static int ti_iodelay_pinconf_group_get(struct pinctrl_dev *pctldev,
578 unsigned int selector,
579 unsigned long *config)
580 {
581 struct ti_iodelay_device *iod;
582 struct ti_iodelay_pingroup *group;
583
584 iod = pinctrl_dev_get_drvdata(pctldev);
585 group = ti_iodelay_get_pingroup(iod, selector);
586
587 if (!group)
588 return -EINVAL;
589
590 *config = group->config;
591 return 0;
592 }
593
594 /**
595 * ti_iodelay_pinconf_group_set() - Configure the groups of pins
596 * @pctldev: pinctrl device representing IODelay device
597 * @selector: Group selector
598 * @configs: Configurations
599 * @num_configs: Number of configurations
600 *
601 * Return: 0 if all went fine, else appropriate error value.
602 */
ti_iodelay_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned int selector,unsigned long * configs,unsigned int num_configs)603 static int ti_iodelay_pinconf_group_set(struct pinctrl_dev *pctldev,
604 unsigned int selector,
605 unsigned long *configs,
606 unsigned int num_configs)
607 {
608 struct ti_iodelay_device *iod;
609 struct device *dev;
610 struct ti_iodelay_pingroup *group;
611 int i;
612
613 iod = pinctrl_dev_get_drvdata(pctldev);
614 dev = iod->dev;
615 group = ti_iodelay_get_pingroup(iod, selector);
616
617 if (num_configs != 1) {
618 dev_err(dev, "Unsupported number of configurations %d\n",
619 num_configs);
620 return -EINVAL;
621 }
622
623 if (*configs != PIN_CONFIG_END) {
624 dev_err(dev, "Unsupported configuration\n");
625 return -EINVAL;
626 }
627
628 for (i = 0; i < group->ncfg; i++) {
629 if (ti_iodelay_pinconf_set(iod, &group->cfg[i]))
630 return -ENOTSUPP;
631 }
632
633 return 0;
634 }
635
636 #ifdef CONFIG_DEBUG_FS
637 /**
638 * ti_iodelay_pin_to_offset() - get pin register offset based on the pin index
639 * @iod: iodelay driver instance
640 * @selector: Pin index
641 */
ti_iodelay_pin_to_offset(struct ti_iodelay_device * iod,unsigned int selector)642 static unsigned int ti_iodelay_pin_to_offset(struct ti_iodelay_device *iod,
643 unsigned int selector)
644 {
645 const struct ti_iodelay_reg_data *r = iod->reg_data;
646 unsigned int offset;
647
648 offset = selector * r->regmap_config->reg_stride;
649 offset *= r->reg_nr_per_pin;
650 offset += r->reg_start_offset;
651
652 return offset;
653 }
654
ti_iodelay_pin_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int pin)655 static void ti_iodelay_pin_dbg_show(struct pinctrl_dev *pctldev,
656 struct seq_file *s,
657 unsigned int pin)
658 {
659 struct ti_iodelay_device *iod;
660 struct pinctrl_pin_desc *pd;
661 struct ti_iodelay_cfg *cfg;
662 const struct ti_iodelay_reg_data *r;
663 unsigned long offset;
664 u32 in, oen, out;
665
666 iod = pinctrl_dev_get_drvdata(pctldev);
667 r = iod->reg_data;
668
669 offset = ti_iodelay_pin_to_offset(iod, pin);
670 pd = &iod->pa[pin];
671 cfg = pd->drv_data;
672
673 regmap_read(iod->regmap, offset, &in);
674 regmap_read(iod->regmap, offset + r->regmap_config->reg_stride, &oen);
675 regmap_read(iod->regmap, offset + r->regmap_config->reg_stride * 2,
676 &out);
677
678 seq_printf(s, "%lx a: %i g: %i (%08x %08x %08x) %s ",
679 iod->phys_base + offset,
680 cfg ? cfg->a_delay : -1,
681 cfg ? cfg->g_delay : -1,
682 in, oen, out, DRIVER_NAME);
683 }
684
685 /**
686 * ti_iodelay_pinconf_group_dbg_show() - show the group information
687 * @pctldev: Show the group information
688 * @s: Sequence file
689 * @selector: Group selector
690 *
691 * Provide the configuration information of the selected group
692 */
ti_iodelay_pinconf_group_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int selector)693 static void ti_iodelay_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
694 struct seq_file *s,
695 unsigned int selector)
696 {
697 struct ti_iodelay_device *iod;
698 struct ti_iodelay_pingroup *group;
699 int i;
700
701 iod = pinctrl_dev_get_drvdata(pctldev);
702 group = ti_iodelay_get_pingroup(iod, selector);
703 if (!group)
704 return;
705
706 for (i = 0; i < group->ncfg; i++) {
707 struct ti_iodelay_cfg *cfg;
708 u32 reg = 0;
709
710 cfg = &group->cfg[i];
711 regmap_read(iod->regmap, cfg->offset, ®);
712 seq_printf(s, "\n\t0x%08x = 0x%08x (%3d, %3d)",
713 cfg->offset, reg, cfg->a_delay, cfg->g_delay);
714 }
715 }
716 #endif
717
718 static const struct pinctrl_ops ti_iodelay_pinctrl_ops = {
719 .get_groups_count = pinctrl_generic_get_group_count,
720 .get_group_name = pinctrl_generic_get_group_name,
721 .get_group_pins = pinctrl_generic_get_group_pins,
722 #ifdef CONFIG_DEBUG_FS
723 .pin_dbg_show = ti_iodelay_pin_dbg_show,
724 #endif
725 .dt_node_to_map = ti_iodelay_dt_node_to_map,
726 };
727
728 static const struct pinconf_ops ti_iodelay_pinctrl_pinconf_ops = {
729 .pin_config_group_get = ti_iodelay_pinconf_group_get,
730 .pin_config_group_set = ti_iodelay_pinconf_group_set,
731 #ifdef CONFIG_DEBUG_FS
732 .pin_config_group_dbg_show = ti_iodelay_pinconf_group_dbg_show,
733 #endif
734 };
735
736 /**
737 * ti_iodelay_alloc_pins() - Allocate structures needed for pins for iodelay
738 * @dev: Device pointer
739 * @iod: iodelay device
740 * @base_phy: Base Physical Address
741 *
742 * Return: 0 if all went fine, else appropriate error value.
743 */
ti_iodelay_alloc_pins(struct device * dev,struct ti_iodelay_device * iod,u32 base_phy)744 static int ti_iodelay_alloc_pins(struct device *dev,
745 struct ti_iodelay_device *iod, u32 base_phy)
746 {
747 const struct ti_iodelay_reg_data *r = iod->reg_data;
748 struct pinctrl_pin_desc *pin;
749 u32 phy_reg;
750 int nr_pins, i;
751
752 nr_pins = ti_iodelay_offset_to_pin(iod, r->regmap_config->max_register);
753 dev_dbg(dev, "Allocating %i pins\n", nr_pins);
754
755 iod->pa = devm_kcalloc(dev, nr_pins, sizeof(*iod->pa), GFP_KERNEL);
756 if (!iod->pa)
757 return -ENOMEM;
758
759 iod->desc.pins = iod->pa;
760 iod->desc.npins = nr_pins;
761
762 phy_reg = r->reg_start_offset + base_phy;
763
764 for (i = 0; i < nr_pins; i++, phy_reg += 4) {
765 pin = &iod->pa[i];
766 pin->number = i;
767 }
768
769 return 0;
770 }
771
772 static struct regmap_config dra7_iodelay_regmap_config = {
773 .reg_bits = 32,
774 .reg_stride = 4,
775 .val_bits = 32,
776 .max_register = 0xd1c,
777 };
778
779 static struct ti_iodelay_reg_data dra7_iodelay_data = {
780 .signature_mask = 0x0003f000,
781 .signature_value = 0x29,
782 .lock_mask = 0x00000400,
783 .lock_val = 1,
784 .unlock_val = 0,
785 .binary_data_coarse_mask = 0x000003e0,
786 .binary_data_fine_mask = 0x0000001f,
787
788 .reg_refclk_offset = 0x14,
789 .refclk_period_mask = 0xffff,
790
791 .reg_coarse_offset = 0x18,
792 .coarse_delay_count_mask = 0xffff0000,
793 .coarse_ref_count_mask = 0x0000ffff,
794
795 .reg_fine_offset = 0x1C,
796 .fine_delay_count_mask = 0xffff0000,
797 .fine_ref_count_mask = 0x0000ffff,
798
799 .reg_global_lock_offset = 0x2c,
800 .global_lock_mask = 0x0000ffff,
801 .global_unlock_val = 0x0000aaaa,
802 .global_lock_val = 0x0000aaab,
803
804 .reg_start_offset = 0x30,
805 .reg_nr_per_pin = 3,
806 .regmap_config = &dra7_iodelay_regmap_config,
807 };
808
809 static const struct of_device_id ti_iodelay_of_match[] = {
810 {.compatible = "ti,dra7-iodelay", .data = &dra7_iodelay_data},
811 { /* Hopefully no more.. */ },
812 };
813 MODULE_DEVICE_TABLE(of, ti_iodelay_of_match);
814
815 /**
816 * ti_iodelay_probe() - Standard probe
817 * @pdev: platform device
818 *
819 * Return: 0 if all went fine, else appropriate error value.
820 */
ti_iodelay_probe(struct platform_device * pdev)821 static int ti_iodelay_probe(struct platform_device *pdev)
822 {
823 struct device *dev = &pdev->dev;
824 struct device_node *np = of_node_get(dev->of_node);
825 const struct of_device_id *match;
826 struct resource *res;
827 struct ti_iodelay_device *iod;
828 int ret = 0;
829
830 if (!np) {
831 ret = -EINVAL;
832 dev_err(dev, "No OF node\n");
833 goto exit_out;
834 }
835
836 match = of_match_device(ti_iodelay_of_match, dev);
837 if (!match) {
838 ret = -EINVAL;
839 dev_err(dev, "No DATA match\n");
840 goto exit_out;
841 }
842
843 iod = devm_kzalloc(dev, sizeof(*iod), GFP_KERNEL);
844 if (!iod) {
845 ret = -ENOMEM;
846 goto exit_out;
847 }
848 iod->dev = dev;
849 iod->reg_data = match->data;
850
851 /* So far We can assume there is only 1 bank of registers */
852 iod->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
853 if (IS_ERR(iod->reg_base)) {
854 ret = PTR_ERR(iod->reg_base);
855 goto exit_out;
856 }
857 iod->phys_base = res->start;
858
859 iod->regmap = devm_regmap_init_mmio(dev, iod->reg_base,
860 iod->reg_data->regmap_config);
861 if (IS_ERR(iod->regmap)) {
862 dev_err(dev, "Regmap MMIO init failed.\n");
863 ret = PTR_ERR(iod->regmap);
864 goto exit_out;
865 }
866
867 ret = ti_iodelay_pinconf_init_dev(iod);
868 if (ret)
869 goto exit_out;
870
871 ret = ti_iodelay_alloc_pins(dev, iod, res->start);
872 if (ret)
873 goto exit_out;
874
875 iod->desc.pctlops = &ti_iodelay_pinctrl_ops;
876 /* no pinmux ops - we are pinconf */
877 iod->desc.confops = &ti_iodelay_pinctrl_pinconf_ops;
878 iod->desc.name = dev_name(dev);
879 iod->desc.owner = THIS_MODULE;
880
881 ret = pinctrl_register_and_init(&iod->desc, dev, iod, &iod->pctl);
882 if (ret) {
883 dev_err(dev, "Failed to register pinctrl\n");
884 goto exit_out;
885 }
886
887 platform_set_drvdata(pdev, iod);
888
889 return pinctrl_enable(iod->pctl);
890
891 exit_out:
892 of_node_put(np);
893 return ret;
894 }
895
896 /**
897 * ti_iodelay_remove() - standard remove
898 * @pdev: platform device
899 *
900 * Return: 0 if all went fine, else appropriate error value.
901 */
ti_iodelay_remove(struct platform_device * pdev)902 static int ti_iodelay_remove(struct platform_device *pdev)
903 {
904 struct ti_iodelay_device *iod = platform_get_drvdata(pdev);
905
906 if (!iod)
907 return 0;
908
909 if (iod->pctl)
910 pinctrl_unregister(iod->pctl);
911
912 ti_iodelay_pinconf_deinit_dev(iod);
913
914 /* Expect other allocations to be freed by devm */
915
916 return 0;
917 }
918
919 static struct platform_driver ti_iodelay_driver = {
920 .probe = ti_iodelay_probe,
921 .remove = ti_iodelay_remove,
922 .driver = {
923 .name = DRIVER_NAME,
924 .of_match_table = ti_iodelay_of_match,
925 },
926 };
927 module_platform_driver(ti_iodelay_driver);
928
929 MODULE_AUTHOR("Texas Instruments, Inc.");
930 MODULE_DESCRIPTION("Pinconf driver for TI's IO Delay module");
931 MODULE_LICENSE("GPL v2");
932
