1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * pinctrl pads, groups, functions for CSR SiRFatlasVII
4 *
5 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
6 * company.
7 */
8
9 #include <linux/init.h>
10 #include <linux/platform_device.h>
11 #include <linux/io.h>
12 #include <linux/bitops.h>
13 #include <linux/irq.h>
14 #include <linux/slab.h>
15 #include <linux/clk.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/of_platform.h>
20 #include <linux/of_irq.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/gpio/driver.h>
28
29 /* Definition of Pad&Mux Properties */
30 #define N 0
31
32 /* The Bank contains input-disable regisgers */
33 #define BANK_DS 0
34
35 /* Clear Register offset */
36 #define CLR_REG(r) ((r) + 0x04)
37
38 /* Definition of multiple function select register */
39 #define FUNC_CLEAR_MASK 0x7
40 #define FUNC_GPIO 0
41 #define FUNC_ANALOGUE 0x8
42 #define ANA_CLEAR_MASK 0x1
43
44 /* The Atlas7's Pad Type List */
45 enum altas7_pad_type {
46 PAD_T_4WE_PD = 0, /* ZIO_PAD3V_4WE_PD */
47 PAD_T_4WE_PU, /* ZIO_PAD3V_4WE_PD */
48 PAD_T_16ST, /* ZIO_PAD3V_SDCLK_PD */
49 PAD_T_M31_0204_PD, /* PRDW0204SDGZ_M311311_PD */
50 PAD_T_M31_0204_PU, /* PRDW0204SDGZ_M311311_PU */
51 PAD_T_M31_0610_PD, /* PRUW0610SDGZ_M311311_PD */
52 PAD_T_M31_0610_PU, /* PRUW0610SDGZ_M311311_PU */
53 PAD_T_AD, /* PRDWUWHW08SCDG_HZ */
54 };
55
56 /* Raw value of Driver-Strength Bits */
57 #define DS3 BIT(3)
58 #define DS2 BIT(2)
59 #define DS1 BIT(1)
60 #define DS0 BIT(0)
61 #define DSZ 0
62
63 /* Drive-Strength Intermediate Values */
64 #define DS_NULL -1
65 #define DS_1BIT_IM_VAL DS0
66 #define DS_1BIT_MASK 0x1
67 #define DS_2BIT_IM_VAL (DS1 | DS0)
68 #define DS_2BIT_MASK 0x3
69 #define DS_4BIT_IM_VAL (DS3 | DS2 | DS1 | DS0)
70 #define DS_4BIT_MASK 0xf
71
72 /* The Drive-Strength of 4WE Pad DS1 0 CO */
73 #define DS_4WE_3 (DS1 | DS0) /* 1 1 3 */
74 #define DS_4WE_2 (DS1) /* 1 0 2 */
75 #define DS_4WE_1 (DS0) /* 0 1 1 */
76 #define DS_4WE_0 (DSZ) /* 0 0 0 */
77
78 /* The Drive-Strength of 16st Pad DS3 2 1 0 CO */
79 #define DS_16ST_15 (DS3 | DS2 | DS1 | DS0) /* 1 1 1 1 15 */
80 #define DS_16ST_14 (DS3 | DS2 | DS0) /* 1 1 0 1 13 */
81 #define DS_16ST_13 (DS3 | DS2 | DS1) /* 1 1 1 0 14 */
82 #define DS_16ST_12 (DS2 | DS1 | DS0) /* 0 1 1 1 7 */
83 #define DS_16ST_11 (DS2 | DS0) /* 0 1 0 1 5 */
84 #define DS_16ST_10 (DS3 | DS1 | DS0) /* 1 0 1 1 11 */
85 #define DS_16ST_9 (DS3 | DS0) /* 1 0 0 1 9 */
86 #define DS_16ST_8 (DS1 | DS0) /* 0 0 1 1 3 */
87 #define DS_16ST_7 (DS2 | DS1) /* 0 1 1 0 6 */
88 #define DS_16ST_6 (DS3 | DS2) /* 1 1 0 0 12 */
89 #define DS_16ST_5 (DS2) /* 0 1 0 0 4 */
90 #define DS_16ST_4 (DS3 | DS1) /* 1 0 1 0 10 */
91 #define DS_16ST_3 (DS1) /* 0 0 1 0 2 */
92 #define DS_16ST_2 (DS0) /* 0 0 0 1 1 */
93 #define DS_16ST_1 (DSZ) /* 0 0 0 0 0 */
94 #define DS_16ST_0 (DS3) /* 1 0 0 0 8 */
95
96 /* The Drive-Strength of M31 Pad DS0 CO */
97 #define DS_M31_0 (DSZ) /* 0 0 */
98 #define DS_M31_1 (DS0) /* 1 1 */
99
100 /* Raw values of Pull Option Bits */
101 #define PUN BIT(1)
102 #define PD BIT(0)
103 #define PE BIT(0)
104 #define PZ 0
105
106 /* Definition of Pull Types */
107 #define PULL_UP 0
108 #define HIGH_HYSTERESIS 1
109 #define HIGH_Z 2
110 #define PULL_DOWN 3
111 #define PULL_DISABLE 4
112 #define PULL_ENABLE 5
113 #define PULL_UNKNOWN -1
114
115 /* Pull Options for 4WE Pad PUN PD CO */
116 #define P4WE_PULL_MASK 0x3
117 #define P4WE_PULL_DOWN (PUN | PD) /* 1 1 3 */
118 #define P4WE_HIGH_Z (PUN) /* 1 0 2 */
119 #define P4WE_HIGH_HYSTERESIS (PD) /* 0 1 1 */
120 #define P4WE_PULL_UP (PZ) /* 0 0 0 */
121
122 /* Pull Options for 16ST Pad PUN PD CO */
123 #define P16ST_PULL_MASK 0x3
124 #define P16ST_PULL_DOWN (PUN | PD) /* 1 1 3 */
125 #define P16ST_HIGH_Z (PUN) /* 1 0 2 */
126 #define P16ST_PULL_UP (PZ) /* 0 0 0 */
127
128 /* Pull Options for M31 Pad PE */
129 #define PM31_PULL_MASK 0x1
130 #define PM31_PULL_ENABLED (PE) /* 1 */
131 #define PM31_PULL_DISABLED (PZ) /* 0 */
132
133 /* Pull Options for A/D Pad PUN PD CO */
134 #define PANGD_PULL_MASK 0x3
135 #define PANGD_PULL_DOWN (PUN | PD) /* 1 1 3 */
136 #define PANGD_HIGH_Z (PUN) /* 1 0 2 */
137 #define PANGD_PULL_UP (PZ) /* 0 0 0 */
138
139 /* Definition of Input Disable */
140 #define DI_MASK 0x1
141 #define DI_DISABLE 0x1
142 #define DI_ENABLE 0x0
143
144 /* Definition of Input Disable Value */
145 #define DIV_MASK 0x1
146 #define DIV_DISABLE 0x1
147 #define DIV_ENABLE 0x0
148
149 /* Number of Function input disable registers */
150 #define NUM_OF_IN_DISABLE_REG 0x2
151
152 /* Offset of Function input disable registers */
153 #define IN_DISABLE_0_REG_SET 0x0A00
154 #define IN_DISABLE_0_REG_CLR 0x0A04
155 #define IN_DISABLE_1_REG_SET 0x0A08
156 #define IN_DISABLE_1_REG_CLR 0x0A0C
157 #define IN_DISABLE_VAL_0_REG_SET 0x0A80
158 #define IN_DISABLE_VAL_0_REG_CLR 0x0A84
159 #define IN_DISABLE_VAL_1_REG_SET 0x0A88
160 #define IN_DISABLE_VAL_1_REG_CLR 0x0A8C
161
162 /* Offset of the SDIO9SEL*/
163 #define SYS2PCI_SDIO9SEL 0x14
164
165 struct dt_params {
166 const char *property;
167 int value;
168 };
169
170 /**
171 * struct atlas7_pad_conf - Atlas7 Pad Configuration
172 * @id The ID of this Pad.
173 * @type: The type of this Pad.
174 * @mux_reg: The mux register offset.
175 * This register contains the mux.
176 * @pupd_reg: The pull-up/down register offset.
177 * @drvstr_reg: The drive-strength register offset.
178 * @ad_ctrl_reg: The Analogue/Digital Control register.
179 *
180 * @mux_bit: The start bit of mux register.
181 * @pupd_bit: The start bit of pull-up/down register.
182 * @drvstr_bit: The start bit of drive-strength register.
183 * @ad_ctrl_bit: The start bit of analogue/digital register.
184 */
185 struct atlas7_pad_config {
186 const u32 id;
187 u32 type;
188 u32 mux_reg;
189 u32 pupd_reg;
190 u32 drvstr_reg;
191 u32 ad_ctrl_reg;
192 /* bits in register */
193 u8 mux_bit;
194 u8 pupd_bit;
195 u8 drvstr_bit;
196 u8 ad_ctrl_bit;
197 };
198
199 #define PADCONF(pad, t, mr, pr, dsr, adr, mb, pb, dsb, adb) \
200 { \
201 .id = pad, \
202 .type = t, \
203 .mux_reg = mr, \
204 .pupd_reg = pr, \
205 .drvstr_reg = dsr, \
206 .ad_ctrl_reg = adr, \
207 .mux_bit = mb, \
208 .pupd_bit = pb, \
209 .drvstr_bit = dsb, \
210 .ad_ctrl_bit = adb, \
211 }
212
213 /**
214 * struct atlas7_pad_status - Atlas7 Pad status
215 */
216 struct atlas7_pad_status {
217 u8 func;
218 u8 pull;
219 u8 dstr;
220 u8 reserved;
221 };
222
223 /**
224 * struct atlas7_pad_mux - Atlas7 mux
225 * @bank: The bank of this pad's registers on.
226 * @pin : The ID of this Pad.
227 * @func: The mux func on this Pad.
228 * @dinput_reg: The Input-Disable register offset.
229 * @dinput_bit: The start bit of Input-Disable register.
230 * @dinput_val_reg: The Input-Disable-value register offset.
231 * This register is used to set the value of this pad
232 * if this pad was disabled.
233 * @dinput_val_bit: The start bit of Input-Disable Value register.
234 */
235 struct atlas7_pad_mux {
236 u32 bank;
237 u32 pin;
238 u32 func;
239 u32 dinput_reg;
240 u32 dinput_bit;
241 u32 dinput_val_reg;
242 u32 dinput_val_bit;
243 };
244
245 #define MUX(b, pad, f, dr, db, dvr, dvb) \
246 { \
247 .bank = b, \
248 .pin = pad, \
249 .func = f, \
250 .dinput_reg = dr, \
251 .dinput_bit = db, \
252 .dinput_val_reg = dvr, \
253 .dinput_val_bit = dvb, \
254 }
255
256 struct atlas7_grp_mux {
257 unsigned int group;
258 unsigned int pad_mux_count;
259 const struct atlas7_pad_mux *pad_mux_list;
260 };
261
262 /**
263 * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
264 * @name: the name of this specific pin group
265 * @pins: an array of discrete physical pins used in this group, taken
266 * from the driver-local pin enumeration space
267 * @num_pins: the number of pins in this group array, i.e. the number of
268 * elements in .pins so we can iterate over that array
269 */
270 struct atlas7_pin_group {
271 const char *name;
272 const unsigned int *pins;
273 const unsigned num_pins;
274 };
275
276 #define GROUP(n, p) \
277 { \
278 .name = n, \
279 .pins = p, \
280 .num_pins = ARRAY_SIZE(p), \
281 }
282
283 struct atlas7_pmx_func {
284 const char *name;
285 const char * const *groups;
286 const unsigned num_groups;
287 const struct atlas7_grp_mux *grpmux;
288 };
289
290 #define FUNCTION(n, g, m) \
291 { \
292 .name = n, \
293 .groups = g, \
294 .num_groups = ARRAY_SIZE(g), \
295 .grpmux = m, \
296 }
297
298 struct atlas7_pinctrl_data {
299 struct pinctrl_pin_desc *pads;
300 int pads_cnt;
301 struct atlas7_pin_group *grps;
302 int grps_cnt;
303 struct atlas7_pmx_func *funcs;
304 int funcs_cnt;
305 struct atlas7_pad_config *confs;
306 int confs_cnt;
307 };
308
309 /* Platform info of atlas7 pinctrl */
310 #define ATLAS7_PINCTRL_REG_BANKS 2
311 #define ATLAS7_PINCTRL_BANK_0_PINS 18
312 #define ATLAS7_PINCTRL_BANK_1_PINS 141
313 #define ATLAS7_PINCTRL_TOTAL_PINS \
314 (ATLAS7_PINCTRL_BANK_0_PINS + ATLAS7_PINCTRL_BANK_1_PINS)
315
316 /**
317 * Atlas7 GPIO Chip
318 */
319
320 #define NGPIO_OF_BANK 32
321 #define GPIO_TO_BANK(gpio) ((gpio) / NGPIO_OF_BANK)
322
323 /* Registers of GPIO Controllers */
324 #define ATLAS7_GPIO_BASE(g, b) ((g)->reg + 0x100 * (b))
325 #define ATLAS7_GPIO_CTRL(b, i) ((b)->base + 4 * (i))
326 #define ATLAS7_GPIO_INT_STATUS(b) ((b)->base + 0x8C)
327
328 /* Definition bits of GPIO Control Registers */
329 #define ATLAS7_GPIO_CTL_INTR_LOW_MASK BIT(0)
330 #define ATLAS7_GPIO_CTL_INTR_HIGH_MASK BIT(1)
331 #define ATLAS7_GPIO_CTL_INTR_TYPE_MASK BIT(2)
332 #define ATLAS7_GPIO_CTL_INTR_EN_MASK BIT(3)
333 #define ATLAS7_GPIO_CTL_INTR_STATUS_MASK BIT(4)
334 #define ATLAS7_GPIO_CTL_OUT_EN_MASK BIT(5)
335 #define ATLAS7_GPIO_CTL_DATAOUT_MASK BIT(6)
336 #define ATLAS7_GPIO_CTL_DATAIN_MASK BIT(7)
337
338 struct atlas7_gpio_bank {
339 int id;
340 int irq;
341 void __iomem *base;
342 unsigned int gpio_offset;
343 unsigned int ngpio;
344 const unsigned int *gpio_pins;
345 u32 sleep_data[NGPIO_OF_BANK];
346 };
347
348 struct atlas7_gpio_chip {
349 const char *name;
350 void __iomem *reg;
351 struct clk *clk;
352 int nbank;
353 raw_spinlock_t lock;
354 struct gpio_chip chip;
355 struct atlas7_gpio_bank banks[0];
356 };
357
358 /**
359 * @dev: a pointer back to containing device
360 * @virtbase: the offset to the controller in virtual memory
361 */
362 struct atlas7_pmx {
363 struct device *dev;
364 struct pinctrl_dev *pctl;
365 struct pinctrl_desc pctl_desc;
366 struct atlas7_pinctrl_data *pctl_data;
367 void __iomem *regs[ATLAS7_PINCTRL_REG_BANKS];
368 void __iomem *sys2pci_base;
369 u32 status_ds[NUM_OF_IN_DISABLE_REG];
370 u32 status_dsv[NUM_OF_IN_DISABLE_REG];
371 struct atlas7_pad_status sleep_data[ATLAS7_PINCTRL_TOTAL_PINS];
372 };
373
374 /*
375 * Pad list for the pinmux subsystem
376 * refer to A7DA IO Summary - CS-314158-DD-4E.xls
377 */
378
379 /*Pads in IOC RTC & TOP */
380 static const struct pinctrl_pin_desc atlas7_ioc_pads[] = {
381 /* RTC PADs */
382 PINCTRL_PIN(0, "rtc_gpio_0"),
383 PINCTRL_PIN(1, "rtc_gpio_1"),
384 PINCTRL_PIN(2, "rtc_gpio_2"),
385 PINCTRL_PIN(3, "rtc_gpio_3"),
386 PINCTRL_PIN(4, "low_bat_ind_b"),
387 PINCTRL_PIN(5, "on_key_b"),
388 PINCTRL_PIN(6, "ext_on"),
389 PINCTRL_PIN(7, "mem_on"),
390 PINCTRL_PIN(8, "core_on"),
391 PINCTRL_PIN(9, "io_on"),
392 PINCTRL_PIN(10, "can0_tx"),
393 PINCTRL_PIN(11, "can0_rx"),
394 PINCTRL_PIN(12, "spi0_clk"),
395 PINCTRL_PIN(13, "spi0_cs_b"),
396 PINCTRL_PIN(14, "spi0_io_0"),
397 PINCTRL_PIN(15, "spi0_io_1"),
398 PINCTRL_PIN(16, "spi0_io_2"),
399 PINCTRL_PIN(17, "spi0_io_3"),
400
401 /* TOP PADs */
402 PINCTRL_PIN(18, "spi1_en"),
403 PINCTRL_PIN(19, "spi1_clk"),
404 PINCTRL_PIN(20, "spi1_din"),
405 PINCTRL_PIN(21, "spi1_dout"),
406 PINCTRL_PIN(22, "trg_spi_clk"),
407 PINCTRL_PIN(23, "trg_spi_di"),
408 PINCTRL_PIN(24, "trg_spi_do"),
409 PINCTRL_PIN(25, "trg_spi_cs_b"),
410 PINCTRL_PIN(26, "trg_acq_d1"),
411 PINCTRL_PIN(27, "trg_irq_b"),
412 PINCTRL_PIN(28, "trg_acq_d0"),
413 PINCTRL_PIN(29, "trg_acq_clk"),
414 PINCTRL_PIN(30, "trg_shutdown_b_out"),
415 PINCTRL_PIN(31, "sdio2_clk"),
416 PINCTRL_PIN(32, "sdio2_cmd"),
417 PINCTRL_PIN(33, "sdio2_dat_0"),
418 PINCTRL_PIN(34, "sdio2_dat_1"),
419 PINCTRL_PIN(35, "sdio2_dat_2"),
420 PINCTRL_PIN(36, "sdio2_dat_3"),
421 PINCTRL_PIN(37, "df_ad_7"),
422 PINCTRL_PIN(38, "df_ad_6"),
423 PINCTRL_PIN(39, "df_ad_5"),
424 PINCTRL_PIN(40, "df_ad_4"),
425 PINCTRL_PIN(41, "df_ad_3"),
426 PINCTRL_PIN(42, "df_ad_2"),
427 PINCTRL_PIN(43, "df_ad_1"),
428 PINCTRL_PIN(44, "df_ad_0"),
429 PINCTRL_PIN(45, "df_dqs"),
430 PINCTRL_PIN(46, "df_cle"),
431 PINCTRL_PIN(47, "df_ale"),
432 PINCTRL_PIN(48, "df_we_b"),
433 PINCTRL_PIN(49, "df_re_b"),
434 PINCTRL_PIN(50, "df_ry_by"),
435 PINCTRL_PIN(51, "df_cs_b_1"),
436 PINCTRL_PIN(52, "df_cs_b_0"),
437 PINCTRL_PIN(53, "l_pclk"),
438 PINCTRL_PIN(54, "l_lck"),
439 PINCTRL_PIN(55, "l_fck"),
440 PINCTRL_PIN(56, "l_de"),
441 PINCTRL_PIN(57, "ldd_0"),
442 PINCTRL_PIN(58, "ldd_1"),
443 PINCTRL_PIN(59, "ldd_2"),
444 PINCTRL_PIN(60, "ldd_3"),
445 PINCTRL_PIN(61, "ldd_4"),
446 PINCTRL_PIN(62, "ldd_5"),
447 PINCTRL_PIN(63, "ldd_6"),
448 PINCTRL_PIN(64, "ldd_7"),
449 PINCTRL_PIN(65, "ldd_8"),
450 PINCTRL_PIN(66, "ldd_9"),
451 PINCTRL_PIN(67, "ldd_10"),
452 PINCTRL_PIN(68, "ldd_11"),
453 PINCTRL_PIN(69, "ldd_12"),
454 PINCTRL_PIN(70, "ldd_13"),
455 PINCTRL_PIN(71, "ldd_14"),
456 PINCTRL_PIN(72, "ldd_15"),
457 PINCTRL_PIN(73, "lcd_gpio_20"),
458 PINCTRL_PIN(74, "vip_0"),
459 PINCTRL_PIN(75, "vip_1"),
460 PINCTRL_PIN(76, "vip_2"),
461 PINCTRL_PIN(77, "vip_3"),
462 PINCTRL_PIN(78, "vip_4"),
463 PINCTRL_PIN(79, "vip_5"),
464 PINCTRL_PIN(80, "vip_6"),
465 PINCTRL_PIN(81, "vip_7"),
466 PINCTRL_PIN(82, "vip_pxclk"),
467 PINCTRL_PIN(83, "vip_hsync"),
468 PINCTRL_PIN(84, "vip_vsync"),
469 PINCTRL_PIN(85, "sdio3_clk"),
470 PINCTRL_PIN(86, "sdio3_cmd"),
471 PINCTRL_PIN(87, "sdio3_dat_0"),
472 PINCTRL_PIN(88, "sdio3_dat_1"),
473 PINCTRL_PIN(89, "sdio3_dat_2"),
474 PINCTRL_PIN(90, "sdio3_dat_3"),
475 PINCTRL_PIN(91, "sdio5_clk"),
476 PINCTRL_PIN(92, "sdio5_cmd"),
477 PINCTRL_PIN(93, "sdio5_dat_0"),
478 PINCTRL_PIN(94, "sdio5_dat_1"),
479 PINCTRL_PIN(95, "sdio5_dat_2"),
480 PINCTRL_PIN(96, "sdio5_dat_3"),
481 PINCTRL_PIN(97, "rgmii_txd_0"),
482 PINCTRL_PIN(98, "rgmii_txd_1"),
483 PINCTRL_PIN(99, "rgmii_txd_2"),
484 PINCTRL_PIN(100, "rgmii_txd_3"),
485 PINCTRL_PIN(101, "rgmii_txclk"),
486 PINCTRL_PIN(102, "rgmii_tx_ctl"),
487 PINCTRL_PIN(103, "rgmii_rxd_0"),
488 PINCTRL_PIN(104, "rgmii_rxd_1"),
489 PINCTRL_PIN(105, "rgmii_rxd_2"),
490 PINCTRL_PIN(106, "rgmii_rxd_3"),
491 PINCTRL_PIN(107, "rgmii_rx_clk"),
492 PINCTRL_PIN(108, "rgmii_rxc_ctl"),
493 PINCTRL_PIN(109, "rgmii_mdio"),
494 PINCTRL_PIN(110, "rgmii_mdc"),
495 PINCTRL_PIN(111, "rgmii_intr_n"),
496 PINCTRL_PIN(112, "i2s_mclk"),
497 PINCTRL_PIN(113, "i2s_bclk"),
498 PINCTRL_PIN(114, "i2s_ws"),
499 PINCTRL_PIN(115, "i2s_dout0"),
500 PINCTRL_PIN(116, "i2s_dout1"),
501 PINCTRL_PIN(117, "i2s_dout2"),
502 PINCTRL_PIN(118, "i2s_din"),
503 PINCTRL_PIN(119, "gpio_0"),
504 PINCTRL_PIN(120, "gpio_1"),
505 PINCTRL_PIN(121, "gpio_2"),
506 PINCTRL_PIN(122, "gpio_3"),
507 PINCTRL_PIN(123, "gpio_4"),
508 PINCTRL_PIN(124, "gpio_5"),
509 PINCTRL_PIN(125, "gpio_6"),
510 PINCTRL_PIN(126, "gpio_7"),
511 PINCTRL_PIN(127, "sda_0"),
512 PINCTRL_PIN(128, "scl_0"),
513 PINCTRL_PIN(129, "coex_pio_0"),
514 PINCTRL_PIN(130, "coex_pio_1"),
515 PINCTRL_PIN(131, "coex_pio_2"),
516 PINCTRL_PIN(132, "coex_pio_3"),
517 PINCTRL_PIN(133, "uart0_tx"),
518 PINCTRL_PIN(134, "uart0_rx"),
519 PINCTRL_PIN(135, "uart1_tx"),
520 PINCTRL_PIN(136, "uart1_rx"),
521 PINCTRL_PIN(137, "uart3_tx"),
522 PINCTRL_PIN(138, "uart3_rx"),
523 PINCTRL_PIN(139, "uart4_tx"),
524 PINCTRL_PIN(140, "uart4_rx"),
525 PINCTRL_PIN(141, "usp0_clk"),
526 PINCTRL_PIN(142, "usp0_tx"),
527 PINCTRL_PIN(143, "usp0_rx"),
528 PINCTRL_PIN(144, "usp0_fs"),
529 PINCTRL_PIN(145, "usp1_clk"),
530 PINCTRL_PIN(146, "usp1_tx"),
531 PINCTRL_PIN(147, "usp1_rx"),
532 PINCTRL_PIN(148, "usp1_fs"),
533 PINCTRL_PIN(149, "lvds_tx0d4p"),
534 PINCTRL_PIN(150, "lvds_tx0d4n"),
535 PINCTRL_PIN(151, "lvds_tx0d3p"),
536 PINCTRL_PIN(152, "lvds_tx0d3n"),
537 PINCTRL_PIN(153, "lvds_tx0d2p"),
538 PINCTRL_PIN(154, "lvds_tx0d2n"),
539 PINCTRL_PIN(155, "lvds_tx0d1p"),
540 PINCTRL_PIN(156, "lvds_tx0d1n"),
541 PINCTRL_PIN(157, "lvds_tx0d0p"),
542 PINCTRL_PIN(158, "lvds_tx0d0n"),
543 PINCTRL_PIN(159, "jtag_tdo"),
544 PINCTRL_PIN(160, "jtag_tms"),
545 PINCTRL_PIN(161, "jtag_tck"),
546 PINCTRL_PIN(162, "jtag_tdi"),
547 PINCTRL_PIN(163, "jtag_trstn"),
548 };
549
550 static struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
551 /* The Configuration of IOC_RTC Pads */
552 PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0),
553 PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0),
554 PADCONF(2, 3, 0x0, 0x100, 0x200, -1, 8, 4, 4, 0),
555 PADCONF(3, 5, 0x0, 0x100, 0x200, -1, 12, 6, 6, 0),
556 PADCONF(4, 4, 0x0, 0x100, 0x200, -1, 16, 8, 8, 0),
557 PADCONF(5, 4, 0x0, 0x100, 0x200, -1, 20, 10, 10, 0),
558 PADCONF(6, 3, 0x0, 0x100, 0x200, -1, 24, 12, 12, 0),
559 PADCONF(7, 3, 0x0, 0x100, 0x200, -1, 28, 14, 14, 0),
560 PADCONF(8, 3, 0x8, 0x100, 0x200, -1, 0, 16, 16, 0),
561 PADCONF(9, 3, 0x8, 0x100, 0x200, -1, 4, 18, 18, 0),
562 PADCONF(10, 4, 0x8, 0x100, 0x200, -1, 8, 20, 20, 0),
563 PADCONF(11, 4, 0x8, 0x100, 0x200, -1, 12, 22, 22, 0),
564 PADCONF(12, 5, 0x8, 0x100, 0x200, -1, 16, 24, 24, 0),
565 PADCONF(13, 6, 0x8, 0x100, 0x200, -1, 20, 26, 26, 0),
566 PADCONF(14, 5, 0x8, 0x100, 0x200, -1, 24, 28, 28, 0),
567 PADCONF(15, 5, 0x8, 0x100, 0x200, -1, 28, 30, 30, 0),
568 PADCONF(16, 5, 0x10, 0x108, 0x208, -1, 0, 0, 0, 0),
569 PADCONF(17, 5, 0x10, 0x108, 0x208, -1, 4, 2, 2, 0),
570 /* The Configuration of IOC_TOP Pads */
571 PADCONF(18, 5, 0x80, 0x180, 0x300, -1, 0, 0, 0, 0),
572 PADCONF(19, 5, 0x80, 0x180, 0x300, -1, 4, 2, 2, 0),
573 PADCONF(20, 5, 0x80, 0x180, 0x300, -1, 8, 4, 4, 0),
574 PADCONF(21, 5, 0x80, 0x180, 0x300, -1, 12, 6, 6, 0),
575 PADCONF(22, 5, 0x88, 0x188, 0x308, -1, 0, 0, 0, 0),
576 PADCONF(23, 5, 0x88, 0x188, 0x308, -1, 4, 2, 2, 0),
577 PADCONF(24, 5, 0x88, 0x188, 0x308, -1, 8, 4, 4, 0),
578 PADCONF(25, 6, 0x88, 0x188, 0x308, -1, 12, 6, 6, 0),
579 PADCONF(26, 5, 0x88, 0x188, 0x308, -1, 16, 8, 8, 0),
580 PADCONF(27, 6, 0x88, 0x188, 0x308, -1, 20, 10, 10, 0),
581 PADCONF(28, 5, 0x88, 0x188, 0x308, -1, 24, 12, 12, 0),
582 PADCONF(29, 5, 0x88, 0x188, 0x308, -1, 28, 14, 14, 0),
583 PADCONF(30, 5, 0x90, 0x188, 0x308, -1, 0, 16, 16, 0),
584 PADCONF(31, 2, 0x98, 0x190, 0x310, -1, 0, 0, 0, 0),
585 PADCONF(32, 1, 0x98, 0x190, 0x310, -1, 4, 2, 4, 0),
586 PADCONF(33, 1, 0x98, 0x190, 0x310, -1, 8, 4, 6, 0),
587 PADCONF(34, 1, 0x98, 0x190, 0x310, -1, 12, 6, 8, 0),
588 PADCONF(35, 1, 0x98, 0x190, 0x310, -1, 16, 8, 10, 0),
589 PADCONF(36, 1, 0x98, 0x190, 0x310, -1, 20, 10, 12, 0),
590 PADCONF(37, 1, 0xa0, 0x198, 0x318, -1, 0, 0, 0, 0),
591 PADCONF(38, 1, 0xa0, 0x198, 0x318, -1, 4, 2, 2, 0),
592 PADCONF(39, 1, 0xa0, 0x198, 0x318, -1, 8, 4, 4, 0),
593 PADCONF(40, 1, 0xa0, 0x198, 0x318, -1, 12, 6, 6, 0),
594 PADCONF(41, 1, 0xa0, 0x198, 0x318, -1, 16, 8, 8, 0),
595 PADCONF(42, 1, 0xa0, 0x198, 0x318, -1, 20, 10, 10, 0),
596 PADCONF(43, 1, 0xa0, 0x198, 0x318, -1, 24, 12, 12, 0),
597 PADCONF(44, 1, 0xa0, 0x198, 0x318, -1, 28, 14, 14, 0),
598 PADCONF(45, 0, 0xa8, 0x198, 0x318, -1, 0, 16, 16, 0),
599 PADCONF(46, 0, 0xa8, 0x198, 0x318, -1, 4, 18, 18, 0),
600 PADCONF(47, 1, 0xa8, 0x198, 0x318, -1, 8, 20, 20, 0),
601 PADCONF(48, 1, 0xa8, 0x198, 0x318, -1, 12, 22, 22, 0),
602 PADCONF(49, 1, 0xa8, 0x198, 0x318, -1, 16, 24, 24, 0),
603 PADCONF(50, 1, 0xa8, 0x198, 0x318, -1, 20, 26, 26, 0),
604 PADCONF(51, 1, 0xa8, 0x198, 0x318, -1, 24, 28, 28, 0),
605 PADCONF(52, 1, 0xa8, 0x198, 0x318, -1, 28, 30, 30, 0),
606 PADCONF(53, 0, 0xb0, 0x1a0, 0x320, -1, 0, 0, 0, 0),
607 PADCONF(54, 0, 0xb0, 0x1a0, 0x320, -1, 4, 2, 2, 0),
608 PADCONF(55, 0, 0xb0, 0x1a0, 0x320, -1, 8, 4, 4, 0),
609 PADCONF(56, 0, 0xb0, 0x1a0, 0x320, -1, 12, 6, 6, 0),
610 PADCONF(57, 0, 0xb0, 0x1a0, 0x320, -1, 16, 8, 8, 0),
611 PADCONF(58, 0, 0xb0, 0x1a0, 0x320, -1, 20, 10, 10, 0),
612 PADCONF(59, 0, 0xb0, 0x1a0, 0x320, -1, 24, 12, 12, 0),
613 PADCONF(60, 0, 0xb0, 0x1a0, 0x320, -1, 28, 14, 14, 0),
614 PADCONF(61, 0, 0xb8, 0x1a0, 0x320, -1, 0, 16, 16, 0),
615 PADCONF(62, 0, 0xb8, 0x1a0, 0x320, -1, 4, 18, 18, 0),
616 PADCONF(63, 0, 0xb8, 0x1a0, 0x320, -1, 8, 20, 20, 0),
617 PADCONF(64, 0, 0xb8, 0x1a0, 0x320, -1, 12, 22, 22, 0),
618 PADCONF(65, 0, 0xb8, 0x1a0, 0x320, -1, 16, 24, 24, 0),
619 PADCONF(66, 0, 0xb8, 0x1a0, 0x320, -1, 20, 26, 26, 0),
620 PADCONF(67, 0, 0xb8, 0x1a0, 0x320, -1, 24, 28, 28, 0),
621 PADCONF(68, 0, 0xb8, 0x1a0, 0x320, -1, 28, 30, 30, 0),
622 PADCONF(69, 0, 0xc0, 0x1a8, 0x328, -1, 0, 0, 0, 0),
623 PADCONF(70, 0, 0xc0, 0x1a8, 0x328, -1, 4, 2, 2, 0),
624 PADCONF(71, 0, 0xc0, 0x1a8, 0x328, -1, 8, 4, 4, 0),
625 PADCONF(72, 0, 0xc0, 0x1a8, 0x328, -1, 12, 6, 6, 0),
626 PADCONF(73, 0, 0xc0, 0x1a8, 0x328, -1, 16, 8, 8, 0),
627 PADCONF(74, 0, 0xc8, 0x1b0, 0x330, -1, 0, 0, 0, 0),
628 PADCONF(75, 0, 0xc8, 0x1b0, 0x330, -1, 4, 2, 2, 0),
629 PADCONF(76, 0, 0xc8, 0x1b0, 0x330, -1, 8, 4, 4, 0),
630 PADCONF(77, 0, 0xc8, 0x1b0, 0x330, -1, 12, 6, 6, 0),
631 PADCONF(78, 0, 0xc8, 0x1b0, 0x330, -1, 16, 8, 8, 0),
632 PADCONF(79, 0, 0xc8, 0x1b0, 0x330, -1, 20, 10, 10, 0),
633 PADCONF(80, 0, 0xc8, 0x1b0, 0x330, -1, 24, 12, 12, 0),
634 PADCONF(81, 0, 0xc8, 0x1b0, 0x330, -1, 28, 14, 14, 0),
635 PADCONF(82, 0, 0xd0, 0x1b0, 0x330, -1, 0, 16, 16, 0),
636 PADCONF(83, 0, 0xd0, 0x1b0, 0x330, -1, 4, 18, 18, 0),
637 PADCONF(84, 0, 0xd0, 0x1b0, 0x330, -1, 8, 20, 20, 0),
638 PADCONF(85, 2, 0xd8, 0x1b8, 0x338, -1, 0, 0, 0, 0),
639 PADCONF(86, 1, 0xd8, 0x1b8, 0x338, -1, 4, 4, 4, 0),
640 PADCONF(87, 1, 0xd8, 0x1b8, 0x338, -1, 8, 6, 6, 0),
641 PADCONF(88, 1, 0xd8, 0x1b8, 0x338, -1, 12, 8, 8, 0),
642 PADCONF(89, 1, 0xd8, 0x1b8, 0x338, -1, 16, 10, 10, 0),
643 PADCONF(90, 1, 0xd8, 0x1b8, 0x338, -1, 20, 12, 12, 0),
644 PADCONF(91, 2, 0xe0, 0x1c0, 0x340, -1, 0, 0, 0, 0),
645 PADCONF(92, 1, 0xe0, 0x1c0, 0x340, -1, 4, 4, 4, 0),
646 PADCONF(93, 1, 0xe0, 0x1c0, 0x340, -1, 8, 6, 6, 0),
647 PADCONF(94, 1, 0xe0, 0x1c0, 0x340, -1, 12, 8, 8, 0),
648 PADCONF(95, 1, 0xe0, 0x1c0, 0x340, -1, 16, 10, 10, 0),
649 PADCONF(96, 1, 0xe0, 0x1c0, 0x340, -1, 20, 12, 12, 0),
650 PADCONF(97, 0, 0xe8, 0x1c8, 0x348, -1, 0, 0, 0, 0),
651 PADCONF(98, 0, 0xe8, 0x1c8, 0x348, -1, 4, 2, 2, 0),
652 PADCONF(99, 0, 0xe8, 0x1c8, 0x348, -1, 8, 4, 4, 0),
653 PADCONF(100, 0, 0xe8, 0x1c8, 0x348, -1, 12, 6, 6, 0),
654 PADCONF(101, 2, 0xe8, 0x1c8, 0x348, -1, 16, 8, 8, 0),
655 PADCONF(102, 0, 0xe8, 0x1c8, 0x348, -1, 20, 12, 12, 0),
656 PADCONF(103, 0, 0xe8, 0x1c8, 0x348, -1, 24, 14, 14, 0),
657 PADCONF(104, 0, 0xe8, 0x1c8, 0x348, -1, 28, 16, 16, 0),
658 PADCONF(105, 0, 0xf0, 0x1c8, 0x348, -1, 0, 18, 18, 0),
659 PADCONF(106, 0, 0xf0, 0x1c8, 0x348, -1, 4, 20, 20, 0),
660 PADCONF(107, 0, 0xf0, 0x1c8, 0x348, -1, 8, 22, 22, 0),
661 PADCONF(108, 0, 0xf0, 0x1c8, 0x348, -1, 12, 24, 24, 0),
662 PADCONF(109, 1, 0xf0, 0x1c8, 0x348, -1, 16, 26, 26, 0),
663 PADCONF(110, 0, 0xf0, 0x1c8, 0x348, -1, 20, 28, 28, 0),
664 PADCONF(111, 1, 0xf0, 0x1c8, 0x348, -1, 24, 30, 30, 0),
665 PADCONF(112, 5, 0xf8, 0x200, 0x350, -1, 0, 0, 0, 0),
666 PADCONF(113, 5, 0xf8, 0x200, 0x350, -1, 4, 2, 2, 0),
667 PADCONF(114, 5, 0xf8, 0x200, 0x350, -1, 8, 4, 4, 0),
668 PADCONF(115, 5, 0xf8, 0x200, 0x350, -1, 12, 6, 6, 0),
669 PADCONF(116, 5, 0xf8, 0x200, 0x350, -1, 16, 8, 8, 0),
670 PADCONF(117, 5, 0xf8, 0x200, 0x350, -1, 20, 10, 10, 0),
671 PADCONF(118, 5, 0xf8, 0x200, 0x350, -1, 24, 12, 12, 0),
672 PADCONF(119, 5, 0x100, 0x250, 0x358, -1, 0, 0, 0, 0),
673 PADCONF(120, 5, 0x100, 0x250, 0x358, -1, 4, 2, 2, 0),
674 PADCONF(121, 5, 0x100, 0x250, 0x358, -1, 8, 4, 4, 0),
675 PADCONF(122, 5, 0x100, 0x250, 0x358, -1, 12, 6, 6, 0),
676 PADCONF(123, 6, 0x100, 0x250, 0x358, -1, 16, 8, 8, 0),
677 PADCONF(124, 6, 0x100, 0x250, 0x358, -1, 20, 10, 10, 0),
678 PADCONF(125, 6, 0x100, 0x250, 0x358, -1, 24, 12, 12, 0),
679 PADCONF(126, 6, 0x100, 0x250, 0x358, -1, 28, 14, 14, 0),
680 PADCONF(127, 6, 0x108, 0x250, 0x358, -1, 16, 24, 24, 0),
681 PADCONF(128, 6, 0x108, 0x250, 0x358, -1, 20, 26, 26, 0),
682 PADCONF(129, 0, 0x110, 0x258, 0x360, -1, 0, 0, 0, 0),
683 PADCONF(130, 0, 0x110, 0x258, 0x360, -1, 4, 2, 2, 0),
684 PADCONF(131, 0, 0x110, 0x258, 0x360, -1, 8, 4, 4, 0),
685 PADCONF(132, 0, 0x110, 0x258, 0x360, -1, 12, 6, 6, 0),
686 PADCONF(133, 6, 0x118, 0x260, 0x368, -1, 0, 0, 0, 0),
687 PADCONF(134, 6, 0x118, 0x260, 0x368, -1, 4, 2, 2, 0),
688 PADCONF(135, 6, 0x118, 0x260, 0x368, -1, 16, 8, 8, 0),
689 PADCONF(136, 6, 0x118, 0x260, 0x368, -1, 20, 10, 10, 0),
690 PADCONF(137, 6, 0x118, 0x260, 0x368, -1, 24, 12, 12, 0),
691 PADCONF(138, 6, 0x118, 0x260, 0x368, -1, 28, 14, 14, 0),
692 PADCONF(139, 6, 0x120, 0x260, 0x368, -1, 0, 16, 16, 0),
693 PADCONF(140, 6, 0x120, 0x260, 0x368, -1, 4, 18, 18, 0),
694 PADCONF(141, 5, 0x128, 0x268, 0x378, -1, 0, 0, 0, 0),
695 PADCONF(142, 5, 0x128, 0x268, 0x378, -1, 4, 2, 2, 0),
696 PADCONF(143, 5, 0x128, 0x268, 0x378, -1, 8, 4, 4, 0),
697 PADCONF(144, 5, 0x128, 0x268, 0x378, -1, 12, 6, 6, 0),
698 PADCONF(145, 5, 0x128, 0x268, 0x378, -1, 16, 8, 8, 0),
699 PADCONF(146, 5, 0x128, 0x268, 0x378, -1, 20, 10, 10, 0),
700 PADCONF(147, 5, 0x128, 0x268, 0x378, -1, 24, 12, 12, 0),
701 PADCONF(148, 5, 0x128, 0x268, 0x378, -1, 28, 14, 14, 0),
702 PADCONF(149, 7, 0x130, 0x270, -1, 0x480, 0, 0, 0, 0),
703 PADCONF(150, 7, 0x130, 0x270, -1, 0x480, 4, 2, 0, 1),
704 PADCONF(151, 7, 0x130, 0x270, -1, 0x480, 8, 4, 0, 2),
705 PADCONF(152, 7, 0x130, 0x270, -1, 0x480, 12, 6, 0, 3),
706 PADCONF(153, 7, 0x130, 0x270, -1, 0x480, 16, 8, 0, 4),
707 PADCONF(154, 7, 0x130, 0x270, -1, 0x480, 20, 10, 0, 5),
708 PADCONF(155, 7, 0x130, 0x270, -1, 0x480, 24, 12, 0, 6),
709 PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7),
710 PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8),
711 PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9),
712 PADCONF(159, 5, 0x140, 0x280, 0x380, -1, 0, 0, 0, 0),
713 PADCONF(160, 6, 0x140, 0x280, 0x380, -1, 4, 2, 2, 0),
714 PADCONF(161, 5, 0x140, 0x280, 0x380, -1, 8, 4, 4, 0),
715 PADCONF(162, 6, 0x140, 0x280, 0x380, -1, 12, 6, 6, 0),
716 PADCONF(163, 6, 0x140, 0x280, 0x380, -1, 16, 8, 8, 0),
717 };
718
719 /* pin list of each pin group */
720 static const unsigned int gnss_gpio_pins[] = { 119, 120, 121, 122, 123, 124,
721 125, 126, 127, 128, 22, 23, 24, 25, 26, 27, 28, 29, 30, };
722 static const unsigned int lcd_vip_gpio_pins[] = { 74, 75, 76, 77, 78, 79, 80,
723 81, 82, 83, 84, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
724 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, };
725 static const unsigned int sdio_i2s_gpio_pins[] = { 31, 32, 33, 34, 35, 36,
726 85, 86, 87, 88, 89, 90, 129, 130, 131, 132, 91, 92, 93, 94,
727 95, 96, 112, 113, 114, 115, 116, 117, 118, };
728 static const unsigned int sp_rgmii_gpio_pins[] = { 97, 98, 99, 100, 101, 102,
729 103, 104, 105, 106, 107, 108, 109, 110, 111, 18, 19, 20, 21,
730 141, 142, 143, 144, 145, 146, 147, 148, };
731 static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154,
732 151, 152, 149, 150, };
733 static const unsigned int jtag_uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40,
734 39, 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135,
735 136, 137, 138, 139, 140, 159, 160, 161, 162, 163, };
736 static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13,
737 14, 15, 16, 17, 9, };
738 static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, };
739 static const unsigned int audio_digmic_pins0[] = { 51, };
740 static const unsigned int audio_digmic_pins1[] = { 122, };
741 static const unsigned int audio_digmic_pins2[] = { 161, };
742 static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41,
743 40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118,
744 115, 49, 50, 142, 143, 80, };
745 static const unsigned int audio_i2s_pins[] = { 118, 115, 116, 117, 112, 113,
746 114, };
747 static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, };
748 static const unsigned int audio_i2s_extclk_pins[] = { 112, };
749 static const unsigned int audio_spdif_out_pins0[] = { 112, };
750 static const unsigned int audio_spdif_out_pins1[] = { 116, };
751 static const unsigned int audio_spdif_out_pins2[] = { 142, };
752 static const unsigned int audio_uart0_basic_pins[] = { 143, 142, 141, 144, };
753 static const unsigned int audio_uart0_urfs_pins0[] = { 117, };
754 static const unsigned int audio_uart0_urfs_pins1[] = { 139, };
755 static const unsigned int audio_uart0_urfs_pins2[] = { 163, };
756 static const unsigned int audio_uart0_urfs_pins3[] = { 162, };
757 static const unsigned int audio_uart1_basic_pins[] = { 147, 146, 145, 148, };
758 static const unsigned int audio_uart1_urfs_pins0[] = { 117, };
759 static const unsigned int audio_uart1_urfs_pins1[] = { 140, };
760 static const unsigned int audio_uart1_urfs_pins2[] = { 163, };
761 static const unsigned int audio_uart2_urfs_pins0[] = { 139, };
762 static const unsigned int audio_uart2_urfs_pins1[] = { 163, };
763 static const unsigned int audio_uart2_urfs_pins2[] = { 96, };
764 static const unsigned int audio_uart2_urxd_pins0[] = { 20, };
765 static const unsigned int audio_uart2_urxd_pins1[] = { 109, };
766 static const unsigned int audio_uart2_urxd_pins2[] = { 93, };
767 static const unsigned int audio_uart2_usclk_pins0[] = { 19, };
768 static const unsigned int audio_uart2_usclk_pins1[] = { 101, };
769 static const unsigned int audio_uart2_usclk_pins2[] = { 91, };
770 static const unsigned int audio_uart2_utfs_pins0[] = { 18, };
771 static const unsigned int audio_uart2_utfs_pins1[] = { 111, };
772 static const unsigned int audio_uart2_utfs_pins2[] = { 94, };
773 static const unsigned int audio_uart2_utxd_pins0[] = { 21, };
774 static const unsigned int audio_uart2_utxd_pins1[] = { 110, };
775 static const unsigned int audio_uart2_utxd_pins2[] = { 92, };
776 static const unsigned int c_can_trnsvr_en_pins0[] = { 2, };
777 static const unsigned int c_can_trnsvr_en_pins1[] = { 0, };
778 static const unsigned int c_can_trnsvr_intr_pins[] = { 1, };
779 static const unsigned int c_can_trnsvr_stb_n_pins[] = { 3, };
780 static const unsigned int c0_can_rxd_trnsv0_pins[] = { 11, };
781 static const unsigned int c0_can_rxd_trnsv1_pins[] = { 2, };
782 static const unsigned int c0_can_txd_trnsv0_pins[] = { 10, };
783 static const unsigned int c0_can_txd_trnsv1_pins[] = { 3, };
784 static const unsigned int c1_can_rxd_pins0[] = { 138, };
785 static const unsigned int c1_can_rxd_pins1[] = { 147, };
786 static const unsigned int c1_can_rxd_pins2[] = { 2, };
787 static const unsigned int c1_can_rxd_pins3[] = { 162, };
788 static const unsigned int c1_can_txd_pins0[] = { 137, };
789 static const unsigned int c1_can_txd_pins1[] = { 146, };
790 static const unsigned int c1_can_txd_pins2[] = { 3, };
791 static const unsigned int c1_can_txd_pins3[] = { 161, };
792 static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68,
793 69, 70, 71, };
794 static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, };
795 static const unsigned int ca_coex_pins[] = { 129, 130, 131, 132, };
796 static const unsigned int ca_curator_lpc_pins[] = { 57, 58, 59, 60, };
797 static const unsigned int ca_pcm_debug_pins[] = { 91, 93, 94, 92, };
798 static const unsigned int ca_pio_pins[] = { 121, 122, 125, 126, 38, 37, 47,
799 49, 50, 54, 55, 56, };
800 static const unsigned int ca_sdio_debug_pins[] = { 40, 39, 44, 43, 42, 41, };
801 static const unsigned int ca_spi_pins[] = { 82, 79, 80, 81, };
802 static const unsigned int ca_trb_pins[] = { 91, 93, 94, 95, 96, 78, 74, 75,
803 76, 77, };
804 static const unsigned int ca_uart_debug_pins[] = { 136, 135, 134, 133, };
805 static const unsigned int clkc_pins0[] = { 30, 47, };
806 static const unsigned int clkc_pins1[] = { 78, 54, };
807 static const unsigned int gn_gnss_i2c_pins[] = { 128, 127, };
808 static const unsigned int gn_gnss_uart_nopause_pins[] = { 134, 133, };
809 static const unsigned int gn_gnss_uart_pins[] = { 134, 133, 136, 135, };
810 static const unsigned int gn_trg_spi_pins0[] = { 22, 25, 23, 24, };
811 static const unsigned int gn_trg_spi_pins1[] = { 82, 79, 80, 81, };
812 static const unsigned int cvbs_dbg_pins[] = { 54, 53, 82, 74, 75, 76, 77, 78,
813 79, 80, 81, 83, 84, 73, 55, 56, };
814 static const unsigned int cvbs_dbg_test_pins0[] = { 57, };
815 static const unsigned int cvbs_dbg_test_pins1[] = { 58, };
816 static const unsigned int cvbs_dbg_test_pins2[] = { 59, };
817 static const unsigned int cvbs_dbg_test_pins3[] = { 60, };
818 static const unsigned int cvbs_dbg_test_pins4[] = { 61, };
819 static const unsigned int cvbs_dbg_test_pins5[] = { 62, };
820 static const unsigned int cvbs_dbg_test_pins6[] = { 63, };
821 static const unsigned int cvbs_dbg_test_pins7[] = { 64, };
822 static const unsigned int cvbs_dbg_test_pins8[] = { 65, };
823 static const unsigned int cvbs_dbg_test_pins9[] = { 66, };
824 static const unsigned int cvbs_dbg_test_pins10[] = { 67, };
825 static const unsigned int cvbs_dbg_test_pins11[] = { 68, };
826 static const unsigned int cvbs_dbg_test_pins12[] = { 69, };
827 static const unsigned int cvbs_dbg_test_pins13[] = { 70, };
828 static const unsigned int cvbs_dbg_test_pins14[] = { 71, };
829 static const unsigned int cvbs_dbg_test_pins15[] = { 72, };
830 static const unsigned int gn_gnss_power_pins[] = { 123, 124, 121, 122, 125,
831 120, };
832 static const unsigned int gn_gnss_sw_status_pins[] = { 57, 58, 59, 60, 61,
833 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 55, 56, 54, };
834 static const unsigned int gn_gnss_eclk_pins[] = { 113, };
835 static const unsigned int gn_gnss_irq1_pins0[] = { 112, };
836 static const unsigned int gn_gnss_irq2_pins0[] = { 118, };
837 static const unsigned int gn_gnss_tm_pins[] = { 115, };
838 static const unsigned int gn_gnss_tsync_pins[] = { 114, };
839 static const unsigned int gn_io_gnsssys_sw_cfg_pins[] = { 44, 43, 42, 41, 40,
840 39, 38, 37, 49, 50, 91, 92, 93, 94, 95, 96, };
841 static const unsigned int gn_trg_pins0[] = { 29, 28, 26, 27, };
842 static const unsigned int gn_trg_pins1[] = { 77, 76, 74, 75, };
843 static const unsigned int gn_trg_shutdown_pins0[] = { 30, };
844 static const unsigned int gn_trg_shutdown_pins1[] = { 83, };
845 static const unsigned int gn_trg_shutdown_pins2[] = { 117, };
846 static const unsigned int gn_trg_shutdown_pins3[] = { 123, };
847 static const unsigned int i2c0_pins[] = { 128, 127, };
848 static const unsigned int i2c1_pins[] = { 126, 125, };
849 static const unsigned int i2s0_pins[] = { 91, 93, 94, 92, };
850 static const unsigned int i2s1_basic_pins[] = { 95, 96, };
851 static const unsigned int i2s1_rxd0_pins0[] = { 61, };
852 static const unsigned int i2s1_rxd0_pins1[] = { 131, };
853 static const unsigned int i2s1_rxd0_pins2[] = { 129, };
854 static const unsigned int i2s1_rxd0_pins3[] = { 117, };
855 static const unsigned int i2s1_rxd0_pins4[] = { 83, };
856 static const unsigned int i2s1_rxd1_pins0[] = { 72, };
857 static const unsigned int i2s1_rxd1_pins1[] = { 132, };
858 static const unsigned int i2s1_rxd1_pins2[] = { 130, };
859 static const unsigned int i2s1_rxd1_pins3[] = { 118, };
860 static const unsigned int i2s1_rxd1_pins4[] = { 84, };
861 static const unsigned int jtag_jt_dbg_nsrst_pins[] = { 125, };
862 static const unsigned int jtag_ntrst_pins0[] = { 4, };
863 static const unsigned int jtag_ntrst_pins1[] = { 163, };
864 static const unsigned int jtag_swdiotms_pins0[] = { 2, };
865 static const unsigned int jtag_swdiotms_pins1[] = { 160, };
866 static const unsigned int jtag_tck_pins0[] = { 0, };
867 static const unsigned int jtag_tck_pins1[] = { 161, };
868 static const unsigned int jtag_tdi_pins0[] = { 1, };
869 static const unsigned int jtag_tdi_pins1[] = { 162, };
870 static const unsigned int jtag_tdo_pins0[] = { 3, };
871 static const unsigned int jtag_tdo_pins1[] = { 159, };
872 static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, };
873 static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64,
874 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80,
875 81, 56, 53, };
876 static const unsigned int ld_ldd_16bit_pins[] = { 57, 58, 59, 60, 61, 62, 63,
877 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, };
878 static const unsigned int ld_ldd_fck_pins[] = { 55, };
879 static const unsigned int ld_ldd_lck_pins[] = { 54, };
880 static const unsigned int lr_lcdrom_pins[] = { 73, 54, 57, 58, 59, 60, 61,
881 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, 55, };
882 static const unsigned int lvds_analog_pins[] = { 149, 150, 151, 152, 153, 154,
883 155, 156, 157, 158, };
884 static const unsigned int nd_df_basic_pins[] = { 44, 43, 42, 41, 40, 39, 38,
885 37, 47, 46, 52, 45, 49, 50, 48, };
886 static const unsigned int nd_df_wp_pins[] = { 124, };
887 static const unsigned int nd_df_cs_pins[] = { 51, };
888 static const unsigned int ps_pins[] = { 120, 119, 121, };
889 static const unsigned int ps_no_dir_pins[] = { 119, };
890 static const unsigned int pwc_core_on_pins[] = { 8, };
891 static const unsigned int pwc_ext_on_pins[] = { 6, };
892 static const unsigned int pwc_gpio3_clk_pins[] = { 3, };
893 static const unsigned int pwc_io_on_pins[] = { 9, };
894 static const unsigned int pwc_lowbatt_b_pins0[] = { 4, };
895 static const unsigned int pwc_mem_on_pins[] = { 7, };
896 static const unsigned int pwc_on_key_b_pins0[] = { 5, };
897 static const unsigned int pwc_wakeup_src0_pins[] = { 0, };
898 static const unsigned int pwc_wakeup_src1_pins[] = { 1, };
899 static const unsigned int pwc_wakeup_src2_pins[] = { 2, };
900 static const unsigned int pwc_wakeup_src3_pins[] = { 3, };
901 static const unsigned int pw_cko0_pins0[] = { 123, };
902 static const unsigned int pw_cko0_pins1[] = { 101, };
903 static const unsigned int pw_cko0_pins2[] = { 82, };
904 static const unsigned int pw_cko0_pins3[] = { 162, };
905 static const unsigned int pw_cko1_pins0[] = { 124, };
906 static const unsigned int pw_cko1_pins1[] = { 110, };
907 static const unsigned int pw_cko1_pins2[] = { 163, };
908 static const unsigned int pw_i2s01_clk_pins0[] = { 125, };
909 static const unsigned int pw_i2s01_clk_pins1[] = { 117, };
910 static const unsigned int pw_i2s01_clk_pins2[] = { 132, };
911 static const unsigned int pw_pwm0_pins0[] = { 119, };
912 static const unsigned int pw_pwm0_pins1[] = { 159, };
913 static const unsigned int pw_pwm1_pins0[] = { 120, };
914 static const unsigned int pw_pwm1_pins1[] = { 160, };
915 static const unsigned int pw_pwm1_pins2[] = { 131, };
916 static const unsigned int pw_pwm2_pins0[] = { 121, };
917 static const unsigned int pw_pwm2_pins1[] = { 98, };
918 static const unsigned int pw_pwm2_pins2[] = { 161, };
919 static const unsigned int pw_pwm3_pins0[] = { 122, };
920 static const unsigned int pw_pwm3_pins1[] = { 73, };
921 static const unsigned int pw_pwm_cpu_vol_pins0[] = { 121, };
922 static const unsigned int pw_pwm_cpu_vol_pins1[] = { 98, };
923 static const unsigned int pw_pwm_cpu_vol_pins2[] = { 161, };
924 static const unsigned int pw_backlight_pins0[] = { 122, };
925 static const unsigned int pw_backlight_pins1[] = { 73, };
926 static const unsigned int rg_eth_mac_pins[] = { 108, 103, 104, 105, 106, 107,
927 102, 97, 98, 99, 100, 101, };
928 static const unsigned int rg_gmac_phy_intr_n_pins[] = { 111, };
929 static const unsigned int rg_rgmii_mac_pins[] = { 109, 110, };
930 static const unsigned int rg_rgmii_phy_ref_clk_pins0[] = { 111, };
931 static const unsigned int rg_rgmii_phy_ref_clk_pins1[] = { 53, };
932 static const unsigned int sd0_pins[] = { 46, 47, 44, 43, 42, 41, 40, 39, 38,
933 37, };
934 static const unsigned int sd0_4bit_pins[] = { 46, 47, 44, 43, 42, 41, };
935 static const unsigned int sd1_pins[] = { 48, 49, 44, 43, 42, 41, 40, 39, 38,
936 37, };
937 static const unsigned int sd1_4bit_pins0[] = { 48, 49, 44, 43, 42, 41, };
938 static const unsigned int sd1_4bit_pins1[] = { 48, 49, 40, 39, 38, 37, };
939 static const unsigned int sd2_basic_pins[] = { 31, 32, 33, 34, 35, 36, };
940 static const unsigned int sd2_cdb_pins0[] = { 124, };
941 static const unsigned int sd2_cdb_pins1[] = { 161, };
942 static const unsigned int sd2_wpb_pins0[] = { 123, };
943 static const unsigned int sd2_wpb_pins1[] = { 163, };
944 static const unsigned int sd3_9_pins[] = { 85, 86, 87, 88, 89, 90, };
945 static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, };
946 static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, };
947 static const unsigned int sd6_pins1[] = { 101, 99, 100, 110, 109, 111, };
948 static const unsigned int sp0_ext_ldo_on_pins[] = { 4, };
949 static const unsigned int sp0_qspi_pins[] = { 12, 13, 14, 15, 16, 17, };
950 static const unsigned int sp1_spi_pins[] = { 19, 20, 21, 18, };
951 static const unsigned int tpiu_trace_pins[] = { 53, 56, 57, 58, 59, 60, 61,
952 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, };
953 static const unsigned int uart0_pins[] = { 121, 120, 134, 133, };
954 static const unsigned int uart0_nopause_pins[] = { 134, 133, };
955 static const unsigned int uart1_pins[] = { 136, 135, };
956 static const unsigned int uart2_cts_pins0[] = { 132, };
957 static const unsigned int uart2_cts_pins1[] = { 162, };
958 static const unsigned int uart2_rts_pins0[] = { 131, };
959 static const unsigned int uart2_rts_pins1[] = { 161, };
960 static const unsigned int uart2_rxd_pins0[] = { 11, };
961 static const unsigned int uart2_rxd_pins1[] = { 160, };
962 static const unsigned int uart2_rxd_pins2[] = { 130, };
963 static const unsigned int uart2_txd_pins0[] = { 10, };
964 static const unsigned int uart2_txd_pins1[] = { 159, };
965 static const unsigned int uart2_txd_pins2[] = { 129, };
966 static const unsigned int uart3_cts_pins0[] = { 125, };
967 static const unsigned int uart3_cts_pins1[] = { 111, };
968 static const unsigned int uart3_cts_pins2[] = { 140, };
969 static const unsigned int uart3_rts_pins0[] = { 126, };
970 static const unsigned int uart3_rts_pins1[] = { 109, };
971 static const unsigned int uart3_rts_pins2[] = { 139, };
972 static const unsigned int uart3_rxd_pins0[] = { 138, };
973 static const unsigned int uart3_rxd_pins1[] = { 84, };
974 static const unsigned int uart3_rxd_pins2[] = { 162, };
975 static const unsigned int uart3_txd_pins0[] = { 137, };
976 static const unsigned int uart3_txd_pins1[] = { 83, };
977 static const unsigned int uart3_txd_pins2[] = { 161, };
978 static const unsigned int uart4_basic_pins[] = { 140, 139, };
979 static const unsigned int uart4_cts_pins0[] = { 122, };
980 static const unsigned int uart4_cts_pins1[] = { 100, };
981 static const unsigned int uart4_cts_pins2[] = { 117, };
982 static const unsigned int uart4_rts_pins0[] = { 123, };
983 static const unsigned int uart4_rts_pins1[] = { 99, };
984 static const unsigned int uart4_rts_pins2[] = { 116, };
985 static const unsigned int usb0_drvvbus_pins0[] = { 51, };
986 static const unsigned int usb0_drvvbus_pins1[] = { 162, };
987 static const unsigned int usb1_drvvbus_pins0[] = { 134, };
988 static const unsigned int usb1_drvvbus_pins1[] = { 163, };
989 static const unsigned int visbus_dout_pins[] = { 57, 58, 59, 60, 61, 62, 63,
990 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 54, 55, 56, 85, 86,
991 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, };
992 static const unsigned int vi_vip1_pins[] = { 74, 75, 76, 77, 78, 79, 80, 81,
993 82, 83, 84, 103, 104, 105, 106, 107, 102, 97, 98, };
994 static const unsigned int vi_vip1_ext_pins[] = { 74, 75, 76, 77, 78, 79, 80,
995 81, 82, 83, 84, 108, 103, 104, 105, 106, 107, 102, 97, 98,
996 99, 100, };
997 static const unsigned int vi_vip1_low8bit_pins[] = { 74, 75, 76, 77, 78, 79,
998 80, 81, 82, 83, 84, };
999 static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 103, 104,
1000 105, 106, 107, 102, 97, 98, };
1001
1002 /* definition of pin group table */
1003 static struct atlas7_pin_group altas7_pin_groups[] = {
1004 GROUP("gnss_gpio_grp", gnss_gpio_pins),
1005 GROUP("lcd_vip_gpio_grp", lcd_vip_gpio_pins),
1006 GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins),
1007 GROUP("sp_rgmii_gpio_grp", sp_rgmii_gpio_pins),
1008 GROUP("lvds_gpio_grp", lvds_gpio_pins),
1009 GROUP("jtag_uart_nand_gpio_grp", jtag_uart_nand_gpio_pins),
1010 GROUP("rtc_gpio_grp", rtc_gpio_pins),
1011 GROUP("audio_ac97_grp", audio_ac97_pins),
1012 GROUP("audio_digmic_grp0", audio_digmic_pins0),
1013 GROUP("audio_digmic_grp1", audio_digmic_pins1),
1014 GROUP("audio_digmic_grp2", audio_digmic_pins2),
1015 GROUP("audio_func_dbg_grp", audio_func_dbg_pins),
1016 GROUP("audio_i2s_grp", audio_i2s_pins),
1017 GROUP("audio_i2s_2ch_grp", audio_i2s_2ch_pins),
1018 GROUP("audio_i2s_extclk_grp", audio_i2s_extclk_pins),
1019 GROUP("audio_spdif_out_grp0", audio_spdif_out_pins0),
1020 GROUP("audio_spdif_out_grp1", audio_spdif_out_pins1),
1021 GROUP("audio_spdif_out_grp2", audio_spdif_out_pins2),
1022 GROUP("audio_uart0_basic_grp", audio_uart0_basic_pins),
1023 GROUP("audio_uart0_urfs_grp0", audio_uart0_urfs_pins0),
1024 GROUP("audio_uart0_urfs_grp1", audio_uart0_urfs_pins1),
1025 GROUP("audio_uart0_urfs_grp2", audio_uart0_urfs_pins2),
1026 GROUP("audio_uart0_urfs_grp3", audio_uart0_urfs_pins3),
1027 GROUP("audio_uart1_basic_grp", audio_uart1_basic_pins),
1028 GROUP("audio_uart1_urfs_grp0", audio_uart1_urfs_pins0),
1029 GROUP("audio_uart1_urfs_grp1", audio_uart1_urfs_pins1),
1030 GROUP("audio_uart1_urfs_grp2", audio_uart1_urfs_pins2),
1031 GROUP("audio_uart2_urfs_grp0", audio_uart2_urfs_pins0),
1032 GROUP("audio_uart2_urfs_grp1", audio_uart2_urfs_pins1),
1033 GROUP("audio_uart2_urfs_grp2", audio_uart2_urfs_pins2),
1034 GROUP("audio_uart2_urxd_grp0", audio_uart2_urxd_pins0),
1035 GROUP("audio_uart2_urxd_grp1", audio_uart2_urxd_pins1),
1036 GROUP("audio_uart2_urxd_grp2", audio_uart2_urxd_pins2),
1037 GROUP("audio_uart2_usclk_grp0", audio_uart2_usclk_pins0),
1038 GROUP("audio_uart2_usclk_grp1", audio_uart2_usclk_pins1),
1039 GROUP("audio_uart2_usclk_grp2", audio_uart2_usclk_pins2),
1040 GROUP("audio_uart2_utfs_grp0", audio_uart2_utfs_pins0),
1041 GROUP("audio_uart2_utfs_grp1", audio_uart2_utfs_pins1),
1042 GROUP("audio_uart2_utfs_grp2", audio_uart2_utfs_pins2),
1043 GROUP("audio_uart2_utxd_grp0", audio_uart2_utxd_pins0),
1044 GROUP("audio_uart2_utxd_grp1", audio_uart2_utxd_pins1),
1045 GROUP("audio_uart2_utxd_grp2", audio_uart2_utxd_pins2),
1046 GROUP("c_can_trnsvr_en_grp0", c_can_trnsvr_en_pins0),
1047 GROUP("c_can_trnsvr_en_grp1", c_can_trnsvr_en_pins1),
1048 GROUP("c_can_trnsvr_intr_grp", c_can_trnsvr_intr_pins),
1049 GROUP("c_can_trnsvr_stb_n_grp", c_can_trnsvr_stb_n_pins),
1050 GROUP("c0_can_rxd_trnsv0_grp", c0_can_rxd_trnsv0_pins),
1051 GROUP("c0_can_rxd_trnsv1_grp", c0_can_rxd_trnsv1_pins),
1052 GROUP("c0_can_txd_trnsv0_grp", c0_can_txd_trnsv0_pins),
1053 GROUP("c0_can_txd_trnsv1_grp", c0_can_txd_trnsv1_pins),
1054 GROUP("c1_can_rxd_grp0", c1_can_rxd_pins0),
1055 GROUP("c1_can_rxd_grp1", c1_can_rxd_pins1),
1056 GROUP("c1_can_rxd_grp2", c1_can_rxd_pins2),
1057 GROUP("c1_can_rxd_grp3", c1_can_rxd_pins3),
1058 GROUP("c1_can_txd_grp0", c1_can_txd_pins0),
1059 GROUP("c1_can_txd_grp1", c1_can_txd_pins1),
1060 GROUP("c1_can_txd_grp2", c1_can_txd_pins2),
1061 GROUP("c1_can_txd_grp3", c1_can_txd_pins3),
1062 GROUP("ca_audio_lpc_grp", ca_audio_lpc_pins),
1063 GROUP("ca_bt_lpc_grp", ca_bt_lpc_pins),
1064 GROUP("ca_coex_grp", ca_coex_pins),
1065 GROUP("ca_curator_lpc_grp", ca_curator_lpc_pins),
1066 GROUP("ca_pcm_debug_grp", ca_pcm_debug_pins),
1067 GROUP("ca_pio_grp", ca_pio_pins),
1068 GROUP("ca_sdio_debug_grp", ca_sdio_debug_pins),
1069 GROUP("ca_spi_grp", ca_spi_pins),
1070 GROUP("ca_trb_grp", ca_trb_pins),
1071 GROUP("ca_uart_debug_grp", ca_uart_debug_pins),
1072 GROUP("clkc_grp0", clkc_pins0),
1073 GROUP("clkc_grp1", clkc_pins1),
1074 GROUP("gn_gnss_i2c_grp", gn_gnss_i2c_pins),
1075 GROUP("gn_gnss_uart_nopause_grp", gn_gnss_uart_nopause_pins),
1076 GROUP("gn_gnss_uart_grp", gn_gnss_uart_pins),
1077 GROUP("gn_trg_spi_grp0", gn_trg_spi_pins0),
1078 GROUP("gn_trg_spi_grp1", gn_trg_spi_pins1),
1079 GROUP("cvbs_dbg_grp", cvbs_dbg_pins),
1080 GROUP("cvbs_dbg_test_grp0", cvbs_dbg_test_pins0),
1081 GROUP("cvbs_dbg_test_grp1", cvbs_dbg_test_pins1),
1082 GROUP("cvbs_dbg_test_grp2", cvbs_dbg_test_pins2),
1083 GROUP("cvbs_dbg_test_grp3", cvbs_dbg_test_pins3),
1084 GROUP("cvbs_dbg_test_grp4", cvbs_dbg_test_pins4),
1085 GROUP("cvbs_dbg_test_grp5", cvbs_dbg_test_pins5),
1086 GROUP("cvbs_dbg_test_grp6", cvbs_dbg_test_pins6),
1087 GROUP("cvbs_dbg_test_grp7", cvbs_dbg_test_pins7),
1088 GROUP("cvbs_dbg_test_grp8", cvbs_dbg_test_pins8),
1089 GROUP("cvbs_dbg_test_grp9", cvbs_dbg_test_pins9),
1090 GROUP("cvbs_dbg_test_grp10", cvbs_dbg_test_pins10),
1091 GROUP("cvbs_dbg_test_grp11", cvbs_dbg_test_pins11),
1092 GROUP("cvbs_dbg_test_grp12", cvbs_dbg_test_pins12),
1093 GROUP("cvbs_dbg_test_grp13", cvbs_dbg_test_pins13),
1094 GROUP("cvbs_dbg_test_grp14", cvbs_dbg_test_pins14),
1095 GROUP("cvbs_dbg_test_grp15", cvbs_dbg_test_pins15),
1096 GROUP("gn_gnss_power_grp", gn_gnss_power_pins),
1097 GROUP("gn_gnss_sw_status_grp", gn_gnss_sw_status_pins),
1098 GROUP("gn_gnss_eclk_grp", gn_gnss_eclk_pins),
1099 GROUP("gn_gnss_irq1_grp0", gn_gnss_irq1_pins0),
1100 GROUP("gn_gnss_irq2_grp0", gn_gnss_irq2_pins0),
1101 GROUP("gn_gnss_tm_grp", gn_gnss_tm_pins),
1102 GROUP("gn_gnss_tsync_grp", gn_gnss_tsync_pins),
1103 GROUP("gn_io_gnsssys_sw_cfg_grp", gn_io_gnsssys_sw_cfg_pins),
1104 GROUP("gn_trg_grp0", gn_trg_pins0),
1105 GROUP("gn_trg_grp1", gn_trg_pins1),
1106 GROUP("gn_trg_shutdown_grp0", gn_trg_shutdown_pins0),
1107 GROUP("gn_trg_shutdown_grp1", gn_trg_shutdown_pins1),
1108 GROUP("gn_trg_shutdown_grp2", gn_trg_shutdown_pins2),
1109 GROUP("gn_trg_shutdown_grp3", gn_trg_shutdown_pins3),
1110 GROUP("i2c0_grp", i2c0_pins),
1111 GROUP("i2c1_grp", i2c1_pins),
1112 GROUP("i2s0_grp", i2s0_pins),
1113 GROUP("i2s1_basic_grp", i2s1_basic_pins),
1114 GROUP("i2s1_rxd0_grp0", i2s1_rxd0_pins0),
1115 GROUP("i2s1_rxd0_grp1", i2s1_rxd0_pins1),
1116 GROUP("i2s1_rxd0_grp2", i2s1_rxd0_pins2),
1117 GROUP("i2s1_rxd0_grp3", i2s1_rxd0_pins3),
1118 GROUP("i2s1_rxd0_grp4", i2s1_rxd0_pins4),
1119 GROUP("i2s1_rxd1_grp0", i2s1_rxd1_pins0),
1120 GROUP("i2s1_rxd1_grp1", i2s1_rxd1_pins1),
1121 GROUP("i2s1_rxd1_grp2", i2s1_rxd1_pins2),
1122 GROUP("i2s1_rxd1_grp3", i2s1_rxd1_pins3),
1123 GROUP("i2s1_rxd1_grp4", i2s1_rxd1_pins4),
1124 GROUP("jtag_jt_dbg_nsrst_grp", jtag_jt_dbg_nsrst_pins),
1125 GROUP("jtag_ntrst_grp0", jtag_ntrst_pins0),
1126 GROUP("jtag_ntrst_grp1", jtag_ntrst_pins1),
1127 GROUP("jtag_swdiotms_grp0", jtag_swdiotms_pins0),
1128 GROUP("jtag_swdiotms_grp1", jtag_swdiotms_pins1),
1129 GROUP("jtag_tck_grp0", jtag_tck_pins0),
1130 GROUP("jtag_tck_grp1", jtag_tck_pins1),
1131 GROUP("jtag_tdi_grp0", jtag_tdi_pins0),
1132 GROUP("jtag_tdi_grp1", jtag_tdi_pins1),
1133 GROUP("jtag_tdo_grp0", jtag_tdo_pins0),
1134 GROUP("jtag_tdo_grp1", jtag_tdo_pins1),
1135 GROUP("ks_kas_spi_grp0", ks_kas_spi_pins0),
1136 GROUP("ld_ldd_grp", ld_ldd_pins),
1137 GROUP("ld_ldd_16bit_grp", ld_ldd_16bit_pins),
1138 GROUP("ld_ldd_fck_grp", ld_ldd_fck_pins),
1139 GROUP("ld_ldd_lck_grp", ld_ldd_lck_pins),
1140 GROUP("lr_lcdrom_grp", lr_lcdrom_pins),
1141 GROUP("lvds_analog_grp", lvds_analog_pins),
1142 GROUP("nd_df_basic_grp", nd_df_basic_pins),
1143 GROUP("nd_df_wp_grp", nd_df_wp_pins),
1144 GROUP("nd_df_cs_grp", nd_df_cs_pins),
1145 GROUP("ps_grp", ps_pins),
1146 GROUP("ps_no_dir_grp", ps_no_dir_pins),
1147 GROUP("pwc_core_on_grp", pwc_core_on_pins),
1148 GROUP("pwc_ext_on_grp", pwc_ext_on_pins),
1149 GROUP("pwc_gpio3_clk_grp", pwc_gpio3_clk_pins),
1150 GROUP("pwc_io_on_grp", pwc_io_on_pins),
1151 GROUP("pwc_lowbatt_b_grp0", pwc_lowbatt_b_pins0),
1152 GROUP("pwc_mem_on_grp", pwc_mem_on_pins),
1153 GROUP("pwc_on_key_b_grp0", pwc_on_key_b_pins0),
1154 GROUP("pwc_wakeup_src0_grp", pwc_wakeup_src0_pins),
1155 GROUP("pwc_wakeup_src1_grp", pwc_wakeup_src1_pins),
1156 GROUP("pwc_wakeup_src2_grp", pwc_wakeup_src2_pins),
1157 GROUP("pwc_wakeup_src3_grp", pwc_wakeup_src3_pins),
1158 GROUP("pw_cko0_grp0", pw_cko0_pins0),
1159 GROUP("pw_cko0_grp1", pw_cko0_pins1),
1160 GROUP("pw_cko0_grp2", pw_cko0_pins2),
1161 GROUP("pw_cko0_grp3", pw_cko0_pins3),
1162 GROUP("pw_cko1_grp0", pw_cko1_pins0),
1163 GROUP("pw_cko1_grp1", pw_cko1_pins1),
1164 GROUP("pw_cko1_grp2", pw_cko1_pins2),
1165 GROUP("pw_i2s01_clk_grp0", pw_i2s01_clk_pins0),
1166 GROUP("pw_i2s01_clk_grp1", pw_i2s01_clk_pins1),
1167 GROUP("pw_i2s01_clk_grp2", pw_i2s01_clk_pins2),
1168 GROUP("pw_pwm0_grp0", pw_pwm0_pins0),
1169 GROUP("pw_pwm0_grp1", pw_pwm0_pins1),
1170 GROUP("pw_pwm1_grp0", pw_pwm1_pins0),
1171 GROUP("pw_pwm1_grp1", pw_pwm1_pins1),
1172 GROUP("pw_pwm1_grp2", pw_pwm1_pins2),
1173 GROUP("pw_pwm2_grp0", pw_pwm2_pins0),
1174 GROUP("pw_pwm2_grp1", pw_pwm2_pins1),
1175 GROUP("pw_pwm2_grp2", pw_pwm2_pins2),
1176 GROUP("pw_pwm3_grp0", pw_pwm3_pins0),
1177 GROUP("pw_pwm3_grp1", pw_pwm3_pins1),
1178 GROUP("pw_pwm_cpu_vol_grp0", pw_pwm_cpu_vol_pins0),
1179 GROUP("pw_pwm_cpu_vol_grp1", pw_pwm_cpu_vol_pins1),
1180 GROUP("pw_pwm_cpu_vol_grp2", pw_pwm_cpu_vol_pins2),
1181 GROUP("pw_backlight_grp0", pw_backlight_pins0),
1182 GROUP("pw_backlight_grp1", pw_backlight_pins1),
1183 GROUP("rg_eth_mac_grp", rg_eth_mac_pins),
1184 GROUP("rg_gmac_phy_intr_n_grp", rg_gmac_phy_intr_n_pins),
1185 GROUP("rg_rgmii_mac_grp", rg_rgmii_mac_pins),
1186 GROUP("rg_rgmii_phy_ref_clk_grp0", rg_rgmii_phy_ref_clk_pins0),
1187 GROUP("rg_rgmii_phy_ref_clk_grp1", rg_rgmii_phy_ref_clk_pins1),
1188 GROUP("sd0_grp", sd0_pins),
1189 GROUP("sd0_4bit_grp", sd0_4bit_pins),
1190 GROUP("sd1_grp", sd1_pins),
1191 GROUP("sd1_4bit_grp0", sd1_4bit_pins0),
1192 GROUP("sd1_4bit_grp1", sd1_4bit_pins1),
1193 GROUP("sd2_basic_grp", sd2_basic_pins),
1194 GROUP("sd2_cdb_grp0", sd2_cdb_pins0),
1195 GROUP("sd2_cdb_grp1", sd2_cdb_pins1),
1196 GROUP("sd2_wpb_grp0", sd2_wpb_pins0),
1197 GROUP("sd2_wpb_grp1", sd2_wpb_pins1),
1198 GROUP("sd3_9_grp", sd3_9_pins),
1199 GROUP("sd5_grp", sd5_pins),
1200 GROUP("sd6_grp0", sd6_pins0),
1201 GROUP("sd6_grp1", sd6_pins1),
1202 GROUP("sp0_ext_ldo_on_grp", sp0_ext_ldo_on_pins),
1203 GROUP("sp0_qspi_grp", sp0_qspi_pins),
1204 GROUP("sp1_spi_grp", sp1_spi_pins),
1205 GROUP("tpiu_trace_grp", tpiu_trace_pins),
1206 GROUP("uart0_grp", uart0_pins),
1207 GROUP("uart0_nopause_grp", uart0_nopause_pins),
1208 GROUP("uart1_grp", uart1_pins),
1209 GROUP("uart2_cts_grp0", uart2_cts_pins0),
1210 GROUP("uart2_cts_grp1", uart2_cts_pins1),
1211 GROUP("uart2_rts_grp0", uart2_rts_pins0),
1212 GROUP("uart2_rts_grp1", uart2_rts_pins1),
1213 GROUP("uart2_rxd_grp0", uart2_rxd_pins0),
1214 GROUP("uart2_rxd_grp1", uart2_rxd_pins1),
1215 GROUP("uart2_rxd_grp2", uart2_rxd_pins2),
1216 GROUP("uart2_txd_grp0", uart2_txd_pins0),
1217 GROUP("uart2_txd_grp1", uart2_txd_pins1),
1218 GROUP("uart2_txd_grp2", uart2_txd_pins2),
1219 GROUP("uart3_cts_grp0", uart3_cts_pins0),
1220 GROUP("uart3_cts_grp1", uart3_cts_pins1),
1221 GROUP("uart3_cts_grp2", uart3_cts_pins2),
1222 GROUP("uart3_rts_grp0", uart3_rts_pins0),
1223 GROUP("uart3_rts_grp1", uart3_rts_pins1),
1224 GROUP("uart3_rts_grp2", uart3_rts_pins2),
1225 GROUP("uart3_rxd_grp0", uart3_rxd_pins0),
1226 GROUP("uart3_rxd_grp1", uart3_rxd_pins1),
1227 GROUP("uart3_rxd_grp2", uart3_rxd_pins2),
1228 GROUP("uart3_txd_grp0", uart3_txd_pins0),
1229 GROUP("uart3_txd_grp1", uart3_txd_pins1),
1230 GROUP("uart3_txd_grp2", uart3_txd_pins2),
1231 GROUP("uart4_basic_grp", uart4_basic_pins),
1232 GROUP("uart4_cts_grp0", uart4_cts_pins0),
1233 GROUP("uart4_cts_grp1", uart4_cts_pins1),
1234 GROUP("uart4_cts_grp2", uart4_cts_pins2),
1235 GROUP("uart4_rts_grp0", uart4_rts_pins0),
1236 GROUP("uart4_rts_grp1", uart4_rts_pins1),
1237 GROUP("uart4_rts_grp2", uart4_rts_pins2),
1238 GROUP("usb0_drvvbus_grp0", usb0_drvvbus_pins0),
1239 GROUP("usb0_drvvbus_grp1", usb0_drvvbus_pins1),
1240 GROUP("usb1_drvvbus_grp0", usb1_drvvbus_pins0),
1241 GROUP("usb1_drvvbus_grp1", usb1_drvvbus_pins1),
1242 GROUP("visbus_dout_grp", visbus_dout_pins),
1243 GROUP("vi_vip1_grp", vi_vip1_pins),
1244 GROUP("vi_vip1_ext_grp", vi_vip1_ext_pins),
1245 GROUP("vi_vip1_low8bit_grp", vi_vip1_low8bit_pins),
1246 GROUP("vi_vip1_high8bit_grp", vi_vip1_high8bit_pins),
1247 };
1248
1249 /* How many groups that a function can use */
1250 static const char * const gnss_gpio_grp[] = { "gnss_gpio_grp", };
1251 static const char * const lcd_vip_gpio_grp[] = { "lcd_vip_gpio_grp", };
1252 static const char * const sdio_i2s_gpio_grp[] = { "sdio_i2s_gpio_grp", };
1253 static const char * const sp_rgmii_gpio_grp[] = { "sp_rgmii_gpio_grp", };
1254 static const char * const lvds_gpio_grp[] = { "lvds_gpio_grp", };
1255 static const char * const jtag_uart_nand_gpio_grp[] = {
1256 "jtag_uart_nand_gpio_grp", };
1257 static const char * const rtc_gpio_grp[] = { "rtc_gpio_grp", };
1258 static const char * const audio_ac97_grp[] = { "audio_ac97_grp", };
1259 static const char * const audio_digmic_grp0[] = { "audio_digmic_grp0", };
1260 static const char * const audio_digmic_grp1[] = { "audio_digmic_grp1", };
1261 static const char * const audio_digmic_grp2[] = { "audio_digmic_grp2", };
1262 static const char * const audio_func_dbg_grp[] = { "audio_func_dbg_grp", };
1263 static const char * const audio_i2s_grp[] = { "audio_i2s_grp", };
1264 static const char * const audio_i2s_2ch_grp[] = { "audio_i2s_2ch_grp", };
1265 static const char * const audio_i2s_extclk_grp[] = { "audio_i2s_extclk_grp", };
1266 static const char * const audio_spdif_out_grp0[] = { "audio_spdif_out_grp0", };
1267 static const char * const audio_spdif_out_grp1[] = { "audio_spdif_out_grp1", };
1268 static const char * const audio_spdif_out_grp2[] = { "audio_spdif_out_grp2", };
1269 static const char * const audio_uart0_basic_grp[] = {
1270 "audio_uart0_basic_grp", };
1271 static const char * const audio_uart0_urfs_grp0[] = {
1272 "audio_uart0_urfs_grp0", };
1273 static const char * const audio_uart0_urfs_grp1[] = {
1274 "audio_uart0_urfs_grp1", };
1275 static const char * const audio_uart0_urfs_grp2[] = {
1276 "audio_uart0_urfs_grp2", };
1277 static const char * const audio_uart0_urfs_grp3[] = {
1278 "audio_uart0_urfs_grp3", };
1279 static const char * const audio_uart1_basic_grp[] = {
1280 "audio_uart1_basic_grp", };
1281 static const char * const audio_uart1_urfs_grp0[] = {
1282 "audio_uart1_urfs_grp0", };
1283 static const char * const audio_uart1_urfs_grp1[] = {
1284 "audio_uart1_urfs_grp1", };
1285 static const char * const audio_uart1_urfs_grp2[] = {
1286 "audio_uart1_urfs_grp2", };
1287 static const char * const audio_uart2_urfs_grp0[] = {
1288 "audio_uart2_urfs_grp0", };
1289 static const char * const audio_uart2_urfs_grp1[] = {
1290 "audio_uart2_urfs_grp1", };
1291 static const char * const audio_uart2_urfs_grp2[] = {
1292 "audio_uart2_urfs_grp2", };
1293 static const char * const audio_uart2_urxd_grp0[] = {
1294 "audio_uart2_urxd_grp0", };
1295 static const char * const audio_uart2_urxd_grp1[] = {
1296 "audio_uart2_urxd_grp1", };
1297 static const char * const audio_uart2_urxd_grp2[] = {
1298 "audio_uart2_urxd_grp2", };
1299 static const char * const audio_uart2_usclk_grp0[] = {
1300 "audio_uart2_usclk_grp0", };
1301 static const char * const audio_uart2_usclk_grp1[] = {
1302 "audio_uart2_usclk_grp1", };
1303 static const char * const audio_uart2_usclk_grp2[] = {
1304 "audio_uart2_usclk_grp2", };
1305 static const char * const audio_uart2_utfs_grp0[] = {
1306 "audio_uart2_utfs_grp0", };
1307 static const char * const audio_uart2_utfs_grp1[] = {
1308 "audio_uart2_utfs_grp1", };
1309 static const char * const audio_uart2_utfs_grp2[] = {
1310 "audio_uart2_utfs_grp2", };
1311 static const char * const audio_uart2_utxd_grp0[] = {
1312 "audio_uart2_utxd_grp0", };
1313 static const char * const audio_uart2_utxd_grp1[] = {
1314 "audio_uart2_utxd_grp1", };
1315 static const char * const audio_uart2_utxd_grp2[] = {
1316 "audio_uart2_utxd_grp2", };
1317 static const char * const c_can_trnsvr_en_grp0[] = { "c_can_trnsvr_en_grp0", };
1318 static const char * const c_can_trnsvr_en_grp1[] = { "c_can_trnsvr_en_grp1", };
1319 static const char * const c_can_trnsvr_intr_grp[] = {
1320 "c_can_trnsvr_intr_grp", };
1321 static const char * const c_can_trnsvr_stb_n_grp[] = {
1322 "c_can_trnsvr_stb_n_grp", };
1323 static const char * const c0_can_rxd_trnsv0_grp[] = {
1324 "c0_can_rxd_trnsv0_grp", };
1325 static const char * const c0_can_rxd_trnsv1_grp[] = {
1326 "c0_can_rxd_trnsv1_grp", };
1327 static const char * const c0_can_txd_trnsv0_grp[] = {
1328 "c0_can_txd_trnsv0_grp", };
1329 static const char * const c0_can_txd_trnsv1_grp[] = {
1330 "c0_can_txd_trnsv1_grp", };
1331 static const char * const c1_can_rxd_grp0[] = { "c1_can_rxd_grp0", };
1332 static const char * const c1_can_rxd_grp1[] = { "c1_can_rxd_grp1", };
1333 static const char * const c1_can_rxd_grp2[] = { "c1_can_rxd_grp2", };
1334 static const char * const c1_can_rxd_grp3[] = { "c1_can_rxd_grp3", };
1335 static const char * const c1_can_txd_grp0[] = { "c1_can_txd_grp0", };
1336 static const char * const c1_can_txd_grp1[] = { "c1_can_txd_grp1", };
1337 static const char * const c1_can_txd_grp2[] = { "c1_can_txd_grp2", };
1338 static const char * const c1_can_txd_grp3[] = { "c1_can_txd_grp3", };
1339 static const char * const ca_audio_lpc_grp[] = { "ca_audio_lpc_grp", };
1340 static const char * const ca_bt_lpc_grp[] = { "ca_bt_lpc_grp", };
1341 static const char * const ca_coex_grp[] = { "ca_coex_grp", };
1342 static const char * const ca_curator_lpc_grp[] = { "ca_curator_lpc_grp", };
1343 static const char * const ca_pcm_debug_grp[] = { "ca_pcm_debug_grp", };
1344 static const char * const ca_pio_grp[] = { "ca_pio_grp", };
1345 static const char * const ca_sdio_debug_grp[] = { "ca_sdio_debug_grp", };
1346 static const char * const ca_spi_grp[] = { "ca_spi_grp", };
1347 static const char * const ca_trb_grp[] = { "ca_trb_grp", };
1348 static const char * const ca_uart_debug_grp[] = { "ca_uart_debug_grp", };
1349 static const char * const clkc_grp0[] = { "clkc_grp0", };
1350 static const char * const clkc_grp1[] = { "clkc_grp1", };
1351 static const char * const gn_gnss_i2c_grp[] = { "gn_gnss_i2c_grp", };
1352 static const char * const gn_gnss_uart_nopause_grp[] = {
1353 "gn_gnss_uart_nopause_grp", };
1354 static const char * const gn_gnss_uart_grp[] = { "gn_gnss_uart_grp", };
1355 static const char * const gn_trg_spi_grp0[] = { "gn_trg_spi_grp0", };
1356 static const char * const gn_trg_spi_grp1[] = { "gn_trg_spi_grp1", };
1357 static const char * const cvbs_dbg_grp[] = { "cvbs_dbg_grp", };
1358 static const char * const cvbs_dbg_test_grp0[] = { "cvbs_dbg_test_grp0", };
1359 static const char * const cvbs_dbg_test_grp1[] = { "cvbs_dbg_test_grp1", };
1360 static const char * const cvbs_dbg_test_grp2[] = { "cvbs_dbg_test_grp2", };
1361 static const char * const cvbs_dbg_test_grp3[] = { "cvbs_dbg_test_grp3", };
1362 static const char * const cvbs_dbg_test_grp4[] = { "cvbs_dbg_test_grp4", };
1363 static const char * const cvbs_dbg_test_grp5[] = { "cvbs_dbg_test_grp5", };
1364 static const char * const cvbs_dbg_test_grp6[] = { "cvbs_dbg_test_grp6", };
1365 static const char * const cvbs_dbg_test_grp7[] = { "cvbs_dbg_test_grp7", };
1366 static const char * const cvbs_dbg_test_grp8[] = { "cvbs_dbg_test_grp8", };
1367 static const char * const cvbs_dbg_test_grp9[] = { "cvbs_dbg_test_grp9", };
1368 static const char * const cvbs_dbg_test_grp10[] = { "cvbs_dbg_test_grp10", };
1369 static const char * const cvbs_dbg_test_grp11[] = { "cvbs_dbg_test_grp11", };
1370 static const char * const cvbs_dbg_test_grp12[] = { "cvbs_dbg_test_grp12", };
1371 static const char * const cvbs_dbg_test_grp13[] = { "cvbs_dbg_test_grp13", };
1372 static const char * const cvbs_dbg_test_grp14[] = { "cvbs_dbg_test_grp14", };
1373 static const char * const cvbs_dbg_test_grp15[] = { "cvbs_dbg_test_grp15", };
1374 static const char * const gn_gnss_power_grp[] = { "gn_gnss_power_grp", };
1375 static const char * const gn_gnss_sw_status_grp[] = {
1376 "gn_gnss_sw_status_grp", };
1377 static const char * const gn_gnss_eclk_grp[] = { "gn_gnss_eclk_grp", };
1378 static const char * const gn_gnss_irq1_grp0[] = { "gn_gnss_irq1_grp0", };
1379 static const char * const gn_gnss_irq2_grp0[] = { "gn_gnss_irq2_grp0", };
1380 static const char * const gn_gnss_tm_grp[] = { "gn_gnss_tm_grp", };
1381 static const char * const gn_gnss_tsync_grp[] = { "gn_gnss_tsync_grp", };
1382 static const char * const gn_io_gnsssys_sw_cfg_grp[] = {
1383 "gn_io_gnsssys_sw_cfg_grp", };
1384 static const char * const gn_trg_grp0[] = { "gn_trg_grp0", };
1385 static const char * const gn_trg_grp1[] = { "gn_trg_grp1", };
1386 static const char * const gn_trg_shutdown_grp0[] = { "gn_trg_shutdown_grp0", };
1387 static const char * const gn_trg_shutdown_grp1[] = { "gn_trg_shutdown_grp1", };
1388 static const char * const gn_trg_shutdown_grp2[] = { "gn_trg_shutdown_grp2", };
1389 static const char * const gn_trg_shutdown_grp3[] = { "gn_trg_shutdown_grp3", };
1390 static const char * const i2c0_grp[] = { "i2c0_grp", };
1391 static const char * const i2c1_grp[] = { "i2c1_grp", };
1392 static const char * const i2s0_grp[] = { "i2s0_grp", };
1393 static const char * const i2s1_basic_grp[] = { "i2s1_basic_grp", };
1394 static const char * const i2s1_rxd0_grp0[] = { "i2s1_rxd0_grp0", };
1395 static const char * const i2s1_rxd0_grp1[] = { "i2s1_rxd0_grp1", };
1396 static const char * const i2s1_rxd0_grp2[] = { "i2s1_rxd0_grp2", };
1397 static const char * const i2s1_rxd0_grp3[] = { "i2s1_rxd0_grp3", };
1398 static const char * const i2s1_rxd0_grp4[] = { "i2s1_rxd0_grp4", };
1399 static const char * const i2s1_rxd1_grp0[] = { "i2s1_rxd1_grp0", };
1400 static const char * const i2s1_rxd1_grp1[] = { "i2s1_rxd1_grp1", };
1401 static const char * const i2s1_rxd1_grp2[] = { "i2s1_rxd1_grp2", };
1402 static const char * const i2s1_rxd1_grp3[] = { "i2s1_rxd1_grp3", };
1403 static const char * const i2s1_rxd1_grp4[] = { "i2s1_rxd1_grp4", };
1404 static const char * const jtag_jt_dbg_nsrst_grp[] = {
1405 "jtag_jt_dbg_nsrst_grp", };
1406 static const char * const jtag_ntrst_grp0[] = { "jtag_ntrst_grp0", };
1407 static const char * const jtag_ntrst_grp1[] = { "jtag_ntrst_grp1", };
1408 static const char * const jtag_swdiotms_grp0[] = { "jtag_swdiotms_grp0", };
1409 static const char * const jtag_swdiotms_grp1[] = { "jtag_swdiotms_grp1", };
1410 static const char * const jtag_tck_grp0[] = { "jtag_tck_grp0", };
1411 static const char * const jtag_tck_grp1[] = { "jtag_tck_grp1", };
1412 static const char * const jtag_tdi_grp0[] = { "jtag_tdi_grp0", };
1413 static const char * const jtag_tdi_grp1[] = { "jtag_tdi_grp1", };
1414 static const char * const jtag_tdo_grp0[] = { "jtag_tdo_grp0", };
1415 static const char * const jtag_tdo_grp1[] = { "jtag_tdo_grp1", };
1416 static const char * const ks_kas_spi_grp0[] = { "ks_kas_spi_grp0", };
1417 static const char * const ld_ldd_grp[] = { "ld_ldd_grp", };
1418 static const char * const ld_ldd_16bit_grp[] = { "ld_ldd_16bit_grp", };
1419 static const char * const ld_ldd_fck_grp[] = { "ld_ldd_fck_grp", };
1420 static const char * const ld_ldd_lck_grp[] = { "ld_ldd_lck_grp", };
1421 static const char * const lr_lcdrom_grp[] = { "lr_lcdrom_grp", };
1422 static const char * const lvds_analog_grp[] = { "lvds_analog_grp", };
1423 static const char * const nd_df_basic_grp[] = { "nd_df_basic_grp", };
1424 static const char * const nd_df_wp_grp[] = { "nd_df_wp_grp", };
1425 static const char * const nd_df_cs_grp[] = { "nd_df_cs_grp", };
1426 static const char * const ps_grp[] = { "ps_grp", };
1427 static const char * const ps_no_dir_grp[] = { "ps_no_dir_grp", };
1428 static const char * const pwc_core_on_grp[] = { "pwc_core_on_grp", };
1429 static const char * const pwc_ext_on_grp[] = { "pwc_ext_on_grp", };
1430 static const char * const pwc_gpio3_clk_grp[] = { "pwc_gpio3_clk_grp", };
1431 static const char * const pwc_io_on_grp[] = { "pwc_io_on_grp", };
1432 static const char * const pwc_lowbatt_b_grp0[] = { "pwc_lowbatt_b_grp0", };
1433 static const char * const pwc_mem_on_grp[] = { "pwc_mem_on_grp", };
1434 static const char * const pwc_on_key_b_grp0[] = { "pwc_on_key_b_grp0", };
1435 static const char * const pwc_wakeup_src0_grp[] = { "pwc_wakeup_src0_grp", };
1436 static const char * const pwc_wakeup_src1_grp[] = { "pwc_wakeup_src1_grp", };
1437 static const char * const pwc_wakeup_src2_grp[] = { "pwc_wakeup_src2_grp", };
1438 static const char * const pwc_wakeup_src3_grp[] = { "pwc_wakeup_src3_grp", };
1439 static const char * const pw_cko0_grp0[] = { "pw_cko0_grp0", };
1440 static const char * const pw_cko0_grp1[] = { "pw_cko0_grp1", };
1441 static const char * const pw_cko0_grp2[] = { "pw_cko0_grp2", };
1442 static const char * const pw_cko0_grp3[] = { "pw_cko0_grp3", };
1443 static const char * const pw_cko1_grp0[] = { "pw_cko1_grp0", };
1444 static const char * const pw_cko1_grp1[] = { "pw_cko1_grp1", };
1445 static const char * const pw_cko1_grp2[] = { "pw_cko1_grp2", };
1446 static const char * const pw_i2s01_clk_grp0[] = { "pw_i2s01_clk_grp0", };
1447 static const char * const pw_i2s01_clk_grp1[] = { "pw_i2s01_clk_grp1", };
1448 static const char * const pw_i2s01_clk_grp2[] = { "pw_i2s01_clk_grp2", };
1449 static const char * const pw_pwm0_grp0[] = { "pw_pwm0_grp0", };
1450 static const char * const pw_pwm0_grp1[] = { "pw_pwm0_grp1", };
1451 static const char * const pw_pwm1_grp0[] = { "pw_pwm1_grp0", };
1452 static const char * const pw_pwm1_grp1[] = { "pw_pwm1_grp1", };
1453 static const char * const pw_pwm1_grp2[] = { "pw_pwm1_grp2", };
1454 static const char * const pw_pwm2_grp0[] = { "pw_pwm2_grp0", };
1455 static const char * const pw_pwm2_grp1[] = { "pw_pwm2_grp1", };
1456 static const char * const pw_pwm2_grp2[] = { "pw_pwm2_grp2", };
1457 static const char * const pw_pwm3_grp0[] = { "pw_pwm3_grp0", };
1458 static const char * const pw_pwm3_grp1[] = { "pw_pwm3_grp1", };
1459 static const char * const pw_pwm_cpu_vol_grp0[] = { "pw_pwm_cpu_vol_grp0", };
1460 static const char * const pw_pwm_cpu_vol_grp1[] = { "pw_pwm_cpu_vol_grp1", };
1461 static const char * const pw_pwm_cpu_vol_grp2[] = { "pw_pwm_cpu_vol_grp2", };
1462 static const char * const pw_backlight_grp0[] = { "pw_backlight_grp0", };
1463 static const char * const pw_backlight_grp1[] = { "pw_backlight_grp1", };
1464 static const char * const rg_eth_mac_grp[] = { "rg_eth_mac_grp", };
1465 static const char * const rg_gmac_phy_intr_n_grp[] = {
1466 "rg_gmac_phy_intr_n_grp", };
1467 static const char * const rg_rgmii_mac_grp[] = { "rg_rgmii_mac_grp", };
1468 static const char * const rg_rgmii_phy_ref_clk_grp0[] = {
1469 "rg_rgmii_phy_ref_clk_grp0", };
1470 static const char * const rg_rgmii_phy_ref_clk_grp1[] = {
1471 "rg_rgmii_phy_ref_clk_grp1", };
1472 static const char * const sd0_grp[] = { "sd0_grp", };
1473 static const char * const sd0_4bit_grp[] = { "sd0_4bit_grp", };
1474 static const char * const sd1_grp[] = { "sd1_grp", };
1475 static const char * const sd1_4bit_grp0[] = { "sd1_4bit_grp0", };
1476 static const char * const sd1_4bit_grp1[] = { "sd1_4bit_grp1", };
1477 static const char * const sd2_basic_grp[] = { "sd2_basic_grp", };
1478 static const char * const sd2_cdb_grp0[] = { "sd2_cdb_grp0", };
1479 static const char * const sd2_cdb_grp1[] = { "sd2_cdb_grp1", };
1480 static const char * const sd2_wpb_grp0[] = { "sd2_wpb_grp0", };
1481 static const char * const sd2_wpb_grp1[] = { "sd2_wpb_grp1", };
1482 static const char * const sd3_9_grp[] = { "sd3_9_grp", };
1483 static const char * const sd5_grp[] = { "sd5_grp", };
1484 static const char * const sd6_grp0[] = { "sd6_grp0", };
1485 static const char * const sd6_grp1[] = { "sd6_grp1", };
1486 static const char * const sp0_ext_ldo_on_grp[] = { "sp0_ext_ldo_on_grp", };
1487 static const char * const sp0_qspi_grp[] = { "sp0_qspi_grp", };
1488 static const char * const sp1_spi_grp[] = { "sp1_spi_grp", };
1489 static const char * const tpiu_trace_grp[] = { "tpiu_trace_grp", };
1490 static const char * const uart0_grp[] = { "uart0_grp", };
1491 static const char * const uart0_nopause_grp[] = { "uart0_nopause_grp", };
1492 static const char * const uart1_grp[] = { "uart1_grp", };
1493 static const char * const uart2_cts_grp0[] = { "uart2_cts_grp0", };
1494 static const char * const uart2_cts_grp1[] = { "uart2_cts_grp1", };
1495 static const char * const uart2_rts_grp0[] = { "uart2_rts_grp0", };
1496 static const char * const uart2_rts_grp1[] = { "uart2_rts_grp1", };
1497 static const char * const uart2_rxd_grp0[] = { "uart2_rxd_grp0", };
1498 static const char * const uart2_rxd_grp1[] = { "uart2_rxd_grp1", };
1499 static const char * const uart2_rxd_grp2[] = { "uart2_rxd_grp2", };
1500 static const char * const uart2_txd_grp0[] = { "uart2_txd_grp0", };
1501 static const char * const uart2_txd_grp1[] = { "uart2_txd_grp1", };
1502 static const char * const uart2_txd_grp2[] = { "uart2_txd_grp2", };
1503 static const char * const uart3_cts_grp0[] = { "uart3_cts_grp0", };
1504 static const char * const uart3_cts_grp1[] = { "uart3_cts_grp1", };
1505 static const char * const uart3_cts_grp2[] = { "uart3_cts_grp2", };
1506 static const char * const uart3_rts_grp0[] = { "uart3_rts_grp0", };
1507 static const char * const uart3_rts_grp1[] = { "uart3_rts_grp1", };
1508 static const char * const uart3_rts_grp2[] = { "uart3_rts_grp2", };
1509 static const char * const uart3_rxd_grp0[] = { "uart3_rxd_grp0", };
1510 static const char * const uart3_rxd_grp1[] = { "uart3_rxd_grp1", };
1511 static const char * const uart3_rxd_grp2[] = { "uart3_rxd_grp2", };
1512 static const char * const uart3_txd_grp0[] = { "uart3_txd_grp0", };
1513 static const char * const uart3_txd_grp1[] = { "uart3_txd_grp1", };
1514 static const char * const uart3_txd_grp2[] = { "uart3_txd_grp2", };
1515 static const char * const uart4_basic_grp[] = { "uart4_basic_grp", };
1516 static const char * const uart4_cts_grp0[] = { "uart4_cts_grp0", };
1517 static const char * const uart4_cts_grp1[] = { "uart4_cts_grp1", };
1518 static const char * const uart4_cts_grp2[] = { "uart4_cts_grp2", };
1519 static const char * const uart4_rts_grp0[] = { "uart4_rts_grp0", };
1520 static const char * const uart4_rts_grp1[] = { "uart4_rts_grp1", };
1521 static const char * const uart4_rts_grp2[] = { "uart4_rts_grp2", };
1522 static const char * const usb0_drvvbus_grp0[] = { "usb0_drvvbus_grp0", };
1523 static const char * const usb0_drvvbus_grp1[] = { "usb0_drvvbus_grp1", };
1524 static const char * const usb1_drvvbus_grp0[] = { "usb1_drvvbus_grp0", };
1525 static const char * const usb1_drvvbus_grp1[] = { "usb1_drvvbus_grp1", };
1526 static const char * const visbus_dout_grp[] = { "visbus_dout_grp", };
1527 static const char * const vi_vip1_grp[] = { "vi_vip1_grp", };
1528 static const char * const vi_vip1_ext_grp[] = { "vi_vip1_ext_grp", };
1529 static const char * const vi_vip1_low8bit_grp[] = { "vi_vip1_low8bit_grp", };
1530 static const char * const vi_vip1_high8bit_grp[] = { "vi_vip1_high8bit_grp", };
1531
1532 static struct atlas7_pad_mux gnss_gpio_grp_pad_mux[] = {
1533 MUX(1, 119, 0, N, N, N, N),
1534 MUX(1, 120, 0, N, N, N, N),
1535 MUX(1, 121, 0, N, N, N, N),
1536 MUX(1, 122, 0, N, N, N, N),
1537 MUX(1, 123, 0, N, N, N, N),
1538 MUX(1, 124, 0, N, N, N, N),
1539 MUX(1, 125, 0, N, N, N, N),
1540 MUX(1, 126, 0, N, N, N, N),
1541 MUX(1, 127, 0, N, N, N, N),
1542 MUX(1, 128, 0, N, N, N, N),
1543 MUX(1, 22, 0, N, N, N, N),
1544 MUX(1, 23, 0, N, N, N, N),
1545 MUX(1, 24, 0, N, N, N, N),
1546 MUX(1, 25, 0, N, N, N, N),
1547 MUX(1, 26, 0, N, N, N, N),
1548 MUX(1, 27, 0, N, N, N, N),
1549 MUX(1, 28, 0, N, N, N, N),
1550 MUX(1, 29, 0, N, N, N, N),
1551 MUX(1, 30, 0, N, N, N, N),
1552 };
1553
1554 static struct atlas7_grp_mux gnss_gpio_grp_mux = {
1555 .pad_mux_count = ARRAY_SIZE(gnss_gpio_grp_pad_mux),
1556 .pad_mux_list = gnss_gpio_grp_pad_mux,
1557 };
1558
1559 static struct atlas7_pad_mux lcd_vip_gpio_grp_pad_mux[] = {
1560 MUX(1, 74, 0, N, N, N, N),
1561 MUX(1, 75, 0, N, N, N, N),
1562 MUX(1, 76, 0, N, N, N, N),
1563 MUX(1, 77, 0, N, N, N, N),
1564 MUX(1, 78, 0, N, N, N, N),
1565 MUX(1, 79, 0, N, N, N, N),
1566 MUX(1, 80, 0, N, N, N, N),
1567 MUX(1, 81, 0, N, N, N, N),
1568 MUX(1, 82, 0, N, N, N, N),
1569 MUX(1, 83, 0, N, N, N, N),
1570 MUX(1, 84, 0, N, N, N, N),
1571 MUX(1, 53, 0, N, N, N, N),
1572 MUX(1, 54, 0, N, N, N, N),
1573 MUX(1, 55, 0, N, N, N, N),
1574 MUX(1, 56, 0, N, N, N, N),
1575 MUX(1, 57, 0, N, N, N, N),
1576 MUX(1, 58, 0, N, N, N, N),
1577 MUX(1, 59, 0, N, N, N, N),
1578 MUX(1, 60, 0, N, N, N, N),
1579 MUX(1, 61, 0, N, N, N, N),
1580 MUX(1, 62, 0, N, N, N, N),
1581 MUX(1, 63, 0, N, N, N, N),
1582 MUX(1, 64, 0, N, N, N, N),
1583 MUX(1, 65, 0, N, N, N, N),
1584 MUX(1, 66, 0, N, N, N, N),
1585 MUX(1, 67, 0, N, N, N, N),
1586 MUX(1, 68, 0, N, N, N, N),
1587 MUX(1, 69, 0, N, N, N, N),
1588 MUX(1, 70, 0, N, N, N, N),
1589 MUX(1, 71, 0, N, N, N, N),
1590 MUX(1, 72, 0, N, N, N, N),
1591 MUX(1, 73, 0, N, N, N, N),
1592 };
1593
1594 static struct atlas7_grp_mux lcd_vip_gpio_grp_mux = {
1595 .pad_mux_count = ARRAY_SIZE(lcd_vip_gpio_grp_pad_mux),
1596 .pad_mux_list = lcd_vip_gpio_grp_pad_mux,
1597 };
1598
1599 static struct atlas7_pad_mux sdio_i2s_gpio_grp_pad_mux[] = {
1600 MUX(1, 31, 0, N, N, N, N),
1601 MUX(1, 32, 0, N, N, N, N),
1602 MUX(1, 33, 0, N, N, N, N),
1603 MUX(1, 34, 0, N, N, N, N),
1604 MUX(1, 35, 0, N, N, N, N),
1605 MUX(1, 36, 0, N, N, N, N),
1606 MUX(1, 85, 0, N, N, N, N),
1607 MUX(1, 86, 0, N, N, N, N),
1608 MUX(1, 87, 0, N, N, N, N),
1609 MUX(1, 88, 0, N, N, N, N),
1610 MUX(1, 89, 0, N, N, N, N),
1611 MUX(1, 90, 0, N, N, N, N),
1612 MUX(1, 129, 0, N, N, N, N),
1613 MUX(1, 130, 0, N, N, N, N),
1614 MUX(1, 131, 0, N, N, N, N),
1615 MUX(1, 132, 0, N, N, N, N),
1616 MUX(1, 91, 0, N, N, N, N),
1617 MUX(1, 92, 0, N, N, N, N),
1618 MUX(1, 93, 0, N, N, N, N),
1619 MUX(1, 94, 0, N, N, N, N),
1620 MUX(1, 95, 0, N, N, N, N),
1621 MUX(1, 96, 0, N, N, N, N),
1622 MUX(1, 112, 0, N, N, N, N),
1623 MUX(1, 113, 0, N, N, N, N),
1624 MUX(1, 114, 0, N, N, N, N),
1625 MUX(1, 115, 0, N, N, N, N),
1626 MUX(1, 116, 0, N, N, N, N),
1627 MUX(1, 117, 0, N, N, N, N),
1628 MUX(1, 118, 0, N, N, N, N),
1629 };
1630
1631 static struct atlas7_grp_mux sdio_i2s_gpio_grp_mux = {
1632 .pad_mux_count = ARRAY_SIZE(sdio_i2s_gpio_grp_pad_mux),
1633 .pad_mux_list = sdio_i2s_gpio_grp_pad_mux,
1634 };
1635
1636 static struct atlas7_pad_mux sp_rgmii_gpio_grp_pad_mux[] = {
1637 MUX(1, 97, 0, N, N, N, N),
1638 MUX(1, 98, 0, N, N, N, N),
1639 MUX(1, 99, 0, N, N, N, N),
1640 MUX(1, 100, 0, N, N, N, N),
1641 MUX(1, 101, 0, N, N, N, N),
1642 MUX(1, 102, 0, N, N, N, N),
1643 MUX(1, 103, 0, N, N, N, N),
1644 MUX(1, 104, 0, N, N, N, N),
1645 MUX(1, 105, 0, N, N, N, N),
1646 MUX(1, 106, 0, N, N, N, N),
1647 MUX(1, 107, 0, N, N, N, N),
1648 MUX(1, 108, 0, N, N, N, N),
1649 MUX(1, 109, 0, N, N, N, N),
1650 MUX(1, 110, 0, N, N, N, N),
1651 MUX(1, 111, 0, N, N, N, N),
1652 MUX(1, 18, 0, N, N, N, N),
1653 MUX(1, 19, 0, N, N, N, N),
1654 MUX(1, 20, 0, N, N, N, N),
1655 MUX(1, 21, 0, N, N, N, N),
1656 MUX(1, 141, 0, N, N, N, N),
1657 MUX(1, 142, 0, N, N, N, N),
1658 MUX(1, 143, 0, N, N, N, N),
1659 MUX(1, 144, 0, N, N, N, N),
1660 MUX(1, 145, 0, N, N, N, N),
1661 MUX(1, 146, 0, N, N, N, N),
1662 MUX(1, 147, 0, N, N, N, N),
1663 MUX(1, 148, 0, N, N, N, N),
1664 };
1665
1666 static struct atlas7_grp_mux sp_rgmii_gpio_grp_mux = {
1667 .pad_mux_count = ARRAY_SIZE(sp_rgmii_gpio_grp_pad_mux),
1668 .pad_mux_list = sp_rgmii_gpio_grp_pad_mux,
1669 };
1670
1671 static struct atlas7_pad_mux lvds_gpio_grp_pad_mux[] = {
1672 MUX(1, 157, 0, N, N, N, N),
1673 MUX(1, 158, 0, N, N, N, N),
1674 MUX(1, 155, 0, N, N, N, N),
1675 MUX(1, 156, 0, N, N, N, N),
1676 MUX(1, 153, 0, N, N, N, N),
1677 MUX(1, 154, 0, N, N, N, N),
1678 MUX(1, 151, 0, N, N, N, N),
1679 MUX(1, 152, 0, N, N, N, N),
1680 MUX(1, 149, 0, N, N, N, N),
1681 MUX(1, 150, 0, N, N, N, N),
1682 };
1683
1684 static struct atlas7_grp_mux lvds_gpio_grp_mux = {
1685 .pad_mux_count = ARRAY_SIZE(lvds_gpio_grp_pad_mux),
1686 .pad_mux_list = lvds_gpio_grp_pad_mux,
1687 };
1688
1689 static struct atlas7_pad_mux jtag_uart_nand_gpio_grp_pad_mux[] = {
1690 MUX(1, 44, 0, N, N, N, N),
1691 MUX(1, 43, 0, N, N, N, N),
1692 MUX(1, 42, 0, N, N, N, N),
1693 MUX(1, 41, 0, N, N, N, N),
1694 MUX(1, 40, 0, N, N, N, N),
1695 MUX(1, 39, 0, N, N, N, N),
1696 MUX(1, 38, 0, N, N, N, N),
1697 MUX(1, 37, 0, N, N, N, N),
1698 MUX(1, 46, 0, N, N, N, N),
1699 MUX(1, 47, 0, N, N, N, N),
1700 MUX(1, 48, 0, N, N, N, N),
1701 MUX(1, 49, 0, N, N, N, N),
1702 MUX(1, 50, 0, N, N, N, N),
1703 MUX(1, 52, 0, N, N, N, N),
1704 MUX(1, 51, 0, N, N, N, N),
1705 MUX(1, 45, 0, N, N, N, N),
1706 MUX(1, 133, 0, N, N, N, N),
1707 MUX(1, 134, 0, N, N, N, N),
1708 MUX(1, 135, 0, N, N, N, N),
1709 MUX(1, 136, 0, N, N, N, N),
1710 MUX(1, 137, 0, N, N, N, N),
1711 MUX(1, 138, 0, N, N, N, N),
1712 MUX(1, 139, 0, N, N, N, N),
1713 MUX(1, 140, 0, N, N, N, N),
1714 MUX(1, 159, 0, N, N, N, N),
1715 MUX(1, 160, 0, N, N, N, N),
1716 MUX(1, 161, 0, N, N, N, N),
1717 MUX(1, 162, 0, N, N, N, N),
1718 MUX(1, 163, 0, N, N, N, N),
1719 };
1720
1721 static struct atlas7_grp_mux jtag_uart_nand_gpio_grp_mux = {
1722 .pad_mux_count = ARRAY_SIZE(jtag_uart_nand_gpio_grp_pad_mux),
1723 .pad_mux_list = jtag_uart_nand_gpio_grp_pad_mux,
1724 };
1725
1726 static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = {
1727 MUX(0, 0, 0, N, N, N, N),
1728 MUX(0, 1, 0, N, N, N, N),
1729 MUX(0, 2, 0, N, N, N, N),
1730 MUX(0, 3, 0, N, N, N, N),
1731 MUX(0, 4, 0, N, N, N, N),
1732 MUX(0, 10, 0, N, N, N, N),
1733 MUX(0, 11, 0, N, N, N, N),
1734 MUX(0, 12, 0, N, N, N, N),
1735 MUX(0, 13, 0, N, N, N, N),
1736 MUX(0, 14, 0, N, N, N, N),
1737 MUX(0, 15, 0, N, N, N, N),
1738 MUX(0, 16, 0, N, N, N, N),
1739 MUX(0, 17, 0, N, N, N, N),
1740 MUX(0, 9, 0, N, N, N, N),
1741 };
1742
1743 static struct atlas7_grp_mux rtc_gpio_grp_mux = {
1744 .pad_mux_count = ARRAY_SIZE(rtc_gpio_grp_pad_mux),
1745 .pad_mux_list = rtc_gpio_grp_pad_mux,
1746 };
1747
1748 static struct atlas7_pad_mux audio_ac97_grp_pad_mux[] = {
1749 MUX(1, 113, 2, N, N, N, N),
1750 MUX(1, 118, 2, N, N, N, N),
1751 MUX(1, 115, 2, N, N, N, N),
1752 MUX(1, 114, 2, N, N, N, N),
1753 };
1754
1755 static struct atlas7_grp_mux audio_ac97_grp_mux = {
1756 .pad_mux_count = ARRAY_SIZE(audio_ac97_grp_pad_mux),
1757 .pad_mux_list = audio_ac97_grp_pad_mux,
1758 };
1759
1760 static struct atlas7_pad_mux audio_digmic_grp0_pad_mux[] = {
1761 MUX(1, 51, 3, 0xa10, 20, 0xa90, 20),
1762 };
1763
1764 static struct atlas7_grp_mux audio_digmic_grp0_mux = {
1765 .pad_mux_count = ARRAY_SIZE(audio_digmic_grp0_pad_mux),
1766 .pad_mux_list = audio_digmic_grp0_pad_mux,
1767 };
1768
1769 static struct atlas7_pad_mux audio_digmic_grp1_pad_mux[] = {
1770 MUX(1, 122, 5, 0xa10, 20, 0xa90, 20),
1771 };
1772
1773 static struct atlas7_grp_mux audio_digmic_grp1_mux = {
1774 .pad_mux_count = ARRAY_SIZE(audio_digmic_grp1_pad_mux),
1775 .pad_mux_list = audio_digmic_grp1_pad_mux,
1776 };
1777
1778 static struct atlas7_pad_mux audio_digmic_grp2_pad_mux[] = {
1779 MUX(1, 161, 7, 0xa10, 20, 0xa90, 20),
1780 };
1781
1782 static struct atlas7_grp_mux audio_digmic_grp2_mux = {
1783 .pad_mux_count = ARRAY_SIZE(audio_digmic_grp2_pad_mux),
1784 .pad_mux_list = audio_digmic_grp2_pad_mux,
1785 };
1786
1787 static struct atlas7_pad_mux audio_func_dbg_grp_pad_mux[] = {
1788 MUX(1, 141, 4, N, N, N, N),
1789 MUX(1, 144, 4, N, N, N, N),
1790 MUX(1, 44, 6, N, N, N, N),
1791 MUX(1, 43, 6, N, N, N, N),
1792 MUX(1, 42, 6, N, N, N, N),
1793 MUX(1, 41, 6, N, N, N, N),
1794 MUX(1, 40, 6, N, N, N, N),
1795 MUX(1, 39, 6, N, N, N, N),
1796 MUX(1, 38, 6, N, N, N, N),
1797 MUX(1, 37, 6, N, N, N, N),
1798 MUX(1, 74, 6, N, N, N, N),
1799 MUX(1, 75, 6, N, N, N, N),
1800 MUX(1, 76, 6, N, N, N, N),
1801 MUX(1, 77, 6, N, N, N, N),
1802 MUX(1, 78, 6, N, N, N, N),
1803 MUX(1, 79, 6, N, N, N, N),
1804 MUX(1, 81, 6, N, N, N, N),
1805 MUX(1, 113, 6, N, N, N, N),
1806 MUX(1, 114, 6, N, N, N, N),
1807 MUX(1, 118, 6, N, N, N, N),
1808 MUX(1, 115, 6, N, N, N, N),
1809 MUX(1, 49, 6, N, N, N, N),
1810 MUX(1, 50, 6, N, N, N, N),
1811 MUX(1, 142, 4, N, N, N, N),
1812 MUX(1, 143, 4, N, N, N, N),
1813 MUX(1, 80, 6, N, N, N, N),
1814 };
1815
1816 static struct atlas7_grp_mux audio_func_dbg_grp_mux = {
1817 .pad_mux_count = ARRAY_SIZE(audio_func_dbg_grp_pad_mux),
1818 .pad_mux_list = audio_func_dbg_grp_pad_mux,
1819 };
1820
1821 static struct atlas7_pad_mux audio_i2s_grp_pad_mux[] = {
1822 MUX(1, 118, 1, N, N, N, N),
1823 MUX(1, 115, 1, N, N, N, N),
1824 MUX(1, 116, 1, N, N, N, N),
1825 MUX(1, 117, 1, N, N, N, N),
1826 MUX(1, 112, 1, N, N, N, N),
1827 MUX(1, 113, 1, N, N, N, N),
1828 MUX(1, 114, 1, N, N, N, N),
1829 };
1830
1831 static struct atlas7_grp_mux audio_i2s_grp_mux = {
1832 .pad_mux_count = ARRAY_SIZE(audio_i2s_grp_pad_mux),
1833 .pad_mux_list = audio_i2s_grp_pad_mux,
1834 };
1835
1836 static struct atlas7_pad_mux audio_i2s_2ch_grp_pad_mux[] = {
1837 MUX(1, 118, 1, N, N, N, N),
1838 MUX(1, 115, 1, N, N, N, N),
1839 MUX(1, 112, 1, N, N, N, N),
1840 MUX(1, 113, 1, N, N, N, N),
1841 MUX(1, 114, 1, N, N, N, N),
1842 };
1843
1844 static struct atlas7_grp_mux audio_i2s_2ch_grp_mux = {
1845 .pad_mux_count = ARRAY_SIZE(audio_i2s_2ch_grp_pad_mux),
1846 .pad_mux_list = audio_i2s_2ch_grp_pad_mux,
1847 };
1848
1849 static struct atlas7_pad_mux audio_i2s_extclk_grp_pad_mux[] = {
1850 MUX(1, 112, 2, N, N, N, N),
1851 };
1852
1853 static struct atlas7_grp_mux audio_i2s_extclk_grp_mux = {
1854 .pad_mux_count = ARRAY_SIZE(audio_i2s_extclk_grp_pad_mux),
1855 .pad_mux_list = audio_i2s_extclk_grp_pad_mux,
1856 };
1857
1858 static struct atlas7_pad_mux audio_spdif_out_grp0_pad_mux[] = {
1859 MUX(1, 112, 3, N, N, N, N),
1860 };
1861
1862 static struct atlas7_grp_mux audio_spdif_out_grp0_mux = {
1863 .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp0_pad_mux),
1864 .pad_mux_list = audio_spdif_out_grp0_pad_mux,
1865 };
1866
1867 static struct atlas7_pad_mux audio_spdif_out_grp1_pad_mux[] = {
1868 MUX(1, 116, 3, N, N, N, N),
1869 };
1870
1871 static struct atlas7_grp_mux audio_spdif_out_grp1_mux = {
1872 .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp1_pad_mux),
1873 .pad_mux_list = audio_spdif_out_grp1_pad_mux,
1874 };
1875
1876 static struct atlas7_pad_mux audio_spdif_out_grp2_pad_mux[] = {
1877 MUX(1, 142, 3, N, N, N, N),
1878 };
1879
1880 static struct atlas7_grp_mux audio_spdif_out_grp2_mux = {
1881 .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp2_pad_mux),
1882 .pad_mux_list = audio_spdif_out_grp2_pad_mux,
1883 };
1884
1885 static struct atlas7_pad_mux audio_uart0_basic_grp_pad_mux[] = {
1886 MUX(1, 143, 1, N, N, N, N),
1887 MUX(1, 142, 1, N, N, N, N),
1888 MUX(1, 141, 1, N, N, N, N),
1889 MUX(1, 144, 1, N, N, N, N),
1890 };
1891
1892 static struct atlas7_grp_mux audio_uart0_basic_grp_mux = {
1893 .pad_mux_count = ARRAY_SIZE(audio_uart0_basic_grp_pad_mux),
1894 .pad_mux_list = audio_uart0_basic_grp_pad_mux,
1895 };
1896
1897 static struct atlas7_pad_mux audio_uart0_urfs_grp0_pad_mux[] = {
1898 MUX(1, 117, 5, 0xa10, 28, 0xa90, 28),
1899 };
1900
1901 static struct atlas7_grp_mux audio_uart0_urfs_grp0_mux = {
1902 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp0_pad_mux),
1903 .pad_mux_list = audio_uart0_urfs_grp0_pad_mux,
1904 };
1905
1906 static struct atlas7_pad_mux audio_uart0_urfs_grp1_pad_mux[] = {
1907 MUX(1, 139, 3, 0xa10, 28, 0xa90, 28),
1908 };
1909
1910 static struct atlas7_grp_mux audio_uart0_urfs_grp1_mux = {
1911 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp1_pad_mux),
1912 .pad_mux_list = audio_uart0_urfs_grp1_pad_mux,
1913 };
1914
1915 static struct atlas7_pad_mux audio_uart0_urfs_grp2_pad_mux[] = {
1916 MUX(1, 163, 3, 0xa10, 28, 0xa90, 28),
1917 };
1918
1919 static struct atlas7_grp_mux audio_uart0_urfs_grp2_mux = {
1920 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp2_pad_mux),
1921 .pad_mux_list = audio_uart0_urfs_grp2_pad_mux,
1922 };
1923
1924 static struct atlas7_pad_mux audio_uart0_urfs_grp3_pad_mux[] = {
1925 MUX(1, 162, 6, 0xa10, 28, 0xa90, 28),
1926 };
1927
1928 static struct atlas7_grp_mux audio_uart0_urfs_grp3_mux = {
1929 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp3_pad_mux),
1930 .pad_mux_list = audio_uart0_urfs_grp3_pad_mux,
1931 };
1932
1933 static struct atlas7_pad_mux audio_uart1_basic_grp_pad_mux[] = {
1934 MUX(1, 147, 1, 0xa10, 24, 0xa90, 24),
1935 MUX(1, 146, 1, 0xa10, 25, 0xa90, 25),
1936 MUX(1, 145, 1, 0xa10, 23, 0xa90, 23),
1937 MUX(1, 148, 1, 0xa10, 22, 0xa90, 22),
1938 };
1939
1940 static struct atlas7_grp_mux audio_uart1_basic_grp_mux = {
1941 .pad_mux_count = ARRAY_SIZE(audio_uart1_basic_grp_pad_mux),
1942 .pad_mux_list = audio_uart1_basic_grp_pad_mux,
1943 };
1944
1945 static struct atlas7_pad_mux audio_uart1_urfs_grp0_pad_mux[] = {
1946 MUX(1, 117, 6, 0xa10, 29, 0xa90, 29),
1947 };
1948
1949 static struct atlas7_grp_mux audio_uart1_urfs_grp0_mux = {
1950 .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp0_pad_mux),
1951 .pad_mux_list = audio_uart1_urfs_grp0_pad_mux,
1952 };
1953
1954 static struct atlas7_pad_mux audio_uart1_urfs_grp1_pad_mux[] = {
1955 MUX(1, 140, 3, 0xa10, 29, 0xa90, 29),
1956 };
1957
1958 static struct atlas7_grp_mux audio_uart1_urfs_grp1_mux = {
1959 .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp1_pad_mux),
1960 .pad_mux_list = audio_uart1_urfs_grp1_pad_mux,
1961 };
1962
1963 static struct atlas7_pad_mux audio_uart1_urfs_grp2_pad_mux[] = {
1964 MUX(1, 163, 4, 0xa10, 29, 0xa90, 29),
1965 };
1966
1967 static struct atlas7_grp_mux audio_uart1_urfs_grp2_mux = {
1968 .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp2_pad_mux),
1969 .pad_mux_list = audio_uart1_urfs_grp2_pad_mux,
1970 };
1971
1972 static struct atlas7_pad_mux audio_uart2_urfs_grp0_pad_mux[] = {
1973 MUX(1, 139, 4, 0xa10, 30, 0xa90, 30),
1974 };
1975
1976 static struct atlas7_grp_mux audio_uart2_urfs_grp0_mux = {
1977 .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp0_pad_mux),
1978 .pad_mux_list = audio_uart2_urfs_grp0_pad_mux,
1979 };
1980
1981 static struct atlas7_pad_mux audio_uart2_urfs_grp1_pad_mux[] = {
1982 MUX(1, 163, 6, 0xa10, 30, 0xa90, 30),
1983 };
1984
1985 static struct atlas7_grp_mux audio_uart2_urfs_grp1_mux = {
1986 .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp1_pad_mux),
1987 .pad_mux_list = audio_uart2_urfs_grp1_pad_mux,
1988 };
1989
1990 static struct atlas7_pad_mux audio_uart2_urfs_grp2_pad_mux[] = {
1991 MUX(1, 96, 3, 0xa10, 30, 0xa90, 30),
1992 };
1993
1994 static struct atlas7_grp_mux audio_uart2_urfs_grp2_mux = {
1995 .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp2_pad_mux),
1996 .pad_mux_list = audio_uart2_urfs_grp2_pad_mux,
1997 };
1998
1999 static struct atlas7_pad_mux audio_uart2_urxd_grp0_pad_mux[] = {
2000 MUX(1, 20, 2, 0xa00, 24, 0xa80, 24),
2001 };
2002
2003 static struct atlas7_grp_mux audio_uart2_urxd_grp0_mux = {
2004 .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp0_pad_mux),
2005 .pad_mux_list = audio_uart2_urxd_grp0_pad_mux,
2006 };
2007
2008 static struct atlas7_pad_mux audio_uart2_urxd_grp1_pad_mux[] = {
2009 MUX(1, 109, 2, 0xa00, 24, 0xa80, 24),
2010 };
2011
2012 static struct atlas7_grp_mux audio_uart2_urxd_grp1_mux = {
2013 .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp1_pad_mux),
2014 .pad_mux_list = audio_uart2_urxd_grp1_pad_mux,
2015 };
2016
2017 static struct atlas7_pad_mux audio_uart2_urxd_grp2_pad_mux[] = {
2018 MUX(1, 93, 3, 0xa00, 24, 0xa80, 24),
2019 };
2020
2021 static struct atlas7_grp_mux audio_uart2_urxd_grp2_mux = {
2022 .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp2_pad_mux),
2023 .pad_mux_list = audio_uart2_urxd_grp2_pad_mux,
2024 };
2025
2026 static struct atlas7_pad_mux audio_uart2_usclk_grp0_pad_mux[] = {
2027 MUX(1, 19, 2, 0xa00, 23, 0xa80, 23),
2028 };
2029
2030 static struct atlas7_grp_mux audio_uart2_usclk_grp0_mux = {
2031 .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp0_pad_mux),
2032 .pad_mux_list = audio_uart2_usclk_grp0_pad_mux,
2033 };
2034
2035 static struct atlas7_pad_mux audio_uart2_usclk_grp1_pad_mux[] = {
2036 MUX(1, 101, 2, 0xa00, 23, 0xa80, 23),
2037 };
2038
2039 static struct atlas7_grp_mux audio_uart2_usclk_grp1_mux = {
2040 .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp1_pad_mux),
2041 .pad_mux_list = audio_uart2_usclk_grp1_pad_mux,
2042 };
2043
2044 static struct atlas7_pad_mux audio_uart2_usclk_grp2_pad_mux[] = {
2045 MUX(1, 91, 3, 0xa00, 23, 0xa80, 23),
2046 };
2047
2048 static struct atlas7_grp_mux audio_uart2_usclk_grp2_mux = {
2049 .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp2_pad_mux),
2050 .pad_mux_list = audio_uart2_usclk_grp2_pad_mux,
2051 };
2052
2053 static struct atlas7_pad_mux audio_uart2_utfs_grp0_pad_mux[] = {
2054 MUX(1, 18, 2, 0xa00, 22, 0xa80, 22),
2055 };
2056
2057 static struct atlas7_grp_mux audio_uart2_utfs_grp0_mux = {
2058 .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp0_pad_mux),
2059 .pad_mux_list = audio_uart2_utfs_grp0_pad_mux,
2060 };
2061
2062 static struct atlas7_pad_mux audio_uart2_utfs_grp1_pad_mux[] = {
2063 MUX(1, 111, 2, 0xa00, 22, 0xa80, 22),
2064 };
2065
2066 static struct atlas7_grp_mux audio_uart2_utfs_grp1_mux = {
2067 .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp1_pad_mux),
2068 .pad_mux_list = audio_uart2_utfs_grp1_pad_mux,
2069 };
2070
2071 static struct atlas7_pad_mux audio_uart2_utfs_grp2_pad_mux[] = {
2072 MUX(1, 94, 3, 0xa00, 22, 0xa80, 22),
2073 };
2074
2075 static struct atlas7_grp_mux audio_uart2_utfs_grp2_mux = {
2076 .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp2_pad_mux),
2077 .pad_mux_list = audio_uart2_utfs_grp2_pad_mux,
2078 };
2079
2080 static struct atlas7_pad_mux audio_uart2_utxd_grp0_pad_mux[] = {
2081 MUX(1, 21, 2, 0xa00, 25, 0xa80, 25),
2082 };
2083
2084 static struct atlas7_grp_mux audio_uart2_utxd_grp0_mux = {
2085 .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp0_pad_mux),
2086 .pad_mux_list = audio_uart2_utxd_grp0_pad_mux,
2087 };
2088
2089 static struct atlas7_pad_mux audio_uart2_utxd_grp1_pad_mux[] = {
2090 MUX(1, 110, 2, 0xa00, 25, 0xa80, 25),
2091 };
2092
2093 static struct atlas7_grp_mux audio_uart2_utxd_grp1_mux = {
2094 .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp1_pad_mux),
2095 .pad_mux_list = audio_uart2_utxd_grp1_pad_mux,
2096 };
2097
2098 static struct atlas7_pad_mux audio_uart2_utxd_grp2_pad_mux[] = {
2099 MUX(1, 92, 3, 0xa00, 25, 0xa80, 25),
2100 };
2101
2102 static struct atlas7_grp_mux audio_uart2_utxd_grp2_mux = {
2103 .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp2_pad_mux),
2104 .pad_mux_list = audio_uart2_utxd_grp2_pad_mux,
2105 };
2106
2107 static struct atlas7_pad_mux c_can_trnsvr_en_grp0_pad_mux[] = {
2108 MUX(0, 2, 6, N, N, N, N),
2109 };
2110
2111 static struct atlas7_grp_mux c_can_trnsvr_en_grp0_mux = {
2112 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp0_pad_mux),
2113 .pad_mux_list = c_can_trnsvr_en_grp0_pad_mux,
2114 };
2115
2116 static struct atlas7_pad_mux c_can_trnsvr_en_grp1_pad_mux[] = {
2117 MUX(0, 0, 2, N, N, N, N),
2118 };
2119
2120 static struct atlas7_grp_mux c_can_trnsvr_en_grp1_mux = {
2121 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp1_pad_mux),
2122 .pad_mux_list = c_can_trnsvr_en_grp1_pad_mux,
2123 };
2124
2125 static struct atlas7_pad_mux c_can_trnsvr_intr_grp_pad_mux[] = {
2126 MUX(0, 1, 2, N, N, N, N),
2127 };
2128
2129 static struct atlas7_grp_mux c_can_trnsvr_intr_grp_mux = {
2130 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_intr_grp_pad_mux),
2131 .pad_mux_list = c_can_trnsvr_intr_grp_pad_mux,
2132 };
2133
2134 static struct atlas7_pad_mux c_can_trnsvr_stb_n_grp_pad_mux[] = {
2135 MUX(0, 3, 6, N, N, N, N),
2136 };
2137
2138 static struct atlas7_grp_mux c_can_trnsvr_stb_n_grp_mux = {
2139 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_stb_n_grp_pad_mux),
2140 .pad_mux_list = c_can_trnsvr_stb_n_grp_pad_mux,
2141 };
2142
2143 static struct atlas7_pad_mux c0_can_rxd_trnsv0_grp_pad_mux[] = {
2144 MUX(0, 11, 1, 0xa08, 9, 0xa88, 9),
2145 };
2146
2147 static struct atlas7_grp_mux c0_can_rxd_trnsv0_grp_mux = {
2148 .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv0_grp_pad_mux),
2149 .pad_mux_list = c0_can_rxd_trnsv0_grp_pad_mux,
2150 };
2151
2152 static struct atlas7_pad_mux c0_can_rxd_trnsv1_grp_pad_mux[] = {
2153 MUX(0, 2, 5, 0xa10, 9, 0xa90, 9),
2154 };
2155
2156 static struct atlas7_grp_mux c0_can_rxd_trnsv1_grp_mux = {
2157 .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv1_grp_pad_mux),
2158 .pad_mux_list = c0_can_rxd_trnsv1_grp_pad_mux,
2159 };
2160
2161 static struct atlas7_pad_mux c0_can_txd_trnsv0_grp_pad_mux[] = {
2162 MUX(0, 10, 1, N, N, N, N),
2163 };
2164
2165 static struct atlas7_grp_mux c0_can_txd_trnsv0_grp_mux = {
2166 .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv0_grp_pad_mux),
2167 .pad_mux_list = c0_can_txd_trnsv0_grp_pad_mux,
2168 };
2169
2170 static struct atlas7_pad_mux c0_can_txd_trnsv1_grp_pad_mux[] = {
2171 MUX(0, 3, 5, N, N, N, N),
2172 };
2173
2174 static struct atlas7_grp_mux c0_can_txd_trnsv1_grp_mux = {
2175 .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv1_grp_pad_mux),
2176 .pad_mux_list = c0_can_txd_trnsv1_grp_pad_mux,
2177 };
2178
2179 static struct atlas7_pad_mux c1_can_rxd_grp0_pad_mux[] = {
2180 MUX(1, 138, 2, 0xa00, 4, 0xa80, 4),
2181 };
2182
2183 static struct atlas7_grp_mux c1_can_rxd_grp0_mux = {
2184 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp0_pad_mux),
2185 .pad_mux_list = c1_can_rxd_grp0_pad_mux,
2186 };
2187
2188 static struct atlas7_pad_mux c1_can_rxd_grp1_pad_mux[] = {
2189 MUX(1, 147, 2, 0xa00, 4, 0xa80, 4),
2190 };
2191
2192 static struct atlas7_grp_mux c1_can_rxd_grp1_mux = {
2193 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp1_pad_mux),
2194 .pad_mux_list = c1_can_rxd_grp1_pad_mux,
2195 };
2196
2197 static struct atlas7_pad_mux c1_can_rxd_grp2_pad_mux[] = {
2198 MUX(0, 2, 2, 0xa00, 4, 0xa80, 4),
2199 };
2200
2201 static struct atlas7_grp_mux c1_can_rxd_grp2_mux = {
2202 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp2_pad_mux),
2203 .pad_mux_list = c1_can_rxd_grp2_pad_mux,
2204 };
2205
2206 static struct atlas7_pad_mux c1_can_rxd_grp3_pad_mux[] = {
2207 MUX(1, 162, 4, 0xa00, 4, 0xa80, 4),
2208 };
2209
2210 static struct atlas7_grp_mux c1_can_rxd_grp3_mux = {
2211 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp3_pad_mux),
2212 .pad_mux_list = c1_can_rxd_grp3_pad_mux,
2213 };
2214
2215 static struct atlas7_pad_mux c1_can_txd_grp0_pad_mux[] = {
2216 MUX(1, 137, 2, N, N, N, N),
2217 };
2218
2219 static struct atlas7_grp_mux c1_can_txd_grp0_mux = {
2220 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp0_pad_mux),
2221 .pad_mux_list = c1_can_txd_grp0_pad_mux,
2222 };
2223
2224 static struct atlas7_pad_mux c1_can_txd_grp1_pad_mux[] = {
2225 MUX(1, 146, 2, N, N, N, N),
2226 };
2227
2228 static struct atlas7_grp_mux c1_can_txd_grp1_mux = {
2229 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp1_pad_mux),
2230 .pad_mux_list = c1_can_txd_grp1_pad_mux,
2231 };
2232
2233 static struct atlas7_pad_mux c1_can_txd_grp2_pad_mux[] = {
2234 MUX(0, 3, 2, N, N, N, N),
2235 };
2236
2237 static struct atlas7_grp_mux c1_can_txd_grp2_mux = {
2238 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp2_pad_mux),
2239 .pad_mux_list = c1_can_txd_grp2_pad_mux,
2240 };
2241
2242 static struct atlas7_pad_mux c1_can_txd_grp3_pad_mux[] = {
2243 MUX(1, 161, 4, N, N, N, N),
2244 };
2245
2246 static struct atlas7_grp_mux c1_can_txd_grp3_mux = {
2247 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp3_pad_mux),
2248 .pad_mux_list = c1_can_txd_grp3_pad_mux,
2249 };
2250
2251 static struct atlas7_pad_mux ca_audio_lpc_grp_pad_mux[] = {
2252 MUX(1, 62, 4, N, N, N, N),
2253 MUX(1, 63, 4, N, N, N, N),
2254 MUX(1, 64, 4, N, N, N, N),
2255 MUX(1, 65, 4, N, N, N, N),
2256 MUX(1, 66, 4, N, N, N, N),
2257 MUX(1, 67, 4, N, N, N, N),
2258 MUX(1, 68, 4, N, N, N, N),
2259 MUX(1, 69, 4, N, N, N, N),
2260 MUX(1, 70, 4, N, N, N, N),
2261 MUX(1, 71, 4, N, N, N, N),
2262 };
2263
2264 static struct atlas7_grp_mux ca_audio_lpc_grp_mux = {
2265 .pad_mux_count = ARRAY_SIZE(ca_audio_lpc_grp_pad_mux),
2266 .pad_mux_list = ca_audio_lpc_grp_pad_mux,
2267 };
2268
2269 static struct atlas7_pad_mux ca_bt_lpc_grp_pad_mux[] = {
2270 MUX(1, 85, 5, N, N, N, N),
2271 MUX(1, 86, 5, N, N, N, N),
2272 MUX(1, 87, 5, N, N, N, N),
2273 MUX(1, 88, 5, N, N, N, N),
2274 MUX(1, 89, 5, N, N, N, N),
2275 MUX(1, 90, 5, N, N, N, N),
2276 };
2277
2278 static struct atlas7_grp_mux ca_bt_lpc_grp_mux = {
2279 .pad_mux_count = ARRAY_SIZE(ca_bt_lpc_grp_pad_mux),
2280 .pad_mux_list = ca_bt_lpc_grp_pad_mux,
2281 };
2282
2283 static struct atlas7_pad_mux ca_coex_grp_pad_mux[] = {
2284 MUX(1, 129, 1, N, N, N, N),
2285 MUX(1, 130, 1, N, N, N, N),
2286 MUX(1, 131, 1, N, N, N, N),
2287 MUX(1, 132, 1, N, N, N, N),
2288 };
2289
2290 static struct atlas7_grp_mux ca_coex_grp_mux = {
2291 .pad_mux_count = ARRAY_SIZE(ca_coex_grp_pad_mux),
2292 .pad_mux_list = ca_coex_grp_pad_mux,
2293 };
2294
2295 static struct atlas7_pad_mux ca_curator_lpc_grp_pad_mux[] = {
2296 MUX(1, 57, 4, N, N, N, N),
2297 MUX(1, 58, 4, N, N, N, N),
2298 MUX(1, 59, 4, N, N, N, N),
2299 MUX(1, 60, 4, N, N, N, N),
2300 };
2301
2302 static struct atlas7_grp_mux ca_curator_lpc_grp_mux = {
2303 .pad_mux_count = ARRAY_SIZE(ca_curator_lpc_grp_pad_mux),
2304 .pad_mux_list = ca_curator_lpc_grp_pad_mux,
2305 };
2306
2307 static struct atlas7_pad_mux ca_pcm_debug_grp_pad_mux[] = {
2308 MUX(1, 91, 5, N, N, N, N),
2309 MUX(1, 93, 5, N, N, N, N),
2310 MUX(1, 94, 5, N, N, N, N),
2311 MUX(1, 92, 5, N, N, N, N),
2312 };
2313
2314 static struct atlas7_grp_mux ca_pcm_debug_grp_mux = {
2315 .pad_mux_count = ARRAY_SIZE(ca_pcm_debug_grp_pad_mux),
2316 .pad_mux_list = ca_pcm_debug_grp_pad_mux,
2317 };
2318
2319 static struct atlas7_pad_mux ca_pio_grp_pad_mux[] = {
2320 MUX(1, 121, 2, N, N, N, N),
2321 MUX(1, 122, 2, N, N, N, N),
2322 MUX(1, 125, 6, N, N, N, N),
2323 MUX(1, 126, 6, N, N, N, N),
2324 MUX(1, 38, 5, N, N, N, N),
2325 MUX(1, 37, 5, N, N, N, N),
2326 MUX(1, 47, 5, N, N, N, N),
2327 MUX(1, 49, 5, N, N, N, N),
2328 MUX(1, 50, 5, N, N, N, N),
2329 MUX(1, 54, 4, N, N, N, N),
2330 MUX(1, 55, 4, N, N, N, N),
2331 MUX(1, 56, 4, N, N, N, N),
2332 };
2333
2334 static struct atlas7_grp_mux ca_pio_grp_mux = {
2335 .pad_mux_count = ARRAY_SIZE(ca_pio_grp_pad_mux),
2336 .pad_mux_list = ca_pio_grp_pad_mux,
2337 };
2338
2339 static struct atlas7_pad_mux ca_sdio_debug_grp_pad_mux[] = {
2340 MUX(1, 40, 5, N, N, N, N),
2341 MUX(1, 39, 5, N, N, N, N),
2342 MUX(1, 44, 5, N, N, N, N),
2343 MUX(1, 43, 5, N, N, N, N),
2344 MUX(1, 42, 5, N, N, N, N),
2345 MUX(1, 41, 5, N, N, N, N),
2346 };
2347
2348 static struct atlas7_grp_mux ca_sdio_debug_grp_mux = {
2349 .pad_mux_count = ARRAY_SIZE(ca_sdio_debug_grp_pad_mux),
2350 .pad_mux_list = ca_sdio_debug_grp_pad_mux,
2351 };
2352
2353 static struct atlas7_pad_mux ca_spi_grp_pad_mux[] = {
2354 MUX(1, 82, 5, N, N, N, N),
2355 MUX(1, 79, 5, 0xa08, 6, 0xa88, 6),
2356 MUX(1, 80, 5, N, N, N, N),
2357 MUX(1, 81, 5, N, N, N, N),
2358 };
2359
2360 static struct atlas7_grp_mux ca_spi_grp_mux = {
2361 .pad_mux_count = ARRAY_SIZE(ca_spi_grp_pad_mux),
2362 .pad_mux_list = ca_spi_grp_pad_mux,
2363 };
2364
2365 static struct atlas7_pad_mux ca_trb_grp_pad_mux[] = {
2366 MUX(1, 91, 4, N, N, N, N),
2367 MUX(1, 93, 4, N, N, N, N),
2368 MUX(1, 94, 4, N, N, N, N),
2369 MUX(1, 95, 4, N, N, N, N),
2370 MUX(1, 96, 4, N, N, N, N),
2371 MUX(1, 78, 5, N, N, N, N),
2372 MUX(1, 74, 5, N, N, N, N),
2373 MUX(1, 75, 5, N, N, N, N),
2374 MUX(1, 76, 5, N, N, N, N),
2375 MUX(1, 77, 5, N, N, N, N),
2376 };
2377
2378 static struct atlas7_grp_mux ca_trb_grp_mux = {
2379 .pad_mux_count = ARRAY_SIZE(ca_trb_grp_pad_mux),
2380 .pad_mux_list = ca_trb_grp_pad_mux,
2381 };
2382
2383 static struct atlas7_pad_mux ca_uart_debug_grp_pad_mux[] = {
2384 MUX(1, 136, 3, N, N, N, N),
2385 MUX(1, 135, 3, N, N, N, N),
2386 MUX(1, 134, 3, N, N, N, N),
2387 MUX(1, 133, 3, N, N, N, N),
2388 };
2389
2390 static struct atlas7_grp_mux ca_uart_debug_grp_mux = {
2391 .pad_mux_count = ARRAY_SIZE(ca_uart_debug_grp_pad_mux),
2392 .pad_mux_list = ca_uart_debug_grp_pad_mux,
2393 };
2394
2395 static struct atlas7_pad_mux clkc_grp0_pad_mux[] = {
2396 MUX(1, 30, 2, 0xa08, 14, 0xa88, 14),
2397 MUX(1, 47, 6, N, N, N, N),
2398 };
2399
2400 static struct atlas7_grp_mux clkc_grp0_mux = {
2401 .pad_mux_count = ARRAY_SIZE(clkc_grp0_pad_mux),
2402 .pad_mux_list = clkc_grp0_pad_mux,
2403 };
2404
2405 static struct atlas7_pad_mux clkc_grp1_pad_mux[] = {
2406 MUX(1, 78, 3, 0xa08, 14, 0xa88, 14),
2407 MUX(1, 54, 5, N, N, N, N),
2408 };
2409
2410 static struct atlas7_grp_mux clkc_grp1_mux = {
2411 .pad_mux_count = ARRAY_SIZE(clkc_grp1_pad_mux),
2412 .pad_mux_list = clkc_grp1_pad_mux,
2413 };
2414
2415 static struct atlas7_pad_mux gn_gnss_i2c_grp_pad_mux[] = {
2416 MUX(1, 128, 2, N, N, N, N),
2417 MUX(1, 127, 2, N, N, N, N),
2418 };
2419
2420 static struct atlas7_grp_mux gn_gnss_i2c_grp_mux = {
2421 .pad_mux_count = ARRAY_SIZE(gn_gnss_i2c_grp_pad_mux),
2422 .pad_mux_list = gn_gnss_i2c_grp_pad_mux,
2423 };
2424
2425 static struct atlas7_pad_mux gn_gnss_uart_nopause_grp_pad_mux[] = {
2426 MUX(1, 134, 4, N, N, N, N),
2427 MUX(1, 133, 4, N, N, N, N),
2428 };
2429
2430 static struct atlas7_grp_mux gn_gnss_uart_nopause_grp_mux = {
2431 .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_nopause_grp_pad_mux),
2432 .pad_mux_list = gn_gnss_uart_nopause_grp_pad_mux,
2433 };
2434
2435 static struct atlas7_pad_mux gn_gnss_uart_grp_pad_mux[] = {
2436 MUX(1, 134, 4, N, N, N, N),
2437 MUX(1, 133, 4, N, N, N, N),
2438 MUX(1, 136, 4, N, N, N, N),
2439 MUX(1, 135, 4, N, N, N, N),
2440 };
2441
2442 static struct atlas7_grp_mux gn_gnss_uart_grp_mux = {
2443 .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_grp_pad_mux),
2444 .pad_mux_list = gn_gnss_uart_grp_pad_mux,
2445 };
2446
2447 static struct atlas7_pad_mux gn_trg_spi_grp0_pad_mux[] = {
2448 MUX(1, 22, 1, N, N, N, N),
2449 MUX(1, 25, 1, N, N, N, N),
2450 MUX(1, 23, 1, 0xa00, 10, 0xa80, 10),
2451 MUX(1, 24, 1, N, N, N, N),
2452 };
2453
2454 static struct atlas7_grp_mux gn_trg_spi_grp0_mux = {
2455 .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp0_pad_mux),
2456 .pad_mux_list = gn_trg_spi_grp0_pad_mux,
2457 };
2458
2459 static struct atlas7_pad_mux gn_trg_spi_grp1_pad_mux[] = {
2460 MUX(1, 82, 3, N, N, N, N),
2461 MUX(1, 79, 3, N, N, N, N),
2462 MUX(1, 80, 3, 0xa00, 10, 0xa80, 10),
2463 MUX(1, 81, 3, N, N, N, N),
2464 };
2465
2466 static struct atlas7_grp_mux gn_trg_spi_grp1_mux = {
2467 .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp1_pad_mux),
2468 .pad_mux_list = gn_trg_spi_grp1_pad_mux,
2469 };
2470
2471 static struct atlas7_pad_mux cvbs_dbg_grp_pad_mux[] = {
2472 MUX(1, 54, 3, N, N, N, N),
2473 MUX(1, 53, 3, N, N, N, N),
2474 MUX(1, 82, 7, N, N, N, N),
2475 MUX(1, 74, 7, N, N, N, N),
2476 MUX(1, 75, 7, N, N, N, N),
2477 MUX(1, 76, 7, N, N, N, N),
2478 MUX(1, 77, 7, N, N, N, N),
2479 MUX(1, 78, 7, N, N, N, N),
2480 MUX(1, 79, 7, N, N, N, N),
2481 MUX(1, 80, 7, N, N, N, N),
2482 MUX(1, 81, 7, N, N, N, N),
2483 MUX(1, 83, 7, N, N, N, N),
2484 MUX(1, 84, 7, N, N, N, N),
2485 MUX(1, 73, 3, N, N, N, N),
2486 MUX(1, 55, 3, N, N, N, N),
2487 MUX(1, 56, 3, N, N, N, N),
2488 };
2489
2490 static struct atlas7_grp_mux cvbs_dbg_grp_mux = {
2491 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_grp_pad_mux),
2492 .pad_mux_list = cvbs_dbg_grp_pad_mux,
2493 };
2494
2495 static struct atlas7_pad_mux cvbs_dbg_test_grp0_pad_mux[] = {
2496 MUX(1, 57, 3, N, N, N, N),
2497 };
2498
2499 static struct atlas7_grp_mux cvbs_dbg_test_grp0_mux = {
2500 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp0_pad_mux),
2501 .pad_mux_list = cvbs_dbg_test_grp0_pad_mux,
2502 };
2503
2504 static struct atlas7_pad_mux cvbs_dbg_test_grp1_pad_mux[] = {
2505 MUX(1, 58, 3, N, N, N, N),
2506 };
2507
2508 static struct atlas7_grp_mux cvbs_dbg_test_grp1_mux = {
2509 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp1_pad_mux),
2510 .pad_mux_list = cvbs_dbg_test_grp1_pad_mux,
2511 };
2512
2513 static struct atlas7_pad_mux cvbs_dbg_test_grp2_pad_mux[] = {
2514 MUX(1, 59, 3, N, N, N, N),
2515 };
2516
2517 static struct atlas7_grp_mux cvbs_dbg_test_grp2_mux = {
2518 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp2_pad_mux),
2519 .pad_mux_list = cvbs_dbg_test_grp2_pad_mux,
2520 };
2521
2522 static struct atlas7_pad_mux cvbs_dbg_test_grp3_pad_mux[] = {
2523 MUX(1, 60, 3, N, N, N, N),
2524 };
2525
2526 static struct atlas7_grp_mux cvbs_dbg_test_grp3_mux = {
2527 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp3_pad_mux),
2528 .pad_mux_list = cvbs_dbg_test_grp3_pad_mux,
2529 };
2530
2531 static struct atlas7_pad_mux cvbs_dbg_test_grp4_pad_mux[] = {
2532 MUX(1, 61, 3, N, N, N, N),
2533 };
2534
2535 static struct atlas7_grp_mux cvbs_dbg_test_grp4_mux = {
2536 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp4_pad_mux),
2537 .pad_mux_list = cvbs_dbg_test_grp4_pad_mux,
2538 };
2539
2540 static struct atlas7_pad_mux cvbs_dbg_test_grp5_pad_mux[] = {
2541 MUX(1, 62, 3, N, N, N, N),
2542 };
2543
2544 static struct atlas7_grp_mux cvbs_dbg_test_grp5_mux = {
2545 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp5_pad_mux),
2546 .pad_mux_list = cvbs_dbg_test_grp5_pad_mux,
2547 };
2548
2549 static struct atlas7_pad_mux cvbs_dbg_test_grp6_pad_mux[] = {
2550 MUX(1, 63, 3, N, N, N, N),
2551 };
2552
2553 static struct atlas7_grp_mux cvbs_dbg_test_grp6_mux = {
2554 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp6_pad_mux),
2555 .pad_mux_list = cvbs_dbg_test_grp6_pad_mux,
2556 };
2557
2558 static struct atlas7_pad_mux cvbs_dbg_test_grp7_pad_mux[] = {
2559 MUX(1, 64, 3, N, N, N, N),
2560 };
2561
2562 static struct atlas7_grp_mux cvbs_dbg_test_grp7_mux = {
2563 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp7_pad_mux),
2564 .pad_mux_list = cvbs_dbg_test_grp7_pad_mux,
2565 };
2566
2567 static struct atlas7_pad_mux cvbs_dbg_test_grp8_pad_mux[] = {
2568 MUX(1, 65, 3, N, N, N, N),
2569 };
2570
2571 static struct atlas7_grp_mux cvbs_dbg_test_grp8_mux = {
2572 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp8_pad_mux),
2573 .pad_mux_list = cvbs_dbg_test_grp8_pad_mux,
2574 };
2575
2576 static struct atlas7_pad_mux cvbs_dbg_test_grp9_pad_mux[] = {
2577 MUX(1, 66, 3, N, N, N, N),
2578 };
2579
2580 static struct atlas7_grp_mux cvbs_dbg_test_grp9_mux = {
2581 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp9_pad_mux),
2582 .pad_mux_list = cvbs_dbg_test_grp9_pad_mux,
2583 };
2584
2585 static struct atlas7_pad_mux cvbs_dbg_test_grp10_pad_mux[] = {
2586 MUX(1, 67, 3, N, N, N, N),
2587 };
2588
2589 static struct atlas7_grp_mux cvbs_dbg_test_grp10_mux = {
2590 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp10_pad_mux),
2591 .pad_mux_list = cvbs_dbg_test_grp10_pad_mux,
2592 };
2593
2594 static struct atlas7_pad_mux cvbs_dbg_test_grp11_pad_mux[] = {
2595 MUX(1, 68, 3, N, N, N, N),
2596 };
2597
2598 static struct atlas7_grp_mux cvbs_dbg_test_grp11_mux = {
2599 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp11_pad_mux),
2600 .pad_mux_list = cvbs_dbg_test_grp11_pad_mux,
2601 };
2602
2603 static struct atlas7_pad_mux cvbs_dbg_test_grp12_pad_mux[] = {
2604 MUX(1, 69, 3, N, N, N, N),
2605 };
2606
2607 static struct atlas7_grp_mux cvbs_dbg_test_grp12_mux = {
2608 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp12_pad_mux),
2609 .pad_mux_list = cvbs_dbg_test_grp12_pad_mux,
2610 };
2611
2612 static struct atlas7_pad_mux cvbs_dbg_test_grp13_pad_mux[] = {
2613 MUX(1, 70, 3, N, N, N, N),
2614 };
2615
2616 static struct atlas7_grp_mux cvbs_dbg_test_grp13_mux = {
2617 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp13_pad_mux),
2618 .pad_mux_list = cvbs_dbg_test_grp13_pad_mux,
2619 };
2620
2621 static struct atlas7_pad_mux cvbs_dbg_test_grp14_pad_mux[] = {
2622 MUX(1, 71, 3, N, N, N, N),
2623 };
2624
2625 static struct atlas7_grp_mux cvbs_dbg_test_grp14_mux = {
2626 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp14_pad_mux),
2627 .pad_mux_list = cvbs_dbg_test_grp14_pad_mux,
2628 };
2629
2630 static struct atlas7_pad_mux cvbs_dbg_test_grp15_pad_mux[] = {
2631 MUX(1, 72, 3, N, N, N, N),
2632 };
2633
2634 static struct atlas7_grp_mux cvbs_dbg_test_grp15_mux = {
2635 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp15_pad_mux),
2636 .pad_mux_list = cvbs_dbg_test_grp15_pad_mux,
2637 };
2638
2639 static struct atlas7_pad_mux gn_gnss_power_grp_pad_mux[] = {
2640 MUX(1, 123, 7, N, N, N, N),
2641 MUX(1, 124, 7, N, N, N, N),
2642 MUX(1, 121, 7, N, N, N, N),
2643 MUX(1, 122, 7, N, N, N, N),
2644 MUX(1, 125, 7, N, N, N, N),
2645 MUX(1, 120, 7, N, N, N, N),
2646 };
2647
2648 static struct atlas7_grp_mux gn_gnss_power_grp_mux = {
2649 .pad_mux_count = ARRAY_SIZE(gn_gnss_power_grp_pad_mux),
2650 .pad_mux_list = gn_gnss_power_grp_pad_mux,
2651 };
2652
2653 static struct atlas7_pad_mux gn_gnss_sw_status_grp_pad_mux[] = {
2654 MUX(1, 57, 7, N, N, N, N),
2655 MUX(1, 58, 7, N, N, N, N),
2656 MUX(1, 59, 7, N, N, N, N),
2657 MUX(1, 60, 7, N, N, N, N),
2658 MUX(1, 61, 7, N, N, N, N),
2659 MUX(1, 62, 7, N, N, N, N),
2660 MUX(1, 63, 7, N, N, N, N),
2661 MUX(1, 64, 7, N, N, N, N),
2662 MUX(1, 65, 7, N, N, N, N),
2663 MUX(1, 66, 7, N, N, N, N),
2664 MUX(1, 67, 7, N, N, N, N),
2665 MUX(1, 68, 7, N, N, N, N),
2666 MUX(1, 69, 7, N, N, N, N),
2667 MUX(1, 70, 7, N, N, N, N),
2668 MUX(1, 71, 7, N, N, N, N),
2669 MUX(1, 72, 7, N, N, N, N),
2670 MUX(1, 53, 7, N, N, N, N),
2671 MUX(1, 55, 7, N, N, N, N),
2672 MUX(1, 56, 7, 0xa08, 12, 0xa88, 12),
2673 MUX(1, 54, 7, N, N, N, N),
2674 };
2675
2676 static struct atlas7_grp_mux gn_gnss_sw_status_grp_mux = {
2677 .pad_mux_count = ARRAY_SIZE(gn_gnss_sw_status_grp_pad_mux),
2678 .pad_mux_list = gn_gnss_sw_status_grp_pad_mux,
2679 };
2680
2681 static struct atlas7_pad_mux gn_gnss_eclk_grp_pad_mux[] = {
2682 MUX(1, 113, 4, N, N, N, N),
2683 };
2684
2685 static struct atlas7_grp_mux gn_gnss_eclk_grp_mux = {
2686 .pad_mux_count = ARRAY_SIZE(gn_gnss_eclk_grp_pad_mux),
2687 .pad_mux_list = gn_gnss_eclk_grp_pad_mux,
2688 };
2689
2690 static struct atlas7_pad_mux gn_gnss_irq1_grp0_pad_mux[] = {
2691 MUX(1, 112, 4, 0xa08, 10, 0xa88, 10),
2692 };
2693
2694 static struct atlas7_grp_mux gn_gnss_irq1_grp0_mux = {
2695 .pad_mux_count = ARRAY_SIZE(gn_gnss_irq1_grp0_pad_mux),
2696 .pad_mux_list = gn_gnss_irq1_grp0_pad_mux,
2697 };
2698
2699 static struct atlas7_pad_mux gn_gnss_irq2_grp0_pad_mux[] = {
2700 MUX(1, 118, 4, 0xa08, 11, 0xa88, 11),
2701 };
2702
2703 static struct atlas7_grp_mux gn_gnss_irq2_grp0_mux = {
2704 .pad_mux_count = ARRAY_SIZE(gn_gnss_irq2_grp0_pad_mux),
2705 .pad_mux_list = gn_gnss_irq2_grp0_pad_mux,
2706 };
2707
2708 static struct atlas7_pad_mux gn_gnss_tm_grp_pad_mux[] = {
2709 MUX(1, 115, 4, N, N, N, N),
2710 };
2711
2712 static struct atlas7_grp_mux gn_gnss_tm_grp_mux = {
2713 .pad_mux_count = ARRAY_SIZE(gn_gnss_tm_grp_pad_mux),
2714 .pad_mux_list = gn_gnss_tm_grp_pad_mux,
2715 };
2716
2717 static struct atlas7_pad_mux gn_gnss_tsync_grp_pad_mux[] = {
2718 MUX(1, 114, 4, N, N, N, N),
2719 };
2720
2721 static struct atlas7_grp_mux gn_gnss_tsync_grp_mux = {
2722 .pad_mux_count = ARRAY_SIZE(gn_gnss_tsync_grp_pad_mux),
2723 .pad_mux_list = gn_gnss_tsync_grp_pad_mux,
2724 };
2725
2726 static struct atlas7_pad_mux gn_io_gnsssys_sw_cfg_grp_pad_mux[] = {
2727 MUX(1, 44, 7, N, N, N, N),
2728 MUX(1, 43, 7, N, N, N, N),
2729 MUX(1, 42, 7, N, N, N, N),
2730 MUX(1, 41, 7, N, N, N, N),
2731 MUX(1, 40, 7, N, N, N, N),
2732 MUX(1, 39, 7, N, N, N, N),
2733 MUX(1, 38, 7, N, N, N, N),
2734 MUX(1, 37, 7, N, N, N, N),
2735 MUX(1, 49, 7, N, N, N, N),
2736 MUX(1, 50, 7, N, N, N, N),
2737 MUX(1, 91, 7, N, N, N, N),
2738 MUX(1, 92, 7, N, N, N, N),
2739 MUX(1, 93, 7, N, N, N, N),
2740 MUX(1, 94, 7, N, N, N, N),
2741 MUX(1, 95, 7, N, N, N, N),
2742 MUX(1, 96, 7, N, N, N, N),
2743 };
2744
2745 static struct atlas7_grp_mux gn_io_gnsssys_sw_cfg_grp_mux = {
2746 .pad_mux_count = ARRAY_SIZE(gn_io_gnsssys_sw_cfg_grp_pad_mux),
2747 .pad_mux_list = gn_io_gnsssys_sw_cfg_grp_pad_mux,
2748 };
2749
2750 static struct atlas7_pad_mux gn_trg_grp0_pad_mux[] = {
2751 MUX(1, 29, 1, 0xa00, 6, 0xa80, 6),
2752 MUX(1, 28, 1, 0xa00, 7, 0xa80, 7),
2753 MUX(1, 26, 1, 0xa00, 8, 0xa80, 8),
2754 MUX(1, 27, 1, 0xa00, 9, 0xa80, 9),
2755 };
2756
2757 static struct atlas7_grp_mux gn_trg_grp0_mux = {
2758 .pad_mux_count = ARRAY_SIZE(gn_trg_grp0_pad_mux),
2759 .pad_mux_list = gn_trg_grp0_pad_mux,
2760 };
2761
2762 static struct atlas7_pad_mux gn_trg_grp1_pad_mux[] = {
2763 MUX(1, 77, 3, 0xa00, 6, 0xa80, 6),
2764 MUX(1, 76, 3, 0xa00, 7, 0xa80, 7),
2765 MUX(1, 74, 3, 0xa00, 8, 0xa80, 8),
2766 MUX(1, 75, 3, 0xa00, 9, 0xa80, 9),
2767 };
2768
2769 static struct atlas7_grp_mux gn_trg_grp1_mux = {
2770 .pad_mux_count = ARRAY_SIZE(gn_trg_grp1_pad_mux),
2771 .pad_mux_list = gn_trg_grp1_pad_mux,
2772 };
2773
2774 static struct atlas7_pad_mux gn_trg_shutdown_grp0_pad_mux[] = {
2775 MUX(1, 30, 1, N, N, N, N),
2776 };
2777
2778 static struct atlas7_grp_mux gn_trg_shutdown_grp0_mux = {
2779 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp0_pad_mux),
2780 .pad_mux_list = gn_trg_shutdown_grp0_pad_mux,
2781 };
2782
2783 static struct atlas7_pad_mux gn_trg_shutdown_grp1_pad_mux[] = {
2784 MUX(1, 83, 3, N, N, N, N),
2785 };
2786
2787 static struct atlas7_grp_mux gn_trg_shutdown_grp1_mux = {
2788 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp1_pad_mux),
2789 .pad_mux_list = gn_trg_shutdown_grp1_pad_mux,
2790 };
2791
2792 static struct atlas7_pad_mux gn_trg_shutdown_grp2_pad_mux[] = {
2793 MUX(1, 117, 4, N, N, N, N),
2794 };
2795
2796 static struct atlas7_grp_mux gn_trg_shutdown_grp2_mux = {
2797 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp2_pad_mux),
2798 .pad_mux_list = gn_trg_shutdown_grp2_pad_mux,
2799 };
2800
2801 static struct atlas7_pad_mux gn_trg_shutdown_grp3_pad_mux[] = {
2802 MUX(1, 123, 5, N, N, N, N),
2803 };
2804
2805 static struct atlas7_grp_mux gn_trg_shutdown_grp3_mux = {
2806 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp3_pad_mux),
2807 .pad_mux_list = gn_trg_shutdown_grp3_pad_mux,
2808 };
2809
2810 static struct atlas7_pad_mux i2c0_grp_pad_mux[] = {
2811 MUX(1, 128, 1, N, N, N, N),
2812 MUX(1, 127, 1, N, N, N, N),
2813 };
2814
2815 static struct atlas7_grp_mux i2c0_grp_mux = {
2816 .pad_mux_count = ARRAY_SIZE(i2c0_grp_pad_mux),
2817 .pad_mux_list = i2c0_grp_pad_mux,
2818 };
2819
2820 static struct atlas7_pad_mux i2c1_grp_pad_mux[] = {
2821 MUX(1, 126, 4, N, N, N, N),
2822 MUX(1, 125, 4, N, N, N, N),
2823 };
2824
2825 static struct atlas7_grp_mux i2c1_grp_mux = {
2826 .pad_mux_count = ARRAY_SIZE(i2c1_grp_pad_mux),
2827 .pad_mux_list = i2c1_grp_pad_mux,
2828 };
2829
2830 static struct atlas7_pad_mux i2s0_grp_pad_mux[] = {
2831 MUX(1, 91, 2, 0xa10, 12, 0xa90, 12),
2832 MUX(1, 93, 2, 0xa10, 13, 0xa90, 13),
2833 MUX(1, 94, 2, 0xa10, 14, 0xa90, 14),
2834 MUX(1, 92, 2, 0xa10, 15, 0xa90, 15),
2835 };
2836
2837 static struct atlas7_grp_mux i2s0_grp_mux = {
2838 .pad_mux_count = ARRAY_SIZE(i2s0_grp_pad_mux),
2839 .pad_mux_list = i2s0_grp_pad_mux,
2840 };
2841
2842 static struct atlas7_pad_mux i2s1_basic_grp_pad_mux[] = {
2843 MUX(1, 95, 2, 0xa10, 16, 0xa90, 16),
2844 MUX(1, 96, 2, 0xa10, 19, 0xa90, 19),
2845 };
2846
2847 static struct atlas7_grp_mux i2s1_basic_grp_mux = {
2848 .pad_mux_count = ARRAY_SIZE(i2s1_basic_grp_pad_mux),
2849 .pad_mux_list = i2s1_basic_grp_pad_mux,
2850 };
2851
2852 static struct atlas7_pad_mux i2s1_rxd0_grp0_pad_mux[] = {
2853 MUX(1, 61, 4, 0xa10, 17, 0xa90, 17),
2854 };
2855
2856 static struct atlas7_grp_mux i2s1_rxd0_grp0_mux = {
2857 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp0_pad_mux),
2858 .pad_mux_list = i2s1_rxd0_grp0_pad_mux,
2859 };
2860
2861 static struct atlas7_pad_mux i2s1_rxd0_grp1_pad_mux[] = {
2862 MUX(1, 131, 4, 0xa10, 17, 0xa90, 17),
2863 };
2864
2865 static struct atlas7_grp_mux i2s1_rxd0_grp1_mux = {
2866 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp1_pad_mux),
2867 .pad_mux_list = i2s1_rxd0_grp1_pad_mux,
2868 };
2869
2870 static struct atlas7_pad_mux i2s1_rxd0_grp2_pad_mux[] = {
2871 MUX(1, 129, 2, 0xa10, 17, 0xa90, 17),
2872 };
2873
2874 static struct atlas7_grp_mux i2s1_rxd0_grp2_mux = {
2875 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp2_pad_mux),
2876 .pad_mux_list = i2s1_rxd0_grp2_pad_mux,
2877 };
2878
2879 static struct atlas7_pad_mux i2s1_rxd0_grp3_pad_mux[] = {
2880 MUX(1, 117, 7, 0xa10, 17, 0xa90, 17),
2881 };
2882
2883 static struct atlas7_grp_mux i2s1_rxd0_grp3_mux = {
2884 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp3_pad_mux),
2885 .pad_mux_list = i2s1_rxd0_grp3_pad_mux,
2886 };
2887
2888 static struct atlas7_pad_mux i2s1_rxd0_grp4_pad_mux[] = {
2889 MUX(1, 83, 4, 0xa10, 17, 0xa90, 17),
2890 };
2891
2892 static struct atlas7_grp_mux i2s1_rxd0_grp4_mux = {
2893 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp4_pad_mux),
2894 .pad_mux_list = i2s1_rxd0_grp4_pad_mux,
2895 };
2896
2897 static struct atlas7_pad_mux i2s1_rxd1_grp0_pad_mux[] = {
2898 MUX(1, 72, 4, 0xa10, 18, 0xa90, 18),
2899 };
2900
2901 static struct atlas7_grp_mux i2s1_rxd1_grp0_mux = {
2902 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp0_pad_mux),
2903 .pad_mux_list = i2s1_rxd1_grp0_pad_mux,
2904 };
2905
2906 static struct atlas7_pad_mux i2s1_rxd1_grp1_pad_mux[] = {
2907 MUX(1, 132, 4, 0xa10, 18, 0xa90, 18),
2908 };
2909
2910 static struct atlas7_grp_mux i2s1_rxd1_grp1_mux = {
2911 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp1_pad_mux),
2912 .pad_mux_list = i2s1_rxd1_grp1_pad_mux,
2913 };
2914
2915 static struct atlas7_pad_mux i2s1_rxd1_grp2_pad_mux[] = {
2916 MUX(1, 130, 2, 0xa10, 18, 0xa90, 18),
2917 };
2918
2919 static struct atlas7_grp_mux i2s1_rxd1_grp2_mux = {
2920 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp2_pad_mux),
2921 .pad_mux_list = i2s1_rxd1_grp2_pad_mux,
2922 };
2923
2924 static struct atlas7_pad_mux i2s1_rxd1_grp3_pad_mux[] = {
2925 MUX(1, 118, 7, 0xa10, 18, 0xa90, 18),
2926 };
2927
2928 static struct atlas7_grp_mux i2s1_rxd1_grp3_mux = {
2929 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp3_pad_mux),
2930 .pad_mux_list = i2s1_rxd1_grp3_pad_mux,
2931 };
2932
2933 static struct atlas7_pad_mux i2s1_rxd1_grp4_pad_mux[] = {
2934 MUX(1, 84, 4, 0xa10, 18, 0xa90, 18),
2935 };
2936
2937 static struct atlas7_grp_mux i2s1_rxd1_grp4_mux = {
2938 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp4_pad_mux),
2939 .pad_mux_list = i2s1_rxd1_grp4_pad_mux,
2940 };
2941
2942 static struct atlas7_pad_mux jtag_jt_dbg_nsrst_grp_pad_mux[] = {
2943 MUX(1, 125, 5, 0xa08, 2, 0xa88, 2),
2944 };
2945
2946 static struct atlas7_grp_mux jtag_jt_dbg_nsrst_grp_mux = {
2947 .pad_mux_count = ARRAY_SIZE(jtag_jt_dbg_nsrst_grp_pad_mux),
2948 .pad_mux_list = jtag_jt_dbg_nsrst_grp_pad_mux,
2949 };
2950
2951 static struct atlas7_pad_mux jtag_ntrst_grp0_pad_mux[] = {
2952 MUX(0, 4, 3, 0xa08, 3, 0xa88, 3),
2953 };
2954
2955 static struct atlas7_grp_mux jtag_ntrst_grp0_mux = {
2956 .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp0_pad_mux),
2957 .pad_mux_list = jtag_ntrst_grp0_pad_mux,
2958 };
2959
2960 static struct atlas7_pad_mux jtag_ntrst_grp1_pad_mux[] = {
2961 MUX(1, 163, 1, 0xa08, 3, 0xa88, 3),
2962 };
2963
2964 static struct atlas7_grp_mux jtag_ntrst_grp1_mux = {
2965 .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp1_pad_mux),
2966 .pad_mux_list = jtag_ntrst_grp1_pad_mux,
2967 };
2968
2969 static struct atlas7_pad_mux jtag_swdiotms_grp0_pad_mux[] = {
2970 MUX(0, 2, 3, 0xa10, 10, 0xa90, 10),
2971 };
2972
2973 static struct atlas7_grp_mux jtag_swdiotms_grp0_mux = {
2974 .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp0_pad_mux),
2975 .pad_mux_list = jtag_swdiotms_grp0_pad_mux,
2976 };
2977
2978 static struct atlas7_pad_mux jtag_swdiotms_grp1_pad_mux[] = {
2979 MUX(1, 160, 1, 0xa10, 10, 0xa90, 10),
2980 };
2981
2982 static struct atlas7_grp_mux jtag_swdiotms_grp1_mux = {
2983 .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp1_pad_mux),
2984 .pad_mux_list = jtag_swdiotms_grp1_pad_mux,
2985 };
2986
2987 static struct atlas7_pad_mux jtag_tck_grp0_pad_mux[] = {
2988 MUX(0, 0, 3, 0xa10, 11, 0xa90, 11),
2989 };
2990
2991 static struct atlas7_grp_mux jtag_tck_grp0_mux = {
2992 .pad_mux_count = ARRAY_SIZE(jtag_tck_grp0_pad_mux),
2993 .pad_mux_list = jtag_tck_grp0_pad_mux,
2994 };
2995
2996 static struct atlas7_pad_mux jtag_tck_grp1_pad_mux[] = {
2997 MUX(1, 161, 1, 0xa10, 11, 0xa90, 11),
2998 };
2999
3000 static struct atlas7_grp_mux jtag_tck_grp1_mux = {
3001 .pad_mux_count = ARRAY_SIZE(jtag_tck_grp1_pad_mux),
3002 .pad_mux_list = jtag_tck_grp1_pad_mux,
3003 };
3004
3005 static struct atlas7_pad_mux jtag_tdi_grp0_pad_mux[] = {
3006 MUX(0, 1, 3, 0xa10, 31, 0xa90, 31),
3007 };
3008
3009 static struct atlas7_grp_mux jtag_tdi_grp0_mux = {
3010 .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp0_pad_mux),
3011 .pad_mux_list = jtag_tdi_grp0_pad_mux,
3012 };
3013
3014 static struct atlas7_pad_mux jtag_tdi_grp1_pad_mux[] = {
3015 MUX(1, 162, 1, 0xa10, 31, 0xa90, 31),
3016 };
3017
3018 static struct atlas7_grp_mux jtag_tdi_grp1_mux = {
3019 .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp1_pad_mux),
3020 .pad_mux_list = jtag_tdi_grp1_pad_mux,
3021 };
3022
3023 static struct atlas7_pad_mux jtag_tdo_grp0_pad_mux[] = {
3024 MUX(0, 3, 3, N, N, N, N),
3025 };
3026
3027 static struct atlas7_grp_mux jtag_tdo_grp0_mux = {
3028 .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp0_pad_mux),
3029 .pad_mux_list = jtag_tdo_grp0_pad_mux,
3030 };
3031
3032 static struct atlas7_pad_mux jtag_tdo_grp1_pad_mux[] = {
3033 MUX(1, 159, 1, N, N, N, N),
3034 };
3035
3036 static struct atlas7_grp_mux jtag_tdo_grp1_mux = {
3037 .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp1_pad_mux),
3038 .pad_mux_list = jtag_tdo_grp1_pad_mux,
3039 };
3040
3041 static struct atlas7_pad_mux ks_kas_spi_grp0_pad_mux[] = {
3042 MUX(1, 141, 2, N, N, N, N),
3043 MUX(1, 144, 2, 0xa08, 8, 0xa88, 8),
3044 MUX(1, 143, 2, N, N, N, N),
3045 MUX(1, 142, 2, N, N, N, N),
3046 };
3047
3048 static struct atlas7_grp_mux ks_kas_spi_grp0_mux = {
3049 .pad_mux_count = ARRAY_SIZE(ks_kas_spi_grp0_pad_mux),
3050 .pad_mux_list = ks_kas_spi_grp0_pad_mux,
3051 };
3052
3053 static struct atlas7_pad_mux ld_ldd_grp_pad_mux[] = {
3054 MUX(1, 57, 1, N, N, N, N),
3055 MUX(1, 58, 1, N, N, N, N),
3056 MUX(1, 59, 1, N, N, N, N),
3057 MUX(1, 60, 1, N, N, N, N),
3058 MUX(1, 61, 1, N, N, N, N),
3059 MUX(1, 62, 1, N, N, N, N),
3060 MUX(1, 63, 1, N, N, N, N),
3061 MUX(1, 64, 1, N, N, N, N),
3062 MUX(1, 65, 1, N, N, N, N),
3063 MUX(1, 66, 1, N, N, N, N),
3064 MUX(1, 67, 1, N, N, N, N),
3065 MUX(1, 68, 1, N, N, N, N),
3066 MUX(1, 69, 1, N, N, N, N),
3067 MUX(1, 70, 1, N, N, N, N),
3068 MUX(1, 71, 1, N, N, N, N),
3069 MUX(1, 72, 1, N, N, N, N),
3070 MUX(1, 74, 2, N, N, N, N),
3071 MUX(1, 75, 2, N, N, N, N),
3072 MUX(1, 76, 2, N, N, N, N),
3073 MUX(1, 77, 2, N, N, N, N),
3074 MUX(1, 78, 2, N, N, N, N),
3075 MUX(1, 79, 2, N, N, N, N),
3076 MUX(1, 80, 2, N, N, N, N),
3077 MUX(1, 81, 2, N, N, N, N),
3078 MUX(1, 56, 1, N, N, N, N),
3079 MUX(1, 53, 1, N, N, N, N),
3080 };
3081
3082 static struct atlas7_grp_mux ld_ldd_grp_mux = {
3083 .pad_mux_count = ARRAY_SIZE(ld_ldd_grp_pad_mux),
3084 .pad_mux_list = ld_ldd_grp_pad_mux,
3085 };
3086
3087 static struct atlas7_pad_mux ld_ldd_16bit_grp_pad_mux[] = {
3088 MUX(1, 57, 1, N, N, N, N),
3089 MUX(1, 58, 1, N, N, N, N),
3090 MUX(1, 59, 1, N, N, N, N),
3091 MUX(1, 60, 1, N, N, N, N),
3092 MUX(1, 61, 1, N, N, N, N),
3093 MUX(1, 62, 1, N, N, N, N),
3094 MUX(1, 63, 1, N, N, N, N),
3095 MUX(1, 64, 1, N, N, N, N),
3096 MUX(1, 65, 1, N, N, N, N),
3097 MUX(1, 66, 1, N, N, N, N),
3098 MUX(1, 67, 1, N, N, N, N),
3099 MUX(1, 68, 1, N, N, N, N),
3100 MUX(1, 69, 1, N, N, N, N),
3101 MUX(1, 70, 1, N, N, N, N),
3102 MUX(1, 71, 1, N, N, N, N),
3103 MUX(1, 72, 1, N, N, N, N),
3104 MUX(1, 56, 1, N, N, N, N),
3105 MUX(1, 53, 1, N, N, N, N),
3106 };
3107
3108 static struct atlas7_grp_mux ld_ldd_16bit_grp_mux = {
3109 .pad_mux_count = ARRAY_SIZE(ld_ldd_16bit_grp_pad_mux),
3110 .pad_mux_list = ld_ldd_16bit_grp_pad_mux,
3111 };
3112
3113 static struct atlas7_pad_mux ld_ldd_fck_grp_pad_mux[] = {
3114 MUX(1, 55, 1, N, N, N, N),
3115 };
3116
3117 static struct atlas7_grp_mux ld_ldd_fck_grp_mux = {
3118 .pad_mux_count = ARRAY_SIZE(ld_ldd_fck_grp_pad_mux),
3119 .pad_mux_list = ld_ldd_fck_grp_pad_mux,
3120 };
3121
3122 static struct atlas7_pad_mux ld_ldd_lck_grp_pad_mux[] = {
3123 MUX(1, 54, 1, N, N, N, N),
3124 };
3125
3126 static struct atlas7_grp_mux ld_ldd_lck_grp_mux = {
3127 .pad_mux_count = ARRAY_SIZE(ld_ldd_lck_grp_pad_mux),
3128 .pad_mux_list = ld_ldd_lck_grp_pad_mux,
3129 };
3130
3131 static struct atlas7_pad_mux lr_lcdrom_grp_pad_mux[] = {
3132 MUX(1, 73, 2, N, N, N, N),
3133 MUX(1, 54, 2, N, N, N, N),
3134 MUX(1, 57, 2, N, N, N, N),
3135 MUX(1, 58, 2, N, N, N, N),
3136 MUX(1, 59, 2, N, N, N, N),
3137 MUX(1, 60, 2, N, N, N, N),
3138 MUX(1, 61, 2, N, N, N, N),
3139 MUX(1, 62, 2, N, N, N, N),
3140 MUX(1, 63, 2, N, N, N, N),
3141 MUX(1, 64, 2, N, N, N, N),
3142 MUX(1, 65, 2, N, N, N, N),
3143 MUX(1, 66, 2, N, N, N, N),
3144 MUX(1, 67, 2, N, N, N, N),
3145 MUX(1, 68, 2, N, N, N, N),
3146 MUX(1, 69, 2, N, N, N, N),
3147 MUX(1, 70, 2, N, N, N, N),
3148 MUX(1, 71, 2, N, N, N, N),
3149 MUX(1, 72, 2, N, N, N, N),
3150 MUX(1, 56, 2, N, N, N, N),
3151 MUX(1, 53, 2, N, N, N, N),
3152 MUX(1, 55, 2, N, N, N, N),
3153 };
3154
3155 static struct atlas7_grp_mux lr_lcdrom_grp_mux = {
3156 .pad_mux_count = ARRAY_SIZE(lr_lcdrom_grp_pad_mux),
3157 .pad_mux_list = lr_lcdrom_grp_pad_mux,
3158 };
3159
3160 static struct atlas7_pad_mux lvds_analog_grp_pad_mux[] = {
3161 MUX(1, 149, 8, N, N, N, N),
3162 MUX(1, 150, 8, N, N, N, N),
3163 MUX(1, 151, 8, N, N, N, N),
3164 MUX(1, 152, 8, N, N, N, N),
3165 MUX(1, 153, 8, N, N, N, N),
3166 MUX(1, 154, 8, N, N, N, N),
3167 MUX(1, 155, 8, N, N, N, N),
3168 MUX(1, 156, 8, N, N, N, N),
3169 MUX(1, 157, 8, N, N, N, N),
3170 MUX(1, 158, 8, N, N, N, N),
3171 };
3172
3173 static struct atlas7_grp_mux lvds_analog_grp_mux = {
3174 .pad_mux_count = ARRAY_SIZE(lvds_analog_grp_pad_mux),
3175 .pad_mux_list = lvds_analog_grp_pad_mux,
3176 };
3177
3178 static struct atlas7_pad_mux nd_df_basic_grp_pad_mux[] = {
3179 MUX(1, 44, 1, N, N, N, N),
3180 MUX(1, 43, 1, N, N, N, N),
3181 MUX(1, 42, 1, N, N, N, N),
3182 MUX(1, 41, 1, N, N, N, N),
3183 MUX(1, 40, 1, N, N, N, N),
3184 MUX(1, 39, 1, N, N, N, N),
3185 MUX(1, 38, 1, N, N, N, N),
3186 MUX(1, 37, 1, N, N, N, N),
3187 MUX(1, 47, 1, N, N, N, N),
3188 MUX(1, 46, 1, N, N, N, N),
3189 MUX(1, 52, 1, N, N, N, N),
3190 MUX(1, 45, 1, N, N, N, N),
3191 MUX(1, 49, 1, N, N, N, N),
3192 MUX(1, 50, 1, N, N, N, N),
3193 MUX(1, 48, 1, N, N, N, N),
3194 };
3195
3196 static struct atlas7_grp_mux nd_df_basic_grp_mux = {
3197 .pad_mux_count = ARRAY_SIZE(nd_df_basic_grp_pad_mux),
3198 .pad_mux_list = nd_df_basic_grp_pad_mux,
3199 };
3200
3201 static struct atlas7_pad_mux nd_df_wp_grp_pad_mux[] = {
3202 MUX(1, 124, 4, N, N, N, N),
3203 };
3204
3205 static struct atlas7_grp_mux nd_df_wp_grp_mux = {
3206 .pad_mux_count = ARRAY_SIZE(nd_df_wp_grp_pad_mux),
3207 .pad_mux_list = nd_df_wp_grp_pad_mux,
3208 };
3209
3210 static struct atlas7_pad_mux nd_df_cs_grp_pad_mux[] = {
3211 MUX(1, 51, 1, N, N, N, N),
3212 };
3213
3214 static struct atlas7_grp_mux nd_df_cs_grp_mux = {
3215 .pad_mux_count = ARRAY_SIZE(nd_df_cs_grp_pad_mux),
3216 .pad_mux_list = nd_df_cs_grp_pad_mux,
3217 };
3218
3219 static struct atlas7_pad_mux ps_grp_pad_mux[] = {
3220 MUX(1, 120, 2, N, N, N, N),
3221 MUX(1, 119, 2, N, N, N, N),
3222 MUX(1, 121, 5, N, N, N, N),
3223 };
3224
3225 static struct atlas7_grp_mux ps_grp_mux = {
3226 .pad_mux_count = ARRAY_SIZE(ps_grp_pad_mux),
3227 .pad_mux_list = ps_grp_pad_mux,
3228 };
3229
3230 static struct atlas7_pad_mux ps_no_dir_grp_pad_mux[] = {
3231 MUX(1, 119, 2, N, N, N, N),
3232 };
3233
3234 static struct atlas7_grp_mux ps_no_dir_grp_mux = {
3235 .pad_mux_count = ARRAY_SIZE(ps_no_dir_grp_pad_mux),
3236 .pad_mux_list = ps_no_dir_grp_pad_mux,
3237 };
3238
3239 static struct atlas7_pad_mux pwc_core_on_grp_pad_mux[] = {
3240 MUX(0, 8, 1, N, N, N, N),
3241 };
3242
3243 static struct atlas7_grp_mux pwc_core_on_grp_mux = {
3244 .pad_mux_count = ARRAY_SIZE(pwc_core_on_grp_pad_mux),
3245 .pad_mux_list = pwc_core_on_grp_pad_mux,
3246 };
3247
3248 static struct atlas7_pad_mux pwc_ext_on_grp_pad_mux[] = {
3249 MUX(0, 6, 1, N, N, N, N),
3250 };
3251
3252 static struct atlas7_grp_mux pwc_ext_on_grp_mux = {
3253 .pad_mux_count = ARRAY_SIZE(pwc_ext_on_grp_pad_mux),
3254 .pad_mux_list = pwc_ext_on_grp_pad_mux,
3255 };
3256
3257 static struct atlas7_pad_mux pwc_gpio3_clk_grp_pad_mux[] = {
3258 MUX(0, 3, 4, N, N, N, N),
3259 };
3260
3261 static struct atlas7_grp_mux pwc_gpio3_clk_grp_mux = {
3262 .pad_mux_count = ARRAY_SIZE(pwc_gpio3_clk_grp_pad_mux),
3263 .pad_mux_list = pwc_gpio3_clk_grp_pad_mux,
3264 };
3265
3266 static struct atlas7_pad_mux pwc_io_on_grp_pad_mux[] = {
3267 MUX(0, 9, 1, N, N, N, N),
3268 };
3269
3270 static struct atlas7_grp_mux pwc_io_on_grp_mux = {
3271 .pad_mux_count = ARRAY_SIZE(pwc_io_on_grp_pad_mux),
3272 .pad_mux_list = pwc_io_on_grp_pad_mux,
3273 };
3274
3275 static struct atlas7_pad_mux pwc_lowbatt_b_grp0_pad_mux[] = {
3276 MUX(0, 4, 1, 0xa08, 4, 0xa88, 4),
3277 };
3278
3279 static struct atlas7_grp_mux pwc_lowbatt_b_grp0_mux = {
3280 .pad_mux_count = ARRAY_SIZE(pwc_lowbatt_b_grp0_pad_mux),
3281 .pad_mux_list = pwc_lowbatt_b_grp0_pad_mux,
3282 };
3283
3284 static struct atlas7_pad_mux pwc_mem_on_grp_pad_mux[] = {
3285 MUX(0, 7, 1, N, N, N, N),
3286 };
3287
3288 static struct atlas7_grp_mux pwc_mem_on_grp_mux = {
3289 .pad_mux_count = ARRAY_SIZE(pwc_mem_on_grp_pad_mux),
3290 .pad_mux_list = pwc_mem_on_grp_pad_mux,
3291 };
3292
3293 static struct atlas7_pad_mux pwc_on_key_b_grp0_pad_mux[] = {
3294 MUX(0, 5, 1, 0xa08, 5, 0xa88, 5),
3295 };
3296
3297 static struct atlas7_grp_mux pwc_on_key_b_grp0_mux = {
3298 .pad_mux_count = ARRAY_SIZE(pwc_on_key_b_grp0_pad_mux),
3299 .pad_mux_list = pwc_on_key_b_grp0_pad_mux,
3300 };
3301
3302 static struct atlas7_pad_mux pwc_wakeup_src0_grp_pad_mux[] = {
3303 MUX(0, 0, 1, N, N, N, N),
3304 };
3305
3306 static struct atlas7_grp_mux pwc_wakeup_src0_grp_mux = {
3307 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src0_grp_pad_mux),
3308 .pad_mux_list = pwc_wakeup_src0_grp_pad_mux,
3309 };
3310
3311 static struct atlas7_pad_mux pwc_wakeup_src1_grp_pad_mux[] = {
3312 MUX(0, 1, 1, N, N, N, N),
3313 };
3314
3315 static struct atlas7_grp_mux pwc_wakeup_src1_grp_mux = {
3316 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src1_grp_pad_mux),
3317 .pad_mux_list = pwc_wakeup_src1_grp_pad_mux,
3318 };
3319
3320 static struct atlas7_pad_mux pwc_wakeup_src2_grp_pad_mux[] = {
3321 MUX(0, 2, 1, N, N, N, N),
3322 };
3323
3324 static struct atlas7_grp_mux pwc_wakeup_src2_grp_mux = {
3325 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src2_grp_pad_mux),
3326 .pad_mux_list = pwc_wakeup_src2_grp_pad_mux,
3327 };
3328
3329 static struct atlas7_pad_mux pwc_wakeup_src3_grp_pad_mux[] = {
3330 MUX(0, 3, 1, N, N, N, N),
3331 };
3332
3333 static struct atlas7_grp_mux pwc_wakeup_src3_grp_mux = {
3334 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src3_grp_pad_mux),
3335 .pad_mux_list = pwc_wakeup_src3_grp_pad_mux,
3336 };
3337
3338 static struct atlas7_pad_mux pw_cko0_grp0_pad_mux[] = {
3339 MUX(1, 123, 3, N, N, N, N),
3340 };
3341
3342 static struct atlas7_grp_mux pw_cko0_grp0_mux = {
3343 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp0_pad_mux),
3344 .pad_mux_list = pw_cko0_grp0_pad_mux,
3345 };
3346
3347 static struct atlas7_pad_mux pw_cko0_grp1_pad_mux[] = {
3348 MUX(1, 101, 4, N, N, N, N),
3349 };
3350
3351 static struct atlas7_grp_mux pw_cko0_grp1_mux = {
3352 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp1_pad_mux),
3353 .pad_mux_list = pw_cko0_grp1_pad_mux,
3354 };
3355
3356 static struct atlas7_pad_mux pw_cko0_grp2_pad_mux[] = {
3357 MUX(1, 82, 2, N, N, N, N),
3358 };
3359
3360 static struct atlas7_grp_mux pw_cko0_grp2_mux = {
3361 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp2_pad_mux),
3362 .pad_mux_list = pw_cko0_grp2_pad_mux,
3363 };
3364
3365 static struct atlas7_pad_mux pw_cko0_grp3_pad_mux[] = {
3366 MUX(1, 162, 5, N, N, N, N),
3367 };
3368
3369 static struct atlas7_grp_mux pw_cko0_grp3_mux = {
3370 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp3_pad_mux),
3371 .pad_mux_list = pw_cko0_grp3_pad_mux,
3372 };
3373
3374 static struct atlas7_pad_mux pw_cko1_grp0_pad_mux[] = {
3375 MUX(1, 124, 3, N, N, N, N),
3376 };
3377
3378 static struct atlas7_grp_mux pw_cko1_grp0_mux = {
3379 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp0_pad_mux),
3380 .pad_mux_list = pw_cko1_grp0_pad_mux,
3381 };
3382
3383 static struct atlas7_pad_mux pw_cko1_grp1_pad_mux[] = {
3384 MUX(1, 110, 4, N, N, N, N),
3385 };
3386
3387 static struct atlas7_grp_mux pw_cko1_grp1_mux = {
3388 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp1_pad_mux),
3389 .pad_mux_list = pw_cko1_grp1_pad_mux,
3390 };
3391
3392 static struct atlas7_pad_mux pw_cko1_grp2_pad_mux[] = {
3393 MUX(1, 163, 5, N, N, N, N),
3394 };
3395
3396 static struct atlas7_grp_mux pw_cko1_grp2_mux = {
3397 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp2_pad_mux),
3398 .pad_mux_list = pw_cko1_grp2_pad_mux,
3399 };
3400
3401 static struct atlas7_pad_mux pw_i2s01_clk_grp0_pad_mux[] = {
3402 MUX(1, 125, 3, N, N, N, N),
3403 };
3404
3405 static struct atlas7_grp_mux pw_i2s01_clk_grp0_mux = {
3406 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp0_pad_mux),
3407 .pad_mux_list = pw_i2s01_clk_grp0_pad_mux,
3408 };
3409
3410 static struct atlas7_pad_mux pw_i2s01_clk_grp1_pad_mux[] = {
3411 MUX(1, 117, 3, N, N, N, N),
3412 };
3413
3414 static struct atlas7_grp_mux pw_i2s01_clk_grp1_mux = {
3415 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp1_pad_mux),
3416 .pad_mux_list = pw_i2s01_clk_grp1_pad_mux,
3417 };
3418
3419 static struct atlas7_pad_mux pw_i2s01_clk_grp2_pad_mux[] = {
3420 MUX(1, 132, 2, N, N, N, N),
3421 };
3422
3423 static struct atlas7_grp_mux pw_i2s01_clk_grp2_mux = {
3424 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp2_pad_mux),
3425 .pad_mux_list = pw_i2s01_clk_grp2_pad_mux,
3426 };
3427
3428 static struct atlas7_pad_mux pw_pwm0_grp0_pad_mux[] = {
3429 MUX(1, 119, 3, N, N, N, N),
3430 };
3431
3432 static struct atlas7_grp_mux pw_pwm0_grp0_mux = {
3433 .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp0_pad_mux),
3434 .pad_mux_list = pw_pwm0_grp0_pad_mux,
3435 };
3436
3437 static struct atlas7_pad_mux pw_pwm0_grp1_pad_mux[] = {
3438 MUX(1, 159, 5, N, N, N, N),
3439 };
3440
3441 static struct atlas7_grp_mux pw_pwm0_grp1_mux = {
3442 .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp1_pad_mux),
3443 .pad_mux_list = pw_pwm0_grp1_pad_mux,
3444 };
3445
3446 static struct atlas7_pad_mux pw_pwm1_grp0_pad_mux[] = {
3447 MUX(1, 120, 3, N, N, N, N),
3448 };
3449
3450 static struct atlas7_grp_mux pw_pwm1_grp0_mux = {
3451 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp0_pad_mux),
3452 .pad_mux_list = pw_pwm1_grp0_pad_mux,
3453 };
3454
3455 static struct atlas7_pad_mux pw_pwm1_grp1_pad_mux[] = {
3456 MUX(1, 160, 5, N, N, N, N),
3457 };
3458
3459 static struct atlas7_grp_mux pw_pwm1_grp1_mux = {
3460 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp1_pad_mux),
3461 .pad_mux_list = pw_pwm1_grp1_pad_mux,
3462 };
3463
3464 static struct atlas7_pad_mux pw_pwm1_grp2_pad_mux[] = {
3465 MUX(1, 131, 2, N, N, N, N),
3466 };
3467
3468 static struct atlas7_grp_mux pw_pwm1_grp2_mux = {
3469 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp2_pad_mux),
3470 .pad_mux_list = pw_pwm1_grp2_pad_mux,
3471 };
3472
3473 static struct atlas7_pad_mux pw_pwm2_grp0_pad_mux[] = {
3474 MUX(1, 121, 3, N, N, N, N),
3475 };
3476
3477 static struct atlas7_grp_mux pw_pwm2_grp0_mux = {
3478 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp0_pad_mux),
3479 .pad_mux_list = pw_pwm2_grp0_pad_mux,
3480 };
3481
3482 static struct atlas7_pad_mux pw_pwm2_grp1_pad_mux[] = {
3483 MUX(1, 98, 3, N, N, N, N),
3484 };
3485
3486 static struct atlas7_grp_mux pw_pwm2_grp1_mux = {
3487 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp1_pad_mux),
3488 .pad_mux_list = pw_pwm2_grp1_pad_mux,
3489 };
3490
3491 static struct atlas7_pad_mux pw_pwm2_grp2_pad_mux[] = {
3492 MUX(1, 161, 5, N, N, N, N),
3493 };
3494
3495 static struct atlas7_grp_mux pw_pwm2_grp2_mux = {
3496 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp2_pad_mux),
3497 .pad_mux_list = pw_pwm2_grp2_pad_mux,
3498 };
3499
3500 static struct atlas7_pad_mux pw_pwm3_grp0_pad_mux[] = {
3501 MUX(1, 122, 3, N, N, N, N),
3502 };
3503
3504 static struct atlas7_grp_mux pw_pwm3_grp0_mux = {
3505 .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp0_pad_mux),
3506 .pad_mux_list = pw_pwm3_grp0_pad_mux,
3507 };
3508
3509 static struct atlas7_pad_mux pw_pwm3_grp1_pad_mux[] = {
3510 MUX(1, 73, 4, N, N, N, N),
3511 };
3512
3513 static struct atlas7_grp_mux pw_pwm3_grp1_mux = {
3514 .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp1_pad_mux),
3515 .pad_mux_list = pw_pwm3_grp1_pad_mux,
3516 };
3517
3518 static struct atlas7_pad_mux pw_pwm_cpu_vol_grp0_pad_mux[] = {
3519 MUX(1, 121, 3, N, N, N, N),
3520 };
3521
3522 static struct atlas7_grp_mux pw_pwm_cpu_vol_grp0_mux = {
3523 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp0_pad_mux),
3524 .pad_mux_list = pw_pwm_cpu_vol_grp0_pad_mux,
3525 };
3526
3527 static struct atlas7_pad_mux pw_pwm_cpu_vol_grp1_pad_mux[] = {
3528 MUX(1, 98, 3, N, N, N, N),
3529 };
3530
3531 static struct atlas7_grp_mux pw_pwm_cpu_vol_grp1_mux = {
3532 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp1_pad_mux),
3533 .pad_mux_list = pw_pwm_cpu_vol_grp1_pad_mux,
3534 };
3535
3536 static struct atlas7_pad_mux pw_pwm_cpu_vol_grp2_pad_mux[] = {
3537 MUX(1, 161, 5, N, N, N, N),
3538 };
3539
3540 static struct atlas7_grp_mux pw_pwm_cpu_vol_grp2_mux = {
3541 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp2_pad_mux),
3542 .pad_mux_list = pw_pwm_cpu_vol_grp2_pad_mux,
3543 };
3544
3545 static struct atlas7_pad_mux pw_backlight_grp0_pad_mux[] = {
3546 MUX(1, 122, 3, N, N, N, N),
3547 };
3548
3549 static struct atlas7_grp_mux pw_backlight_grp0_mux = {
3550 .pad_mux_count = ARRAY_SIZE(pw_backlight_grp0_pad_mux),
3551 .pad_mux_list = pw_backlight_grp0_pad_mux,
3552 };
3553
3554 static struct atlas7_pad_mux pw_backlight_grp1_pad_mux[] = {
3555 MUX(1, 73, 4, N, N, N, N),
3556 };
3557
3558 static struct atlas7_grp_mux pw_backlight_grp1_mux = {
3559 .pad_mux_count = ARRAY_SIZE(pw_backlight_grp1_pad_mux),
3560 .pad_mux_list = pw_backlight_grp1_pad_mux,
3561 };
3562
3563 static struct atlas7_pad_mux rg_eth_mac_grp_pad_mux[] = {
3564 MUX(1, 108, 1, N, N, N, N),
3565 MUX(1, 103, 1, N, N, N, N),
3566 MUX(1, 104, 1, N, N, N, N),
3567 MUX(1, 105, 1, N, N, N, N),
3568 MUX(1, 106, 1, N, N, N, N),
3569 MUX(1, 107, 1, N, N, N, N),
3570 MUX(1, 102, 1, N, N, N, N),
3571 MUX(1, 97, 1, N, N, N, N),
3572 MUX(1, 98, 1, N, N, N, N),
3573 MUX(1, 99, 1, N, N, N, N),
3574 MUX(1, 100, 1, N, N, N, N),
3575 MUX(1, 101, 1, N, N, N, N),
3576 };
3577
3578 static struct atlas7_grp_mux rg_eth_mac_grp_mux = {
3579 .pad_mux_count = ARRAY_SIZE(rg_eth_mac_grp_pad_mux),
3580 .pad_mux_list = rg_eth_mac_grp_pad_mux,
3581 };
3582
3583 static struct atlas7_pad_mux rg_gmac_phy_intr_n_grp_pad_mux[] = {
3584 MUX(1, 111, 1, 0xa08, 13, 0xa88, 13),
3585 };
3586
3587 static struct atlas7_grp_mux rg_gmac_phy_intr_n_grp_mux = {
3588 .pad_mux_count = ARRAY_SIZE(rg_gmac_phy_intr_n_grp_pad_mux),
3589 .pad_mux_list = rg_gmac_phy_intr_n_grp_pad_mux,
3590 };
3591
3592 static struct atlas7_pad_mux rg_rgmii_mac_grp_pad_mux[] = {
3593 MUX(1, 109, 1, N, N, N, N),
3594 MUX(1, 110, 1, N, N, N, N),
3595 };
3596
3597 static struct atlas7_grp_mux rg_rgmii_mac_grp_mux = {
3598 .pad_mux_count = ARRAY_SIZE(rg_rgmii_mac_grp_pad_mux),
3599 .pad_mux_list = rg_rgmii_mac_grp_pad_mux,
3600 };
3601
3602 static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp0_pad_mux[] = {
3603 MUX(1, 111, 5, N, N, N, N),
3604 };
3605
3606 static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp0_mux = {
3607 .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp0_pad_mux),
3608 .pad_mux_list = rg_rgmii_phy_ref_clk_grp0_pad_mux,
3609 };
3610
3611 static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp1_pad_mux[] = {
3612 MUX(1, 53, 4, N, N, N, N),
3613 };
3614
3615 static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp1_mux = {
3616 .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp1_pad_mux),
3617 .pad_mux_list = rg_rgmii_phy_ref_clk_grp1_pad_mux,
3618 };
3619
3620 static struct atlas7_pad_mux sd0_grp_pad_mux[] = {
3621 MUX(1, 46, 2, N, N, N, N),
3622 MUX(1, 47, 2, N, N, N, N),
3623 MUX(1, 44, 2, N, N, N, N),
3624 MUX(1, 43, 2, N, N, N, N),
3625 MUX(1, 42, 2, N, N, N, N),
3626 MUX(1, 41, 2, N, N, N, N),
3627 MUX(1, 40, 2, N, N, N, N),
3628 MUX(1, 39, 2, N, N, N, N),
3629 MUX(1, 38, 2, N, N, N, N),
3630 MUX(1, 37, 2, N, N, N, N),
3631 };
3632
3633 static struct atlas7_grp_mux sd0_grp_mux = {
3634 .pad_mux_count = ARRAY_SIZE(sd0_grp_pad_mux),
3635 .pad_mux_list = sd0_grp_pad_mux,
3636 };
3637
3638 static struct atlas7_pad_mux sd0_4bit_grp_pad_mux[] = {
3639 MUX(1, 46, 2, N, N, N, N),
3640 MUX(1, 47, 2, N, N, N, N),
3641 MUX(1, 44, 2, N, N, N, N),
3642 MUX(1, 43, 2, N, N, N, N),
3643 MUX(1, 42, 2, N, N, N, N),
3644 MUX(1, 41, 2, N, N, N, N),
3645 };
3646
3647 static struct atlas7_grp_mux sd0_4bit_grp_mux = {
3648 .pad_mux_count = ARRAY_SIZE(sd0_4bit_grp_pad_mux),
3649 .pad_mux_list = sd0_4bit_grp_pad_mux,
3650 };
3651
3652 static struct atlas7_pad_mux sd1_grp_pad_mux[] = {
3653 MUX(1, 48, 3, N, N, N, N),
3654 MUX(1, 49, 3, N, N, N, N),
3655 MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
3656 MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
3657 MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
3658 MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
3659 MUX(1, 40, 3, N, N, N, N),
3660 MUX(1, 39, 3, N, N, N, N),
3661 MUX(1, 38, 3, N, N, N, N),
3662 MUX(1, 37, 3, N, N, N, N),
3663 };
3664
3665 static struct atlas7_grp_mux sd1_grp_mux = {
3666 .pad_mux_count = ARRAY_SIZE(sd1_grp_pad_mux),
3667 .pad_mux_list = sd1_grp_pad_mux,
3668 };
3669
3670 static struct atlas7_pad_mux sd1_4bit_grp0_pad_mux[] = {
3671 MUX(1, 48, 3, N, N, N, N),
3672 MUX(1, 49, 3, N, N, N, N),
3673 MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
3674 MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
3675 MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
3676 MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
3677 };
3678
3679 static struct atlas7_grp_mux sd1_4bit_grp0_mux = {
3680 .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp0_pad_mux),
3681 .pad_mux_list = sd1_4bit_grp0_pad_mux,
3682 };
3683
3684 static struct atlas7_pad_mux sd1_4bit_grp1_pad_mux[] = {
3685 MUX(1, 48, 3, N, N, N, N),
3686 MUX(1, 49, 3, N, N, N, N),
3687 MUX(1, 40, 4, 0xa00, 0, 0xa80, 0),
3688 MUX(1, 39, 4, 0xa00, 1, 0xa80, 1),
3689 MUX(1, 38, 4, 0xa00, 2, 0xa80, 2),
3690 MUX(1, 37, 4, 0xa00, 3, 0xa80, 3),
3691 };
3692
3693 static struct atlas7_grp_mux sd1_4bit_grp1_mux = {
3694 .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp1_pad_mux),
3695 .pad_mux_list = sd1_4bit_grp1_pad_mux,
3696 };
3697
3698 static struct atlas7_pad_mux sd2_basic_grp_pad_mux[] = {
3699 MUX(1, 31, 1, N, N, N, N),
3700 MUX(1, 32, 1, N, N, N, N),
3701 MUX(1, 33, 1, N, N, N, N),
3702 MUX(1, 34, 1, N, N, N, N),
3703 MUX(1, 35, 1, N, N, N, N),
3704 MUX(1, 36, 1, N, N, N, N),
3705 };
3706
3707 static struct atlas7_grp_mux sd2_basic_grp_mux = {
3708 .pad_mux_count = ARRAY_SIZE(sd2_basic_grp_pad_mux),
3709 .pad_mux_list = sd2_basic_grp_pad_mux,
3710 };
3711
3712 static struct atlas7_pad_mux sd2_cdb_grp0_pad_mux[] = {
3713 MUX(1, 124, 2, 0xa08, 7, 0xa88, 7),
3714 };
3715
3716 static struct atlas7_grp_mux sd2_cdb_grp0_mux = {
3717 .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp0_pad_mux),
3718 .pad_mux_list = sd2_cdb_grp0_pad_mux,
3719 };
3720
3721 static struct atlas7_pad_mux sd2_cdb_grp1_pad_mux[] = {
3722 MUX(1, 161, 6, 0xa08, 7, 0xa88, 7),
3723 };
3724
3725 static struct atlas7_grp_mux sd2_cdb_grp1_mux = {
3726 .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp1_pad_mux),
3727 .pad_mux_list = sd2_cdb_grp1_pad_mux,
3728 };
3729
3730 static struct atlas7_pad_mux sd2_wpb_grp0_pad_mux[] = {
3731 MUX(1, 123, 2, 0xa10, 6, 0xa90, 6),
3732 };
3733
3734 static struct atlas7_grp_mux sd2_wpb_grp0_mux = {
3735 .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp0_pad_mux),
3736 .pad_mux_list = sd2_wpb_grp0_pad_mux,
3737 };
3738
3739 static struct atlas7_pad_mux sd2_wpb_grp1_pad_mux[] = {
3740 MUX(1, 163, 7, 0xa10, 6, 0xa90, 6),
3741 };
3742
3743 static struct atlas7_grp_mux sd2_wpb_grp1_mux = {
3744 .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp1_pad_mux),
3745 .pad_mux_list = sd2_wpb_grp1_pad_mux,
3746 };
3747
3748 static struct atlas7_pad_mux sd3_9_grp_pad_mux[] = {
3749 MUX(1, 85, 1, N, N, N, N),
3750 MUX(1, 86, 1, N, N, N, N),
3751 MUX(1, 87, 1, N, N, N, N),
3752 MUX(1, 88, 1, N, N, N, N),
3753 MUX(1, 89, 1, N, N, N, N),
3754 MUX(1, 90, 1, N, N, N, N),
3755 };
3756
3757 static struct atlas7_grp_mux sd3_9_grp_mux = {
3758 .pad_mux_count = ARRAY_SIZE(sd3_9_grp_pad_mux),
3759 .pad_mux_list = sd3_9_grp_pad_mux,
3760 };
3761
3762 static struct atlas7_pad_mux sd5_grp_pad_mux[] = {
3763 MUX(1, 91, 1, N, N, N, N),
3764 MUX(1, 92, 1, N, N, N, N),
3765 MUX(1, 93, 1, N, N, N, N),
3766 MUX(1, 94, 1, N, N, N, N),
3767 MUX(1, 95, 1, N, N, N, N),
3768 MUX(1, 96, 1, N, N, N, N),
3769 };
3770
3771 static struct atlas7_grp_mux sd5_grp_mux = {
3772 .pad_mux_count = ARRAY_SIZE(sd5_grp_pad_mux),
3773 .pad_mux_list = sd5_grp_pad_mux,
3774 };
3775
3776 static struct atlas7_pad_mux sd6_grp0_pad_mux[] = {
3777 MUX(1, 79, 4, 0xa00, 27, 0xa80, 27),
3778 MUX(1, 78, 4, 0xa00, 26, 0xa80, 26),
3779 MUX(1, 74, 4, 0xa00, 28, 0xa80, 28),
3780 MUX(1, 75, 4, 0xa00, 29, 0xa80, 29),
3781 MUX(1, 76, 4, 0xa00, 30, 0xa80, 30),
3782 MUX(1, 77, 4, 0xa00, 31, 0xa80, 31),
3783 };
3784
3785 static struct atlas7_grp_mux sd6_grp0_mux = {
3786 .pad_mux_count = ARRAY_SIZE(sd6_grp0_pad_mux),
3787 .pad_mux_list = sd6_grp0_pad_mux,
3788 };
3789
3790 static struct atlas7_pad_mux sd6_grp1_pad_mux[] = {
3791 MUX(1, 101, 3, 0xa00, 27, 0xa80, 27),
3792 MUX(1, 99, 3, 0xa00, 26, 0xa80, 26),
3793 MUX(1, 100, 3, 0xa00, 28, 0xa80, 28),
3794 MUX(1, 110, 3, 0xa00, 29, 0xa80, 29),
3795 MUX(1, 109, 3, 0xa00, 30, 0xa80, 30),
3796 MUX(1, 111, 3, 0xa00, 31, 0xa80, 31),
3797 };
3798
3799 static struct atlas7_grp_mux sd6_grp1_mux = {
3800 .pad_mux_count = ARRAY_SIZE(sd6_grp1_pad_mux),
3801 .pad_mux_list = sd6_grp1_pad_mux,
3802 };
3803
3804 static struct atlas7_pad_mux sp0_ext_ldo_on_grp_pad_mux[] = {
3805 MUX(0, 4, 2, N, N, N, N),
3806 };
3807
3808 static struct atlas7_grp_mux sp0_ext_ldo_on_grp_mux = {
3809 .pad_mux_count = ARRAY_SIZE(sp0_ext_ldo_on_grp_pad_mux),
3810 .pad_mux_list = sp0_ext_ldo_on_grp_pad_mux,
3811 };
3812
3813 static struct atlas7_pad_mux sp0_qspi_grp_pad_mux[] = {
3814 MUX(0, 12, 1, N, N, N, N),
3815 MUX(0, 13, 1, N, N, N, N),
3816 MUX(0, 14, 1, N, N, N, N),
3817 MUX(0, 15, 1, N, N, N, N),
3818 MUX(0, 16, 1, N, N, N, N),
3819 MUX(0, 17, 1, N, N, N, N),
3820 };
3821
3822 static struct atlas7_grp_mux sp0_qspi_grp_mux = {
3823 .pad_mux_count = ARRAY_SIZE(sp0_qspi_grp_pad_mux),
3824 .pad_mux_list = sp0_qspi_grp_pad_mux,
3825 };
3826
3827 static struct atlas7_pad_mux sp1_spi_grp_pad_mux[] = {
3828 MUX(1, 19, 1, N, N, N, N),
3829 MUX(1, 20, 1, N, N, N, N),
3830 MUX(1, 21, 1, N, N, N, N),
3831 MUX(1, 18, 1, N, N, N, N),
3832 };
3833
3834 static struct atlas7_grp_mux sp1_spi_grp_mux = {
3835 .pad_mux_count = ARRAY_SIZE(sp1_spi_grp_pad_mux),
3836 .pad_mux_list = sp1_spi_grp_pad_mux,
3837 };
3838
3839 static struct atlas7_pad_mux tpiu_trace_grp_pad_mux[] = {
3840 MUX(1, 53, 5, N, N, N, N),
3841 MUX(1, 56, 5, N, N, N, N),
3842 MUX(1, 57, 5, N, N, N, N),
3843 MUX(1, 58, 5, N, N, N, N),
3844 MUX(1, 59, 5, N, N, N, N),
3845 MUX(1, 60, 5, N, N, N, N),
3846 MUX(1, 61, 5, N, N, N, N),
3847 MUX(1, 62, 5, N, N, N, N),
3848 MUX(1, 63, 5, N, N, N, N),
3849 MUX(1, 64, 5, N, N, N, N),
3850 MUX(1, 65, 5, N, N, N, N),
3851 MUX(1, 66, 5, N, N, N, N),
3852 MUX(1, 67, 5, N, N, N, N),
3853 MUX(1, 68, 5, N, N, N, N),
3854 MUX(1, 69, 5, N, N, N, N),
3855 MUX(1, 70, 5, N, N, N, N),
3856 MUX(1, 71, 5, N, N, N, N),
3857 MUX(1, 72, 5, N, N, N, N),
3858 };
3859
3860 static struct atlas7_grp_mux tpiu_trace_grp_mux = {
3861 .pad_mux_count = ARRAY_SIZE(tpiu_trace_grp_pad_mux),
3862 .pad_mux_list = tpiu_trace_grp_pad_mux,
3863 };
3864
3865 static struct atlas7_pad_mux uart0_grp_pad_mux[] = {
3866 MUX(1, 121, 4, N, N, N, N),
3867 MUX(1, 120, 4, N, N, N, N),
3868 MUX(1, 134, 1, N, N, N, N),
3869 MUX(1, 133, 1, N, N, N, N),
3870 };
3871
3872 static struct atlas7_grp_mux uart0_grp_mux = {
3873 .pad_mux_count = ARRAY_SIZE(uart0_grp_pad_mux),
3874 .pad_mux_list = uart0_grp_pad_mux,
3875 };
3876
3877 static struct atlas7_pad_mux uart0_nopause_grp_pad_mux[] = {
3878 MUX(1, 134, 1, N, N, N, N),
3879 MUX(1, 133, 1, N, N, N, N),
3880 };
3881
3882 static struct atlas7_grp_mux uart0_nopause_grp_mux = {
3883 .pad_mux_count = ARRAY_SIZE(uart0_nopause_grp_pad_mux),
3884 .pad_mux_list = uart0_nopause_grp_pad_mux,
3885 };
3886
3887 static struct atlas7_pad_mux uart1_grp_pad_mux[] = {
3888 MUX(1, 136, 1, N, N, N, N),
3889 MUX(1, 135, 1, N, N, N, N),
3890 };
3891
3892 static struct atlas7_grp_mux uart1_grp_mux = {
3893 .pad_mux_count = ARRAY_SIZE(uart1_grp_pad_mux),
3894 .pad_mux_list = uart1_grp_pad_mux,
3895 };
3896
3897 static struct atlas7_pad_mux uart2_cts_grp0_pad_mux[] = {
3898 MUX(1, 132, 3, 0xa10, 2, 0xa90, 2),
3899 };
3900
3901 static struct atlas7_grp_mux uart2_cts_grp0_mux = {
3902 .pad_mux_count = ARRAY_SIZE(uart2_cts_grp0_pad_mux),
3903 .pad_mux_list = uart2_cts_grp0_pad_mux,
3904 };
3905
3906 static struct atlas7_pad_mux uart2_cts_grp1_pad_mux[] = {
3907 MUX(1, 162, 2, 0xa10, 2, 0xa90, 2),
3908 };
3909
3910 static struct atlas7_grp_mux uart2_cts_grp1_mux = {
3911 .pad_mux_count = ARRAY_SIZE(uart2_cts_grp1_pad_mux),
3912 .pad_mux_list = uart2_cts_grp1_pad_mux,
3913 };
3914
3915 static struct atlas7_pad_mux uart2_rts_grp0_pad_mux[] = {
3916 MUX(1, 131, 3, N, N, N, N),
3917 };
3918
3919 static struct atlas7_grp_mux uart2_rts_grp0_mux = {
3920 .pad_mux_count = ARRAY_SIZE(uart2_rts_grp0_pad_mux),
3921 .pad_mux_list = uart2_rts_grp0_pad_mux,
3922 };
3923
3924 static struct atlas7_pad_mux uart2_rts_grp1_pad_mux[] = {
3925 MUX(1, 161, 2, N, N, N, N),
3926 };
3927
3928 static struct atlas7_grp_mux uart2_rts_grp1_mux = {
3929 .pad_mux_count = ARRAY_SIZE(uart2_rts_grp1_pad_mux),
3930 .pad_mux_list = uart2_rts_grp1_pad_mux,
3931 };
3932
3933 static struct atlas7_pad_mux uart2_rxd_grp0_pad_mux[] = {
3934 MUX(0, 11, 2, 0xa10, 5, 0xa90, 5),
3935 };
3936
3937 static struct atlas7_grp_mux uart2_rxd_grp0_mux = {
3938 .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp0_pad_mux),
3939 .pad_mux_list = uart2_rxd_grp0_pad_mux,
3940 };
3941
3942 static struct atlas7_pad_mux uart2_rxd_grp1_pad_mux[] = {
3943 MUX(1, 160, 2, 0xa10, 5, 0xa90, 5),
3944 };
3945
3946 static struct atlas7_grp_mux uart2_rxd_grp1_mux = {
3947 .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp1_pad_mux),
3948 .pad_mux_list = uart2_rxd_grp1_pad_mux,
3949 };
3950
3951 static struct atlas7_pad_mux uart2_rxd_grp2_pad_mux[] = {
3952 MUX(1, 130, 3, 0xa10, 5, 0xa90, 5),
3953 };
3954
3955 static struct atlas7_grp_mux uart2_rxd_grp2_mux = {
3956 .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp2_pad_mux),
3957 .pad_mux_list = uart2_rxd_grp2_pad_mux,
3958 };
3959
3960 static struct atlas7_pad_mux uart2_txd_grp0_pad_mux[] = {
3961 MUX(0, 10, 2, N, N, N, N),
3962 };
3963
3964 static struct atlas7_grp_mux uart2_txd_grp0_mux = {
3965 .pad_mux_count = ARRAY_SIZE(uart2_txd_grp0_pad_mux),
3966 .pad_mux_list = uart2_txd_grp0_pad_mux,
3967 };
3968
3969 static struct atlas7_pad_mux uart2_txd_grp1_pad_mux[] = {
3970 MUX(1, 159, 2, N, N, N, N),
3971 };
3972
3973 static struct atlas7_grp_mux uart2_txd_grp1_mux = {
3974 .pad_mux_count = ARRAY_SIZE(uart2_txd_grp1_pad_mux),
3975 .pad_mux_list = uart2_txd_grp1_pad_mux,
3976 };
3977
3978 static struct atlas7_pad_mux uart2_txd_grp2_pad_mux[] = {
3979 MUX(1, 129, 3, N, N, N, N),
3980 };
3981
3982 static struct atlas7_grp_mux uart2_txd_grp2_mux = {
3983 .pad_mux_count = ARRAY_SIZE(uart2_txd_grp2_pad_mux),
3984 .pad_mux_list = uart2_txd_grp2_pad_mux,
3985 };
3986
3987 static struct atlas7_pad_mux uart3_cts_grp0_pad_mux[] = {
3988 MUX(1, 125, 2, 0xa08, 0, 0xa88, 0),
3989 };
3990
3991 static struct atlas7_grp_mux uart3_cts_grp0_mux = {
3992 .pad_mux_count = ARRAY_SIZE(uart3_cts_grp0_pad_mux),
3993 .pad_mux_list = uart3_cts_grp0_pad_mux,
3994 };
3995
3996 static struct atlas7_pad_mux uart3_cts_grp1_pad_mux[] = {
3997 MUX(1, 111, 4, 0xa08, 0, 0xa88, 0),
3998 };
3999
4000 static struct atlas7_grp_mux uart3_cts_grp1_mux = {
4001 .pad_mux_count = ARRAY_SIZE(uart3_cts_grp1_pad_mux),
4002 .pad_mux_list = uart3_cts_grp1_pad_mux,
4003 };
4004
4005 static struct atlas7_pad_mux uart3_cts_grp2_pad_mux[] = {
4006 MUX(1, 140, 2, 0xa08, 0, 0xa88, 0),
4007 };
4008
4009 static struct atlas7_grp_mux uart3_cts_grp2_mux = {
4010 .pad_mux_count = ARRAY_SIZE(uart3_cts_grp2_pad_mux),
4011 .pad_mux_list = uart3_cts_grp2_pad_mux,
4012 };
4013
4014 static struct atlas7_pad_mux uart3_rts_grp0_pad_mux[] = {
4015 MUX(1, 126, 2, N, N, N, N),
4016 };
4017
4018 static struct atlas7_grp_mux uart3_rts_grp0_mux = {
4019 .pad_mux_count = ARRAY_SIZE(uart3_rts_grp0_pad_mux),
4020 .pad_mux_list = uart3_rts_grp0_pad_mux,
4021 };
4022
4023 static struct atlas7_pad_mux uart3_rts_grp1_pad_mux[] = {
4024 MUX(1, 109, 4, N, N, N, N),
4025 };
4026
4027 static struct atlas7_grp_mux uart3_rts_grp1_mux = {
4028 .pad_mux_count = ARRAY_SIZE(uart3_rts_grp1_pad_mux),
4029 .pad_mux_list = uart3_rts_grp1_pad_mux,
4030 };
4031
4032 static struct atlas7_pad_mux uart3_rts_grp2_pad_mux[] = {
4033 MUX(1, 139, 2, N, N, N, N),
4034 };
4035
4036 static struct atlas7_grp_mux uart3_rts_grp2_mux = {
4037 .pad_mux_count = ARRAY_SIZE(uart3_rts_grp2_pad_mux),
4038 .pad_mux_list = uart3_rts_grp2_pad_mux,
4039 };
4040
4041 static struct atlas7_pad_mux uart3_rxd_grp0_pad_mux[] = {
4042 MUX(1, 138, 1, 0xa00, 5, 0xa80, 5),
4043 };
4044
4045 static struct atlas7_grp_mux uart3_rxd_grp0_mux = {
4046 .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp0_pad_mux),
4047 .pad_mux_list = uart3_rxd_grp0_pad_mux,
4048 };
4049
4050 static struct atlas7_pad_mux uart3_rxd_grp1_pad_mux[] = {
4051 MUX(1, 84, 2, 0xa00, 5, 0xa80, 5),
4052 };
4053
4054 static struct atlas7_grp_mux uart3_rxd_grp1_mux = {
4055 .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp1_pad_mux),
4056 .pad_mux_list = uart3_rxd_grp1_pad_mux,
4057 };
4058
4059 static struct atlas7_pad_mux uart3_rxd_grp2_pad_mux[] = {
4060 MUX(1, 162, 3, 0xa00, 5, 0xa80, 5),
4061 };
4062
4063 static struct atlas7_grp_mux uart3_rxd_grp2_mux = {
4064 .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp2_pad_mux),
4065 .pad_mux_list = uart3_rxd_grp2_pad_mux,
4066 };
4067
4068 static struct atlas7_pad_mux uart3_txd_grp0_pad_mux[] = {
4069 MUX(1, 137, 1, N, N, N, N),
4070 };
4071
4072 static struct atlas7_grp_mux uart3_txd_grp0_mux = {
4073 .pad_mux_count = ARRAY_SIZE(uart3_txd_grp0_pad_mux),
4074 .pad_mux_list = uart3_txd_grp0_pad_mux,
4075 };
4076
4077 static struct atlas7_pad_mux uart3_txd_grp1_pad_mux[] = {
4078 MUX(1, 83, 2, N, N, N, N),
4079 };
4080
4081 static struct atlas7_grp_mux uart3_txd_grp1_mux = {
4082 .pad_mux_count = ARRAY_SIZE(uart3_txd_grp1_pad_mux),
4083 .pad_mux_list = uart3_txd_grp1_pad_mux,
4084 };
4085
4086 static struct atlas7_pad_mux uart3_txd_grp2_pad_mux[] = {
4087 MUX(1, 161, 3, N, N, N, N),
4088 };
4089
4090 static struct atlas7_grp_mux uart3_txd_grp2_mux = {
4091 .pad_mux_count = ARRAY_SIZE(uart3_txd_grp2_pad_mux),
4092 .pad_mux_list = uart3_txd_grp2_pad_mux,
4093 };
4094
4095 static struct atlas7_pad_mux uart4_basic_grp_pad_mux[] = {
4096 MUX(1, 140, 1, N, N, N, N),
4097 MUX(1, 139, 1, N, N, N, N),
4098 };
4099
4100 static struct atlas7_grp_mux uart4_basic_grp_mux = {
4101 .pad_mux_count = ARRAY_SIZE(uart4_basic_grp_pad_mux),
4102 .pad_mux_list = uart4_basic_grp_pad_mux,
4103 };
4104
4105 static struct atlas7_pad_mux uart4_cts_grp0_pad_mux[] = {
4106 MUX(1, 122, 4, 0xa08, 1, 0xa88, 1),
4107 };
4108
4109 static struct atlas7_grp_mux uart4_cts_grp0_mux = {
4110 .pad_mux_count = ARRAY_SIZE(uart4_cts_grp0_pad_mux),
4111 .pad_mux_list = uart4_cts_grp0_pad_mux,
4112 };
4113
4114 static struct atlas7_pad_mux uart4_cts_grp1_pad_mux[] = {
4115 MUX(1, 100, 4, 0xa08, 1, 0xa88, 1),
4116 };
4117
4118 static struct atlas7_grp_mux uart4_cts_grp1_mux = {
4119 .pad_mux_count = ARRAY_SIZE(uart4_cts_grp1_pad_mux),
4120 .pad_mux_list = uart4_cts_grp1_pad_mux,
4121 };
4122
4123 static struct atlas7_pad_mux uart4_cts_grp2_pad_mux[] = {
4124 MUX(1, 117, 2, 0xa08, 1, 0xa88, 1),
4125 };
4126
4127 static struct atlas7_grp_mux uart4_cts_grp2_mux = {
4128 .pad_mux_count = ARRAY_SIZE(uart4_cts_grp2_pad_mux),
4129 .pad_mux_list = uart4_cts_grp2_pad_mux,
4130 };
4131
4132 static struct atlas7_pad_mux uart4_rts_grp0_pad_mux[] = {
4133 MUX(1, 123, 4, N, N, N, N),
4134 };
4135
4136 static struct atlas7_grp_mux uart4_rts_grp0_mux = {
4137 .pad_mux_count = ARRAY_SIZE(uart4_rts_grp0_pad_mux),
4138 .pad_mux_list = uart4_rts_grp0_pad_mux,
4139 };
4140
4141 static struct atlas7_pad_mux uart4_rts_grp1_pad_mux[] = {
4142 MUX(1, 99, 4, N, N, N, N),
4143 };
4144
4145 static struct atlas7_grp_mux uart4_rts_grp1_mux = {
4146 .pad_mux_count = ARRAY_SIZE(uart4_rts_grp1_pad_mux),
4147 .pad_mux_list = uart4_rts_grp1_pad_mux,
4148 };
4149
4150 static struct atlas7_pad_mux uart4_rts_grp2_pad_mux[] = {
4151 MUX(1, 116, 2, N, N, N, N),
4152 };
4153
4154 static struct atlas7_grp_mux uart4_rts_grp2_mux = {
4155 .pad_mux_count = ARRAY_SIZE(uart4_rts_grp2_pad_mux),
4156 .pad_mux_list = uart4_rts_grp2_pad_mux,
4157 };
4158
4159 static struct atlas7_pad_mux usb0_drvvbus_grp0_pad_mux[] = {
4160 MUX(1, 51, 2, N, N, N, N),
4161 };
4162
4163 static struct atlas7_grp_mux usb0_drvvbus_grp0_mux = {
4164 .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp0_pad_mux),
4165 .pad_mux_list = usb0_drvvbus_grp0_pad_mux,
4166 };
4167
4168 static struct atlas7_pad_mux usb0_drvvbus_grp1_pad_mux[] = {
4169 MUX(1, 162, 7, N, N, N, N),
4170 };
4171
4172 static struct atlas7_grp_mux usb0_drvvbus_grp1_mux = {
4173 .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp1_pad_mux),
4174 .pad_mux_list = usb0_drvvbus_grp1_pad_mux,
4175 };
4176
4177 static struct atlas7_pad_mux usb1_drvvbus_grp0_pad_mux[] = {
4178 MUX(1, 134, 2, N, N, N, N),
4179 };
4180
4181 static struct atlas7_grp_mux usb1_drvvbus_grp0_mux = {
4182 .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp0_pad_mux),
4183 .pad_mux_list = usb1_drvvbus_grp0_pad_mux,
4184 };
4185
4186 static struct atlas7_pad_mux usb1_drvvbus_grp1_pad_mux[] = {
4187 MUX(1, 163, 2, N, N, N, N),
4188 };
4189
4190 static struct atlas7_grp_mux usb1_drvvbus_grp1_mux = {
4191 .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp1_pad_mux),
4192 .pad_mux_list = usb1_drvvbus_grp1_pad_mux,
4193 };
4194
4195 static struct atlas7_pad_mux visbus_dout_grp_pad_mux[] = {
4196 MUX(1, 57, 6, N, N, N, N),
4197 MUX(1, 58, 6, N, N, N, N),
4198 MUX(1, 59, 6, N, N, N, N),
4199 MUX(1, 60, 6, N, N, N, N),
4200 MUX(1, 61, 6, N, N, N, N),
4201 MUX(1, 62, 6, N, N, N, N),
4202 MUX(1, 63, 6, N, N, N, N),
4203 MUX(1, 64, 6, N, N, N, N),
4204 MUX(1, 65, 6, N, N, N, N),
4205 MUX(1, 66, 6, N, N, N, N),
4206 MUX(1, 67, 6, N, N, N, N),
4207 MUX(1, 68, 6, N, N, N, N),
4208 MUX(1, 69, 6, N, N, N, N),
4209 MUX(1, 70, 6, N, N, N, N),
4210 MUX(1, 71, 6, N, N, N, N),
4211 MUX(1, 72, 6, N, N, N, N),
4212 MUX(1, 53, 6, N, N, N, N),
4213 MUX(1, 54, 6, N, N, N, N),
4214 MUX(1, 55, 6, N, N, N, N),
4215 MUX(1, 56, 6, N, N, N, N),
4216 MUX(1, 85, 6, N, N, N, N),
4217 MUX(1, 86, 6, N, N, N, N),
4218 MUX(1, 87, 6, N, N, N, N),
4219 MUX(1, 88, 6, N, N, N, N),
4220 MUX(1, 89, 6, N, N, N, N),
4221 MUX(1, 90, 6, N, N, N, N),
4222 MUX(1, 91, 6, N, N, N, N),
4223 MUX(1, 92, 6, N, N, N, N),
4224 MUX(1, 93, 6, N, N, N, N),
4225 MUX(1, 94, 6, N, N, N, N),
4226 MUX(1, 95, 6, N, N, N, N),
4227 MUX(1, 96, 6, N, N, N, N),
4228 };
4229
4230 static struct atlas7_grp_mux visbus_dout_grp_mux = {
4231 .pad_mux_count = ARRAY_SIZE(visbus_dout_grp_pad_mux),
4232 .pad_mux_list = visbus_dout_grp_pad_mux,
4233 };
4234
4235 static struct atlas7_pad_mux vi_vip1_grp_pad_mux[] = {
4236 MUX(1, 74, 1, N, N, N, N),
4237 MUX(1, 75, 1, N, N, N, N),
4238 MUX(1, 76, 1, N, N, N, N),
4239 MUX(1, 77, 1, N, N, N, N),
4240 MUX(1, 78, 1, N, N, N, N),
4241 MUX(1, 79, 1, N, N, N, N),
4242 MUX(1, 80, 1, N, N, N, N),
4243 MUX(1, 81, 1, N, N, N, N),
4244 MUX(1, 82, 1, N, N, N, N),
4245 MUX(1, 83, 1, N, N, N, N),
4246 MUX(1, 84, 1, N, N, N, N),
4247 MUX(1, 103, 2, N, N, N, N),
4248 MUX(1, 104, 2, N, N, N, N),
4249 MUX(1, 105, 2, N, N, N, N),
4250 MUX(1, 106, 2, N, N, N, N),
4251 MUX(1, 107, 2, N, N, N, N),
4252 MUX(1, 102, 2, N, N, N, N),
4253 MUX(1, 97, 2, N, N, N, N),
4254 MUX(1, 98, 2, N, N, N, N),
4255 };
4256
4257 static struct atlas7_grp_mux vi_vip1_grp_mux = {
4258 .pad_mux_count = ARRAY_SIZE(vi_vip1_grp_pad_mux),
4259 .pad_mux_list = vi_vip1_grp_pad_mux,
4260 };
4261
4262 static struct atlas7_pad_mux vi_vip1_ext_grp_pad_mux[] = {
4263 MUX(1, 74, 1, N, N, N, N),
4264 MUX(1, 75, 1, N, N, N, N),
4265 MUX(1, 76, 1, N, N, N, N),
4266 MUX(1, 77, 1, N, N, N, N),
4267 MUX(1, 78, 1, N, N, N, N),
4268 MUX(1, 79, 1, N, N, N, N),
4269 MUX(1, 80, 1, N, N, N, N),
4270 MUX(1, 81, 1, N, N, N, N),
4271 MUX(1, 82, 1, N, N, N, N),
4272 MUX(1, 83, 1, N, N, N, N),
4273 MUX(1, 84, 1, N, N, N, N),
4274 MUX(1, 108, 2, N, N, N, N),
4275 MUX(1, 103, 2, N, N, N, N),
4276 MUX(1, 104, 2, N, N, N, N),
4277 MUX(1, 105, 2, N, N, N, N),
4278 MUX(1, 106, 2, N, N, N, N),
4279 MUX(1, 107, 2, N, N, N, N),
4280 MUX(1, 102, 2, N, N, N, N),
4281 MUX(1, 97, 2, N, N, N, N),
4282 MUX(1, 98, 2, N, N, N, N),
4283 MUX(1, 99, 2, N, N, N, N),
4284 MUX(1, 100, 2, N, N, N, N),
4285 };
4286
4287 static struct atlas7_grp_mux vi_vip1_ext_grp_mux = {
4288 .pad_mux_count = ARRAY_SIZE(vi_vip1_ext_grp_pad_mux),
4289 .pad_mux_list = vi_vip1_ext_grp_pad_mux,
4290 };
4291
4292 static struct atlas7_pad_mux vi_vip1_low8bit_grp_pad_mux[] = {
4293 MUX(1, 74, 1, N, N, N, N),
4294 MUX(1, 75, 1, N, N, N, N),
4295 MUX(1, 76, 1, N, N, N, N),
4296 MUX(1, 77, 1, N, N, N, N),
4297 MUX(1, 78, 1, N, N, N, N),
4298 MUX(1, 79, 1, N, N, N, N),
4299 MUX(1, 80, 1, N, N, N, N),
4300 MUX(1, 81, 1, N, N, N, N),
4301 MUX(1, 82, 1, N, N, N, N),
4302 MUX(1, 83, 1, N, N, N, N),
4303 MUX(1, 84, 1, N, N, N, N),
4304 };
4305
4306 static struct atlas7_grp_mux vi_vip1_low8bit_grp_mux = {
4307 .pad_mux_count = ARRAY_SIZE(vi_vip1_low8bit_grp_pad_mux),
4308 .pad_mux_list = vi_vip1_low8bit_grp_pad_mux,
4309 };
4310
4311 static struct atlas7_pad_mux vi_vip1_high8bit_grp_pad_mux[] = {
4312 MUX(1, 82, 1, N, N, N, N),
4313 MUX(1, 83, 1, N, N, N, N),
4314 MUX(1, 84, 1, N, N, N, N),
4315 MUX(1, 103, 2, N, N, N, N),
4316 MUX(1, 104, 2, N, N, N, N),
4317 MUX(1, 105, 2, N, N, N, N),
4318 MUX(1, 106, 2, N, N, N, N),
4319 MUX(1, 107, 2, N, N, N, N),
4320 MUX(1, 102, 2, N, N, N, N),
4321 MUX(1, 97, 2, N, N, N, N),
4322 MUX(1, 98, 2, N, N, N, N),
4323 };
4324
4325 static struct atlas7_grp_mux vi_vip1_high8bit_grp_mux = {
4326 .pad_mux_count = ARRAY_SIZE(vi_vip1_high8bit_grp_pad_mux),
4327 .pad_mux_list = vi_vip1_high8bit_grp_pad_mux,
4328 };
4329
4330 static struct atlas7_pmx_func atlas7_pmx_functions[] = {
4331 FUNCTION("gnss_gpio", gnss_gpio_grp, &gnss_gpio_grp_mux),
4332 FUNCTION("lcd_vip_gpio", lcd_vip_gpio_grp, &lcd_vip_gpio_grp_mux),
4333 FUNCTION("sdio_i2s_gpio", sdio_i2s_gpio_grp, &sdio_i2s_gpio_grp_mux),
4334 FUNCTION("sp_rgmii_gpio", sp_rgmii_gpio_grp, &sp_rgmii_gpio_grp_mux),
4335 FUNCTION("lvds_gpio", lvds_gpio_grp, &lvds_gpio_grp_mux),
4336 FUNCTION("jtag_uart_nand_gpio",
4337 jtag_uart_nand_gpio_grp,
4338 &jtag_uart_nand_gpio_grp_mux),
4339 FUNCTION("rtc_gpio", rtc_gpio_grp, &rtc_gpio_grp_mux),
4340 FUNCTION("audio_ac97", audio_ac97_grp, &audio_ac97_grp_mux),
4341 FUNCTION("audio_digmic_m0",
4342 audio_digmic_grp0,
4343 &audio_digmic_grp0_mux),
4344 FUNCTION("audio_digmic_m1",
4345 audio_digmic_grp1,
4346 &audio_digmic_grp1_mux),
4347 FUNCTION("audio_digmic_m2",
4348 audio_digmic_grp2,
4349 &audio_digmic_grp2_mux),
4350 FUNCTION("audio_func_dbg",
4351 audio_func_dbg_grp,
4352 &audio_func_dbg_grp_mux),
4353 FUNCTION("audio_i2s", audio_i2s_grp, &audio_i2s_grp_mux),
4354 FUNCTION("audio_i2s_2ch", audio_i2s_2ch_grp, &audio_i2s_2ch_grp_mux),
4355 FUNCTION("audio_i2s_extclk",
4356 audio_i2s_extclk_grp,
4357 &audio_i2s_extclk_grp_mux),
4358 FUNCTION("audio_spdif_out_m0",
4359 audio_spdif_out_grp0,
4360 &audio_spdif_out_grp0_mux),
4361 FUNCTION("audio_spdif_out_m1",
4362 audio_spdif_out_grp1,
4363 &audio_spdif_out_grp1_mux),
4364 FUNCTION("audio_spdif_out_m2",
4365 audio_spdif_out_grp2,
4366 &audio_spdif_out_grp2_mux),
4367 FUNCTION("audio_uart0_basic",
4368 audio_uart0_basic_grp,
4369 &audio_uart0_basic_grp_mux),
4370 FUNCTION("audio_uart0_urfs_m0",
4371 audio_uart0_urfs_grp0,
4372 &audio_uart0_urfs_grp0_mux),
4373 FUNCTION("audio_uart0_urfs_m1",
4374 audio_uart0_urfs_grp1,
4375 &audio_uart0_urfs_grp1_mux),
4376 FUNCTION("audio_uart0_urfs_m2",
4377 audio_uart0_urfs_grp2,
4378 &audio_uart0_urfs_grp2_mux),
4379 FUNCTION("audio_uart0_urfs_m3",
4380 audio_uart0_urfs_grp3,
4381 &audio_uart0_urfs_grp3_mux),
4382 FUNCTION("audio_uart1_basic",
4383 audio_uart1_basic_grp,
4384 &audio_uart1_basic_grp_mux),
4385 FUNCTION("audio_uart1_urfs_m0",
4386 audio_uart1_urfs_grp0,
4387 &audio_uart1_urfs_grp0_mux),
4388 FUNCTION("audio_uart1_urfs_m1",
4389 audio_uart1_urfs_grp1,
4390 &audio_uart1_urfs_grp1_mux),
4391 FUNCTION("audio_uart1_urfs_m2",
4392 audio_uart1_urfs_grp2,
4393 &audio_uart1_urfs_grp2_mux),
4394 FUNCTION("audio_uart2_urfs_m0",
4395 audio_uart2_urfs_grp0,
4396 &audio_uart2_urfs_grp0_mux),
4397 FUNCTION("audio_uart2_urfs_m1",
4398 audio_uart2_urfs_grp1,
4399 &audio_uart2_urfs_grp1_mux),
4400 FUNCTION("audio_uart2_urfs_m2",
4401 audio_uart2_urfs_grp2,
4402 &audio_uart2_urfs_grp2_mux),
4403 FUNCTION("audio_uart2_urxd_m0",
4404 audio_uart2_urxd_grp0,
4405 &audio_uart2_urxd_grp0_mux),
4406 FUNCTION("audio_uart2_urxd_m1",
4407 audio_uart2_urxd_grp1,
4408 &audio_uart2_urxd_grp1_mux),
4409 FUNCTION("audio_uart2_urxd_m2",
4410 audio_uart2_urxd_grp2,
4411 &audio_uart2_urxd_grp2_mux),
4412 FUNCTION("audio_uart2_usclk_m0",
4413 audio_uart2_usclk_grp0,
4414 &audio_uart2_usclk_grp0_mux),
4415 FUNCTION("audio_uart2_usclk_m1",
4416 audio_uart2_usclk_grp1,
4417 &audio_uart2_usclk_grp1_mux),
4418 FUNCTION("audio_uart2_usclk_m2",
4419 audio_uart2_usclk_grp2,
4420 &audio_uart2_usclk_grp2_mux),
4421 FUNCTION("audio_uart2_utfs_m0",
4422 audio_uart2_utfs_grp0,
4423 &audio_uart2_utfs_grp0_mux),
4424 FUNCTION("audio_uart2_utfs_m1",
4425 audio_uart2_utfs_grp1,
4426 &audio_uart2_utfs_grp1_mux),
4427 FUNCTION("audio_uart2_utfs_m2",
4428 audio_uart2_utfs_grp2,
4429 &audio_uart2_utfs_grp2_mux),
4430 FUNCTION("audio_uart2_utxd_m0",
4431 audio_uart2_utxd_grp0,
4432 &audio_uart2_utxd_grp0_mux),
4433 FUNCTION("audio_uart2_utxd_m1",
4434 audio_uart2_utxd_grp1,
4435 &audio_uart2_utxd_grp1_mux),
4436 FUNCTION("audio_uart2_utxd_m2",
4437 audio_uart2_utxd_grp2,
4438 &audio_uart2_utxd_grp2_mux),
4439 FUNCTION("c_can_trnsvr_en_m0",
4440 c_can_trnsvr_en_grp0,
4441 &c_can_trnsvr_en_grp0_mux),
4442 FUNCTION("c_can_trnsvr_en_m1",
4443 c_can_trnsvr_en_grp1,
4444 &c_can_trnsvr_en_grp1_mux),
4445 FUNCTION("c_can_trnsvr_intr",
4446 c_can_trnsvr_intr_grp,
4447 &c_can_trnsvr_intr_grp_mux),
4448 FUNCTION("c_can_trnsvr_stb_n",
4449 c_can_trnsvr_stb_n_grp,
4450 &c_can_trnsvr_stb_n_grp_mux),
4451 FUNCTION("c0_can_rxd_trnsv0",
4452 c0_can_rxd_trnsv0_grp,
4453 &c0_can_rxd_trnsv0_grp_mux),
4454 FUNCTION("c0_can_rxd_trnsv1",
4455 c0_can_rxd_trnsv1_grp,
4456 &c0_can_rxd_trnsv1_grp_mux),
4457 FUNCTION("c0_can_txd_trnsv0",
4458 c0_can_txd_trnsv0_grp,
4459 &c0_can_txd_trnsv0_grp_mux),
4460 FUNCTION("c0_can_txd_trnsv1",
4461 c0_can_txd_trnsv1_grp,
4462 &c0_can_txd_trnsv1_grp_mux),
4463 FUNCTION("c1_can_rxd_m0", c1_can_rxd_grp0, &c1_can_rxd_grp0_mux),
4464 FUNCTION("c1_can_rxd_m1", c1_can_rxd_grp1, &c1_can_rxd_grp1_mux),
4465 FUNCTION("c1_can_rxd_m2", c1_can_rxd_grp2, &c1_can_rxd_grp2_mux),
4466 FUNCTION("c1_can_rxd_m3", c1_can_rxd_grp3, &c1_can_rxd_grp3_mux),
4467 FUNCTION("c1_can_txd_m0", c1_can_txd_grp0, &c1_can_txd_grp0_mux),
4468 FUNCTION("c1_can_txd_m1", c1_can_txd_grp1, &c1_can_txd_grp1_mux),
4469 FUNCTION("c1_can_txd_m2", c1_can_txd_grp2, &c1_can_txd_grp2_mux),
4470 FUNCTION("c1_can_txd_m3", c1_can_txd_grp3, &c1_can_txd_grp3_mux),
4471 FUNCTION("ca_audio_lpc", ca_audio_lpc_grp, &ca_audio_lpc_grp_mux),
4472 FUNCTION("ca_bt_lpc", ca_bt_lpc_grp, &ca_bt_lpc_grp_mux),
4473 FUNCTION("ca_coex", ca_coex_grp, &ca_coex_grp_mux),
4474 FUNCTION("ca_curator_lpc",
4475 ca_curator_lpc_grp,
4476 &ca_curator_lpc_grp_mux),
4477 FUNCTION("ca_pcm_debug", ca_pcm_debug_grp, &ca_pcm_debug_grp_mux),
4478 FUNCTION("ca_pio", ca_pio_grp, &ca_pio_grp_mux),
4479 FUNCTION("ca_sdio_debug", ca_sdio_debug_grp, &ca_sdio_debug_grp_mux),
4480 FUNCTION("ca_spi", ca_spi_grp, &ca_spi_grp_mux),
4481 FUNCTION("ca_trb", ca_trb_grp, &ca_trb_grp_mux),
4482 FUNCTION("ca_uart_debug", ca_uart_debug_grp, &ca_uart_debug_grp_mux),
4483 FUNCTION("clkc_m0", clkc_grp0, &clkc_grp0_mux),
4484 FUNCTION("clkc_m1", clkc_grp1, &clkc_grp1_mux),
4485 FUNCTION("gn_gnss_i2c", gn_gnss_i2c_grp, &gn_gnss_i2c_grp_mux),
4486 FUNCTION("gn_gnss_uart_nopause",
4487 gn_gnss_uart_nopause_grp,
4488 &gn_gnss_uart_nopause_grp_mux),
4489 FUNCTION("gn_gnss_uart", gn_gnss_uart_grp, &gn_gnss_uart_grp_mux),
4490 FUNCTION("gn_trg_spi_m0", gn_trg_spi_grp0, &gn_trg_spi_grp0_mux),
4491 FUNCTION("gn_trg_spi_m1", gn_trg_spi_grp1, &gn_trg_spi_grp1_mux),
4492 FUNCTION("cvbs_dbg", cvbs_dbg_grp, &cvbs_dbg_grp_mux),
4493 FUNCTION("cvbs_dbg_test_m0",
4494 cvbs_dbg_test_grp0,
4495 &cvbs_dbg_test_grp0_mux),
4496 FUNCTION("cvbs_dbg_test_m1",
4497 cvbs_dbg_test_grp1,
4498 &cvbs_dbg_test_grp1_mux),
4499 FUNCTION("cvbs_dbg_test_m2",
4500 cvbs_dbg_test_grp2,
4501 &cvbs_dbg_test_grp2_mux),
4502 FUNCTION("cvbs_dbg_test_m3",
4503 cvbs_dbg_test_grp3,
4504 &cvbs_dbg_test_grp3_mux),
4505 FUNCTION("cvbs_dbg_test_m4",
4506 cvbs_dbg_test_grp4,
4507 &cvbs_dbg_test_grp4_mux),
4508 FUNCTION("cvbs_dbg_test_m5",
4509 cvbs_dbg_test_grp5,
4510 &cvbs_dbg_test_grp5_mux),
4511 FUNCTION("cvbs_dbg_test_m6",
4512 cvbs_dbg_test_grp6,
4513 &cvbs_dbg_test_grp6_mux),
4514 FUNCTION("cvbs_dbg_test_m7",
4515 cvbs_dbg_test_grp7,
4516 &cvbs_dbg_test_grp7_mux),
4517 FUNCTION("cvbs_dbg_test_m8",
4518 cvbs_dbg_test_grp8,
4519 &cvbs_dbg_test_grp8_mux),
4520 FUNCTION("cvbs_dbg_test_m9",
4521 cvbs_dbg_test_grp9,
4522 &cvbs_dbg_test_grp9_mux),
4523 FUNCTION("cvbs_dbg_test_m10",
4524 cvbs_dbg_test_grp10,
4525 &cvbs_dbg_test_grp10_mux),
4526 FUNCTION("cvbs_dbg_test_m11",
4527 cvbs_dbg_test_grp11,
4528 &cvbs_dbg_test_grp11_mux),
4529 FUNCTION("cvbs_dbg_test_m12",
4530 cvbs_dbg_test_grp12,
4531 &cvbs_dbg_test_grp12_mux),
4532 FUNCTION("cvbs_dbg_test_m13",
4533 cvbs_dbg_test_grp13,
4534 &cvbs_dbg_test_grp13_mux),
4535 FUNCTION("cvbs_dbg_test_m14",
4536 cvbs_dbg_test_grp14,
4537 &cvbs_dbg_test_grp14_mux),
4538 FUNCTION("cvbs_dbg_test_m15",
4539 cvbs_dbg_test_grp15,
4540 &cvbs_dbg_test_grp15_mux),
4541 FUNCTION("gn_gnss_power", gn_gnss_power_grp, &gn_gnss_power_grp_mux),
4542 FUNCTION("gn_gnss_sw_status",
4543 gn_gnss_sw_status_grp,
4544 &gn_gnss_sw_status_grp_mux),
4545 FUNCTION("gn_gnss_eclk", gn_gnss_eclk_grp, &gn_gnss_eclk_grp_mux),
4546 FUNCTION("gn_gnss_irq1_m0",
4547 gn_gnss_irq1_grp0,
4548 &gn_gnss_irq1_grp0_mux),
4549 FUNCTION("gn_gnss_irq2_m0",
4550 gn_gnss_irq2_grp0,
4551 &gn_gnss_irq2_grp0_mux),
4552 FUNCTION("gn_gnss_tm", gn_gnss_tm_grp, &gn_gnss_tm_grp_mux),
4553 FUNCTION("gn_gnss_tsync", gn_gnss_tsync_grp, &gn_gnss_tsync_grp_mux),
4554 FUNCTION("gn_io_gnsssys_sw_cfg",
4555 gn_io_gnsssys_sw_cfg_grp,
4556 &gn_io_gnsssys_sw_cfg_grp_mux),
4557 FUNCTION("gn_trg_m0", gn_trg_grp0, &gn_trg_grp0_mux),
4558 FUNCTION("gn_trg_m1", gn_trg_grp1, &gn_trg_grp1_mux),
4559 FUNCTION("gn_trg_shutdown_m0",
4560 gn_trg_shutdown_grp0,
4561 &gn_trg_shutdown_grp0_mux),
4562 FUNCTION("gn_trg_shutdown_m1",
4563 gn_trg_shutdown_grp1,
4564 &gn_trg_shutdown_grp1_mux),
4565 FUNCTION("gn_trg_shutdown_m2",
4566 gn_trg_shutdown_grp2,
4567 &gn_trg_shutdown_grp2_mux),
4568 FUNCTION("gn_trg_shutdown_m3",
4569 gn_trg_shutdown_grp3,
4570 &gn_trg_shutdown_grp3_mux),
4571 FUNCTION("i2c0", i2c0_grp, &i2c0_grp_mux),
4572 FUNCTION("i2c1", i2c1_grp, &i2c1_grp_mux),
4573 FUNCTION("i2s0", i2s0_grp, &i2s0_grp_mux),
4574 FUNCTION("i2s1_basic", i2s1_basic_grp, &i2s1_basic_grp_mux),
4575 FUNCTION("i2s1_rxd0_m0", i2s1_rxd0_grp0, &i2s1_rxd0_grp0_mux),
4576 FUNCTION("i2s1_rxd0_m1", i2s1_rxd0_grp1, &i2s1_rxd0_grp1_mux),
4577 FUNCTION("i2s1_rxd0_m2", i2s1_rxd0_grp2, &i2s1_rxd0_grp2_mux),
4578 FUNCTION("i2s1_rxd0_m3", i2s1_rxd0_grp3, &i2s1_rxd0_grp3_mux),
4579 FUNCTION("i2s1_rxd0_m4", i2s1_rxd0_grp4, &i2s1_rxd0_grp4_mux),
4580 FUNCTION("i2s1_rxd1_m0", i2s1_rxd1_grp0, &i2s1_rxd1_grp0_mux),
4581 FUNCTION("i2s1_rxd1_m1", i2s1_rxd1_grp1, &i2s1_rxd1_grp1_mux),
4582 FUNCTION("i2s1_rxd1_m2", i2s1_rxd1_grp2, &i2s1_rxd1_grp2_mux),
4583 FUNCTION("i2s1_rxd1_m3", i2s1_rxd1_grp3, &i2s1_rxd1_grp3_mux),
4584 FUNCTION("i2s1_rxd1_m4", i2s1_rxd1_grp4, &i2s1_rxd1_grp4_mux),
4585 FUNCTION("jtag_jt_dbg_nsrst",
4586 jtag_jt_dbg_nsrst_grp,
4587 &jtag_jt_dbg_nsrst_grp_mux),
4588 FUNCTION("jtag_ntrst_m0", jtag_ntrst_grp0, &jtag_ntrst_grp0_mux),
4589 FUNCTION("jtag_ntrst_m1", jtag_ntrst_grp1, &jtag_ntrst_grp1_mux),
4590 FUNCTION("jtag_swdiotms_m0",
4591 jtag_swdiotms_grp0,
4592 &jtag_swdiotms_grp0_mux),
4593 FUNCTION("jtag_swdiotms_m1",
4594 jtag_swdiotms_grp1,
4595 &jtag_swdiotms_grp1_mux),
4596 FUNCTION("jtag_tck_m0", jtag_tck_grp0, &jtag_tck_grp0_mux),
4597 FUNCTION("jtag_tck_m1", jtag_tck_grp1, &jtag_tck_grp1_mux),
4598 FUNCTION("jtag_tdi_m0", jtag_tdi_grp0, &jtag_tdi_grp0_mux),
4599 FUNCTION("jtag_tdi_m1", jtag_tdi_grp1, &jtag_tdi_grp1_mux),
4600 FUNCTION("jtag_tdo_m0", jtag_tdo_grp0, &jtag_tdo_grp0_mux),
4601 FUNCTION("jtag_tdo_m1", jtag_tdo_grp1, &jtag_tdo_grp1_mux),
4602 FUNCTION("ks_kas_spi_m0", ks_kas_spi_grp0, &ks_kas_spi_grp0_mux),
4603 FUNCTION("ld_ldd", ld_ldd_grp, &ld_ldd_grp_mux),
4604 FUNCTION("ld_ldd_16bit", ld_ldd_16bit_grp, &ld_ldd_16bit_grp_mux),
4605 FUNCTION("ld_ldd_fck", ld_ldd_fck_grp, &ld_ldd_fck_grp_mux),
4606 FUNCTION("ld_ldd_lck", ld_ldd_lck_grp, &ld_ldd_lck_grp_mux),
4607 FUNCTION("lr_lcdrom", lr_lcdrom_grp, &lr_lcdrom_grp_mux),
4608 FUNCTION("lvds_analog", lvds_analog_grp, &lvds_analog_grp_mux),
4609 FUNCTION("nd_df_basic", nd_df_basic_grp, &nd_df_basic_grp_mux),
4610 FUNCTION("nd_df_wp", nd_df_wp_grp, &nd_df_wp_grp_mux),
4611 FUNCTION("nd_df_cs", nd_df_cs_grp, &nd_df_cs_grp_mux),
4612 FUNCTION("ps", ps_grp, &ps_grp_mux),
4613 FUNCTION("ps_no_dir", ps_no_dir_grp, &ps_no_dir_grp_mux),
4614 FUNCTION("pwc_core_on", pwc_core_on_grp, &pwc_core_on_grp_mux),
4615 FUNCTION("pwc_ext_on", pwc_ext_on_grp, &pwc_ext_on_grp_mux),
4616 FUNCTION("pwc_gpio3_clk", pwc_gpio3_clk_grp, &pwc_gpio3_clk_grp_mux),
4617 FUNCTION("pwc_io_on", pwc_io_on_grp, &pwc_io_on_grp_mux),
4618 FUNCTION("pwc_lowbatt_b_m0",
4619 pwc_lowbatt_b_grp0,
4620 &pwc_lowbatt_b_grp0_mux),
4621 FUNCTION("pwc_mem_on", pwc_mem_on_grp, &pwc_mem_on_grp_mux),
4622 FUNCTION("pwc_on_key_b_m0",
4623 pwc_on_key_b_grp0,
4624 &pwc_on_key_b_grp0_mux),
4625 FUNCTION("pwc_wakeup_src0",
4626 pwc_wakeup_src0_grp,
4627 &pwc_wakeup_src0_grp_mux),
4628 FUNCTION("pwc_wakeup_src1",
4629 pwc_wakeup_src1_grp,
4630 &pwc_wakeup_src1_grp_mux),
4631 FUNCTION("pwc_wakeup_src2",
4632 pwc_wakeup_src2_grp,
4633 &pwc_wakeup_src2_grp_mux),
4634 FUNCTION("pwc_wakeup_src3",
4635 pwc_wakeup_src3_grp,
4636 &pwc_wakeup_src3_grp_mux),
4637 FUNCTION("pw_cko0_m0", pw_cko0_grp0, &pw_cko0_grp0_mux),
4638 FUNCTION("pw_cko0_m1", pw_cko0_grp1, &pw_cko0_grp1_mux),
4639 FUNCTION("pw_cko0_m2", pw_cko0_grp2, &pw_cko0_grp2_mux),
4640 FUNCTION("pw_cko0_m3", pw_cko0_grp3, &pw_cko0_grp3_mux),
4641 FUNCTION("pw_cko1_m0", pw_cko1_grp0, &pw_cko1_grp0_mux),
4642 FUNCTION("pw_cko1_m1", pw_cko1_grp1, &pw_cko1_grp1_mux),
4643 FUNCTION("pw_cko1_m2", pw_cko1_grp2, &pw_cko1_grp2_mux),
4644 FUNCTION("pw_i2s01_clk_m0",
4645 pw_i2s01_clk_grp0,
4646 &pw_i2s01_clk_grp0_mux),
4647 FUNCTION("pw_i2s01_clk_m1",
4648 pw_i2s01_clk_grp1,
4649 &pw_i2s01_clk_grp1_mux),
4650 FUNCTION("pw_i2s01_clk_m2",
4651 pw_i2s01_clk_grp2,
4652 &pw_i2s01_clk_grp2_mux),
4653 FUNCTION("pw_pwm0_m0", pw_pwm0_grp0, &pw_pwm0_grp0_mux),
4654 FUNCTION("pw_pwm0_m1", pw_pwm0_grp1, &pw_pwm0_grp1_mux),
4655 FUNCTION("pw_pwm1_m0", pw_pwm1_grp0, &pw_pwm1_grp0_mux),
4656 FUNCTION("pw_pwm1_m1", pw_pwm1_grp1, &pw_pwm1_grp1_mux),
4657 FUNCTION("pw_pwm1_m2", pw_pwm1_grp2, &pw_pwm1_grp2_mux),
4658 FUNCTION("pw_pwm2_m0", pw_pwm2_grp0, &pw_pwm2_grp0_mux),
4659 FUNCTION("pw_pwm2_m1", pw_pwm2_grp1, &pw_pwm2_grp1_mux),
4660 FUNCTION("pw_pwm2_m2", pw_pwm2_grp2, &pw_pwm2_grp2_mux),
4661 FUNCTION("pw_pwm3_m0", pw_pwm3_grp0, &pw_pwm3_grp0_mux),
4662 FUNCTION("pw_pwm3_m1", pw_pwm3_grp1, &pw_pwm3_grp1_mux),
4663 FUNCTION("pw_pwm_cpu_vol_m0",
4664 pw_pwm_cpu_vol_grp0,
4665 &pw_pwm_cpu_vol_grp0_mux),
4666 FUNCTION("pw_pwm_cpu_vol_m1",
4667 pw_pwm_cpu_vol_grp1,
4668 &pw_pwm_cpu_vol_grp1_mux),
4669 FUNCTION("pw_pwm_cpu_vol_m2",
4670 pw_pwm_cpu_vol_grp2,
4671 &pw_pwm_cpu_vol_grp2_mux),
4672 FUNCTION("pw_backlight_m0",
4673 pw_backlight_grp0,
4674 &pw_backlight_grp0_mux),
4675 FUNCTION("pw_backlight_m1",
4676 pw_backlight_grp1,
4677 &pw_backlight_grp1_mux),
4678 FUNCTION("rg_eth_mac", rg_eth_mac_grp, &rg_eth_mac_grp_mux),
4679 FUNCTION("rg_gmac_phy_intr_n",
4680 rg_gmac_phy_intr_n_grp,
4681 &rg_gmac_phy_intr_n_grp_mux),
4682 FUNCTION("rg_rgmii_mac", rg_rgmii_mac_grp, &rg_rgmii_mac_grp_mux),
4683 FUNCTION("rg_rgmii_phy_ref_clk_m0",
4684 rg_rgmii_phy_ref_clk_grp0,
4685 &rg_rgmii_phy_ref_clk_grp0_mux),
4686 FUNCTION("rg_rgmii_phy_ref_clk_m1",
4687 rg_rgmii_phy_ref_clk_grp1,
4688 &rg_rgmii_phy_ref_clk_grp1_mux),
4689 FUNCTION("sd0", sd0_grp, &sd0_grp_mux),
4690 FUNCTION("sd0_4bit", sd0_4bit_grp, &sd0_4bit_grp_mux),
4691 FUNCTION("sd1", sd1_grp, &sd1_grp_mux),
4692 FUNCTION("sd1_4bit_m0", sd1_4bit_grp0, &sd1_4bit_grp0_mux),
4693 FUNCTION("sd1_4bit_m1", sd1_4bit_grp1, &sd1_4bit_grp1_mux),
4694 FUNCTION("sd2_basic", sd2_basic_grp, &sd2_basic_grp_mux),
4695 FUNCTION("sd2_cdb_m0", sd2_cdb_grp0, &sd2_cdb_grp0_mux),
4696 FUNCTION("sd2_cdb_m1", sd2_cdb_grp1, &sd2_cdb_grp1_mux),
4697 FUNCTION("sd2_wpb_m0", sd2_wpb_grp0, &sd2_wpb_grp0_mux),
4698 FUNCTION("sd2_wpb_m1", sd2_wpb_grp1, &sd2_wpb_grp1_mux),
4699 FUNCTION("sd3", sd3_9_grp, &sd3_9_grp_mux),
4700 FUNCTION("sd5", sd5_grp, &sd5_grp_mux),
4701 FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux),
4702 FUNCTION("sd6_m1", sd6_grp1, &sd6_grp1_mux),
4703 FUNCTION("sd9", sd3_9_grp, &sd3_9_grp_mux),
4704 FUNCTION("sp0_ext_ldo_on",
4705 sp0_ext_ldo_on_grp,
4706 &sp0_ext_ldo_on_grp_mux),
4707 FUNCTION("sp0_qspi", sp0_qspi_grp, &sp0_qspi_grp_mux),
4708 FUNCTION("sp1_spi", sp1_spi_grp, &sp1_spi_grp_mux),
4709 FUNCTION("tpiu_trace", tpiu_trace_grp, &tpiu_trace_grp_mux),
4710 FUNCTION("uart0", uart0_grp, &uart0_grp_mux),
4711 FUNCTION("uart0_nopause", uart0_nopause_grp, &uart0_nopause_grp_mux),
4712 FUNCTION("uart1", uart1_grp, &uart1_grp_mux),
4713 FUNCTION("uart2_cts_m0", uart2_cts_grp0, &uart2_cts_grp0_mux),
4714 FUNCTION("uart2_cts_m1", uart2_cts_grp1, &uart2_cts_grp1_mux),
4715 FUNCTION("uart2_rts_m0", uart2_rts_grp0, &uart2_rts_grp0_mux),
4716 FUNCTION("uart2_rts_m1", uart2_rts_grp1, &uart2_rts_grp1_mux),
4717 FUNCTION("uart2_rxd_m0", uart2_rxd_grp0, &uart2_rxd_grp0_mux),
4718 FUNCTION("uart2_rxd_m1", uart2_rxd_grp1, &uart2_rxd_grp1_mux),
4719 FUNCTION("uart2_rxd_m2", uart2_rxd_grp2, &uart2_rxd_grp2_mux),
4720 FUNCTION("uart2_txd_m0", uart2_txd_grp0, &uart2_txd_grp0_mux),
4721 FUNCTION("uart2_txd_m1", uart2_txd_grp1, &uart2_txd_grp1_mux),
4722 FUNCTION("uart2_txd_m2", uart2_txd_grp2, &uart2_txd_grp2_mux),
4723 FUNCTION("uart3_cts_m0", uart3_cts_grp0, &uart3_cts_grp0_mux),
4724 FUNCTION("uart3_cts_m1", uart3_cts_grp1, &uart3_cts_grp1_mux),
4725 FUNCTION("uart3_cts_m2", uart3_cts_grp2, &uart3_cts_grp2_mux),
4726 FUNCTION("uart3_rts_m0", uart3_rts_grp0, &uart3_rts_grp0_mux),
4727 FUNCTION("uart3_rts_m1", uart3_rts_grp1, &uart3_rts_grp1_mux),
4728 FUNCTION("uart3_rts_m2", uart3_rts_grp2, &uart3_rts_grp2_mux),
4729 FUNCTION("uart3_rxd_m0", uart3_rxd_grp0, &uart3_rxd_grp0_mux),
4730 FUNCTION("uart3_rxd_m1", uart3_rxd_grp1, &uart3_rxd_grp1_mux),
4731 FUNCTION("uart3_rxd_m2", uart3_rxd_grp2, &uart3_rxd_grp2_mux),
4732 FUNCTION("uart3_txd_m0", uart3_txd_grp0, &uart3_txd_grp0_mux),
4733 FUNCTION("uart3_txd_m1", uart3_txd_grp1, &uart3_txd_grp1_mux),
4734 FUNCTION("uart3_txd_m2", uart3_txd_grp2, &uart3_txd_grp2_mux),
4735 FUNCTION("uart4_basic", uart4_basic_grp, &uart4_basic_grp_mux),
4736 FUNCTION("uart4_cts_m0", uart4_cts_grp0, &uart4_cts_grp0_mux),
4737 FUNCTION("uart4_cts_m1", uart4_cts_grp1, &uart4_cts_grp1_mux),
4738 FUNCTION("uart4_cts_m2", uart4_cts_grp2, &uart4_cts_grp2_mux),
4739 FUNCTION("uart4_rts_m0", uart4_rts_grp0, &uart4_rts_grp0_mux),
4740 FUNCTION("uart4_rts_m1", uart4_rts_grp1, &uart4_rts_grp1_mux),
4741 FUNCTION("uart4_rts_m2", uart4_rts_grp2, &uart4_rts_grp2_mux),
4742 FUNCTION("usb0_drvvbus_m0",
4743 usb0_drvvbus_grp0,
4744 &usb0_drvvbus_grp0_mux),
4745 FUNCTION("usb0_drvvbus_m1",
4746 usb0_drvvbus_grp1,
4747 &usb0_drvvbus_grp1_mux),
4748 FUNCTION("usb1_drvvbus_m0",
4749 usb1_drvvbus_grp0,
4750 &usb1_drvvbus_grp0_mux),
4751 FUNCTION("usb1_drvvbus_m1",
4752 usb1_drvvbus_grp1,
4753 &usb1_drvvbus_grp1_mux),
4754 FUNCTION("visbus_dout", visbus_dout_grp, &visbus_dout_grp_mux),
4755 FUNCTION("vi_vip1", vi_vip1_grp, &vi_vip1_grp_mux),
4756 FUNCTION("vi_vip1_ext", vi_vip1_ext_grp, &vi_vip1_ext_grp_mux),
4757 FUNCTION("vi_vip1_low8bit",
4758 vi_vip1_low8bit_grp,
4759 &vi_vip1_low8bit_grp_mux),
4760 FUNCTION("vi_vip1_high8bit",
4761 vi_vip1_high8bit_grp,
4762 &vi_vip1_high8bit_grp_mux),
4763 };
4764
4765 static struct atlas7_pinctrl_data atlas7_ioc_data = {
4766 .pads = (struct pinctrl_pin_desc *)atlas7_ioc_pads,
4767 .pads_cnt = ARRAY_SIZE(atlas7_ioc_pads),
4768 .grps = (struct atlas7_pin_group *)altas7_pin_groups,
4769 .grps_cnt = ARRAY_SIZE(altas7_pin_groups),
4770 .funcs = (struct atlas7_pmx_func *)atlas7_pmx_functions,
4771 .funcs_cnt = ARRAY_SIZE(atlas7_pmx_functions),
4772 .confs = (struct atlas7_pad_config *)atlas7_ioc_pad_confs,
4773 .confs_cnt = ARRAY_SIZE(atlas7_ioc_pad_confs),
4774 };
4775
4776 /* Simple map data structure */
4777 struct map_data {
4778 u8 idx;
4779 u8 data;
4780 };
4781
4782 /**
4783 * struct atlas7_pull_info - Atlas7 Pad pull info
4784 * @type:The type of this Pad.
4785 * @mask:The mas value of this pin's pull bits.
4786 * @v2s: The map of pull register value to pull status.
4787 * @s2v: The map of pull status to pull register value.
4788 */
4789 struct atlas7_pull_info {
4790 u8 pad_type;
4791 u8 mask;
4792 const struct map_data *v2s;
4793 const struct map_data *s2v;
4794 };
4795
4796 /* Pull Register value map to status */
4797 static const struct map_data p4we_pull_v2s[] = {
4798 { P4WE_PULL_UP, PULL_UP },
4799 { P4WE_HIGH_HYSTERESIS, HIGH_HYSTERESIS },
4800 { P4WE_HIGH_Z, HIGH_Z },
4801 { P4WE_PULL_DOWN, PULL_DOWN },
4802 };
4803
4804 static const struct map_data p16st_pull_v2s[] = {
4805 { P16ST_PULL_UP, PULL_UP },
4806 { PD, PULL_UNKNOWN },
4807 { P16ST_HIGH_Z, HIGH_Z },
4808 { P16ST_PULL_DOWN, PULL_DOWN },
4809 };
4810
4811 static const struct map_data pm31_pull_v2s[] = {
4812 { PM31_PULL_DISABLED, PULL_DOWN },
4813 { PM31_PULL_ENABLED, PULL_UP },
4814 };
4815
4816 static const struct map_data pangd_pull_v2s[] = {
4817 { PANGD_PULL_UP, PULL_UP },
4818 { PD, PULL_UNKNOWN },
4819 { PANGD_HIGH_Z, HIGH_Z },
4820 { PANGD_PULL_DOWN, PULL_DOWN },
4821 };
4822
4823 /* Pull status map to register value */
4824 static const struct map_data p4we_pull_s2v[] = {
4825 { PULL_UP, P4WE_PULL_UP },
4826 { HIGH_HYSTERESIS, P4WE_HIGH_HYSTERESIS },
4827 { HIGH_Z, P4WE_HIGH_Z },
4828 { PULL_DOWN, P4WE_PULL_DOWN },
4829 { PULL_DISABLE, -1 },
4830 { PULL_ENABLE, -1 },
4831 };
4832
4833 static const struct map_data p16st_pull_s2v[] = {
4834 { PULL_UP, P16ST_PULL_UP },
4835 { HIGH_HYSTERESIS, -1 },
4836 { HIGH_Z, P16ST_HIGH_Z },
4837 { PULL_DOWN, P16ST_PULL_DOWN },
4838 { PULL_DISABLE, -1 },
4839 { PULL_ENABLE, -1 },
4840 };
4841
4842 static const struct map_data pm31_pull_s2v[] = {
4843 { PULL_UP, PM31_PULL_ENABLED },
4844 { HIGH_HYSTERESIS, -1 },
4845 { HIGH_Z, -1 },
4846 { PULL_DOWN, PM31_PULL_DISABLED },
4847 { PULL_DISABLE, -1 },
4848 { PULL_ENABLE, -1 },
4849 };
4850
4851 static const struct map_data pangd_pull_s2v[] = {
4852 { PULL_UP, PANGD_PULL_UP },
4853 { HIGH_HYSTERESIS, -1 },
4854 { HIGH_Z, PANGD_HIGH_Z },
4855 { PULL_DOWN, PANGD_PULL_DOWN },
4856 { PULL_DISABLE, -1 },
4857 { PULL_ENABLE, -1 },
4858 };
4859
4860 static const struct atlas7_pull_info atlas7_pull_map[] = {
4861 { PAD_T_4WE_PD, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
4862 { PAD_T_4WE_PU, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
4863 { PAD_T_16ST, P16ST_PULL_MASK, p16st_pull_v2s, p16st_pull_s2v },
4864 { PAD_T_M31_0204_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4865 { PAD_T_M31_0204_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4866 { PAD_T_M31_0610_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4867 { PAD_T_M31_0610_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4868 { PAD_T_AD, PANGD_PULL_MASK, pangd_pull_v2s, pangd_pull_s2v },
4869 };
4870
4871 /**
4872 * struct atlas7_ds_ma_info - Atlas7 Pad DriveStrength & currents info
4873 * @ma: The Drive Strength in current value .
4874 * @ds_16st: The correspond raw value of 16st pad.
4875 * @ds_4we: The correspond raw value of 4we pad.
4876 * @ds_0204m31: The correspond raw value of 0204m31 pad.
4877 * @ds_0610m31: The correspond raw value of 0610m31 pad.
4878 */
4879 struct atlas7_ds_ma_info {
4880 u32 ma;
4881 u32 ds_16st;
4882 u32 ds_4we;
4883 u32 ds_0204m31;
4884 u32 ds_0610m31;
4885 };
4886
4887 static const struct atlas7_ds_ma_info atlas7_ma2ds_map[] = {
4888 { 2, DS_16ST_0, DS_4WE_0, DS_M31_0, DS_NULL },
4889 { 4, DS_16ST_1, DS_NULL, DS_M31_1, DS_NULL },
4890 { 6, DS_16ST_2, DS_NULL, DS_NULL, DS_M31_0 },
4891 { 8, DS_16ST_3, DS_4WE_1, DS_NULL, DS_NULL },
4892 { 10, DS_16ST_4, DS_NULL, DS_NULL, DS_M31_1 },
4893 { 12, DS_16ST_5, DS_NULL, DS_NULL, DS_NULL },
4894 { 14, DS_16ST_6, DS_NULL, DS_NULL, DS_NULL },
4895 { 16, DS_16ST_7, DS_4WE_2, DS_NULL, DS_NULL },
4896 { 18, DS_16ST_8, DS_NULL, DS_NULL, DS_NULL },
4897 { 20, DS_16ST_9, DS_NULL, DS_NULL, DS_NULL },
4898 { 22, DS_16ST_10, DS_NULL, DS_NULL, DS_NULL },
4899 { 24, DS_16ST_11, DS_NULL, DS_NULL, DS_NULL },
4900 { 26, DS_16ST_12, DS_NULL, DS_NULL, DS_NULL },
4901 { 28, DS_16ST_13, DS_4WE_3, DS_NULL, DS_NULL },
4902 { 30, DS_16ST_14, DS_NULL, DS_NULL, DS_NULL },
4903 { 32, DS_16ST_15, DS_NULL, DS_NULL, DS_NULL },
4904 };
4905
4906 /**
4907 * struct atlas7_ds_info - Atlas7 Pad DriveStrength info
4908 * @type: The type of this Pad.
4909 * @mask: The mask value of this pin's pull bits.
4910 * @imval: The immediate value of drives trength register.
4911 */
4912 struct atlas7_ds_info {
4913 u8 type;
4914 u8 mask;
4915 u8 imval;
4916 u8 reserved;
4917 };
4918
4919 static const struct atlas7_ds_info atlas7_ds_map[] = {
4920 { PAD_T_4WE_PD, DS_2BIT_MASK, DS_2BIT_IM_VAL },
4921 { PAD_T_4WE_PU, DS_2BIT_MASK, DS_2BIT_IM_VAL },
4922 { PAD_T_16ST, DS_4BIT_MASK, DS_4BIT_IM_VAL },
4923 { PAD_T_M31_0204_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4924 { PAD_T_M31_0204_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4925 { PAD_T_M31_0610_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4926 { PAD_T_M31_0610_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4927 { PAD_T_AD, DS_NULL, DS_NULL },
4928 };
4929
atlas7_pin_to_bank(u32 pin)4930 static inline u32 atlas7_pin_to_bank(u32 pin)
4931 {
4932 return (pin >= ATLAS7_PINCTRL_BANK_0_PINS) ? 1 : 0;
4933 }
4934
atlas7_pmx_get_funcs_count(struct pinctrl_dev * pctldev)4935 static int atlas7_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
4936 {
4937 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4938
4939 return pmx->pctl_data->funcs_cnt;
4940 }
4941
atlas7_pmx_get_func_name(struct pinctrl_dev * pctldev,u32 selector)4942 static const char *atlas7_pmx_get_func_name(struct pinctrl_dev *pctldev,
4943 u32 selector)
4944 {
4945 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4946
4947 return pmx->pctl_data->funcs[selector].name;
4948 }
4949
atlas7_pmx_get_func_groups(struct pinctrl_dev * pctldev,u32 selector,const char * const ** groups,u32 * const num_groups)4950 static int atlas7_pmx_get_func_groups(struct pinctrl_dev *pctldev,
4951 u32 selector, const char * const **groups,
4952 u32 * const num_groups)
4953 {
4954 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4955
4956 *groups = pmx->pctl_data->funcs[selector].groups;
4957 *num_groups = pmx->pctl_data->funcs[selector].num_groups;
4958
4959 return 0;
4960 }
4961
__atlas7_pmx_pin_input_disable_set(struct atlas7_pmx * pmx,const struct atlas7_pad_mux * mux)4962 static void __atlas7_pmx_pin_input_disable_set(struct atlas7_pmx *pmx,
4963 const struct atlas7_pad_mux *mux)
4964 {
4965 /* Set Input Disable to avoid input glitches
4966 *
4967 * All Input-Disable Control registers are located on IOCRTC.
4968 * So the regs bank is always 0.
4969 *
4970 */
4971 if (mux->dinput_reg && mux->dinput_val_reg) {
4972 writel(DI_MASK << mux->dinput_bit,
4973 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
4974 writel(DI_DISABLE << mux->dinput_bit,
4975 pmx->regs[BANK_DS] + mux->dinput_reg);
4976
4977
4978 writel(DIV_MASK << mux->dinput_val_bit,
4979 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
4980 writel(DIV_DISABLE << mux->dinput_val_bit,
4981 pmx->regs[BANK_DS] + mux->dinput_val_reg);
4982 }
4983 }
4984
__atlas7_pmx_pin_input_disable_clr(struct atlas7_pmx * pmx,const struct atlas7_pad_mux * mux)4985 static void __atlas7_pmx_pin_input_disable_clr(struct atlas7_pmx *pmx,
4986 const struct atlas7_pad_mux *mux)
4987 {
4988 /* Clear Input Disable to avoid input glitches */
4989 if (mux->dinput_reg && mux->dinput_val_reg) {
4990 writel(DI_MASK << mux->dinput_bit,
4991 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
4992 writel(DI_ENABLE << mux->dinput_bit,
4993 pmx->regs[BANK_DS] + mux->dinput_reg);
4994
4995 writel(DIV_MASK << mux->dinput_val_bit,
4996 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
4997 writel(DIV_ENABLE << mux->dinput_val_bit,
4998 pmx->regs[BANK_DS] + mux->dinput_val_reg);
4999 }
5000 }
5001
__atlas7_pmx_pin_ad_sel(struct atlas7_pmx * pmx,struct atlas7_pad_config * conf,u32 bank,u32 ad_sel)5002 static int __atlas7_pmx_pin_ad_sel(struct atlas7_pmx *pmx,
5003 struct atlas7_pad_config *conf,
5004 u32 bank, u32 ad_sel)
5005 {
5006 unsigned long regv;
5007
5008 /* Write to clear register to clear A/D selector */
5009 writel(ANA_CLEAR_MASK << conf->ad_ctrl_bit,
5010 pmx->regs[bank] + CLR_REG(conf->ad_ctrl_reg));
5011
5012 /* Set target pad A/D selector */
5013 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
5014 regv &= ~(ANA_CLEAR_MASK << conf->ad_ctrl_bit);
5015 writel(regv | (ad_sel << conf->ad_ctrl_bit),
5016 pmx->regs[bank] + conf->ad_ctrl_reg);
5017
5018 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
5019 pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
5020 bank, conf->ad_ctrl_reg, regv);
5021 return 0;
5022 }
5023
__atlas7_pmx_pin_analog_enable(struct atlas7_pmx * pmx,struct atlas7_pad_config * conf,u32 bank)5024 static int __atlas7_pmx_pin_analog_enable(struct atlas7_pmx *pmx,
5025 struct atlas7_pad_config *conf, u32 bank)
5026 {
5027 /* Only PAD_T_AD pins can change between Analogue&Digital */
5028 if (conf->type != PAD_T_AD)
5029 return -EINVAL;
5030
5031 return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 0);
5032 }
5033
__atlas7_pmx_pin_digital_enable(struct atlas7_pmx * pmx,struct atlas7_pad_config * conf,u32 bank)5034 static int __atlas7_pmx_pin_digital_enable(struct atlas7_pmx *pmx,
5035 struct atlas7_pad_config *conf, u32 bank)
5036 {
5037 /* Other type pads are always digital */
5038 if (conf->type != PAD_T_AD)
5039 return 0;
5040
5041 return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 1);
5042 }
5043
__atlas7_pmx_pin_enable(struct atlas7_pmx * pmx,u32 pin,u32 func)5044 static int __atlas7_pmx_pin_enable(struct atlas7_pmx *pmx,
5045 u32 pin, u32 func)
5046 {
5047 struct atlas7_pad_config *conf;
5048 u32 bank;
5049 int ret;
5050 unsigned long regv;
5051
5052 pr_debug("PMX DUMP ### pin#%d func:%d #### START >>>\n",
5053 pin, func);
5054
5055 /* Get this Pad's descriptor from PINCTRL */
5056 conf = &pmx->pctl_data->confs[pin];
5057 bank = atlas7_pin_to_bank(pin);
5058
5059 /* Just enable the analog function of this pad */
5060 if (FUNC_ANALOGUE == func) {
5061 ret = __atlas7_pmx_pin_analog_enable(pmx, conf, bank);
5062 if (ret)
5063 dev_err(pmx->dev,
5064 "Convert pad#%d to analog failed, ret=%d\n",
5065 pin, ret);
5066 return ret;
5067 }
5068
5069 /* Set Pads from analog to digital */
5070 ret = __atlas7_pmx_pin_digital_enable(pmx, conf, bank);
5071 if (ret) {
5072 dev_err(pmx->dev,
5073 "Convert pad#%d to digital failed, ret=%d\n",
5074 pin, ret);
5075 return ret;
5076 }
5077
5078 /* Write to clear register to clear current function */
5079 writel(FUNC_CLEAR_MASK << conf->mux_bit,
5080 pmx->regs[bank] + CLR_REG(conf->mux_reg));
5081
5082 /* Set target pad mux function */
5083 regv = readl(pmx->regs[bank] + conf->mux_reg);
5084 regv &= ~(FUNC_CLEAR_MASK << conf->mux_bit);
5085 writel(regv | (func << conf->mux_bit),
5086 pmx->regs[bank] + conf->mux_reg);
5087
5088 regv = readl(pmx->regs[bank] + conf->mux_reg);
5089 pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
5090 bank, conf->mux_reg, regv);
5091
5092 return 0;
5093 }
5094
atlas7_pmx_set_mux(struct pinctrl_dev * pctldev,u32 func_selector,u32 group_selector)5095 static int atlas7_pmx_set_mux(struct pinctrl_dev *pctldev,
5096 u32 func_selector, u32 group_selector)
5097 {
5098 int idx, ret;
5099 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5100 struct atlas7_pmx_func *pmx_func;
5101 struct atlas7_pin_group *pin_grp;
5102 const struct atlas7_grp_mux *grp_mux;
5103 const struct atlas7_pad_mux *mux;
5104
5105 pmx_func = &pmx->pctl_data->funcs[func_selector];
5106 pin_grp = &pmx->pctl_data->grps[group_selector];
5107
5108 pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### START >>>\n",
5109 pmx_func->name, pin_grp->name);
5110
5111 /* the sd3 and sd9 pin select by SYS2PCI_SDIO9SEL register */
5112 if (pin_grp->pins == (unsigned int *)&sd3_9_pins) {
5113 if (!strcmp(pmx_func->name, "sd9"))
5114 writel(1, pmx->sys2pci_base + SYS2PCI_SDIO9SEL);
5115 else
5116 writel(0, pmx->sys2pci_base + SYS2PCI_SDIO9SEL);
5117 }
5118
5119 grp_mux = pmx_func->grpmux;
5120
5121 for (idx = 0; idx < grp_mux->pad_mux_count; idx++) {
5122 mux = &grp_mux->pad_mux_list[idx];
5123 __atlas7_pmx_pin_input_disable_set(pmx, mux);
5124 ret = __atlas7_pmx_pin_enable(pmx, mux->pin, mux->func);
5125 if (ret) {
5126 dev_err(pmx->dev,
5127 "FUNC:%s GRP:%s PIN#%d.%d failed, ret=%d\n",
5128 pmx_func->name, pin_grp->name,
5129 mux->pin, mux->func, ret);
5130 BUG_ON(1);
5131 }
5132 __atlas7_pmx_pin_input_disable_clr(pmx, mux);
5133 }
5134 pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### END <<<\n",
5135 pmx_func->name, pin_grp->name);
5136
5137 return 0;
5138 }
5139
convert_current_to_drive_strength(u32 type,u32 ma)5140 static u32 convert_current_to_drive_strength(u32 type, u32 ma)
5141 {
5142 int idx;
5143
5144 for (idx = 0; idx < ARRAY_SIZE(atlas7_ma2ds_map); idx++) {
5145 if (atlas7_ma2ds_map[idx].ma != ma)
5146 continue;
5147
5148 if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU)
5149 return atlas7_ma2ds_map[idx].ds_4we;
5150 else if (type == PAD_T_16ST)
5151 return atlas7_ma2ds_map[idx].ds_16st;
5152 else if (type == PAD_T_M31_0204_PD || type == PAD_T_M31_0204_PU)
5153 return atlas7_ma2ds_map[idx].ds_0204m31;
5154 else if (type == PAD_T_M31_0610_PD || type == PAD_T_M31_0610_PU)
5155 return atlas7_ma2ds_map[idx].ds_0610m31;
5156 }
5157
5158 return DS_NULL;
5159 }
5160
altas7_pinctrl_set_pull_sel(struct pinctrl_dev * pctldev,u32 pin,u32 sel)5161 static int altas7_pinctrl_set_pull_sel(struct pinctrl_dev *pctldev,
5162 u32 pin, u32 sel)
5163 {
5164 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5165 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
5166 const struct atlas7_pull_info *pull_info;
5167 u32 bank;
5168 unsigned long regv;
5169 void __iomem *pull_sel_reg;
5170
5171 bank = atlas7_pin_to_bank(pin);
5172 pull_info = &atlas7_pull_map[conf->type];
5173 pull_sel_reg = pmx->regs[bank] + conf->pupd_reg;
5174
5175 /* Retrieve correspond register value from table by sel */
5176 regv = pull_info->s2v[sel].data & pull_info->mask;
5177
5178 /* Clear & Set new value to pull register */
5179 writel(pull_info->mask << conf->pupd_bit, CLR_REG(pull_sel_reg));
5180 writel(regv << conf->pupd_bit, pull_sel_reg);
5181
5182 pr_debug("PIN_CFG ### SET PIN#%d PULL SELECTOR:%d == OK ####\n",
5183 pin, sel);
5184 return 0;
5185 }
5186
__altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev * pctldev,u32 pin,u32 sel)5187 static int __altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
5188 u32 pin, u32 sel)
5189 {
5190 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5191 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
5192 const struct atlas7_ds_info *ds_info;
5193 u32 bank;
5194 void __iomem *ds_sel_reg;
5195
5196 ds_info = &atlas7_ds_map[conf->type];
5197 if (sel & (~(ds_info->mask)))
5198 goto unsupport;
5199
5200 bank = atlas7_pin_to_bank(pin);
5201 ds_sel_reg = pmx->regs[bank] + conf->drvstr_reg;
5202
5203 writel(ds_info->imval << conf->drvstr_bit, CLR_REG(ds_sel_reg));
5204 writel(sel << conf->drvstr_bit, ds_sel_reg);
5205
5206 return 0;
5207
5208 unsupport:
5209 pr_err("Pad#%d type[%d] doesn't support ds code[%d]!\n",
5210 pin, conf->type, sel);
5211 return -ENOTSUPP;
5212 }
5213
altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev * pctldev,u32 pin,u32 ma)5214 static int altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
5215 u32 pin, u32 ma)
5216 {
5217 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5218 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
5219 u32 type = conf->type;
5220 u32 sel;
5221 int ret;
5222
5223 sel = convert_current_to_drive_strength(conf->type, ma);
5224 if (DS_NULL == sel) {
5225 pr_err("Pad#%d type[%d] doesn't support ds current[%d]!\n",
5226 pin, type, ma);
5227 return -ENOTSUPP;
5228 }
5229
5230 ret = __altas7_pinctrl_set_drive_strength_sel(pctldev,
5231 pin, sel);
5232 pr_debug("PIN_CFG ### SET PIN#%d DS:%d MA:%d == %s ####\n",
5233 pin, sel, ma, ret?"FAILED":"OK");
5234 return ret;
5235 }
5236
atlas7_pmx_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,u32 pin)5237 static int atlas7_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
5238 struct pinctrl_gpio_range *range, u32 pin)
5239 {
5240 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5241 u32 idx;
5242
5243 dev_dbg(pmx->dev,
5244 "atlas7_pmx_gpio_request_enable: pin=%d\n", pin);
5245 for (idx = 0; idx < range->npins; idx++) {
5246 if (pin == range->pins[idx])
5247 break;
5248 }
5249
5250 if (idx >= range->npins) {
5251 dev_err(pmx->dev,
5252 "The pin#%d could not be requested as GPIO!!\n",
5253 pin);
5254 return -EPERM;
5255 }
5256
5257 __atlas7_pmx_pin_enable(pmx, pin, FUNC_GPIO);
5258
5259 return 0;
5260 }
5261
5262 static const struct pinmux_ops atlas7_pinmux_ops = {
5263 .get_functions_count = atlas7_pmx_get_funcs_count,
5264 .get_function_name = atlas7_pmx_get_func_name,
5265 .get_function_groups = atlas7_pmx_get_func_groups,
5266 .set_mux = atlas7_pmx_set_mux,
5267 .gpio_request_enable = atlas7_pmx_gpio_request_enable,
5268 };
5269
atlas7_pinctrl_get_groups_count(struct pinctrl_dev * pctldev)5270 static int atlas7_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
5271 {
5272 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5273
5274 return pmx->pctl_data->grps_cnt;
5275 }
5276
atlas7_pinctrl_get_group_name(struct pinctrl_dev * pctldev,u32 group)5277 static const char *atlas7_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
5278 u32 group)
5279 {
5280 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5281
5282 return pmx->pctl_data->grps[group].name;
5283 }
5284
atlas7_pinctrl_get_group_pins(struct pinctrl_dev * pctldev,u32 group,const u32 ** pins,u32 * num_pins)5285 static int atlas7_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
5286 u32 group, const u32 **pins, u32 *num_pins)
5287 {
5288 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5289
5290 *num_pins = pmx->pctl_data->grps[group].num_pins;
5291 *pins = pmx->pctl_data->grps[group].pins;
5292
5293 return 0;
5294 }
5295
atlas7_pinctrl_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np_config,struct pinctrl_map ** map,u32 * num_maps)5296 static int atlas7_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
5297 struct device_node *np_config,
5298 struct pinctrl_map **map,
5299 u32 *num_maps)
5300 {
5301 return pinconf_generic_dt_node_to_map(pctldev, np_config, map,
5302 num_maps, PIN_MAP_TYPE_INVALID);
5303 }
5304
atlas7_pinctrl_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,u32 num_maps)5305 static void atlas7_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
5306 struct pinctrl_map *map, u32 num_maps)
5307 {
5308 kfree(map);
5309 }
5310
5311 static const struct pinctrl_ops atlas7_pinctrl_ops = {
5312 .get_groups_count = atlas7_pinctrl_get_groups_count,
5313 .get_group_name = atlas7_pinctrl_get_group_name,
5314 .get_group_pins = atlas7_pinctrl_get_group_pins,
5315 .dt_node_to_map = atlas7_pinctrl_dt_node_to_map,
5316 .dt_free_map = atlas7_pinctrl_dt_free_map,
5317 };
5318
atlas7_pin_config_set(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * configs,unsigned num_configs)5319 static int atlas7_pin_config_set(struct pinctrl_dev *pctldev,
5320 unsigned pin, unsigned long *configs,
5321 unsigned num_configs)
5322 {
5323 u16 param;
5324 u32 arg;
5325 int idx, err;
5326
5327 for (idx = 0; idx < num_configs; idx++) {
5328 param = pinconf_to_config_param(configs[idx]);
5329 arg = pinconf_to_config_argument(configs[idx]);
5330
5331 pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d >>>>>\n",
5332 pin, atlas7_ioc_pads[pin].name, param, arg);
5333 switch (param) {
5334 case PIN_CONFIG_BIAS_PULL_UP:
5335 err = altas7_pinctrl_set_pull_sel(pctldev,
5336 pin, PULL_UP);
5337 if (err)
5338 return err;
5339 break;
5340
5341 case PIN_CONFIG_BIAS_PULL_DOWN:
5342 err = altas7_pinctrl_set_pull_sel(pctldev,
5343 pin, PULL_DOWN);
5344 if (err)
5345 return err;
5346 break;
5347
5348 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
5349 err = altas7_pinctrl_set_pull_sel(pctldev,
5350 pin, HIGH_HYSTERESIS);
5351 if (err)
5352 return err;
5353 break;
5354 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
5355 err = altas7_pinctrl_set_pull_sel(pctldev,
5356 pin, HIGH_Z);
5357 if (err)
5358 return err;
5359 break;
5360
5361 case PIN_CONFIG_DRIVE_STRENGTH:
5362 err = altas7_pinctrl_set_drive_strength_sel(pctldev,
5363 pin, arg);
5364 if (err)
5365 return err;
5366 break;
5367 default:
5368 return -ENOTSUPP;
5369 }
5370 pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d <<<<\n",
5371 pin, atlas7_ioc_pads[pin].name, param, arg);
5372 }
5373
5374 return 0;
5375 }
5376
atlas7_pin_config_group_set(struct pinctrl_dev * pctldev,unsigned group,unsigned long * configs,unsigned num_configs)5377 static int atlas7_pin_config_group_set(struct pinctrl_dev *pctldev,
5378 unsigned group, unsigned long *configs,
5379 unsigned num_configs)
5380 {
5381 const unsigned *pins;
5382 unsigned npins;
5383 int i, ret;
5384
5385 ret = atlas7_pinctrl_get_group_pins(pctldev, group, &pins, &npins);
5386 if (ret)
5387 return ret;
5388 for (i = 0; i < npins; i++) {
5389 if (atlas7_pin_config_set(pctldev, pins[i],
5390 configs, num_configs))
5391 return -ENOTSUPP;
5392 }
5393 return 0;
5394 }
5395
5396 static const struct pinconf_ops atlas7_pinconf_ops = {
5397 .pin_config_set = atlas7_pin_config_set,
5398 .pin_config_group_set = atlas7_pin_config_group_set,
5399 .is_generic = true,
5400 };
5401
atlas7_pinmux_probe(struct platform_device * pdev)5402 static int atlas7_pinmux_probe(struct platform_device *pdev)
5403 {
5404 int ret, idx;
5405 struct atlas7_pmx *pmx;
5406 struct device_node *np = pdev->dev.of_node;
5407 u32 banks = ATLAS7_PINCTRL_REG_BANKS;
5408 struct device_node *sys2pci_np;
5409 struct resource res;
5410
5411 /* Create state holders etc for this driver */
5412 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
5413 if (!pmx)
5414 return -ENOMEM;
5415
5416 /* The sd3 and sd9 shared all pins, and the function select by
5417 * SYS2PCI_SDIO9SEL register
5418 */
5419 sys2pci_np = of_find_node_by_name(NULL, "sys2pci");
5420 if (!sys2pci_np)
5421 return -EINVAL;
5422
5423 ret = of_address_to_resource(sys2pci_np, 0, &res);
5424 of_node_put(sys2pci_np);
5425 if (ret)
5426 return ret;
5427
5428 pmx->sys2pci_base = devm_ioremap_resource(&pdev->dev, &res);
5429 if (IS_ERR(pmx->sys2pci_base))
5430 return -ENOMEM;
5431
5432 pmx->dev = &pdev->dev;
5433
5434 pmx->pctl_data = &atlas7_ioc_data;
5435 pmx->pctl_desc.name = "pinctrl-atlas7";
5436 pmx->pctl_desc.pins = pmx->pctl_data->pads;
5437 pmx->pctl_desc.npins = pmx->pctl_data->pads_cnt;
5438 pmx->pctl_desc.pctlops = &atlas7_pinctrl_ops;
5439 pmx->pctl_desc.pmxops = &atlas7_pinmux_ops;
5440 pmx->pctl_desc.confops = &atlas7_pinconf_ops;
5441
5442 for (idx = 0; idx < banks; idx++) {
5443 pmx->regs[idx] = of_iomap(np, idx);
5444 if (!pmx->regs[idx]) {
5445 dev_err(&pdev->dev,
5446 "can't map ioc bank#%d registers\n", idx);
5447 ret = -ENOMEM;
5448 goto unmap_io;
5449 }
5450 }
5451
5452 /* Now register the pin controller and all pins it handles */
5453 pmx->pctl = pinctrl_register(&pmx->pctl_desc, &pdev->dev, pmx);
5454 if (IS_ERR(pmx->pctl)) {
5455 dev_err(&pdev->dev, "could not register atlas7 pinmux driver\n");
5456 ret = PTR_ERR(pmx->pctl);
5457 goto unmap_io;
5458 }
5459
5460 platform_set_drvdata(pdev, pmx);
5461
5462 dev_info(&pdev->dev, "initialized atlas7 pinmux driver\n");
5463
5464 return 0;
5465
5466 unmap_io:
5467 for (idx = 0; idx < banks; idx++) {
5468 if (!pmx->regs[idx])
5469 break;
5470 iounmap(pmx->regs[idx]);
5471 }
5472
5473 return ret;
5474 }
5475
5476 #ifdef CONFIG_PM_SLEEP
atlas7_pinmux_suspend_noirq(struct device * dev)5477 static int atlas7_pinmux_suspend_noirq(struct device *dev)
5478 {
5479 struct atlas7_pmx *pmx = dev_get_drvdata(dev);
5480 struct atlas7_pad_status *status;
5481 struct atlas7_pad_config *conf;
5482 const struct atlas7_ds_info *ds_info;
5483 const struct atlas7_pull_info *pull_info;
5484 int idx;
5485 u32 bank;
5486 unsigned long regv;
5487
5488 for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
5489 /* Get this Pad's descriptor from PINCTRL */
5490 conf = &pmx->pctl_data->confs[idx];
5491 bank = atlas7_pin_to_bank(idx);
5492 status = &pmx->sleep_data[idx];
5493
5494 /* Save Function selector */
5495 regv = readl(pmx->regs[bank] + conf->mux_reg);
5496 status->func = (regv >> conf->mux_bit) & FUNC_CLEAR_MASK;
5497
5498 /* Check if Pad is in Analogue selector */
5499 if (conf->ad_ctrl_reg == -1)
5500 goto save_ds_sel;
5501
5502 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
5503 if (!(regv & (conf->ad_ctrl_bit << ANA_CLEAR_MASK)))
5504 status->func = FUNC_ANALOGUE;
5505
5506 save_ds_sel:
5507 if (conf->drvstr_reg == -1)
5508 goto save_pull_sel;
5509
5510 /* Save Drive Strength selector */
5511 ds_info = &atlas7_ds_map[conf->type];
5512 regv = readl(pmx->regs[bank] + conf->drvstr_reg);
5513 status->dstr = (regv >> conf->drvstr_bit) & ds_info->mask;
5514
5515 save_pull_sel:
5516 /* Save Pull selector */
5517 pull_info = &atlas7_pull_map[conf->type];
5518 regv = readl(pmx->regs[bank] + conf->pupd_reg);
5519 regv = (regv >> conf->pupd_bit) & pull_info->mask;
5520 status->pull = pull_info->v2s[regv].data;
5521 }
5522
5523 /*
5524 * Save disable input selector, this selector is not for Pin,
5525 * but for Mux function.
5526 */
5527 for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
5528 pmx->status_ds[idx] = readl(pmx->regs[BANK_DS] +
5529 IN_DISABLE_0_REG_SET + 0x8 * idx);
5530 pmx->status_dsv[idx] = readl(pmx->regs[BANK_DS] +
5531 IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
5532 }
5533
5534 return 0;
5535 }
5536
atlas7_pinmux_resume_noirq(struct device * dev)5537 static int atlas7_pinmux_resume_noirq(struct device *dev)
5538 {
5539 struct atlas7_pmx *pmx = dev_get_drvdata(dev);
5540 struct atlas7_pad_status *status;
5541 int idx;
5542
5543 for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
5544 /* Get this Pad's descriptor from PINCTRL */
5545 status = &pmx->sleep_data[idx];
5546
5547 /* Restore Function selector */
5548 __atlas7_pmx_pin_enable(pmx, idx, (u32)status->func & 0xff);
5549
5550 if (FUNC_ANALOGUE == status->func)
5551 goto restore_pull_sel;
5552
5553 /* Restore Drive Strength selector */
5554 __altas7_pinctrl_set_drive_strength_sel(pmx->pctl, idx,
5555 (u32)status->dstr & 0xff);
5556
5557 restore_pull_sel:
5558 /* Restore Pull selector */
5559 altas7_pinctrl_set_pull_sel(pmx->pctl, idx,
5560 (u32)status->pull & 0xff);
5561 }
5562
5563 /*
5564 * Restore disable input selector, this selector is not for Pin,
5565 * but for Mux function
5566 */
5567 for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
5568 writel(~0, pmx->regs[BANK_DS] +
5569 IN_DISABLE_0_REG_CLR + 0x8 * idx);
5570 writel(pmx->status_ds[idx], pmx->regs[BANK_DS] +
5571 IN_DISABLE_0_REG_SET + 0x8 * idx);
5572 writel(~0, pmx->regs[BANK_DS] +
5573 IN_DISABLE_VAL_0_REG_CLR + 0x8 * idx);
5574 writel(pmx->status_dsv[idx], pmx->regs[BANK_DS] +
5575 IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
5576 }
5577
5578 return 0;
5579 }
5580
5581 static const struct dev_pm_ops atlas7_pinmux_pm_ops = {
5582 .suspend_noirq = atlas7_pinmux_suspend_noirq,
5583 .resume_noirq = atlas7_pinmux_resume_noirq,
5584 .freeze_noirq = atlas7_pinmux_suspend_noirq,
5585 .restore_noirq = atlas7_pinmux_resume_noirq,
5586 };
5587 #endif
5588
5589 static const struct of_device_id atlas7_pinmux_ids[] = {
5590 { .compatible = "sirf,atlas7-ioc",},
5591 {},
5592 };
5593
5594 static struct platform_driver atlas7_pinmux_driver = {
5595 .driver = {
5596 .name = "atlas7-ioc",
5597 .of_match_table = atlas7_pinmux_ids,
5598 #ifdef CONFIG_PM_SLEEP
5599 .pm = &atlas7_pinmux_pm_ops,
5600 #endif
5601 },
5602 .probe = atlas7_pinmux_probe,
5603 };
5604
atlas7_pinmux_init(void)5605 static int __init atlas7_pinmux_init(void)
5606 {
5607 return platform_driver_register(&atlas7_pinmux_driver);
5608 }
5609 arch_initcall(atlas7_pinmux_init);
5610
5611
5612 /**
5613 * The Following is GPIO Code
5614 */
5615 static inline struct
atlas7_gpio_to_bank(struct atlas7_gpio_chip * a7gc,u32 gpio)5616 atlas7_gpio_bank *atlas7_gpio_to_bank(struct atlas7_gpio_chip *a7gc, u32 gpio)
5617 {
5618 return &a7gc->banks[GPIO_TO_BANK(gpio)];
5619 }
5620
__atlas7_gpio_to_pin(struct atlas7_gpio_chip * a7gc,u32 gpio)5621 static int __atlas7_gpio_to_pin(struct atlas7_gpio_chip *a7gc, u32 gpio)
5622 {
5623 struct atlas7_gpio_bank *bank;
5624 u32 ofs;
5625
5626 bank = atlas7_gpio_to_bank(a7gc, gpio);
5627 ofs = gpio - bank->gpio_offset;
5628 if (ofs >= bank->ngpio)
5629 return -ENODEV;
5630
5631 return bank->gpio_pins[ofs];
5632 }
5633
atlas7_gpio_irq_ack(struct irq_data * d)5634 static void atlas7_gpio_irq_ack(struct irq_data *d)
5635 {
5636 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5637 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5638 struct atlas7_gpio_bank *bank;
5639 void __iomem *ctrl_reg;
5640 u32 val, pin_in_bank;
5641 unsigned long flags;
5642
5643 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
5644 pin_in_bank = d->hwirq - bank->gpio_offset;
5645 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5646
5647 raw_spin_lock_irqsave(&a7gc->lock, flags);
5648
5649 val = readl(ctrl_reg);
5650 /* clear interrupt status */
5651 writel(val, ctrl_reg);
5652
5653 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5654 }
5655
__atlas7_gpio_irq_mask(struct atlas7_gpio_chip * a7gc,int idx)5656 static void __atlas7_gpio_irq_mask(struct atlas7_gpio_chip *a7gc, int idx)
5657 {
5658 struct atlas7_gpio_bank *bank;
5659 void __iomem *ctrl_reg;
5660 u32 val, pin_in_bank;
5661
5662 bank = atlas7_gpio_to_bank(a7gc, idx);
5663 pin_in_bank = idx - bank->gpio_offset;
5664 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5665
5666 val = readl(ctrl_reg);
5667 val &= ~(ATLAS7_GPIO_CTL_INTR_EN_MASK |
5668 ATLAS7_GPIO_CTL_INTR_STATUS_MASK);
5669 writel(val, ctrl_reg);
5670 }
5671
atlas7_gpio_irq_mask(struct irq_data * d)5672 static void atlas7_gpio_irq_mask(struct irq_data *d)
5673 {
5674 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5675 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5676 unsigned long flags;
5677
5678 raw_spin_lock_irqsave(&a7gc->lock, flags);
5679
5680 __atlas7_gpio_irq_mask(a7gc, d->hwirq);
5681
5682 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5683 }
5684
atlas7_gpio_irq_unmask(struct irq_data * d)5685 static void atlas7_gpio_irq_unmask(struct irq_data *d)
5686 {
5687 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5688 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5689 struct atlas7_gpio_bank *bank;
5690 void __iomem *ctrl_reg;
5691 u32 val, pin_in_bank;
5692 unsigned long flags;
5693
5694 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
5695 pin_in_bank = d->hwirq - bank->gpio_offset;
5696 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5697
5698 raw_spin_lock_irqsave(&a7gc->lock, flags);
5699
5700 val = readl(ctrl_reg);
5701 val &= ~ATLAS7_GPIO_CTL_INTR_STATUS_MASK;
5702 val |= ATLAS7_GPIO_CTL_INTR_EN_MASK;
5703 writel(val, ctrl_reg);
5704
5705 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5706 }
5707
atlas7_gpio_irq_type(struct irq_data * d,unsigned int type)5708 static int atlas7_gpio_irq_type(struct irq_data *d,
5709 unsigned int type)
5710 {
5711 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5712 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5713 struct atlas7_gpio_bank *bank;
5714 void __iomem *ctrl_reg;
5715 u32 val, pin_in_bank;
5716 unsigned long flags;
5717
5718 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
5719 pin_in_bank = d->hwirq - bank->gpio_offset;
5720 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5721
5722 raw_spin_lock_irqsave(&a7gc->lock, flags);
5723
5724 val = readl(ctrl_reg);
5725 val &= ~(ATLAS7_GPIO_CTL_INTR_STATUS_MASK |
5726 ATLAS7_GPIO_CTL_INTR_EN_MASK);
5727
5728 switch (type) {
5729 case IRQ_TYPE_NONE:
5730 break;
5731
5732 case IRQ_TYPE_EDGE_RISING:
5733 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
5734 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
5735 val &= ~ATLAS7_GPIO_CTL_INTR_LOW_MASK;
5736 break;
5737
5738 case IRQ_TYPE_EDGE_FALLING:
5739 val &= ~ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
5740 val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK |
5741 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
5742 break;
5743
5744 case IRQ_TYPE_EDGE_BOTH:
5745 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
5746 ATLAS7_GPIO_CTL_INTR_LOW_MASK |
5747 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
5748 break;
5749
5750 case IRQ_TYPE_LEVEL_LOW:
5751 val &= ~(ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
5752 ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
5753 val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK;
5754 break;
5755
5756 case IRQ_TYPE_LEVEL_HIGH:
5757 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
5758 val &= ~(ATLAS7_GPIO_CTL_INTR_LOW_MASK |
5759 ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
5760 break;
5761 }
5762
5763 writel(val, ctrl_reg);
5764
5765 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5766
5767 return 0;
5768 }
5769
5770 static struct irq_chip atlas7_gpio_irq_chip = {
5771 .name = "atlas7-gpio-irq",
5772 .irq_ack = atlas7_gpio_irq_ack,
5773 .irq_mask = atlas7_gpio_irq_mask,
5774 .irq_unmask = atlas7_gpio_irq_unmask,
5775 .irq_set_type = atlas7_gpio_irq_type,
5776 };
5777
atlas7_gpio_handle_irq(struct irq_desc * desc)5778 static void atlas7_gpio_handle_irq(struct irq_desc *desc)
5779 {
5780 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
5781 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
5782 struct atlas7_gpio_bank *bank = NULL;
5783 u32 status, ctrl;
5784 int pin_in_bank = 0, idx;
5785 struct irq_chip *chip = irq_desc_get_chip(desc);
5786 unsigned int irq = irq_desc_get_irq(desc);
5787
5788 for (idx = 0; idx < a7gc->nbank; idx++) {
5789 bank = &a7gc->banks[idx];
5790 if (bank->irq == irq)
5791 break;
5792 }
5793 BUG_ON(idx == a7gc->nbank);
5794
5795 chained_irq_enter(chip, desc);
5796
5797 status = readl(ATLAS7_GPIO_INT_STATUS(bank));
5798 if (!status) {
5799 pr_warn("%s: gpio [%s] status %#x no interrupt is flagged\n",
5800 __func__, gc->label, status);
5801 handle_bad_irq(desc);
5802 return;
5803 }
5804
5805 while (status) {
5806 ctrl = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
5807
5808 /*
5809 * Here we must check whether the corresponding GPIO's
5810 * interrupt has been enabled, otherwise just skip it
5811 */
5812 if ((status & 0x1) && (ctrl & ATLAS7_GPIO_CTL_INTR_EN_MASK)) {
5813 pr_debug("%s: chip[%s] gpio:%d happens\n",
5814 __func__, gc->label,
5815 bank->gpio_offset + pin_in_bank);
5816 generic_handle_irq(
5817 irq_find_mapping(gc->irq.domain,
5818 bank->gpio_offset + pin_in_bank));
5819 }
5820
5821 if (++pin_in_bank >= bank->ngpio)
5822 break;
5823
5824 status = status >> 1;
5825 }
5826
5827 chained_irq_exit(chip, desc);
5828 }
5829
__atlas7_gpio_set_input(struct atlas7_gpio_chip * a7gc,unsigned int gpio)5830 static void __atlas7_gpio_set_input(struct atlas7_gpio_chip *a7gc,
5831 unsigned int gpio)
5832 {
5833 struct atlas7_gpio_bank *bank;
5834 void __iomem *ctrl_reg;
5835 u32 val, pin_in_bank;
5836
5837 bank = atlas7_gpio_to_bank(a7gc, gpio);
5838 pin_in_bank = gpio - bank->gpio_offset;
5839 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5840
5841 val = readl(ctrl_reg);
5842 val &= ~ATLAS7_GPIO_CTL_OUT_EN_MASK;
5843 writel(val, ctrl_reg);
5844 }
5845
atlas7_gpio_request(struct gpio_chip * chip,unsigned int gpio)5846 static int atlas7_gpio_request(struct gpio_chip *chip,
5847 unsigned int gpio)
5848 {
5849 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5850 int ret;
5851 unsigned long flags;
5852
5853 ret = __atlas7_gpio_to_pin(a7gc, gpio);
5854 if (ret < 0)
5855 return ret;
5856
5857 if (pinctrl_gpio_request(chip->base + gpio))
5858 return -ENODEV;
5859
5860 raw_spin_lock_irqsave(&a7gc->lock, flags);
5861
5862 /*
5863 * default status:
5864 * set direction as input and mask irq
5865 */
5866 __atlas7_gpio_set_input(a7gc, gpio);
5867 __atlas7_gpio_irq_mask(a7gc, gpio);
5868
5869 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5870
5871 return 0;
5872 }
5873
atlas7_gpio_free(struct gpio_chip * chip,unsigned int gpio)5874 static void atlas7_gpio_free(struct gpio_chip *chip,
5875 unsigned int gpio)
5876 {
5877 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5878 unsigned long flags;
5879
5880 raw_spin_lock_irqsave(&a7gc->lock, flags);
5881
5882 __atlas7_gpio_irq_mask(a7gc, gpio);
5883 __atlas7_gpio_set_input(a7gc, gpio);
5884
5885 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5886
5887 pinctrl_gpio_free(chip->base + gpio);
5888 }
5889
atlas7_gpio_direction_input(struct gpio_chip * chip,unsigned int gpio)5890 static int atlas7_gpio_direction_input(struct gpio_chip *chip,
5891 unsigned int gpio)
5892 {
5893 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5894 unsigned long flags;
5895
5896 raw_spin_lock_irqsave(&a7gc->lock, flags);
5897
5898 __atlas7_gpio_set_input(a7gc, gpio);
5899
5900 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5901
5902 return 0;
5903 }
5904
__atlas7_gpio_set_output(struct atlas7_gpio_chip * a7gc,unsigned int gpio,int value)5905 static void __atlas7_gpio_set_output(struct atlas7_gpio_chip *a7gc,
5906 unsigned int gpio, int value)
5907 {
5908 struct atlas7_gpio_bank *bank;
5909 void __iomem *ctrl_reg;
5910 u32 out_ctrl, pin_in_bank;
5911
5912 bank = atlas7_gpio_to_bank(a7gc, gpio);
5913 pin_in_bank = gpio - bank->gpio_offset;
5914 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5915
5916 out_ctrl = readl(ctrl_reg);
5917 if (value)
5918 out_ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
5919 else
5920 out_ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
5921
5922 out_ctrl &= ~ATLAS7_GPIO_CTL_INTR_EN_MASK;
5923 out_ctrl |= ATLAS7_GPIO_CTL_OUT_EN_MASK;
5924 writel(out_ctrl, ctrl_reg);
5925 }
5926
atlas7_gpio_direction_output(struct gpio_chip * chip,unsigned int gpio,int value)5927 static int atlas7_gpio_direction_output(struct gpio_chip *chip,
5928 unsigned int gpio, int value)
5929 {
5930 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5931 unsigned long flags;
5932
5933 raw_spin_lock_irqsave(&a7gc->lock, flags);
5934
5935 __atlas7_gpio_set_output(a7gc, gpio, value);
5936
5937 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5938
5939 return 0;
5940 }
5941
atlas7_gpio_get_value(struct gpio_chip * chip,unsigned int gpio)5942 static int atlas7_gpio_get_value(struct gpio_chip *chip,
5943 unsigned int gpio)
5944 {
5945 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5946 struct atlas7_gpio_bank *bank;
5947 u32 val, pin_in_bank;
5948 unsigned long flags;
5949
5950 bank = atlas7_gpio_to_bank(a7gc, gpio);
5951 pin_in_bank = gpio - bank->gpio_offset;
5952
5953 raw_spin_lock_irqsave(&a7gc->lock, flags);
5954
5955 val = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
5956
5957 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5958
5959 return !!(val & ATLAS7_GPIO_CTL_DATAIN_MASK);
5960 }
5961
atlas7_gpio_set_value(struct gpio_chip * chip,unsigned int gpio,int value)5962 static void atlas7_gpio_set_value(struct gpio_chip *chip,
5963 unsigned int gpio, int value)
5964 {
5965 struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
5966 struct atlas7_gpio_bank *bank;
5967 void __iomem *ctrl_reg;
5968 u32 ctrl, pin_in_bank;
5969 unsigned long flags;
5970
5971 bank = atlas7_gpio_to_bank(a7gc, gpio);
5972 pin_in_bank = gpio - bank->gpio_offset;
5973 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5974
5975 raw_spin_lock_irqsave(&a7gc->lock, flags);
5976
5977 ctrl = readl(ctrl_reg);
5978 if (value)
5979 ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
5980 else
5981 ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
5982 writel(ctrl, ctrl_reg);
5983
5984 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5985 }
5986
5987 static const struct of_device_id atlas7_gpio_ids[] = {
5988 { .compatible = "sirf,atlas7-gpio", },
5989 {},
5990 };
5991
atlas7_gpio_probe(struct platform_device * pdev)5992 static int atlas7_gpio_probe(struct platform_device *pdev)
5993 {
5994 struct device_node *np = pdev->dev.of_node;
5995 struct atlas7_gpio_chip *a7gc;
5996 struct gpio_chip *chip;
5997 u32 nbank;
5998 int ret, idx;
5999
6000 ret = of_property_read_u32(np, "gpio-banks", &nbank);
6001 if (ret) {
6002 dev_err(&pdev->dev,
6003 "Could not find GPIO bank info,ret=%d!\n",
6004 ret);
6005 return ret;
6006 }
6007
6008 /* retrieve gpio descriptor data */
6009 a7gc = devm_kzalloc(&pdev->dev, struct_size(a7gc, banks, nbank),
6010 GFP_KERNEL);
6011 if (!a7gc)
6012 return -ENOMEM;
6013
6014 /* Get Gpio clk */
6015 a7gc->clk = of_clk_get(np, 0);
6016 if (!IS_ERR(a7gc->clk)) {
6017 ret = clk_prepare_enable(a7gc->clk);
6018 if (ret) {
6019 dev_err(&pdev->dev,
6020 "Could not enable clock!\n");
6021 return ret;
6022 }
6023 }
6024
6025 /* Get Gpio Registers */
6026 a7gc->reg = of_iomap(np, 0);
6027 if (!a7gc->reg) {
6028 dev_err(&pdev->dev, "Could not map GPIO Registers!\n");
6029 return -ENOMEM;
6030 }
6031
6032 a7gc->nbank = nbank;
6033 raw_spin_lock_init(&a7gc->lock);
6034
6035 /* Setup GPIO Chip */
6036 chip = &a7gc->chip;
6037 chip->request = atlas7_gpio_request;
6038 chip->free = atlas7_gpio_free;
6039 chip->direction_input = atlas7_gpio_direction_input;
6040 chip->get = atlas7_gpio_get_value;
6041 chip->direction_output = atlas7_gpio_direction_output;
6042 chip->set = atlas7_gpio_set_value;
6043 chip->base = -1;
6044 /* Each chip can support 32 pins at one bank */
6045 chip->ngpio = NGPIO_OF_BANK * nbank;
6046 chip->label = kstrdup(np->name, GFP_KERNEL);
6047 chip->of_node = np;
6048 chip->of_gpio_n_cells = 2;
6049 chip->parent = &pdev->dev;
6050
6051 /* Add gpio chip to system */
6052 ret = gpiochip_add_data(chip, a7gc);
6053 if (ret) {
6054 dev_err(&pdev->dev,
6055 "%pOF: error in probe function with status %d\n",
6056 np, ret);
6057 goto failed;
6058 }
6059
6060 /* Add gpio chip to irq subsystem */
6061 ret = gpiochip_irqchip_add(chip, &atlas7_gpio_irq_chip,
6062 0, handle_level_irq, IRQ_TYPE_NONE);
6063 if (ret) {
6064 dev_err(&pdev->dev,
6065 "could not connect irqchip to gpiochip\n");
6066 goto failed;
6067 }
6068
6069 for (idx = 0; idx < nbank; idx++) {
6070 struct atlas7_gpio_bank *bank;
6071
6072 bank = &a7gc->banks[idx];
6073 /* Set ctrl registers' base of this bank */
6074 bank->base = ATLAS7_GPIO_BASE(a7gc, idx);
6075 bank->gpio_offset = idx * NGPIO_OF_BANK;
6076
6077 /* Get interrupt number from DTS */
6078 ret = of_irq_get(np, idx);
6079 if (ret <= 0) {
6080 dev_err(&pdev->dev,
6081 "Unable to find IRQ number. ret=%d\n", ret);
6082 if (!ret)
6083 ret = -ENXIO;
6084 goto failed;
6085 }
6086 bank->irq = ret;
6087
6088 gpiochip_set_chained_irqchip(chip, &atlas7_gpio_irq_chip,
6089 bank->irq, atlas7_gpio_handle_irq);
6090 }
6091
6092 platform_set_drvdata(pdev, a7gc);
6093 dev_info(&pdev->dev, "add to system.\n");
6094 return 0;
6095 failed:
6096 return ret;
6097 }
6098
6099 #ifdef CONFIG_PM_SLEEP
atlas7_gpio_suspend_noirq(struct device * dev)6100 static int atlas7_gpio_suspend_noirq(struct device *dev)
6101 {
6102 struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
6103 struct atlas7_gpio_bank *bank;
6104 void __iomem *ctrl_reg;
6105 u32 idx, pin;
6106
6107 for (idx = 0; idx < a7gc->nbank; idx++) {
6108 bank = &a7gc->banks[idx];
6109 for (pin = 0; pin < bank->ngpio; pin++) {
6110 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
6111 bank->sleep_data[pin] = readl(ctrl_reg);
6112 }
6113 }
6114
6115 return 0;
6116 }
6117
atlas7_gpio_resume_noirq(struct device * dev)6118 static int atlas7_gpio_resume_noirq(struct device *dev)
6119 {
6120 struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
6121 struct atlas7_gpio_bank *bank;
6122 void __iomem *ctrl_reg;
6123 u32 idx, pin;
6124
6125 for (idx = 0; idx < a7gc->nbank; idx++) {
6126 bank = &a7gc->banks[idx];
6127 for (pin = 0; pin < bank->ngpio; pin++) {
6128 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
6129 writel(bank->sleep_data[pin], ctrl_reg);
6130 }
6131 }
6132
6133 return 0;
6134 }
6135
6136 static const struct dev_pm_ops atlas7_gpio_pm_ops = {
6137 .suspend_noirq = atlas7_gpio_suspend_noirq,
6138 .resume_noirq = atlas7_gpio_resume_noirq,
6139 .freeze_noirq = atlas7_gpio_suspend_noirq,
6140 .restore_noirq = atlas7_gpio_resume_noirq,
6141 };
6142 #endif
6143
6144 static struct platform_driver atlas7_gpio_driver = {
6145 .driver = {
6146 .name = "atlas7-gpio",
6147 .of_match_table = atlas7_gpio_ids,
6148 #ifdef CONFIG_PM_SLEEP
6149 .pm = &atlas7_gpio_pm_ops,
6150 #endif
6151 },
6152 .probe = atlas7_gpio_probe,
6153 };
6154
atlas7_gpio_init(void)6155 static int __init atlas7_gpio_init(void)
6156 {
6157 return platform_driver_register(&atlas7_gpio_driver);
6158 }
6159 subsys_initcall(atlas7_gpio_init);
6160
