1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * i.MX drm driver - Television Encoder (TVEv2)
4 *
5 * Copyright (C) 2013 Philipp Zabel, Pengutronix
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/clk.h>
10 #include <linux/component.h>
11 #include <linux/i2c.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/videodev2.h>
17
18 #include <video/imx-ipu-v3.h>
19
20 #include <drm/drm_atomic_helper.h>
21 #include <drm/drm_edid.h>
22 #include <drm/drm_fb_helper.h>
23 #include <drm/drm_managed.h>
24 #include <drm/drm_probe_helper.h>
25 #include <drm/drm_simple_kms_helper.h>
26
27 #include "imx-drm.h"
28
29 #define TVE_COM_CONF_REG 0x00
30 #define TVE_TVDAC0_CONT_REG 0x28
31 #define TVE_TVDAC1_CONT_REG 0x2c
32 #define TVE_TVDAC2_CONT_REG 0x30
33 #define TVE_CD_CONT_REG 0x34
34 #define TVE_INT_CONT_REG 0x64
35 #define TVE_STAT_REG 0x68
36 #define TVE_TST_MODE_REG 0x6c
37 #define TVE_MV_CONT_REG 0xdc
38
39 /* TVE_COM_CONF_REG */
40 #define TVE_SYNC_CH_2_EN BIT(22)
41 #define TVE_SYNC_CH_1_EN BIT(21)
42 #define TVE_SYNC_CH_0_EN BIT(20)
43 #define TVE_TV_OUT_MODE_MASK (0x7 << 12)
44 #define TVE_TV_OUT_DISABLE (0x0 << 12)
45 #define TVE_TV_OUT_CVBS_0 (0x1 << 12)
46 #define TVE_TV_OUT_CVBS_2 (0x2 << 12)
47 #define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
48 #define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
49 #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
50 #define TVE_TV_OUT_YPBPR (0x6 << 12)
51 #define TVE_TV_OUT_RGB (0x7 << 12)
52 #define TVE_TV_STAND_MASK (0xf << 8)
53 #define TVE_TV_STAND_HD_1080P30 (0xc << 8)
54 #define TVE_P2I_CONV_EN BIT(7)
55 #define TVE_INP_VIDEO_FORM BIT(6)
56 #define TVE_INP_YCBCR_422 (0x0 << 6)
57 #define TVE_INP_YCBCR_444 (0x1 << 6)
58 #define TVE_DATA_SOURCE_MASK (0x3 << 4)
59 #define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
60 #define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
61 #define TVE_DATA_SOURCE_EXT (0x2 << 4)
62 #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
63 #define TVE_IPU_CLK_EN_OFS 3
64 #define TVE_IPU_CLK_EN BIT(3)
65 #define TVE_DAC_SAMP_RATE_OFS 1
66 #define TVE_DAC_SAMP_RATE_WIDTH 2
67 #define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
68 #define TVE_DAC_FULL_RATE (0x0 << 1)
69 #define TVE_DAC_DIV2_RATE (0x1 << 1)
70 #define TVE_DAC_DIV4_RATE (0x2 << 1)
71 #define TVE_EN BIT(0)
72
73 /* TVE_TVDACx_CONT_REG */
74 #define TVE_TVDAC_GAIN_MASK (0x3f << 0)
75
76 /* TVE_CD_CONT_REG */
77 #define TVE_CD_CH_2_SM_EN BIT(22)
78 #define TVE_CD_CH_1_SM_EN BIT(21)
79 #define TVE_CD_CH_0_SM_EN BIT(20)
80 #define TVE_CD_CH_2_LM_EN BIT(18)
81 #define TVE_CD_CH_1_LM_EN BIT(17)
82 #define TVE_CD_CH_0_LM_EN BIT(16)
83 #define TVE_CD_CH_2_REF_LVL BIT(10)
84 #define TVE_CD_CH_1_REF_LVL BIT(9)
85 #define TVE_CD_CH_0_REF_LVL BIT(8)
86 #define TVE_CD_EN BIT(0)
87
88 /* TVE_INT_CONT_REG */
89 #define TVE_FRAME_END_IEN BIT(13)
90 #define TVE_CD_MON_END_IEN BIT(2)
91 #define TVE_CD_SM_IEN BIT(1)
92 #define TVE_CD_LM_IEN BIT(0)
93
94 /* TVE_TST_MODE_REG */
95 #define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
96
97 #define IMX_TVE_DAC_VOLTAGE 2750000
98
99 enum {
100 TVE_MODE_TVOUT,
101 TVE_MODE_VGA,
102 };
103
104 struct imx_tve_encoder {
105 struct drm_connector connector;
106 struct drm_encoder encoder;
107 struct imx_tve *tve;
108 };
109
110 struct imx_tve {
111 struct device *dev;
112 int mode;
113 int di_hsync_pin;
114 int di_vsync_pin;
115
116 struct regmap *regmap;
117 struct regulator *dac_reg;
118 struct i2c_adapter *ddc;
119 struct clk *clk;
120 struct clk *di_sel_clk;
121 struct clk_hw clk_hw_di;
122 struct clk *di_clk;
123 };
124
con_to_tve(struct drm_connector * c)125 static inline struct imx_tve *con_to_tve(struct drm_connector *c)
126 {
127 return container_of(c, struct imx_tve_encoder, connector)->tve;
128 }
129
enc_to_tve(struct drm_encoder * e)130 static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
131 {
132 return container_of(e, struct imx_tve_encoder, encoder)->tve;
133 }
134
tve_enable(struct imx_tve * tve)135 static void tve_enable(struct imx_tve *tve)
136 {
137 clk_prepare_enable(tve->clk);
138 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, TVE_EN);
139
140 /* clear interrupt status register */
141 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
142
143 /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
144 if (tve->mode == TVE_MODE_VGA)
145 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
146 else
147 regmap_write(tve->regmap, TVE_INT_CONT_REG,
148 TVE_CD_SM_IEN |
149 TVE_CD_LM_IEN |
150 TVE_CD_MON_END_IEN);
151 }
152
tve_disable(struct imx_tve * tve)153 static void tve_disable(struct imx_tve *tve)
154 {
155 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0);
156 clk_disable_unprepare(tve->clk);
157 }
158
tve_setup_tvout(struct imx_tve * tve)159 static int tve_setup_tvout(struct imx_tve *tve)
160 {
161 return -ENOTSUPP;
162 }
163
tve_setup_vga(struct imx_tve * tve)164 static int tve_setup_vga(struct imx_tve *tve)
165 {
166 unsigned int mask;
167 unsigned int val;
168 int ret;
169
170 /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
171 ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
172 TVE_TVDAC_GAIN_MASK, 0x0a);
173 if (ret)
174 return ret;
175
176 ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
177 TVE_TVDAC_GAIN_MASK, 0x0a);
178 if (ret)
179 return ret;
180
181 ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
182 TVE_TVDAC_GAIN_MASK, 0x0a);
183 if (ret)
184 return ret;
185
186 /* set configuration register */
187 mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
188 val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
189 mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
190 val |= TVE_TV_STAND_HD_1080P30 | 0;
191 mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
192 val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
193 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
194 if (ret)
195 return ret;
196
197 /* set test mode (as documented) */
198 return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
199 TVE_TVDAC_TEST_MODE_MASK, 1);
200 }
201
imx_tve_connector_get_modes(struct drm_connector * connector)202 static int imx_tve_connector_get_modes(struct drm_connector *connector)
203 {
204 struct imx_tve *tve = con_to_tve(connector);
205 struct edid *edid;
206 int ret = 0;
207
208 if (!tve->ddc)
209 return 0;
210
211 edid = drm_get_edid(connector, tve->ddc);
212 if (edid) {
213 drm_connector_update_edid_property(connector, edid);
214 ret = drm_add_edid_modes(connector, edid);
215 kfree(edid);
216 }
217
218 return ret;
219 }
220
221 static enum drm_mode_status
imx_tve_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)222 imx_tve_connector_mode_valid(struct drm_connector *connector,
223 struct drm_display_mode *mode)
224 {
225 struct imx_tve *tve = con_to_tve(connector);
226 unsigned long rate;
227
228 /* pixel clock with 2x oversampling */
229 rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
230 if (rate == mode->clock)
231 return MODE_OK;
232
233 /* pixel clock without oversampling */
234 rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
235 if (rate == mode->clock)
236 return MODE_OK;
237
238 dev_warn(tve->dev, "ignoring mode %dx%d\n",
239 mode->hdisplay, mode->vdisplay);
240
241 return MODE_BAD;
242 }
243
imx_tve_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * orig_mode,struct drm_display_mode * mode)244 static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
245 struct drm_display_mode *orig_mode,
246 struct drm_display_mode *mode)
247 {
248 struct imx_tve *tve = enc_to_tve(encoder);
249 unsigned long rounded_rate;
250 unsigned long rate;
251 int div = 1;
252 int ret;
253
254 /*
255 * FIXME
256 * we should try 4k * mode->clock first,
257 * and enable 4x oversampling for lower resolutions
258 */
259 rate = 2000UL * mode->clock;
260 clk_set_rate(tve->clk, rate);
261 rounded_rate = clk_get_rate(tve->clk);
262 if (rounded_rate >= rate)
263 div = 2;
264 clk_set_rate(tve->di_clk, rounded_rate / div);
265
266 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
267 if (ret < 0) {
268 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
269 ret);
270 }
271
272 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
273 TVE_IPU_CLK_EN, TVE_IPU_CLK_EN);
274
275 if (tve->mode == TVE_MODE_VGA)
276 ret = tve_setup_vga(tve);
277 else
278 ret = tve_setup_tvout(tve);
279 if (ret)
280 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
281 }
282
imx_tve_encoder_enable(struct drm_encoder * encoder)283 static void imx_tve_encoder_enable(struct drm_encoder *encoder)
284 {
285 struct imx_tve *tve = enc_to_tve(encoder);
286
287 tve_enable(tve);
288 }
289
imx_tve_encoder_disable(struct drm_encoder * encoder)290 static void imx_tve_encoder_disable(struct drm_encoder *encoder)
291 {
292 struct imx_tve *tve = enc_to_tve(encoder);
293
294 tve_disable(tve);
295 }
296
imx_tve_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)297 static int imx_tve_atomic_check(struct drm_encoder *encoder,
298 struct drm_crtc_state *crtc_state,
299 struct drm_connector_state *conn_state)
300 {
301 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
302 struct imx_tve *tve = enc_to_tve(encoder);
303
304 imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
305 imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;
306 imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;
307
308 return 0;
309 }
310
311 static const struct drm_connector_funcs imx_tve_connector_funcs = {
312 .fill_modes = drm_helper_probe_single_connector_modes,
313 .destroy = imx_drm_connector_destroy,
314 .reset = drm_atomic_helper_connector_reset,
315 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
316 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
317 };
318
319 static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
320 .get_modes = imx_tve_connector_get_modes,
321 .mode_valid = imx_tve_connector_mode_valid,
322 };
323
324 static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
325 .mode_set = imx_tve_encoder_mode_set,
326 .enable = imx_tve_encoder_enable,
327 .disable = imx_tve_encoder_disable,
328 .atomic_check = imx_tve_atomic_check,
329 };
330
imx_tve_irq_handler(int irq,void * data)331 static irqreturn_t imx_tve_irq_handler(int irq, void *data)
332 {
333 struct imx_tve *tve = data;
334 unsigned int val;
335
336 regmap_read(tve->regmap, TVE_STAT_REG, &val);
337
338 /* clear interrupt status register */
339 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
340
341 return IRQ_HANDLED;
342 }
343
clk_tve_di_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)344 static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
345 unsigned long parent_rate)
346 {
347 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
348 unsigned int val;
349 int ret;
350
351 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
352 if (ret < 0)
353 return 0;
354
355 switch (val & TVE_DAC_SAMP_RATE_MASK) {
356 case TVE_DAC_DIV4_RATE:
357 return parent_rate / 4;
358 case TVE_DAC_DIV2_RATE:
359 return parent_rate / 2;
360 case TVE_DAC_FULL_RATE:
361 default:
362 return parent_rate;
363 }
364
365 return 0;
366 }
367
clk_tve_di_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)368 static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
369 unsigned long *prate)
370 {
371 unsigned long div;
372
373 div = *prate / rate;
374 if (div >= 4)
375 return *prate / 4;
376 else if (div >= 2)
377 return *prate / 2;
378 return *prate;
379 }
380
clk_tve_di_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)381 static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
382 unsigned long parent_rate)
383 {
384 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
385 unsigned long div;
386 u32 val;
387 int ret;
388
389 div = parent_rate / rate;
390 if (div >= 4)
391 val = TVE_DAC_DIV4_RATE;
392 else if (div >= 2)
393 val = TVE_DAC_DIV2_RATE;
394 else
395 val = TVE_DAC_FULL_RATE;
396
397 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
398 TVE_DAC_SAMP_RATE_MASK, val);
399
400 if (ret < 0) {
401 dev_err(tve->dev, "failed to set divider: %d\n", ret);
402 return ret;
403 }
404
405 return 0;
406 }
407
408 static const struct clk_ops clk_tve_di_ops = {
409 .round_rate = clk_tve_di_round_rate,
410 .set_rate = clk_tve_di_set_rate,
411 .recalc_rate = clk_tve_di_recalc_rate,
412 };
413
tve_clk_init(struct imx_tve * tve,void __iomem * base)414 static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
415 {
416 const char *tve_di_parent[1];
417 struct clk_init_data init = {
418 .name = "tve_di",
419 .ops = &clk_tve_di_ops,
420 .num_parents = 1,
421 .flags = 0,
422 };
423
424 tve_di_parent[0] = __clk_get_name(tve->clk);
425 init.parent_names = (const char **)&tve_di_parent;
426
427 tve->clk_hw_di.init = &init;
428 tve->di_clk = devm_clk_register(tve->dev, &tve->clk_hw_di);
429 if (IS_ERR(tve->di_clk)) {
430 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
431 PTR_ERR(tve->di_clk));
432 return PTR_ERR(tve->di_clk);
433 }
434
435 return 0;
436 }
437
imx_tve_disable_regulator(void * data)438 static void imx_tve_disable_regulator(void *data)
439 {
440 struct imx_tve *tve = data;
441
442 regulator_disable(tve->dac_reg);
443 }
444
imx_tve_readable_reg(struct device * dev,unsigned int reg)445 static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
446 {
447 return (reg % 4 == 0) && (reg <= 0xdc);
448 }
449
450 static struct regmap_config tve_regmap_config = {
451 .reg_bits = 32,
452 .val_bits = 32,
453 .reg_stride = 4,
454
455 .readable_reg = imx_tve_readable_reg,
456
457 .fast_io = true,
458
459 .max_register = 0xdc,
460 };
461
462 static const char * const imx_tve_modes[] = {
463 [TVE_MODE_TVOUT] = "tvout",
464 [TVE_MODE_VGA] = "vga",
465 };
466
of_get_tve_mode(struct device_node * np)467 static int of_get_tve_mode(struct device_node *np)
468 {
469 const char *bm;
470 int ret, i;
471
472 ret = of_property_read_string(np, "fsl,tve-mode", &bm);
473 if (ret < 0)
474 return ret;
475
476 for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
477 if (!strcasecmp(bm, imx_tve_modes[i]))
478 return i;
479
480 return -EINVAL;
481 }
482
imx_tve_bind(struct device * dev,struct device * master,void * data)483 static int imx_tve_bind(struct device *dev, struct device *master, void *data)
484 {
485 struct drm_device *drm = data;
486 struct imx_tve *tve = dev_get_drvdata(dev);
487 struct imx_tve_encoder *tvee;
488 struct drm_encoder *encoder;
489 struct drm_connector *connector;
490 int encoder_type;
491 int ret;
492
493 encoder_type = tve->mode == TVE_MODE_VGA ?
494 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
495
496 tvee = drmm_simple_encoder_alloc(drm, struct imx_tve_encoder, encoder,
497 encoder_type);
498 if (IS_ERR(tvee))
499 return PTR_ERR(tvee);
500
501 tvee->tve = tve;
502 encoder = &tvee->encoder;
503 connector = &tvee->connector;
504
505 ret = imx_drm_encoder_parse_of(drm, encoder, tve->dev->of_node);
506 if (ret)
507 return ret;
508
509 drm_encoder_helper_add(encoder, &imx_tve_encoder_helper_funcs);
510
511 drm_connector_helper_add(connector, &imx_tve_connector_helper_funcs);
512 ret = drm_connector_init_with_ddc(drm, connector,
513 &imx_tve_connector_funcs,
514 DRM_MODE_CONNECTOR_VGA, tve->ddc);
515 if (ret)
516 return ret;
517
518 return drm_connector_attach_encoder(connector, encoder);
519 }
520
521 static const struct component_ops imx_tve_ops = {
522 .bind = imx_tve_bind,
523 };
524
imx_tve_probe(struct platform_device * pdev)525 static int imx_tve_probe(struct platform_device *pdev)
526 {
527 struct device *dev = &pdev->dev;
528 struct device_node *np = dev->of_node;
529 struct device_node *ddc_node;
530 struct imx_tve *tve;
531 void __iomem *base;
532 unsigned int val;
533 int irq;
534 int ret;
535
536 tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
537 if (!tve)
538 return -ENOMEM;
539
540 tve->dev = dev;
541
542 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
543 if (ddc_node) {
544 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
545 of_node_put(ddc_node);
546 }
547
548 tve->mode = of_get_tve_mode(np);
549 if (tve->mode != TVE_MODE_VGA) {
550 dev_err(dev, "only VGA mode supported, currently\n");
551 return -EINVAL;
552 }
553
554 if (tve->mode == TVE_MODE_VGA) {
555 ret = of_property_read_u32(np, "fsl,hsync-pin",
556 &tve->di_hsync_pin);
557
558 if (ret < 0) {
559 dev_err(dev, "failed to get hsync pin\n");
560 return ret;
561 }
562
563 ret = of_property_read_u32(np, "fsl,vsync-pin",
564 &tve->di_vsync_pin);
565
566 if (ret < 0) {
567 dev_err(dev, "failed to get vsync pin\n");
568 return ret;
569 }
570 }
571
572 base = devm_platform_ioremap_resource(pdev, 0);
573 if (IS_ERR(base))
574 return PTR_ERR(base);
575
576 tve_regmap_config.lock_arg = tve;
577 tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
578 &tve_regmap_config);
579 if (IS_ERR(tve->regmap)) {
580 dev_err(dev, "failed to init regmap: %ld\n",
581 PTR_ERR(tve->regmap));
582 return PTR_ERR(tve->regmap);
583 }
584
585 irq = platform_get_irq(pdev, 0);
586 if (irq < 0)
587 return irq;
588
589 ret = devm_request_threaded_irq(dev, irq, NULL,
590 imx_tve_irq_handler, IRQF_ONESHOT,
591 "imx-tve", tve);
592 if (ret < 0) {
593 dev_err(dev, "failed to request irq: %d\n", ret);
594 return ret;
595 }
596
597 tve->dac_reg = devm_regulator_get(dev, "dac");
598 if (!IS_ERR(tve->dac_reg)) {
599 if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE)
600 dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE);
601 ret = regulator_enable(tve->dac_reg);
602 if (ret)
603 return ret;
604 ret = devm_add_action_or_reset(dev, imx_tve_disable_regulator, tve);
605 if (ret)
606 return ret;
607 }
608
609 tve->clk = devm_clk_get(dev, "tve");
610 if (IS_ERR(tve->clk)) {
611 dev_err(dev, "failed to get high speed tve clock: %ld\n",
612 PTR_ERR(tve->clk));
613 return PTR_ERR(tve->clk);
614 }
615
616 /* this is the IPU DI clock input selector, can be parented to tve_di */
617 tve->di_sel_clk = devm_clk_get(dev, "di_sel");
618 if (IS_ERR(tve->di_sel_clk)) {
619 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
620 PTR_ERR(tve->di_sel_clk));
621 return PTR_ERR(tve->di_sel_clk);
622 }
623
624 ret = tve_clk_init(tve, base);
625 if (ret < 0)
626 return ret;
627
628 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
629 if (ret < 0) {
630 dev_err(dev, "failed to read configuration register: %d\n",
631 ret);
632 return ret;
633 }
634 if (val != 0x00100000) {
635 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
636 return -ENODEV;
637 }
638
639 /* disable cable detection for VGA mode */
640 ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
641 if (ret)
642 return ret;
643
644 platform_set_drvdata(pdev, tve);
645
646 return component_add(dev, &imx_tve_ops);
647 }
648
imx_tve_remove(struct platform_device * pdev)649 static int imx_tve_remove(struct platform_device *pdev)
650 {
651 component_del(&pdev->dev, &imx_tve_ops);
652 return 0;
653 }
654
655 static const struct of_device_id imx_tve_dt_ids[] = {
656 { .compatible = "fsl,imx53-tve", },
657 { /* sentinel */ }
658 };
659 MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
660
661 static struct platform_driver imx_tve_driver = {
662 .probe = imx_tve_probe,
663 .remove = imx_tve_remove,
664 .driver = {
665 .of_match_table = imx_tve_dt_ids,
666 .name = "imx-tve",
667 },
668 };
669
670 module_platform_driver(imx_tve_driver);
671
672 MODULE_DESCRIPTION("i.MX Television Encoder driver");
673 MODULE_AUTHOR("Philipp Zabel, Pengutronix");
674 MODULE_LICENSE("GPL");
675 MODULE_ALIAS("platform:imx-tve");
676
