1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc.
4 * All rights reserved.
5 *
6 * Author: Li Yang <leoli@freescale.com>
7 * Jiang Bo <tanya.jiang@freescale.com>
8 *
9 * Description:
10 * Freescale high-speed USB SOC DR module device controller driver.
11 * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
12 * The driver is previously named as mpc_udc. Based on bare board
13 * code from Dave Liu and Shlomi Gridish.
14 */
15
16 #undef VERBOSE
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/ioport.h>
21 #include <linux/types.h>
22 #include <linux/errno.h>
23 #include <linux/err.h>
24 #include <linux/slab.h>
25 #include <linux/init.h>
26 #include <linux/list.h>
27 #include <linux/interrupt.h>
28 #include <linux/proc_fs.h>
29 #include <linux/mm.h>
30 #include <linux/moduleparam.h>
31 #include <linux/device.h>
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
34 #include <linux/usb/otg.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/platform_device.h>
37 #include <linux/fsl_devices.h>
38 #include <linux/dmapool.h>
39 #include <linux/of_device.h>
40
41 #include <asm/byteorder.h>
42 #include <asm/io.h>
43 #include <asm/unaligned.h>
44 #include <asm/dma.h>
45
46 #include "fsl_usb2_udc.h"
47
48 #define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
49 #define DRIVER_AUTHOR "Li Yang/Jiang Bo"
50 #define DRIVER_VERSION "Apr 20, 2007"
51
52 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
53
54 static const char driver_name[] = "fsl-usb2-udc";
55
56 static struct usb_dr_device __iomem *dr_regs;
57
58 static struct usb_sys_interface __iomem *usb_sys_regs;
59
60 /* it is initialized in probe() */
61 static struct fsl_udc *udc_controller = NULL;
62
63 static const struct usb_endpoint_descriptor
64 fsl_ep0_desc = {
65 .bLength = USB_DT_ENDPOINT_SIZE,
66 .bDescriptorType = USB_DT_ENDPOINT,
67 .bEndpointAddress = 0,
68 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
69 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
70 };
71
72 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
73
74 #ifdef CONFIG_PPC32
75 /*
76 * On some SoCs, the USB controller registers can be big or little endian,
77 * depending on the version of the chip. In order to be able to run the
78 * same kernel binary on 2 different versions of an SoC, the BE/LE decision
79 * must be made at run time. _fsl_readl and fsl_writel are pointers to the
80 * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
81 * call through those pointers. Platform code for SoCs that have BE USB
82 * registers should set pdata->big_endian_mmio flag.
83 *
84 * This also applies to controller-to-cpu accessors for the USB descriptors,
85 * since their endianness is also SoC dependant. Platform code for SoCs that
86 * have BE USB descriptors should set pdata->big_endian_desc flag.
87 */
_fsl_readl_be(const unsigned __iomem * p)88 static u32 _fsl_readl_be(const unsigned __iomem *p)
89 {
90 return in_be32(p);
91 }
92
_fsl_readl_le(const unsigned __iomem * p)93 static u32 _fsl_readl_le(const unsigned __iomem *p)
94 {
95 return in_le32(p);
96 }
97
_fsl_writel_be(u32 v,unsigned __iomem * p)98 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
99 {
100 out_be32(p, v);
101 }
102
_fsl_writel_le(u32 v,unsigned __iomem * p)103 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
104 {
105 out_le32(p, v);
106 }
107
108 static u32 (*_fsl_readl)(const unsigned __iomem *p);
109 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
110
111 #define fsl_readl(p) (*_fsl_readl)((p))
112 #define fsl_writel(v, p) (*_fsl_writel)((v), (p))
113
fsl_set_accessors(struct fsl_usb2_platform_data * pdata)114 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
115 {
116 if (pdata->big_endian_mmio) {
117 _fsl_readl = _fsl_readl_be;
118 _fsl_writel = _fsl_writel_be;
119 } else {
120 _fsl_readl = _fsl_readl_le;
121 _fsl_writel = _fsl_writel_le;
122 }
123 }
124
cpu_to_hc32(const u32 x)125 static inline u32 cpu_to_hc32(const u32 x)
126 {
127 return udc_controller->pdata->big_endian_desc
128 ? (__force u32)cpu_to_be32(x)
129 : (__force u32)cpu_to_le32(x);
130 }
131
hc32_to_cpu(const u32 x)132 static inline u32 hc32_to_cpu(const u32 x)
133 {
134 return udc_controller->pdata->big_endian_desc
135 ? be32_to_cpu((__force __be32)x)
136 : le32_to_cpu((__force __le32)x);
137 }
138 #else /* !CONFIG_PPC32 */
fsl_set_accessors(struct fsl_usb2_platform_data * pdata)139 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
140
141 #define fsl_readl(addr) readl(addr)
142 #define fsl_writel(val32, addr) writel(val32, addr)
143 #define cpu_to_hc32(x) cpu_to_le32(x)
144 #define hc32_to_cpu(x) le32_to_cpu(x)
145 #endif /* CONFIG_PPC32 */
146
147 /********************************************************************
148 * Internal Used Function
149 ********************************************************************/
150 /*-----------------------------------------------------------------
151 * done() - retire a request; caller blocked irqs
152 * @status : request status to be set, only works when
153 * request is still in progress.
154 *--------------------------------------------------------------*/
done(struct fsl_ep * ep,struct fsl_req * req,int status)155 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
156 __releases(ep->udc->lock)
157 __acquires(ep->udc->lock)
158 {
159 struct fsl_udc *udc = NULL;
160 unsigned char stopped = ep->stopped;
161 struct ep_td_struct *curr_td, *next_td;
162 int j;
163
164 udc = (struct fsl_udc *)ep->udc;
165 /* Removed the req from fsl_ep->queue */
166 list_del_init(&req->queue);
167
168 /* req.status should be set as -EINPROGRESS in ep_queue() */
169 if (req->req.status == -EINPROGRESS)
170 req->req.status = status;
171 else
172 status = req->req.status;
173
174 /* Free dtd for the request */
175 next_td = req->head;
176 for (j = 0; j < req->dtd_count; j++) {
177 curr_td = next_td;
178 if (j != req->dtd_count - 1) {
179 next_td = curr_td->next_td_virt;
180 }
181 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
182 }
183
184 usb_gadget_unmap_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
185
186 if (status && (status != -ESHUTDOWN))
187 VDBG("complete %s req %p stat %d len %u/%u",
188 ep->ep.name, &req->req, status,
189 req->req.actual, req->req.length);
190
191 ep->stopped = 1;
192
193 spin_unlock(&ep->udc->lock);
194
195 usb_gadget_giveback_request(&ep->ep, &req->req);
196
197 spin_lock(&ep->udc->lock);
198 ep->stopped = stopped;
199 }
200
201 /*-----------------------------------------------------------------
202 * nuke(): delete all requests related to this ep
203 * called with spinlock held
204 *--------------------------------------------------------------*/
nuke(struct fsl_ep * ep,int status)205 static void nuke(struct fsl_ep *ep, int status)
206 {
207 ep->stopped = 1;
208
209 /* Flush fifo */
210 fsl_ep_fifo_flush(&ep->ep);
211
212 /* Whether this eq has request linked */
213 while (!list_empty(&ep->queue)) {
214 struct fsl_req *req = NULL;
215
216 req = list_entry(ep->queue.next, struct fsl_req, queue);
217 done(ep, req, status);
218 }
219 }
220
221 /*------------------------------------------------------------------
222 Internal Hardware related function
223 ------------------------------------------------------------------*/
224
dr_controller_setup(struct fsl_udc * udc)225 static int dr_controller_setup(struct fsl_udc *udc)
226 {
227 unsigned int tmp, portctrl, ep_num;
228 unsigned int max_no_of_ep;
229 unsigned int ctrl;
230 unsigned long timeout;
231
232 #define FSL_UDC_RESET_TIMEOUT 1000
233
234 /* Config PHY interface */
235 portctrl = fsl_readl(&dr_regs->portsc1);
236 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
237 switch (udc->phy_mode) {
238 case FSL_USB2_PHY_ULPI:
239 if (udc->pdata->have_sysif_regs) {
240 if (udc->pdata->controller_ver) {
241 /* controller version 1.6 or above */
242 ctrl = __raw_readl(&usb_sys_regs->control);
243 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
244 ctrl |= USB_CTRL_USB_EN;
245 __raw_writel(ctrl, &usb_sys_regs->control);
246 }
247 }
248 portctrl |= PORTSCX_PTS_ULPI;
249 break;
250 case FSL_USB2_PHY_UTMI_WIDE:
251 portctrl |= PORTSCX_PTW_16BIT;
252 fallthrough;
253 case FSL_USB2_PHY_UTMI:
254 case FSL_USB2_PHY_UTMI_DUAL:
255 if (udc->pdata->have_sysif_regs) {
256 if (udc->pdata->controller_ver) {
257 /* controller version 1.6 or above */
258 ctrl = __raw_readl(&usb_sys_regs->control);
259 ctrl |= (USB_CTRL_UTMI_PHY_EN |
260 USB_CTRL_USB_EN);
261 __raw_writel(ctrl, &usb_sys_regs->control);
262 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
263 PHY CLK to become stable - 10ms*/
264 }
265 }
266 portctrl |= PORTSCX_PTS_UTMI;
267 break;
268 case FSL_USB2_PHY_SERIAL:
269 portctrl |= PORTSCX_PTS_FSLS;
270 break;
271 default:
272 return -EINVAL;
273 }
274 fsl_writel(portctrl, &dr_regs->portsc1);
275
276 /* Stop and reset the usb controller */
277 tmp = fsl_readl(&dr_regs->usbcmd);
278 tmp &= ~USB_CMD_RUN_STOP;
279 fsl_writel(tmp, &dr_regs->usbcmd);
280
281 tmp = fsl_readl(&dr_regs->usbcmd);
282 tmp |= USB_CMD_CTRL_RESET;
283 fsl_writel(tmp, &dr_regs->usbcmd);
284
285 /* Wait for reset to complete */
286 timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
287 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
288 if (time_after(jiffies, timeout)) {
289 ERR("udc reset timeout!\n");
290 return -ETIMEDOUT;
291 }
292 cpu_relax();
293 }
294
295 /* Set the controller as device mode */
296 tmp = fsl_readl(&dr_regs->usbmode);
297 tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
298 tmp |= USB_MODE_CTRL_MODE_DEVICE;
299 /* Disable Setup Lockout */
300 tmp |= USB_MODE_SETUP_LOCK_OFF;
301 if (udc->pdata->es)
302 tmp |= USB_MODE_ES;
303 fsl_writel(tmp, &dr_regs->usbmode);
304
305 /* Clear the setup status */
306 fsl_writel(0, &dr_regs->usbsts);
307
308 tmp = udc->ep_qh_dma;
309 tmp &= USB_EP_LIST_ADDRESS_MASK;
310 fsl_writel(tmp, &dr_regs->endpointlistaddr);
311
312 VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
313 udc->ep_qh, (int)tmp,
314 fsl_readl(&dr_regs->endpointlistaddr));
315
316 max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
317 for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
318 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
319 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
320 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
321 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
322 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
323 }
324 /* Config control enable i/o output, cpu endian register */
325 if (udc->pdata->have_sysif_regs) {
326 ctrl = __raw_readl(&usb_sys_regs->control);
327 ctrl |= USB_CTRL_IOENB;
328 __raw_writel(ctrl, &usb_sys_regs->control);
329 }
330
331 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
332 /* Turn on cache snooping hardware, since some PowerPC platforms
333 * wholly rely on hardware to deal with cache coherent. */
334
335 if (udc->pdata->have_sysif_regs) {
336 /* Setup Snooping for all the 4GB space */
337 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
338 __raw_writel(tmp, &usb_sys_regs->snoop1);
339 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
340 __raw_writel(tmp, &usb_sys_regs->snoop2);
341 }
342 #endif
343
344 return 0;
345 }
346
347 /* Enable DR irq and set controller to run state */
dr_controller_run(struct fsl_udc * udc)348 static void dr_controller_run(struct fsl_udc *udc)
349 {
350 u32 temp;
351
352 /* Enable DR irq reg */
353 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
354 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
355 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
356
357 fsl_writel(temp, &dr_regs->usbintr);
358
359 /* Clear stopped bit */
360 udc->stopped = 0;
361
362 /* Set the controller as device mode */
363 temp = fsl_readl(&dr_regs->usbmode);
364 temp |= USB_MODE_CTRL_MODE_DEVICE;
365 fsl_writel(temp, &dr_regs->usbmode);
366
367 /* Set controller to Run */
368 temp = fsl_readl(&dr_regs->usbcmd);
369 temp |= USB_CMD_RUN_STOP;
370 fsl_writel(temp, &dr_regs->usbcmd);
371 }
372
dr_controller_stop(struct fsl_udc * udc)373 static void dr_controller_stop(struct fsl_udc *udc)
374 {
375 unsigned int tmp;
376
377 pr_debug("%s\n", __func__);
378
379 /* if we're in OTG mode, and the Host is currently using the port,
380 * stop now and don't rip the controller out from under the
381 * ehci driver
382 */
383 if (udc->gadget.is_otg) {
384 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
385 pr_debug("udc: Leaving early\n");
386 return;
387 }
388 }
389
390 /* disable all INTR */
391 fsl_writel(0, &dr_regs->usbintr);
392
393 /* Set stopped bit for isr */
394 udc->stopped = 1;
395
396 /* disable IO output */
397 /* usb_sys_regs->control = 0; */
398
399 /* set controller to Stop */
400 tmp = fsl_readl(&dr_regs->usbcmd);
401 tmp &= ~USB_CMD_RUN_STOP;
402 fsl_writel(tmp, &dr_regs->usbcmd);
403 }
404
dr_ep_setup(unsigned char ep_num,unsigned char dir,unsigned char ep_type)405 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
406 unsigned char ep_type)
407 {
408 unsigned int tmp_epctrl = 0;
409
410 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
411 if (dir) {
412 if (ep_num)
413 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
414 tmp_epctrl |= EPCTRL_TX_ENABLE;
415 tmp_epctrl &= ~EPCTRL_TX_TYPE;
416 tmp_epctrl |= ((unsigned int)(ep_type)
417 << EPCTRL_TX_EP_TYPE_SHIFT);
418 } else {
419 if (ep_num)
420 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
421 tmp_epctrl |= EPCTRL_RX_ENABLE;
422 tmp_epctrl &= ~EPCTRL_RX_TYPE;
423 tmp_epctrl |= ((unsigned int)(ep_type)
424 << EPCTRL_RX_EP_TYPE_SHIFT);
425 }
426
427 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
428 }
429
430 static void
dr_ep_change_stall(unsigned char ep_num,unsigned char dir,int value)431 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
432 {
433 u32 tmp_epctrl = 0;
434
435 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
436
437 if (value) {
438 /* set the stall bit */
439 if (dir)
440 tmp_epctrl |= EPCTRL_TX_EP_STALL;
441 else
442 tmp_epctrl |= EPCTRL_RX_EP_STALL;
443 } else {
444 /* clear the stall bit and reset data toggle */
445 if (dir) {
446 tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
447 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
448 } else {
449 tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
450 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
451 }
452 }
453 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
454 }
455
456 /* Get stall status of a specific ep
457 Return: 0: not stalled; 1:stalled */
dr_ep_get_stall(unsigned char ep_num,unsigned char dir)458 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
459 {
460 u32 epctrl;
461
462 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
463 if (dir)
464 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
465 else
466 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
467 }
468
469 /********************************************************************
470 Internal Structure Build up functions
471 ********************************************************************/
472
473 /*------------------------------------------------------------------
474 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
475 * @zlt: Zero Length Termination Select (1: disable; 0: enable)
476 * @mult: Mult field
477 ------------------------------------------------------------------*/
struct_ep_qh_setup(struct fsl_udc * udc,unsigned char ep_num,unsigned char dir,unsigned char ep_type,unsigned int max_pkt_len,unsigned int zlt,unsigned char mult)478 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
479 unsigned char dir, unsigned char ep_type,
480 unsigned int max_pkt_len,
481 unsigned int zlt, unsigned char mult)
482 {
483 struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
484 unsigned int tmp = 0;
485
486 /* set the Endpoint Capabilites in QH */
487 switch (ep_type) {
488 case USB_ENDPOINT_XFER_CONTROL:
489 /* Interrupt On Setup (IOS). for control ep */
490 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
491 | EP_QUEUE_HEAD_IOS;
492 break;
493 case USB_ENDPOINT_XFER_ISOC:
494 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
495 | (mult << EP_QUEUE_HEAD_MULT_POS);
496 break;
497 case USB_ENDPOINT_XFER_BULK:
498 case USB_ENDPOINT_XFER_INT:
499 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
500 break;
501 default:
502 VDBG("error ep type is %d", ep_type);
503 return;
504 }
505 if (zlt)
506 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
507
508 p_QH->max_pkt_length = cpu_to_hc32(tmp);
509 p_QH->next_dtd_ptr = 1;
510 p_QH->size_ioc_int_sts = 0;
511 }
512
513 /* Setup qh structure and ep register for ep0. */
ep0_setup(struct fsl_udc * udc)514 static void ep0_setup(struct fsl_udc *udc)
515 {
516 /* the initialization of an ep includes: fields in QH, Regs,
517 * fsl_ep struct */
518 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
519 USB_MAX_CTRL_PAYLOAD, 0, 0);
520 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
521 USB_MAX_CTRL_PAYLOAD, 0, 0);
522 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
523 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
524
525 return;
526
527 }
528
529 /***********************************************************************
530 Endpoint Management Functions
531 ***********************************************************************/
532
533 /*-------------------------------------------------------------------------
534 * when configurations are set, or when interface settings change
535 * for example the do_set_interface() in gadget layer,
536 * the driver will enable or disable the relevant endpoints
537 * ep0 doesn't use this routine. It is always enabled.
538 -------------------------------------------------------------------------*/
fsl_ep_enable(struct usb_ep * _ep,const struct usb_endpoint_descriptor * desc)539 static int fsl_ep_enable(struct usb_ep *_ep,
540 const struct usb_endpoint_descriptor *desc)
541 {
542 struct fsl_udc *udc = NULL;
543 struct fsl_ep *ep = NULL;
544 unsigned short max = 0;
545 unsigned char mult = 0, zlt;
546 int retval = -EINVAL;
547 unsigned long flags;
548
549 ep = container_of(_ep, struct fsl_ep, ep);
550
551 /* catch various bogus parameters */
552 if (!_ep || !desc
553 || (desc->bDescriptorType != USB_DT_ENDPOINT))
554 return -EINVAL;
555
556 udc = ep->udc;
557
558 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
559 return -ESHUTDOWN;
560
561 max = usb_endpoint_maxp(desc);
562
563 /* Disable automatic zlp generation. Driver is responsible to indicate
564 * explicitly through req->req.zero. This is needed to enable multi-td
565 * request. */
566 zlt = 1;
567
568 /* Assume the max packet size from gadget is always correct */
569 switch (desc->bmAttributes & 0x03) {
570 case USB_ENDPOINT_XFER_CONTROL:
571 case USB_ENDPOINT_XFER_BULK:
572 case USB_ENDPOINT_XFER_INT:
573 /* mult = 0. Execute N Transactions as demonstrated by
574 * the USB variable length packet protocol where N is
575 * computed using the Maximum Packet Length (dQH) and
576 * the Total Bytes field (dTD) */
577 mult = 0;
578 break;
579 case USB_ENDPOINT_XFER_ISOC:
580 /* Calculate transactions needed for high bandwidth iso */
581 mult = usb_endpoint_maxp_mult(desc);
582 /* 3 transactions at most */
583 if (mult > 3)
584 goto en_done;
585 break;
586 default:
587 goto en_done;
588 }
589
590 spin_lock_irqsave(&udc->lock, flags);
591 ep->ep.maxpacket = max;
592 ep->ep.desc = desc;
593 ep->stopped = 0;
594
595 /* Controller related setup */
596 /* Init EPx Queue Head (Ep Capabilites field in QH
597 * according to max, zlt, mult) */
598 struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
599 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
600 ? USB_SEND : USB_RECV),
601 (unsigned char) (desc->bmAttributes
602 & USB_ENDPOINT_XFERTYPE_MASK),
603 max, zlt, mult);
604
605 /* Init endpoint ctrl register */
606 dr_ep_setup((unsigned char) ep_index(ep),
607 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
608 ? USB_SEND : USB_RECV),
609 (unsigned char) (desc->bmAttributes
610 & USB_ENDPOINT_XFERTYPE_MASK));
611
612 spin_unlock_irqrestore(&udc->lock, flags);
613 retval = 0;
614
615 VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
616 ep->ep.desc->bEndpointAddress & 0x0f,
617 (desc->bEndpointAddress & USB_DIR_IN)
618 ? "in" : "out", max);
619 en_done:
620 return retval;
621 }
622
623 /*---------------------------------------------------------------------
624 * @ep : the ep being unconfigured. May not be ep0
625 * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
626 *---------------------------------------------------------------------*/
fsl_ep_disable(struct usb_ep * _ep)627 static int fsl_ep_disable(struct usb_ep *_ep)
628 {
629 struct fsl_udc *udc = NULL;
630 struct fsl_ep *ep = NULL;
631 unsigned long flags;
632 u32 epctrl;
633 int ep_num;
634
635 ep = container_of(_ep, struct fsl_ep, ep);
636 if (!_ep || !ep->ep.desc) {
637 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
638 return -EINVAL;
639 }
640
641 /* disable ep on controller */
642 ep_num = ep_index(ep);
643 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
644 if (ep_is_in(ep)) {
645 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
646 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
647 } else {
648 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
649 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
650 }
651 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
652
653 udc = (struct fsl_udc *)ep->udc;
654 spin_lock_irqsave(&udc->lock, flags);
655
656 /* nuke all pending requests (does flush) */
657 nuke(ep, -ESHUTDOWN);
658
659 ep->ep.desc = NULL;
660 ep->stopped = 1;
661 spin_unlock_irqrestore(&udc->lock, flags);
662
663 VDBG("disabled %s OK", _ep->name);
664 return 0;
665 }
666
667 /*---------------------------------------------------------------------
668 * allocate a request object used by this endpoint
669 * the main operation is to insert the req->queue to the eq->queue
670 * Returns the request, or null if one could not be allocated
671 *---------------------------------------------------------------------*/
672 static struct usb_request *
fsl_alloc_request(struct usb_ep * _ep,gfp_t gfp_flags)673 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
674 {
675 struct fsl_req *req = NULL;
676
677 req = kzalloc(sizeof *req, gfp_flags);
678 if (!req)
679 return NULL;
680
681 req->req.dma = DMA_ADDR_INVALID;
682 INIT_LIST_HEAD(&req->queue);
683
684 return &req->req;
685 }
686
fsl_free_request(struct usb_ep * _ep,struct usb_request * _req)687 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
688 {
689 struct fsl_req *req = NULL;
690
691 req = container_of(_req, struct fsl_req, req);
692
693 if (_req)
694 kfree(req);
695 }
696
697 /* Actually add a dTD chain to an empty dQH and let go */
fsl_prime_ep(struct fsl_ep * ep,struct ep_td_struct * td)698 static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
699 {
700 struct ep_queue_head *qh = get_qh_by_ep(ep);
701
702 /* Write dQH next pointer and terminate bit to 0 */
703 qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
704 & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
705
706 /* Clear active and halt bit */
707 qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
708 | EP_QUEUE_HEAD_STATUS_HALT));
709
710 /* Ensure that updates to the QH will occur before priming. */
711 wmb();
712
713 /* Prime endpoint by writing correct bit to ENDPTPRIME */
714 fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
715 : (1 << (ep_index(ep))), &dr_regs->endpointprime);
716 }
717
718 /* Add dTD chain to the dQH of an EP */
fsl_queue_td(struct fsl_ep * ep,struct fsl_req * req)719 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
720 {
721 u32 temp, bitmask, tmp_stat;
722
723 /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
724 VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
725
726 bitmask = ep_is_in(ep)
727 ? (1 << (ep_index(ep) + 16))
728 : (1 << (ep_index(ep)));
729
730 /* check if the pipe is empty */
731 if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) {
732 /* Add td to the end */
733 struct fsl_req *lastreq;
734 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
735 lastreq->tail->next_td_ptr =
736 cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
737 /* Ensure dTD's next dtd pointer to be updated */
738 wmb();
739 /* Read prime bit, if 1 goto done */
740 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
741 return;
742
743 do {
744 /* Set ATDTW bit in USBCMD */
745 temp = fsl_readl(&dr_regs->usbcmd);
746 fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
747
748 /* Read correct status bit */
749 tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
750
751 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
752
753 /* Write ATDTW bit to 0 */
754 temp = fsl_readl(&dr_regs->usbcmd);
755 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
756
757 if (tmp_stat)
758 return;
759 }
760
761 fsl_prime_ep(ep, req->head);
762 }
763
764 /* Fill in the dTD structure
765 * @req: request that the transfer belongs to
766 * @length: return actually data length of the dTD
767 * @dma: return dma address of the dTD
768 * @is_last: return flag if it is the last dTD of the request
769 * return: pointer to the built dTD */
fsl_build_dtd(struct fsl_req * req,unsigned * length,dma_addr_t * dma,int * is_last,gfp_t gfp_flags)770 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
771 dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
772 {
773 u32 swap_temp;
774 struct ep_td_struct *dtd;
775
776 /* how big will this transfer be? */
777 *length = min(req->req.length - req->req.actual,
778 (unsigned)EP_MAX_LENGTH_TRANSFER);
779
780 dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
781 if (dtd == NULL)
782 return dtd;
783
784 dtd->td_dma = *dma;
785 /* Clear reserved field */
786 swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
787 swap_temp &= ~DTD_RESERVED_FIELDS;
788 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
789
790 /* Init all of buffer page pointers */
791 swap_temp = (u32) (req->req.dma + req->req.actual);
792 dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
793 dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
794 dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
795 dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
796 dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
797
798 req->req.actual += *length;
799
800 /* zlp is needed if req->req.zero is set */
801 if (req->req.zero) {
802 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
803 *is_last = 1;
804 else
805 *is_last = 0;
806 } else if (req->req.length == req->req.actual)
807 *is_last = 1;
808 else
809 *is_last = 0;
810
811 if ((*is_last) == 0)
812 VDBG("multi-dtd request!");
813 /* Fill in the transfer size; set active bit */
814 swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
815
816 /* Enable interrupt for the last dtd of a request */
817 if (*is_last && !req->req.no_interrupt)
818 swap_temp |= DTD_IOC;
819
820 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
821
822 mb();
823
824 VDBG("length = %d address= 0x%x", *length, (int)*dma);
825
826 return dtd;
827 }
828
829 /* Generate dtd chain for a request */
fsl_req_to_dtd(struct fsl_req * req,gfp_t gfp_flags)830 static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
831 {
832 unsigned count;
833 int is_last;
834 int is_first =1;
835 struct ep_td_struct *last_dtd = NULL, *dtd;
836 dma_addr_t dma;
837
838 do {
839 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
840 if (dtd == NULL)
841 return -ENOMEM;
842
843 if (is_first) {
844 is_first = 0;
845 req->head = dtd;
846 } else {
847 last_dtd->next_td_ptr = cpu_to_hc32(dma);
848 last_dtd->next_td_virt = dtd;
849 }
850 last_dtd = dtd;
851
852 req->dtd_count++;
853 } while (!is_last);
854
855 dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
856
857 req->tail = dtd;
858
859 return 0;
860 }
861
862 /* queues (submits) an I/O request to an endpoint */
863 static int
fsl_ep_queue(struct usb_ep * _ep,struct usb_request * _req,gfp_t gfp_flags)864 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
865 {
866 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
867 struct fsl_req *req = container_of(_req, struct fsl_req, req);
868 struct fsl_udc *udc;
869 unsigned long flags;
870 int ret;
871
872 /* catch various bogus parameters */
873 if (!_req || !req->req.complete || !req->req.buf
874 || !list_empty(&req->queue)) {
875 VDBG("%s, bad params", __func__);
876 return -EINVAL;
877 }
878 if (unlikely(!_ep || !ep->ep.desc)) {
879 VDBG("%s, bad ep", __func__);
880 return -EINVAL;
881 }
882 if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
883 if (req->req.length > ep->ep.maxpacket)
884 return -EMSGSIZE;
885 }
886
887 udc = ep->udc;
888 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
889 return -ESHUTDOWN;
890
891 req->ep = ep;
892
893 ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
894 if (ret)
895 return ret;
896
897 req->req.status = -EINPROGRESS;
898 req->req.actual = 0;
899 req->dtd_count = 0;
900
901 /* build dtds and push them to device queue */
902 if (!fsl_req_to_dtd(req, gfp_flags)) {
903 spin_lock_irqsave(&udc->lock, flags);
904 fsl_queue_td(ep, req);
905 } else {
906 return -ENOMEM;
907 }
908
909 /* irq handler advances the queue */
910 if (req != NULL)
911 list_add_tail(&req->queue, &ep->queue);
912 spin_unlock_irqrestore(&udc->lock, flags);
913
914 return 0;
915 }
916
917 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
fsl_ep_dequeue(struct usb_ep * _ep,struct usb_request * _req)918 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
919 {
920 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
921 struct fsl_req *req;
922 unsigned long flags;
923 int ep_num, stopped, ret = 0;
924 u32 epctrl;
925
926 if (!_ep || !_req)
927 return -EINVAL;
928
929 spin_lock_irqsave(&ep->udc->lock, flags);
930 stopped = ep->stopped;
931
932 /* Stop the ep before we deal with the queue */
933 ep->stopped = 1;
934 ep_num = ep_index(ep);
935 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
936 if (ep_is_in(ep))
937 epctrl &= ~EPCTRL_TX_ENABLE;
938 else
939 epctrl &= ~EPCTRL_RX_ENABLE;
940 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
941
942 /* make sure it's actually queued on this endpoint */
943 list_for_each_entry(req, &ep->queue, queue) {
944 if (&req->req == _req)
945 break;
946 }
947 if (&req->req != _req) {
948 ret = -EINVAL;
949 goto out;
950 }
951
952 /* The request is in progress, or completed but not dequeued */
953 if (ep->queue.next == &req->queue) {
954 _req->status = -ECONNRESET;
955 fsl_ep_fifo_flush(_ep); /* flush current transfer */
956
957 /* The request isn't the last request in this ep queue */
958 if (req->queue.next != &ep->queue) {
959 struct fsl_req *next_req;
960
961 next_req = list_entry(req->queue.next, struct fsl_req,
962 queue);
963
964 /* prime with dTD of next request */
965 fsl_prime_ep(ep, next_req->head);
966 }
967 /* The request hasn't been processed, patch up the TD chain */
968 } else {
969 struct fsl_req *prev_req;
970
971 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
972 prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
973 }
974
975 done(ep, req, -ECONNRESET);
976
977 /* Enable EP */
978 out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
979 if (ep_is_in(ep))
980 epctrl |= EPCTRL_TX_ENABLE;
981 else
982 epctrl |= EPCTRL_RX_ENABLE;
983 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
984 ep->stopped = stopped;
985
986 spin_unlock_irqrestore(&ep->udc->lock, flags);
987 return ret;
988 }
989
990 /*-------------------------------------------------------------------------*/
991
992 /*-----------------------------------------------------------------
993 * modify the endpoint halt feature
994 * @ep: the non-isochronous endpoint being stalled
995 * @value: 1--set halt 0--clear halt
996 * Returns zero, or a negative error code.
997 *----------------------------------------------------------------*/
fsl_ep_set_halt(struct usb_ep * _ep,int value)998 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
999 {
1000 struct fsl_ep *ep = NULL;
1001 unsigned long flags;
1002 int status = -EOPNOTSUPP; /* operation not supported */
1003 unsigned char ep_dir = 0, ep_num = 0;
1004 struct fsl_udc *udc = NULL;
1005
1006 ep = container_of(_ep, struct fsl_ep, ep);
1007 udc = ep->udc;
1008 if (!_ep || !ep->ep.desc) {
1009 status = -EINVAL;
1010 goto out;
1011 }
1012
1013 if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
1014 status = -EOPNOTSUPP;
1015 goto out;
1016 }
1017
1018 /* Attempt to halt IN ep will fail if any transfer requests
1019 * are still queue */
1020 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1021 status = -EAGAIN;
1022 goto out;
1023 }
1024
1025 status = 0;
1026 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1027 ep_num = (unsigned char)(ep_index(ep));
1028 spin_lock_irqsave(&ep->udc->lock, flags);
1029 dr_ep_change_stall(ep_num, ep_dir, value);
1030 spin_unlock_irqrestore(&ep->udc->lock, flags);
1031
1032 if (ep_index(ep) == 0) {
1033 udc->ep0_state = WAIT_FOR_SETUP;
1034 udc->ep0_dir = 0;
1035 }
1036 out:
1037 VDBG(" %s %s halt stat %d", ep->ep.name,
1038 value ? "set" : "clear", status);
1039
1040 return status;
1041 }
1042
fsl_ep_fifo_status(struct usb_ep * _ep)1043 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1044 {
1045 struct fsl_ep *ep;
1046 struct fsl_udc *udc;
1047 int size = 0;
1048 u32 bitmask;
1049 struct ep_queue_head *qh;
1050
1051 if (!_ep || !_ep->desc || !(_ep->desc->bEndpointAddress&0xF))
1052 return -ENODEV;
1053
1054 ep = container_of(_ep, struct fsl_ep, ep);
1055
1056 udc = (struct fsl_udc *)ep->udc;
1057
1058 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1059 return -ESHUTDOWN;
1060
1061 qh = get_qh_by_ep(ep);
1062
1063 bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1064 (1 << (ep_index(ep)));
1065
1066 if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1067 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1068 >> DTD_LENGTH_BIT_POS;
1069
1070 pr_debug("%s %u\n", __func__, size);
1071 return size;
1072 }
1073
fsl_ep_fifo_flush(struct usb_ep * _ep)1074 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1075 {
1076 struct fsl_ep *ep;
1077 int ep_num, ep_dir;
1078 u32 bits;
1079 unsigned long timeout;
1080 #define FSL_UDC_FLUSH_TIMEOUT 1000
1081
1082 if (!_ep) {
1083 return;
1084 } else {
1085 ep = container_of(_ep, struct fsl_ep, ep);
1086 if (!ep->ep.desc)
1087 return;
1088 }
1089 ep_num = ep_index(ep);
1090 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1091
1092 if (ep_num == 0)
1093 bits = (1 << 16) | 1;
1094 else if (ep_dir == USB_SEND)
1095 bits = 1 << (16 + ep_num);
1096 else
1097 bits = 1 << ep_num;
1098
1099 timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1100 do {
1101 fsl_writel(bits, &dr_regs->endptflush);
1102
1103 /* Wait until flush complete */
1104 while (fsl_readl(&dr_regs->endptflush)) {
1105 if (time_after(jiffies, timeout)) {
1106 ERR("ep flush timeout\n");
1107 return;
1108 }
1109 cpu_relax();
1110 }
1111 /* See if we need to flush again */
1112 } while (fsl_readl(&dr_regs->endptstatus) & bits);
1113 }
1114
1115 static const struct usb_ep_ops fsl_ep_ops = {
1116 .enable = fsl_ep_enable,
1117 .disable = fsl_ep_disable,
1118
1119 .alloc_request = fsl_alloc_request,
1120 .free_request = fsl_free_request,
1121
1122 .queue = fsl_ep_queue,
1123 .dequeue = fsl_ep_dequeue,
1124
1125 .set_halt = fsl_ep_set_halt,
1126 .fifo_status = fsl_ep_fifo_status,
1127 .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
1128 };
1129
1130 /*-------------------------------------------------------------------------
1131 Gadget Driver Layer Operations
1132 -------------------------------------------------------------------------*/
1133
1134 /*----------------------------------------------------------------------
1135 * Get the current frame number (from DR frame_index Reg )
1136 *----------------------------------------------------------------------*/
fsl_get_frame(struct usb_gadget * gadget)1137 static int fsl_get_frame(struct usb_gadget *gadget)
1138 {
1139 return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1140 }
1141
1142 /*-----------------------------------------------------------------------
1143 * Tries to wake up the host connected to this gadget
1144 -----------------------------------------------------------------------*/
fsl_wakeup(struct usb_gadget * gadget)1145 static int fsl_wakeup(struct usb_gadget *gadget)
1146 {
1147 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1148 u32 portsc;
1149
1150 /* Remote wakeup feature not enabled by host */
1151 if (!udc->remote_wakeup)
1152 return -ENOTSUPP;
1153
1154 portsc = fsl_readl(&dr_regs->portsc1);
1155 /* not suspended? */
1156 if (!(portsc & PORTSCX_PORT_SUSPEND))
1157 return 0;
1158 /* trigger force resume */
1159 portsc |= PORTSCX_PORT_FORCE_RESUME;
1160 fsl_writel(portsc, &dr_regs->portsc1);
1161 return 0;
1162 }
1163
can_pullup(struct fsl_udc * udc)1164 static int can_pullup(struct fsl_udc *udc)
1165 {
1166 return udc->driver && udc->softconnect && udc->vbus_active;
1167 }
1168
1169 /* Notify controller that VBUS is powered, Called by whatever
1170 detects VBUS sessions */
fsl_vbus_session(struct usb_gadget * gadget,int is_active)1171 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1172 {
1173 struct fsl_udc *udc;
1174 unsigned long flags;
1175
1176 udc = container_of(gadget, struct fsl_udc, gadget);
1177 spin_lock_irqsave(&udc->lock, flags);
1178 VDBG("VBUS %s", is_active ? "on" : "off");
1179 udc->vbus_active = (is_active != 0);
1180 if (can_pullup(udc))
1181 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1182 &dr_regs->usbcmd);
1183 else
1184 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1185 &dr_regs->usbcmd);
1186 spin_unlock_irqrestore(&udc->lock, flags);
1187 return 0;
1188 }
1189
1190 /* constrain controller's VBUS power usage
1191 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1192 * reporting how much power the device may consume. For example, this
1193 * could affect how quickly batteries are recharged.
1194 *
1195 * Returns zero on success, else negative errno.
1196 */
fsl_vbus_draw(struct usb_gadget * gadget,unsigned mA)1197 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1198 {
1199 struct fsl_udc *udc;
1200
1201 udc = container_of(gadget, struct fsl_udc, gadget);
1202 if (!IS_ERR_OR_NULL(udc->transceiver))
1203 return usb_phy_set_power(udc->transceiver, mA);
1204 return -ENOTSUPP;
1205 }
1206
1207 /* Change Data+ pullup status
1208 * this func is used by usb_gadget_connect/disconnect
1209 */
fsl_pullup(struct usb_gadget * gadget,int is_on)1210 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1211 {
1212 struct fsl_udc *udc;
1213
1214 udc = container_of(gadget, struct fsl_udc, gadget);
1215
1216 if (!udc->vbus_active)
1217 return -EOPNOTSUPP;
1218
1219 udc->softconnect = (is_on != 0);
1220 if (can_pullup(udc))
1221 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1222 &dr_regs->usbcmd);
1223 else
1224 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1225 &dr_regs->usbcmd);
1226
1227 return 0;
1228 }
1229
1230 static int fsl_udc_start(struct usb_gadget *g,
1231 struct usb_gadget_driver *driver);
1232 static int fsl_udc_stop(struct usb_gadget *g);
1233
1234 static const struct usb_gadget_ops fsl_gadget_ops = {
1235 .get_frame = fsl_get_frame,
1236 .wakeup = fsl_wakeup,
1237 /* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1238 .vbus_session = fsl_vbus_session,
1239 .vbus_draw = fsl_vbus_draw,
1240 .pullup = fsl_pullup,
1241 .udc_start = fsl_udc_start,
1242 .udc_stop = fsl_udc_stop,
1243 };
1244
1245 /*
1246 * Empty complete function used by this driver to fill in the req->complete
1247 * field when creating a request since the complete field is mandatory.
1248 */
fsl_noop_complete(struct usb_ep * ep,struct usb_request * req)1249 static void fsl_noop_complete(struct usb_ep *ep, struct usb_request *req) { }
1250
1251 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1252 on new transaction */
ep0stall(struct fsl_udc * udc)1253 static void ep0stall(struct fsl_udc *udc)
1254 {
1255 u32 tmp;
1256
1257 /* must set tx and rx to stall at the same time */
1258 tmp = fsl_readl(&dr_regs->endptctrl[0]);
1259 tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1260 fsl_writel(tmp, &dr_regs->endptctrl[0]);
1261 udc->ep0_state = WAIT_FOR_SETUP;
1262 udc->ep0_dir = 0;
1263 }
1264
1265 /* Prime a status phase for ep0 */
ep0_prime_status(struct fsl_udc * udc,int direction)1266 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1267 {
1268 struct fsl_req *req = udc->status_req;
1269 struct fsl_ep *ep;
1270 int ret;
1271
1272 if (direction == EP_DIR_IN)
1273 udc->ep0_dir = USB_DIR_IN;
1274 else
1275 udc->ep0_dir = USB_DIR_OUT;
1276
1277 ep = &udc->eps[0];
1278 if (udc->ep0_state != DATA_STATE_XMIT)
1279 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1280
1281 req->ep = ep;
1282 req->req.length = 0;
1283 req->req.status = -EINPROGRESS;
1284 req->req.actual = 0;
1285 req->req.complete = fsl_noop_complete;
1286 req->dtd_count = 0;
1287
1288 ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1289 if (ret)
1290 return ret;
1291
1292 if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
1293 fsl_queue_td(ep, req);
1294 else
1295 return -ENOMEM;
1296
1297 list_add_tail(&req->queue, &ep->queue);
1298
1299 return 0;
1300 }
1301
udc_reset_ep_queue(struct fsl_udc * udc,u8 pipe)1302 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1303 {
1304 struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1305
1306 if (ep->ep.name)
1307 nuke(ep, -ESHUTDOWN);
1308 }
1309
1310 /*
1311 * ch9 Set address
1312 */
ch9setaddress(struct fsl_udc * udc,u16 value,u16 index,u16 length)1313 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1314 {
1315 /* Save the new address to device struct */
1316 udc->device_address = (u8) value;
1317 /* Update usb state */
1318 udc->usb_state = USB_STATE_ADDRESS;
1319 /* Status phase */
1320 if (ep0_prime_status(udc, EP_DIR_IN))
1321 ep0stall(udc);
1322 }
1323
1324 /*
1325 * ch9 Get status
1326 */
ch9getstatus(struct fsl_udc * udc,u8 request_type,u16 value,u16 index,u16 length)1327 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1328 u16 index, u16 length)
1329 {
1330 u16 tmp = 0; /* Status, cpu endian */
1331 struct fsl_req *req;
1332 struct fsl_ep *ep;
1333 int ret;
1334
1335 ep = &udc->eps[0];
1336
1337 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1338 /* Get device status */
1339 tmp = udc->gadget.is_selfpowered;
1340 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1341 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1342 /* Get interface status */
1343 /* We don't have interface information in udc driver */
1344 tmp = 0;
1345 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1346 /* Get endpoint status */
1347 struct fsl_ep *target_ep;
1348
1349 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1350
1351 /* stall if endpoint doesn't exist */
1352 if (!target_ep->ep.desc)
1353 goto stall;
1354 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1355 << USB_ENDPOINT_HALT;
1356 }
1357
1358 udc->ep0_dir = USB_DIR_IN;
1359 /* Borrow the per device status_req */
1360 req = udc->status_req;
1361 /* Fill in the reqest structure */
1362 *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1363
1364 req->ep = ep;
1365 req->req.length = 2;
1366 req->req.status = -EINPROGRESS;
1367 req->req.actual = 0;
1368 req->req.complete = fsl_noop_complete;
1369 req->dtd_count = 0;
1370
1371 ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1372 if (ret)
1373 goto stall;
1374
1375 /* prime the data phase */
1376 if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1377 fsl_queue_td(ep, req);
1378 else /* no mem */
1379 goto stall;
1380
1381 list_add_tail(&req->queue, &ep->queue);
1382 udc->ep0_state = DATA_STATE_XMIT;
1383 if (ep0_prime_status(udc, EP_DIR_OUT))
1384 ep0stall(udc);
1385
1386 return;
1387 stall:
1388 ep0stall(udc);
1389 }
1390
setup_received_irq(struct fsl_udc * udc,struct usb_ctrlrequest * setup)1391 static void setup_received_irq(struct fsl_udc *udc,
1392 struct usb_ctrlrequest *setup)
1393 __releases(udc->lock)
1394 __acquires(udc->lock)
1395 {
1396 u16 wValue = le16_to_cpu(setup->wValue);
1397 u16 wIndex = le16_to_cpu(setup->wIndex);
1398 u16 wLength = le16_to_cpu(setup->wLength);
1399
1400 udc_reset_ep_queue(udc, 0);
1401
1402 /* We process some stardard setup requests here */
1403 switch (setup->bRequest) {
1404 case USB_REQ_GET_STATUS:
1405 /* Data+Status phase from udc */
1406 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1407 != (USB_DIR_IN | USB_TYPE_STANDARD))
1408 break;
1409 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1410 return;
1411
1412 case USB_REQ_SET_ADDRESS:
1413 /* Status phase from udc */
1414 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1415 | USB_RECIP_DEVICE))
1416 break;
1417 ch9setaddress(udc, wValue, wIndex, wLength);
1418 return;
1419
1420 case USB_REQ_CLEAR_FEATURE:
1421 case USB_REQ_SET_FEATURE:
1422 /* Status phase from udc */
1423 {
1424 int rc = -EOPNOTSUPP;
1425 u16 ptc = 0;
1426
1427 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1428 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1429 int pipe = get_pipe_by_windex(wIndex);
1430 struct fsl_ep *ep;
1431
1432 if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
1433 break;
1434 ep = get_ep_by_pipe(udc, pipe);
1435
1436 spin_unlock(&udc->lock);
1437 rc = fsl_ep_set_halt(&ep->ep,
1438 (setup->bRequest == USB_REQ_SET_FEATURE)
1439 ? 1 : 0);
1440 spin_lock(&udc->lock);
1441
1442 } else if ((setup->bRequestType & (USB_RECIP_MASK
1443 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1444 | USB_TYPE_STANDARD)) {
1445 /* Note: The driver has not include OTG support yet.
1446 * This will be set when OTG support is added */
1447 if (wValue == USB_DEVICE_TEST_MODE)
1448 ptc = wIndex >> 8;
1449 else if (gadget_is_otg(&udc->gadget)) {
1450 if (setup->bRequest ==
1451 USB_DEVICE_B_HNP_ENABLE)
1452 udc->gadget.b_hnp_enable = 1;
1453 else if (setup->bRequest ==
1454 USB_DEVICE_A_HNP_SUPPORT)
1455 udc->gadget.a_hnp_support = 1;
1456 else if (setup->bRequest ==
1457 USB_DEVICE_A_ALT_HNP_SUPPORT)
1458 udc->gadget.a_alt_hnp_support = 1;
1459 }
1460 rc = 0;
1461 } else
1462 break;
1463
1464 if (rc == 0) {
1465 if (ep0_prime_status(udc, EP_DIR_IN))
1466 ep0stall(udc);
1467 }
1468 if (ptc) {
1469 u32 tmp;
1470
1471 mdelay(10);
1472 tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1473 fsl_writel(tmp, &dr_regs->portsc1);
1474 printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1475 }
1476
1477 return;
1478 }
1479
1480 default:
1481 break;
1482 }
1483
1484 /* Requests handled by gadget */
1485 if (wLength) {
1486 /* Data phase from gadget, status phase from udc */
1487 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1488 ? USB_DIR_IN : USB_DIR_OUT;
1489 spin_unlock(&udc->lock);
1490 if (udc->driver->setup(&udc->gadget,
1491 &udc->local_setup_buff) < 0)
1492 ep0stall(udc);
1493 spin_lock(&udc->lock);
1494 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1495 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1496 /*
1497 * If the data stage is IN, send status prime immediately.
1498 * See 2.0 Spec chapter 8.5.3.3 for detail.
1499 */
1500 if (udc->ep0_state == DATA_STATE_XMIT)
1501 if (ep0_prime_status(udc, EP_DIR_OUT))
1502 ep0stall(udc);
1503
1504 } else {
1505 /* No data phase, IN status from gadget */
1506 udc->ep0_dir = USB_DIR_IN;
1507 spin_unlock(&udc->lock);
1508 if (udc->driver->setup(&udc->gadget,
1509 &udc->local_setup_buff) < 0)
1510 ep0stall(udc);
1511 spin_lock(&udc->lock);
1512 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1513 }
1514 }
1515
1516 /* Process request for Data or Status phase of ep0
1517 * prime status phase if needed */
ep0_req_complete(struct fsl_udc * udc,struct fsl_ep * ep0,struct fsl_req * req)1518 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1519 struct fsl_req *req)
1520 {
1521 if (udc->usb_state == USB_STATE_ADDRESS) {
1522 /* Set the new address */
1523 u32 new_address = (u32) udc->device_address;
1524 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1525 &dr_regs->deviceaddr);
1526 }
1527
1528 done(ep0, req, 0);
1529
1530 switch (udc->ep0_state) {
1531 case DATA_STATE_XMIT:
1532 /* already primed at setup_received_irq */
1533 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1534 break;
1535 case DATA_STATE_RECV:
1536 /* send status phase */
1537 if (ep0_prime_status(udc, EP_DIR_IN))
1538 ep0stall(udc);
1539 break;
1540 case WAIT_FOR_OUT_STATUS:
1541 udc->ep0_state = WAIT_FOR_SETUP;
1542 break;
1543 case WAIT_FOR_SETUP:
1544 ERR("Unexpected ep0 packets\n");
1545 break;
1546 default:
1547 ep0stall(udc);
1548 break;
1549 }
1550 }
1551
1552 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1553 * being corrupted by another incoming setup packet */
tripwire_handler(struct fsl_udc * udc,u8 ep_num,u8 * buffer_ptr)1554 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1555 {
1556 u32 temp;
1557 struct ep_queue_head *qh;
1558 struct fsl_usb2_platform_data *pdata = udc->pdata;
1559
1560 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1561
1562 /* Clear bit in ENDPTSETUPSTAT */
1563 temp = fsl_readl(&dr_regs->endptsetupstat);
1564 fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1565
1566 /* while a hazard exists when setup package arrives */
1567 do {
1568 /* Set Setup Tripwire */
1569 temp = fsl_readl(&dr_regs->usbcmd);
1570 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1571
1572 /* Copy the setup packet to local buffer */
1573 if (pdata->le_setup_buf) {
1574 u32 *p = (u32 *)buffer_ptr;
1575 u32 *s = (u32 *)qh->setup_buffer;
1576
1577 /* Convert little endian setup buffer to CPU endian */
1578 *p++ = le32_to_cpu(*s++);
1579 *p = le32_to_cpu(*s);
1580 } else {
1581 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1582 }
1583 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1584
1585 /* Clear Setup Tripwire */
1586 temp = fsl_readl(&dr_regs->usbcmd);
1587 fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1588 }
1589
1590 /* process-ep_req(): free the completed Tds for this req */
process_ep_req(struct fsl_udc * udc,int pipe,struct fsl_req * curr_req)1591 static int process_ep_req(struct fsl_udc *udc, int pipe,
1592 struct fsl_req *curr_req)
1593 {
1594 struct ep_td_struct *curr_td;
1595 int actual, remaining_length, j, tmp;
1596 int status = 0;
1597 int errors = 0;
1598 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1599 int direction = pipe % 2;
1600
1601 curr_td = curr_req->head;
1602 actual = curr_req->req.length;
1603
1604 for (j = 0; j < curr_req->dtd_count; j++) {
1605 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1606 & DTD_PACKET_SIZE)
1607 >> DTD_LENGTH_BIT_POS;
1608 actual -= remaining_length;
1609
1610 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1611 if (errors & DTD_ERROR_MASK) {
1612 if (errors & DTD_STATUS_HALTED) {
1613 ERR("dTD error %08x QH=%d\n", errors, pipe);
1614 /* Clear the errors and Halt condition */
1615 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1616 tmp &= ~errors;
1617 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1618 status = -EPIPE;
1619 /* FIXME: continue with next queued TD? */
1620
1621 break;
1622 }
1623 if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1624 VDBG("Transfer overflow");
1625 status = -EPROTO;
1626 break;
1627 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1628 VDBG("ISO error");
1629 status = -EILSEQ;
1630 break;
1631 } else
1632 ERR("Unknown error has occurred (0x%x)!\n",
1633 errors);
1634
1635 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1636 & DTD_STATUS_ACTIVE) {
1637 VDBG("Request not complete");
1638 status = REQ_UNCOMPLETE;
1639 return status;
1640 } else if (remaining_length) {
1641 if (direction) {
1642 VDBG("Transmit dTD remaining length not zero");
1643 status = -EPROTO;
1644 break;
1645 } else {
1646 break;
1647 }
1648 } else {
1649 VDBG("dTD transmitted successful");
1650 }
1651
1652 if (j != curr_req->dtd_count - 1)
1653 curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1654 }
1655
1656 if (status)
1657 return status;
1658
1659 curr_req->req.actual = actual;
1660
1661 return 0;
1662 }
1663
1664 /* Process a DTD completion interrupt */
dtd_complete_irq(struct fsl_udc * udc)1665 static void dtd_complete_irq(struct fsl_udc *udc)
1666 {
1667 u32 bit_pos;
1668 int i, ep_num, direction, bit_mask, status;
1669 struct fsl_ep *curr_ep;
1670 struct fsl_req *curr_req, *temp_req;
1671
1672 /* Clear the bits in the register */
1673 bit_pos = fsl_readl(&dr_regs->endptcomplete);
1674 fsl_writel(bit_pos, &dr_regs->endptcomplete);
1675
1676 if (!bit_pos)
1677 return;
1678
1679 for (i = 0; i < udc->max_ep; i++) {
1680 ep_num = i >> 1;
1681 direction = i % 2;
1682
1683 bit_mask = 1 << (ep_num + 16 * direction);
1684
1685 if (!(bit_pos & bit_mask))
1686 continue;
1687
1688 curr_ep = get_ep_by_pipe(udc, i);
1689
1690 /* If the ep is configured */
1691 if (!curr_ep->ep.name) {
1692 WARNING("Invalid EP?");
1693 continue;
1694 }
1695
1696 /* process the req queue until an uncomplete request */
1697 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1698 queue) {
1699 status = process_ep_req(udc, i, curr_req);
1700
1701 VDBG("status of process_ep_req= %d, ep = %d",
1702 status, ep_num);
1703 if (status == REQ_UNCOMPLETE)
1704 break;
1705 /* write back status to req */
1706 curr_req->req.status = status;
1707
1708 if (ep_num == 0) {
1709 ep0_req_complete(udc, curr_ep, curr_req);
1710 break;
1711 } else
1712 done(curr_ep, curr_req, status);
1713 }
1714 }
1715 }
1716
portscx_device_speed(u32 reg)1717 static inline enum usb_device_speed portscx_device_speed(u32 reg)
1718 {
1719 switch (reg & PORTSCX_PORT_SPEED_MASK) {
1720 case PORTSCX_PORT_SPEED_HIGH:
1721 return USB_SPEED_HIGH;
1722 case PORTSCX_PORT_SPEED_FULL:
1723 return USB_SPEED_FULL;
1724 case PORTSCX_PORT_SPEED_LOW:
1725 return USB_SPEED_LOW;
1726 default:
1727 return USB_SPEED_UNKNOWN;
1728 }
1729 }
1730
1731 /* Process a port change interrupt */
port_change_irq(struct fsl_udc * udc)1732 static void port_change_irq(struct fsl_udc *udc)
1733 {
1734 if (udc->bus_reset)
1735 udc->bus_reset = 0;
1736
1737 /* Bus resetting is finished */
1738 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
1739 /* Get the speed */
1740 udc->gadget.speed =
1741 portscx_device_speed(fsl_readl(&dr_regs->portsc1));
1742
1743 /* Update USB state */
1744 if (!udc->resume_state)
1745 udc->usb_state = USB_STATE_DEFAULT;
1746 }
1747
1748 /* Process suspend interrupt */
suspend_irq(struct fsl_udc * udc)1749 static void suspend_irq(struct fsl_udc *udc)
1750 {
1751 udc->resume_state = udc->usb_state;
1752 udc->usb_state = USB_STATE_SUSPENDED;
1753
1754 /* report suspend to the driver, serial.c does not support this */
1755 if (udc->driver->suspend)
1756 udc->driver->suspend(&udc->gadget);
1757 }
1758
bus_resume(struct fsl_udc * udc)1759 static void bus_resume(struct fsl_udc *udc)
1760 {
1761 udc->usb_state = udc->resume_state;
1762 udc->resume_state = 0;
1763
1764 /* report resume to the driver, serial.c does not support this */
1765 if (udc->driver->resume)
1766 udc->driver->resume(&udc->gadget);
1767 }
1768
1769 /* Clear up all ep queues */
reset_queues(struct fsl_udc * udc,bool bus_reset)1770 static int reset_queues(struct fsl_udc *udc, bool bus_reset)
1771 {
1772 u8 pipe;
1773
1774 for (pipe = 0; pipe < udc->max_pipes; pipe++)
1775 udc_reset_ep_queue(udc, pipe);
1776
1777 /* report disconnect; the driver is already quiesced */
1778 spin_unlock(&udc->lock);
1779 if (bus_reset)
1780 usb_gadget_udc_reset(&udc->gadget, udc->driver);
1781 else
1782 udc->driver->disconnect(&udc->gadget);
1783 spin_lock(&udc->lock);
1784
1785 return 0;
1786 }
1787
1788 /* Process reset interrupt */
reset_irq(struct fsl_udc * udc)1789 static void reset_irq(struct fsl_udc *udc)
1790 {
1791 u32 temp;
1792 unsigned long timeout;
1793
1794 /* Clear the device address */
1795 temp = fsl_readl(&dr_regs->deviceaddr);
1796 fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1797
1798 udc->device_address = 0;
1799
1800 /* Clear usb state */
1801 udc->resume_state = 0;
1802 udc->ep0_dir = 0;
1803 udc->ep0_state = WAIT_FOR_SETUP;
1804 udc->remote_wakeup = 0; /* default to 0 on reset */
1805 udc->gadget.b_hnp_enable = 0;
1806 udc->gadget.a_hnp_support = 0;
1807 udc->gadget.a_alt_hnp_support = 0;
1808
1809 /* Clear all the setup token semaphores */
1810 temp = fsl_readl(&dr_regs->endptsetupstat);
1811 fsl_writel(temp, &dr_regs->endptsetupstat);
1812
1813 /* Clear all the endpoint complete status bits */
1814 temp = fsl_readl(&dr_regs->endptcomplete);
1815 fsl_writel(temp, &dr_regs->endptcomplete);
1816
1817 timeout = jiffies + 100;
1818 while (fsl_readl(&dr_regs->endpointprime)) {
1819 /* Wait until all endptprime bits cleared */
1820 if (time_after(jiffies, timeout)) {
1821 ERR("Timeout for reset\n");
1822 break;
1823 }
1824 cpu_relax();
1825 }
1826
1827 /* Write 1s to the flush register */
1828 fsl_writel(0xffffffff, &dr_regs->endptflush);
1829
1830 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1831 VDBG("Bus reset");
1832 /* Bus is reseting */
1833 udc->bus_reset = 1;
1834 /* Reset all the queues, include XD, dTD, EP queue
1835 * head and TR Queue */
1836 reset_queues(udc, true);
1837 udc->usb_state = USB_STATE_DEFAULT;
1838 } else {
1839 VDBG("Controller reset");
1840 /* initialize usb hw reg except for regs for EP, not
1841 * touch usbintr reg */
1842 dr_controller_setup(udc);
1843
1844 /* Reset all internal used Queues */
1845 reset_queues(udc, false);
1846
1847 ep0_setup(udc);
1848
1849 /* Enable DR IRQ reg, Set Run bit, change udc state */
1850 dr_controller_run(udc);
1851 udc->usb_state = USB_STATE_ATTACHED;
1852 }
1853 }
1854
1855 /*
1856 * USB device controller interrupt handler
1857 */
fsl_udc_irq(int irq,void * _udc)1858 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1859 {
1860 struct fsl_udc *udc = _udc;
1861 u32 irq_src;
1862 irqreturn_t status = IRQ_NONE;
1863 unsigned long flags;
1864
1865 /* Disable ISR for OTG host mode */
1866 if (udc->stopped)
1867 return IRQ_NONE;
1868 spin_lock_irqsave(&udc->lock, flags);
1869 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1870 /* Clear notification bits */
1871 fsl_writel(irq_src, &dr_regs->usbsts);
1872
1873 /* VDBG("irq_src [0x%8x]", irq_src); */
1874
1875 /* Need to resume? */
1876 if (udc->usb_state == USB_STATE_SUSPENDED)
1877 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1878 bus_resume(udc);
1879
1880 /* USB Interrupt */
1881 if (irq_src & USB_STS_INT) {
1882 VDBG("Packet int");
1883 /* Setup package, we only support ep0 as control ep */
1884 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1885 tripwire_handler(udc, 0,
1886 (u8 *) (&udc->local_setup_buff));
1887 setup_received_irq(udc, &udc->local_setup_buff);
1888 status = IRQ_HANDLED;
1889 }
1890
1891 /* completion of dtd */
1892 if (fsl_readl(&dr_regs->endptcomplete)) {
1893 dtd_complete_irq(udc);
1894 status = IRQ_HANDLED;
1895 }
1896 }
1897
1898 /* SOF (for ISO transfer) */
1899 if (irq_src & USB_STS_SOF) {
1900 status = IRQ_HANDLED;
1901 }
1902
1903 /* Port Change */
1904 if (irq_src & USB_STS_PORT_CHANGE) {
1905 port_change_irq(udc);
1906 status = IRQ_HANDLED;
1907 }
1908
1909 /* Reset Received */
1910 if (irq_src & USB_STS_RESET) {
1911 VDBG("reset int");
1912 reset_irq(udc);
1913 status = IRQ_HANDLED;
1914 }
1915
1916 /* Sleep Enable (Suspend) */
1917 if (irq_src & USB_STS_SUSPEND) {
1918 suspend_irq(udc);
1919 status = IRQ_HANDLED;
1920 }
1921
1922 if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1923 VDBG("Error IRQ %x", irq_src);
1924 }
1925
1926 spin_unlock_irqrestore(&udc->lock, flags);
1927 return status;
1928 }
1929
1930 /*----------------------------------------------------------------*
1931 * Hook to gadget drivers
1932 * Called by initialization code of gadget drivers
1933 *----------------------------------------------------------------*/
fsl_udc_start(struct usb_gadget * g,struct usb_gadget_driver * driver)1934 static int fsl_udc_start(struct usb_gadget *g,
1935 struct usb_gadget_driver *driver)
1936 {
1937 int retval = 0;
1938 unsigned long flags;
1939
1940 /* lock is needed but whether should use this lock or another */
1941 spin_lock_irqsave(&udc_controller->lock, flags);
1942
1943 driver->driver.bus = NULL;
1944 /* hook up the driver */
1945 udc_controller->driver = driver;
1946 spin_unlock_irqrestore(&udc_controller->lock, flags);
1947 g->is_selfpowered = 1;
1948
1949 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1950 /* Suspend the controller until OTG enable it */
1951 udc_controller->stopped = 1;
1952 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1953
1954 /* connect to bus through transceiver */
1955 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1956 retval = otg_set_peripheral(
1957 udc_controller->transceiver->otg,
1958 &udc_controller->gadget);
1959 if (retval < 0) {
1960 ERR("can't bind to transceiver\n");
1961 udc_controller->driver = NULL;
1962 return retval;
1963 }
1964 }
1965 } else {
1966 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1967 dr_controller_run(udc_controller);
1968 udc_controller->usb_state = USB_STATE_ATTACHED;
1969 udc_controller->ep0_state = WAIT_FOR_SETUP;
1970 udc_controller->ep0_dir = 0;
1971 }
1972
1973 return retval;
1974 }
1975
1976 /* Disconnect from gadget driver */
fsl_udc_stop(struct usb_gadget * g)1977 static int fsl_udc_stop(struct usb_gadget *g)
1978 {
1979 struct fsl_ep *loop_ep;
1980 unsigned long flags;
1981
1982 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
1983 otg_set_peripheral(udc_controller->transceiver->otg, NULL);
1984
1985 /* stop DR, disable intr */
1986 dr_controller_stop(udc_controller);
1987
1988 /* in fact, no needed */
1989 udc_controller->usb_state = USB_STATE_ATTACHED;
1990 udc_controller->ep0_state = WAIT_FOR_SETUP;
1991 udc_controller->ep0_dir = 0;
1992
1993 /* stand operation */
1994 spin_lock_irqsave(&udc_controller->lock, flags);
1995 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
1996 nuke(&udc_controller->eps[0], -ESHUTDOWN);
1997 list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
1998 ep.ep_list)
1999 nuke(loop_ep, -ESHUTDOWN);
2000 spin_unlock_irqrestore(&udc_controller->lock, flags);
2001
2002 udc_controller->driver = NULL;
2003
2004 return 0;
2005 }
2006
2007 /*-------------------------------------------------------------------------
2008 PROC File System Support
2009 -------------------------------------------------------------------------*/
2010 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2011
2012 #include <linux/seq_file.h>
2013
2014 static const char proc_filename[] = "driver/fsl_usb2_udc";
2015
fsl_proc_read(struct seq_file * m,void * v)2016 static int fsl_proc_read(struct seq_file *m, void *v)
2017 {
2018 unsigned long flags;
2019 int i;
2020 u32 tmp_reg;
2021 struct fsl_ep *ep = NULL;
2022 struct fsl_req *req;
2023
2024 struct fsl_udc *udc = udc_controller;
2025
2026 spin_lock_irqsave(&udc->lock, flags);
2027
2028 /* ------basic driver information ---- */
2029 seq_printf(m,
2030 DRIVER_DESC "\n"
2031 "%s version: %s\n"
2032 "Gadget driver: %s\n\n",
2033 driver_name, DRIVER_VERSION,
2034 udc->driver ? udc->driver->driver.name : "(none)");
2035
2036 /* ------ DR Registers ----- */
2037 tmp_reg = fsl_readl(&dr_regs->usbcmd);
2038 seq_printf(m,
2039 "USBCMD reg:\n"
2040 "SetupTW: %d\n"
2041 "Run/Stop: %s\n\n",
2042 (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2043 (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2044
2045 tmp_reg = fsl_readl(&dr_regs->usbsts);
2046 seq_printf(m,
2047 "USB Status Reg:\n"
2048 "Dr Suspend: %d Reset Received: %d System Error: %s "
2049 "USB Error Interrupt: %s\n\n",
2050 (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2051 (tmp_reg & USB_STS_RESET) ? 1 : 0,
2052 (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2053 (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2054
2055 tmp_reg = fsl_readl(&dr_regs->usbintr);
2056 seq_printf(m,
2057 "USB Interrupt Enable Reg:\n"
2058 "Sleep Enable: %d SOF Received Enable: %d "
2059 "Reset Enable: %d\n"
2060 "System Error Enable: %d "
2061 "Port Change Detected Enable: %d\n"
2062 "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2063 (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2064 (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2065 (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2066 (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2067 (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2068 (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2069 (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2070
2071 tmp_reg = fsl_readl(&dr_regs->frindex);
2072 seq_printf(m,
2073 "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2074 (tmp_reg & USB_FRINDEX_MASKS));
2075
2076 tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2077 seq_printf(m,
2078 "USB Device Address Reg: Device Addr is 0x%x\n\n",
2079 (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2080
2081 tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2082 seq_printf(m,
2083 "USB Endpoint List Address Reg: "
2084 "Device Addr is 0x%x\n\n",
2085 (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2086
2087 tmp_reg = fsl_readl(&dr_regs->portsc1);
2088 seq_printf(m,
2089 "USB Port Status&Control Reg:\n"
2090 "Port Transceiver Type : %s Port Speed: %s\n"
2091 "PHY Low Power Suspend: %s Port Reset: %s "
2092 "Port Suspend Mode: %s\n"
2093 "Over-current Change: %s "
2094 "Port Enable/Disable Change: %s\n"
2095 "Port Enabled/Disabled: %s "
2096 "Current Connect Status: %s\n\n", ( {
2097 const char *s;
2098 switch (tmp_reg & PORTSCX_PTS_FSLS) {
2099 case PORTSCX_PTS_UTMI:
2100 s = "UTMI"; break;
2101 case PORTSCX_PTS_ULPI:
2102 s = "ULPI "; break;
2103 case PORTSCX_PTS_FSLS:
2104 s = "FS/LS Serial"; break;
2105 default:
2106 s = "None"; break;
2107 }
2108 s;} ),
2109 usb_speed_string(portscx_device_speed(tmp_reg)),
2110 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2111 "Normal PHY mode" : "Low power mode",
2112 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2113 "Not in Reset",
2114 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2115 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2116 "No",
2117 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2118 "Not change",
2119 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2120 "Not correct",
2121 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2122 "Attached" : "Not-Att");
2123
2124 tmp_reg = fsl_readl(&dr_regs->usbmode);
2125 seq_printf(m,
2126 "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2127 const char *s;
2128 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2129 case USB_MODE_CTRL_MODE_IDLE:
2130 s = "Idle"; break;
2131 case USB_MODE_CTRL_MODE_DEVICE:
2132 s = "Device Controller"; break;
2133 case USB_MODE_CTRL_MODE_HOST:
2134 s = "Host Controller"; break;
2135 default:
2136 s = "None"; break;
2137 }
2138 s;
2139 } ));
2140
2141 tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2142 seq_printf(m,
2143 "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2144 (tmp_reg & EP_SETUP_STATUS_MASK));
2145
2146 for (i = 0; i < udc->max_ep / 2; i++) {
2147 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2148 seq_printf(m, "EP Ctrl Reg [0x%x]: = [0x%x]\n", i, tmp_reg);
2149 }
2150 tmp_reg = fsl_readl(&dr_regs->endpointprime);
2151 seq_printf(m, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2152
2153 if (udc->pdata->have_sysif_regs) {
2154 tmp_reg = usb_sys_regs->snoop1;
2155 seq_printf(m, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2156
2157 tmp_reg = usb_sys_regs->control;
2158 seq_printf(m, "General Control Reg : = [0x%x]\n\n", tmp_reg);
2159 }
2160
2161 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2162 ep = &udc->eps[0];
2163 seq_printf(m, "For %s Maxpkt is 0x%x index is 0x%x\n",
2164 ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2165
2166 if (list_empty(&ep->queue)) {
2167 seq_puts(m, "its req queue is empty\n\n");
2168 } else {
2169 list_for_each_entry(req, &ep->queue, queue) {
2170 seq_printf(m,
2171 "req %p actual 0x%x length 0x%x buf %p\n",
2172 &req->req, req->req.actual,
2173 req->req.length, req->req.buf);
2174 }
2175 }
2176 /* other gadget->eplist ep */
2177 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2178 if (ep->ep.desc) {
2179 seq_printf(m,
2180 "\nFor %s Maxpkt is 0x%x "
2181 "index is 0x%x\n",
2182 ep->ep.name, ep_maxpacket(ep),
2183 ep_index(ep));
2184
2185 if (list_empty(&ep->queue)) {
2186 seq_puts(m, "its req queue is empty\n\n");
2187 } else {
2188 list_for_each_entry(req, &ep->queue, queue) {
2189 seq_printf(m,
2190 "req %p actual 0x%x length "
2191 "0x%x buf %p\n",
2192 &req->req, req->req.actual,
2193 req->req.length, req->req.buf);
2194 } /* end for each_entry of ep req */
2195 } /* end for else */
2196 } /* end for if(ep->queue) */
2197 } /* end (ep->desc) */
2198
2199 spin_unlock_irqrestore(&udc->lock, flags);
2200 return 0;
2201 }
2202
2203 #define create_proc_file() \
2204 proc_create_single(proc_filename, 0, NULL, fsl_proc_read)
2205 #define remove_proc_file() remove_proc_entry(proc_filename, NULL)
2206
2207 #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
2208
2209 #define create_proc_file() do {} while (0)
2210 #define remove_proc_file() do {} while (0)
2211
2212 #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
2213
2214 /*-------------------------------------------------------------------------*/
2215
2216 /* Release udc structures */
fsl_udc_release(struct device * dev)2217 static void fsl_udc_release(struct device *dev)
2218 {
2219 complete(udc_controller->done);
2220 dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2221 udc_controller->ep_qh, udc_controller->ep_qh_dma);
2222 kfree(udc_controller);
2223 }
2224
2225 /******************************************************************
2226 Internal structure setup functions
2227 *******************************************************************/
2228 /*------------------------------------------------------------------
2229 * init resource for global controller called by fsl_udc_probe()
2230 * On success the udc handle is initialized, on failure it is
2231 * unchanged (reset).
2232 * Return 0 on success and -1 on allocation failure
2233 ------------------------------------------------------------------*/
struct_udc_setup(struct fsl_udc * udc,struct platform_device * pdev)2234 static int struct_udc_setup(struct fsl_udc *udc,
2235 struct platform_device *pdev)
2236 {
2237 struct fsl_usb2_platform_data *pdata;
2238 size_t size;
2239
2240 pdata = dev_get_platdata(&pdev->dev);
2241 udc->phy_mode = pdata->phy_mode;
2242
2243 udc->eps = kcalloc(udc->max_ep, sizeof(struct fsl_ep), GFP_KERNEL);
2244 if (!udc->eps) {
2245 ERR("kmalloc udc endpoint status failed\n");
2246 goto eps_alloc_failed;
2247 }
2248
2249 /* initialized QHs, take care of alignment */
2250 size = udc->max_ep * sizeof(struct ep_queue_head);
2251 if (size < QH_ALIGNMENT)
2252 size = QH_ALIGNMENT;
2253 else if ((size % QH_ALIGNMENT) != 0) {
2254 size += QH_ALIGNMENT + 1;
2255 size &= ~(QH_ALIGNMENT - 1);
2256 }
2257 udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2258 &udc->ep_qh_dma, GFP_KERNEL);
2259 if (!udc->ep_qh) {
2260 ERR("malloc QHs for udc failed\n");
2261 goto ep_queue_alloc_failed;
2262 }
2263
2264 udc->ep_qh_size = size;
2265
2266 /* Initialize ep0 status request structure */
2267 /* FIXME: fsl_alloc_request() ignores ep argument */
2268 udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2269 struct fsl_req, req);
2270 if (!udc->status_req) {
2271 ERR("kzalloc for udc status request failed\n");
2272 goto udc_status_alloc_failed;
2273 }
2274
2275 /* allocate a small amount of memory to get valid address */
2276 udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2277 if (!udc->status_req->req.buf) {
2278 ERR("kzalloc for udc request buffer failed\n");
2279 goto udc_req_buf_alloc_failed;
2280 }
2281
2282 udc->resume_state = USB_STATE_NOTATTACHED;
2283 udc->usb_state = USB_STATE_POWERED;
2284 udc->ep0_dir = 0;
2285 udc->remote_wakeup = 0; /* default to 0 on reset */
2286
2287 return 0;
2288
2289 udc_req_buf_alloc_failed:
2290 kfree(udc->status_req);
2291 udc_status_alloc_failed:
2292 kfree(udc->ep_qh);
2293 udc->ep_qh_size = 0;
2294 ep_queue_alloc_failed:
2295 kfree(udc->eps);
2296 eps_alloc_failed:
2297 udc->phy_mode = 0;
2298 return -1;
2299
2300 }
2301
2302 /*----------------------------------------------------------------
2303 * Setup the fsl_ep struct for eps
2304 * Link fsl_ep->ep to gadget->ep_list
2305 * ep0out is not used so do nothing here
2306 * ep0in should be taken care
2307 *--------------------------------------------------------------*/
struct_ep_setup(struct fsl_udc * udc,unsigned char index,char * name,int link)2308 static int struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2309 char *name, int link)
2310 {
2311 struct fsl_ep *ep = &udc->eps[index];
2312
2313 ep->udc = udc;
2314 strcpy(ep->name, name);
2315 ep->ep.name = ep->name;
2316
2317 ep->ep.ops = &fsl_ep_ops;
2318 ep->stopped = 0;
2319
2320 if (index == 0) {
2321 ep->ep.caps.type_control = true;
2322 } else {
2323 ep->ep.caps.type_iso = true;
2324 ep->ep.caps.type_bulk = true;
2325 ep->ep.caps.type_int = true;
2326 }
2327
2328 if (index & 1)
2329 ep->ep.caps.dir_in = true;
2330 else
2331 ep->ep.caps.dir_out = true;
2332
2333 /* for ep0: maxP defined in desc
2334 * for other eps, maxP is set by epautoconfig() called by gadget layer
2335 */
2336 usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
2337
2338 /* the queue lists any req for this ep */
2339 INIT_LIST_HEAD(&ep->queue);
2340
2341 /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2342 if (link)
2343 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2344 ep->gadget = &udc->gadget;
2345 ep->qh = &udc->ep_qh[index];
2346
2347 return 0;
2348 }
2349
2350 /* Driver probe function
2351 * all initialization operations implemented here except enabling usb_intr reg
2352 * board setup should have been done in the platform code
2353 */
fsl_udc_probe(struct platform_device * pdev)2354 static int fsl_udc_probe(struct platform_device *pdev)
2355 {
2356 struct fsl_usb2_platform_data *pdata;
2357 struct resource *res;
2358 int ret = -ENODEV;
2359 unsigned int i;
2360 u32 dccparams;
2361
2362 udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2363 if (udc_controller == NULL)
2364 return -ENOMEM;
2365
2366 pdata = dev_get_platdata(&pdev->dev);
2367 udc_controller->pdata = pdata;
2368 spin_lock_init(&udc_controller->lock);
2369 udc_controller->stopped = 1;
2370
2371 #ifdef CONFIG_USB_OTG
2372 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2373 udc_controller->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
2374 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2375 ERR("Can't find OTG driver!\n");
2376 ret = -ENODEV;
2377 goto err_kfree;
2378 }
2379 }
2380 #endif
2381
2382 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2383 if (!res) {
2384 ret = -ENXIO;
2385 goto err_kfree;
2386 }
2387
2388 if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2389 if (!request_mem_region(res->start, resource_size(res),
2390 driver_name)) {
2391 ERR("request mem region for %s failed\n", pdev->name);
2392 ret = -EBUSY;
2393 goto err_kfree;
2394 }
2395 }
2396
2397 dr_regs = ioremap(res->start, resource_size(res));
2398 if (!dr_regs) {
2399 ret = -ENOMEM;
2400 goto err_release_mem_region;
2401 }
2402
2403 pdata->regs = (void __iomem *)dr_regs;
2404
2405 /*
2406 * do platform specific init: check the clock, grab/config pins, etc.
2407 */
2408 if (pdata->init && pdata->init(pdev)) {
2409 ret = -ENODEV;
2410 goto err_iounmap;
2411 }
2412
2413 /* Set accessors only after pdata->init() ! */
2414 fsl_set_accessors(pdata);
2415
2416 if (pdata->have_sysif_regs)
2417 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
2418
2419 /* Read Device Controller Capability Parameters register */
2420 dccparams = fsl_readl(&dr_regs->dccparams);
2421 if (!(dccparams & DCCPARAMS_DC)) {
2422 ERR("This SOC doesn't support device role\n");
2423 ret = -ENODEV;
2424 goto err_exit;
2425 }
2426 /* Get max device endpoints */
2427 /* DEN is bidirectional ep number, max_ep doubles the number */
2428 udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2429
2430 ret = platform_get_irq(pdev, 0);
2431 if (ret <= 0) {
2432 ret = ret ? : -ENODEV;
2433 goto err_exit;
2434 }
2435 udc_controller->irq = ret;
2436
2437 ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2438 driver_name, udc_controller);
2439 if (ret != 0) {
2440 ERR("cannot request irq %d err %d\n",
2441 udc_controller->irq, ret);
2442 goto err_exit;
2443 }
2444
2445 /* Initialize the udc structure including QH member and other member */
2446 if (struct_udc_setup(udc_controller, pdev)) {
2447 ERR("Can't initialize udc data structure\n");
2448 ret = -ENOMEM;
2449 goto err_free_irq;
2450 }
2451
2452 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2453 /* initialize usb hw reg except for regs for EP,
2454 * leave usbintr reg untouched */
2455 dr_controller_setup(udc_controller);
2456 }
2457
2458 /* Setup gadget structure */
2459 udc_controller->gadget.ops = &fsl_gadget_ops;
2460 udc_controller->gadget.max_speed = USB_SPEED_HIGH;
2461 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2462 INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2463 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2464 udc_controller->gadget.name = driver_name;
2465
2466 /* Setup gadget.dev and register with kernel */
2467 dev_set_name(&udc_controller->gadget.dev, "gadget");
2468 udc_controller->gadget.dev.of_node = pdev->dev.of_node;
2469
2470 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
2471 udc_controller->gadget.is_otg = 1;
2472
2473 /* setup QH and epctrl for ep0 */
2474 ep0_setup(udc_controller);
2475
2476 /* setup udc->eps[] for ep0 */
2477 struct_ep_setup(udc_controller, 0, "ep0", 0);
2478 /* for ep0: the desc defined here;
2479 * for other eps, gadget layer called ep_enable with defined desc
2480 */
2481 udc_controller->eps[0].ep.desc = &fsl_ep0_desc;
2482 usb_ep_set_maxpacket_limit(&udc_controller->eps[0].ep,
2483 USB_MAX_CTRL_PAYLOAD);
2484
2485 /* setup the udc->eps[] for non-control endpoints and link
2486 * to gadget.ep_list */
2487 for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2488 char name[14];
2489
2490 sprintf(name, "ep%dout", i);
2491 struct_ep_setup(udc_controller, i * 2, name, 1);
2492 sprintf(name, "ep%din", i);
2493 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2494 }
2495
2496 /* use dma_pool for TD management */
2497 udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2498 sizeof(struct ep_td_struct),
2499 DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2500 if (udc_controller->td_pool == NULL) {
2501 ret = -ENOMEM;
2502 goto err_free_irq;
2503 }
2504
2505 ret = usb_add_gadget_udc_release(&pdev->dev, &udc_controller->gadget,
2506 fsl_udc_release);
2507 if (ret)
2508 goto err_del_udc;
2509
2510 create_proc_file();
2511 return 0;
2512
2513 err_del_udc:
2514 dma_pool_destroy(udc_controller->td_pool);
2515 err_free_irq:
2516 free_irq(udc_controller->irq, udc_controller);
2517 err_exit:
2518 if (pdata->exit)
2519 pdata->exit(pdev);
2520 err_iounmap:
2521 iounmap(dr_regs);
2522 err_release_mem_region:
2523 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2524 release_mem_region(res->start, resource_size(res));
2525 err_kfree:
2526 kfree(udc_controller);
2527 udc_controller = NULL;
2528 return ret;
2529 }
2530
2531 /* Driver removal function
2532 * Free resources and finish pending transactions
2533 */
fsl_udc_remove(struct platform_device * pdev)2534 static int fsl_udc_remove(struct platform_device *pdev)
2535 {
2536 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2537 struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
2538
2539 DECLARE_COMPLETION_ONSTACK(done);
2540
2541 if (!udc_controller)
2542 return -ENODEV;
2543
2544 udc_controller->done = &done;
2545 usb_del_gadget_udc(&udc_controller->gadget);
2546
2547 /* DR has been stopped in usb_gadget_unregister_driver() */
2548 remove_proc_file();
2549
2550 /* Free allocated memory */
2551 kfree(udc_controller->status_req->req.buf);
2552 kfree(udc_controller->status_req);
2553 kfree(udc_controller->eps);
2554
2555 dma_pool_destroy(udc_controller->td_pool);
2556 free_irq(udc_controller->irq, udc_controller);
2557 iounmap(dr_regs);
2558 if (res && (pdata->operating_mode == FSL_USB2_DR_DEVICE))
2559 release_mem_region(res->start, resource_size(res));
2560
2561 /* free udc --wait for the release() finished */
2562 wait_for_completion(&done);
2563
2564 /*
2565 * do platform specific un-initialization:
2566 * release iomux pins, etc.
2567 */
2568 if (pdata->exit)
2569 pdata->exit(pdev);
2570
2571 return 0;
2572 }
2573
2574 /*-----------------------------------------------------------------
2575 * Modify Power management attributes
2576 * Used by OTG statemachine to disable gadget temporarily
2577 -----------------------------------------------------------------*/
fsl_udc_suspend(struct platform_device * pdev,pm_message_t state)2578 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2579 {
2580 dr_controller_stop(udc_controller);
2581 return 0;
2582 }
2583
2584 /*-----------------------------------------------------------------
2585 * Invoked on USB resume. May be called in_interrupt.
2586 * Here we start the DR controller and enable the irq
2587 *-----------------------------------------------------------------*/
fsl_udc_resume(struct platform_device * pdev)2588 static int fsl_udc_resume(struct platform_device *pdev)
2589 {
2590 /* Enable DR irq reg and set controller Run */
2591 if (udc_controller->stopped) {
2592 dr_controller_setup(udc_controller);
2593 dr_controller_run(udc_controller);
2594 }
2595 udc_controller->usb_state = USB_STATE_ATTACHED;
2596 udc_controller->ep0_state = WAIT_FOR_SETUP;
2597 udc_controller->ep0_dir = 0;
2598 return 0;
2599 }
2600
fsl_udc_otg_suspend(struct device * dev,pm_message_t state)2601 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2602 {
2603 struct fsl_udc *udc = udc_controller;
2604 u32 mode, usbcmd;
2605
2606 mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2607
2608 pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2609
2610 /*
2611 * If the controller is already stopped, then this must be a
2612 * PM suspend. Remember this fact, so that we will leave the
2613 * controller stopped at PM resume time.
2614 */
2615 if (udc->stopped) {
2616 pr_debug("gadget already stopped, leaving early\n");
2617 udc->already_stopped = 1;
2618 return 0;
2619 }
2620
2621 if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2622 pr_debug("gadget not in device mode, leaving early\n");
2623 return 0;
2624 }
2625
2626 /* stop the controller */
2627 usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2628 fsl_writel(usbcmd, &dr_regs->usbcmd);
2629
2630 udc->stopped = 1;
2631
2632 pr_info("USB Gadget suspended\n");
2633
2634 return 0;
2635 }
2636
fsl_udc_otg_resume(struct device * dev)2637 static int fsl_udc_otg_resume(struct device *dev)
2638 {
2639 pr_debug("%s(): stopped %d already_stopped %d\n", __func__,
2640 udc_controller->stopped, udc_controller->already_stopped);
2641
2642 /*
2643 * If the controller was stopped at suspend time, then
2644 * don't resume it now.
2645 */
2646 if (udc_controller->already_stopped) {
2647 udc_controller->already_stopped = 0;
2648 pr_debug("gadget was already stopped, leaving early\n");
2649 return 0;
2650 }
2651
2652 pr_info("USB Gadget resume\n");
2653
2654 return fsl_udc_resume(NULL);
2655 }
2656 /*-------------------------------------------------------------------------
2657 Register entry point for the peripheral controller driver
2658 --------------------------------------------------------------------------*/
2659 static const struct platform_device_id fsl_udc_devtype[] = {
2660 {
2661 .name = "fsl-usb2-udc",
2662 }, {
2663 /* sentinel */
2664 }
2665 };
2666 MODULE_DEVICE_TABLE(platform, fsl_udc_devtype);
2667 static struct platform_driver udc_driver = {
2668 .remove = fsl_udc_remove,
2669 .id_table = fsl_udc_devtype,
2670 /* these suspend and resume are not usb suspend and resume */
2671 .suspend = fsl_udc_suspend,
2672 .resume = fsl_udc_resume,
2673 .driver = {
2674 .name = driver_name,
2675 /* udc suspend/resume called from OTG driver */
2676 .suspend = fsl_udc_otg_suspend,
2677 .resume = fsl_udc_otg_resume,
2678 },
2679 };
2680
2681 module_platform_driver_probe(udc_driver, fsl_udc_probe);
2682
2683 MODULE_DESCRIPTION(DRIVER_DESC);
2684 MODULE_AUTHOR(DRIVER_AUTHOR);
2685 MODULE_LICENSE("GPL");
2686 MODULE_ALIAS("platform:fsl-usb2-udc");
2687
