1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * ***************************************************************************
4 * Marvell Armada-3700 Serial Driver
5 * Author: Wilson Ding <dingwei@marvell.com>
6 * Copyright (C) 2015 Marvell International Ltd.
7 * ***************************************************************************
8 */
9
10 #include <linux/clk.h>
11 #include <linux/console.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/init.h>
15 #include <linux/io.h>
16 #include <linux/iopoll.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/serial.h>
24 #include <linux/serial_core.h>
25 #include <linux/slab.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28
29 /* Register Map */
30 #define UART_STD_RBR 0x00
31 #define UART_EXT_RBR 0x18
32
33 #define UART_STD_TSH 0x04
34 #define UART_EXT_TSH 0x1C
35
36 #define UART_STD_CTRL1 0x08
37 #define UART_EXT_CTRL1 0x04
38 #define CTRL_SOFT_RST BIT(31)
39 #define CTRL_TXFIFO_RST BIT(15)
40 #define CTRL_RXFIFO_RST BIT(14)
41 #define CTRL_SND_BRK_SEQ BIT(11)
42 #define CTRL_BRK_DET_INT BIT(3)
43 #define CTRL_FRM_ERR_INT BIT(2)
44 #define CTRL_PAR_ERR_INT BIT(1)
45 #define CTRL_OVR_ERR_INT BIT(0)
46 #define CTRL_BRK_INT (CTRL_BRK_DET_INT | CTRL_FRM_ERR_INT | \
47 CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT)
48
49 #define UART_STD_CTRL2 UART_STD_CTRL1
50 #define UART_EXT_CTRL2 0x20
51 #define CTRL_STD_TX_RDY_INT BIT(5)
52 #define CTRL_EXT_TX_RDY_INT BIT(6)
53 #define CTRL_STD_RX_RDY_INT BIT(4)
54 #define CTRL_EXT_RX_RDY_INT BIT(5)
55
56 #define UART_STAT 0x0C
57 #define STAT_TX_FIFO_EMP BIT(13)
58 #define STAT_TX_FIFO_FUL BIT(11)
59 #define STAT_TX_EMP BIT(6)
60 #define STAT_STD_TX_RDY BIT(5)
61 #define STAT_EXT_TX_RDY BIT(15)
62 #define STAT_STD_RX_RDY BIT(4)
63 #define STAT_EXT_RX_RDY BIT(14)
64 #define STAT_BRK_DET BIT(3)
65 #define STAT_FRM_ERR BIT(2)
66 #define STAT_PAR_ERR BIT(1)
67 #define STAT_OVR_ERR BIT(0)
68 #define STAT_BRK_ERR (STAT_BRK_DET | STAT_FRM_ERR \
69 | STAT_PAR_ERR | STAT_OVR_ERR)
70
71 #define UART_BRDV 0x10
72 #define BRDV_BAUD_MASK 0x3FF
73
74 #define UART_OSAMP 0x14
75 #define OSAMP_DEFAULT_DIVISOR 16
76 #define OSAMP_DIVISORS_MASK 0x3F3F3F3F
77
78 #define MVEBU_NR_UARTS 2
79
80 #define MVEBU_UART_TYPE "mvebu-uart"
81 #define DRIVER_NAME "mvebu_serial"
82
83 enum {
84 /* Either there is only one summed IRQ... */
85 UART_IRQ_SUM = 0,
86 /* ...or there are two separate IRQ for RX and TX */
87 UART_RX_IRQ = 0,
88 UART_TX_IRQ,
89 UART_IRQ_COUNT
90 };
91
92 /* Diverging register offsets */
93 struct uart_regs_layout {
94 unsigned int rbr;
95 unsigned int tsh;
96 unsigned int ctrl;
97 unsigned int intr;
98 };
99
100 /* Diverging flags */
101 struct uart_flags {
102 unsigned int ctrl_tx_rdy_int;
103 unsigned int ctrl_rx_rdy_int;
104 unsigned int stat_tx_rdy;
105 unsigned int stat_rx_rdy;
106 };
107
108 /* Driver data, a structure for each UART port */
109 struct mvebu_uart_driver_data {
110 bool is_ext;
111 struct uart_regs_layout regs;
112 struct uart_flags flags;
113 };
114
115 /* Saved registers during suspend */
116 struct mvebu_uart_pm_regs {
117 unsigned int rbr;
118 unsigned int tsh;
119 unsigned int ctrl;
120 unsigned int intr;
121 unsigned int stat;
122 unsigned int brdv;
123 unsigned int osamp;
124 };
125
126 /* MVEBU UART driver structure */
127 struct mvebu_uart {
128 struct uart_port *port;
129 struct clk *clk;
130 int irq[UART_IRQ_COUNT];
131 struct mvebu_uart_driver_data *data;
132 #if defined(CONFIG_PM)
133 struct mvebu_uart_pm_regs pm_regs;
134 #endif /* CONFIG_PM */
135 };
136
to_mvuart(struct uart_port * port)137 static struct mvebu_uart *to_mvuart(struct uart_port *port)
138 {
139 return (struct mvebu_uart *)port->private_data;
140 }
141
142 #define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext)
143
144 #define UART_RBR(port) (to_mvuart(port)->data->regs.rbr)
145 #define UART_TSH(port) (to_mvuart(port)->data->regs.tsh)
146 #define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl)
147 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr)
148
149 #define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int)
150 #define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int)
151 #define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy)
152 #define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy)
153
154 static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS];
155
156 /* Core UART Driver Operations */
mvebu_uart_tx_empty(struct uart_port * port)157 static unsigned int mvebu_uart_tx_empty(struct uart_port *port)
158 {
159 unsigned long flags;
160 unsigned int st;
161
162 spin_lock_irqsave(&port->lock, flags);
163 st = readl(port->membase + UART_STAT);
164 spin_unlock_irqrestore(&port->lock, flags);
165
166 return (st & STAT_TX_EMP) ? TIOCSER_TEMT : 0;
167 }
168
mvebu_uart_get_mctrl(struct uart_port * port)169 static unsigned int mvebu_uart_get_mctrl(struct uart_port *port)
170 {
171 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
172 }
173
mvebu_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)174 static void mvebu_uart_set_mctrl(struct uart_port *port,
175 unsigned int mctrl)
176 {
177 /*
178 * Even if we do not support configuring the modem control lines, this
179 * function must be proided to the serial core
180 */
181 }
182
mvebu_uart_stop_tx(struct uart_port * port)183 static void mvebu_uart_stop_tx(struct uart_port *port)
184 {
185 unsigned int ctl = readl(port->membase + UART_INTR(port));
186
187 ctl &= ~CTRL_TX_RDY_INT(port);
188 writel(ctl, port->membase + UART_INTR(port));
189 }
190
mvebu_uart_start_tx(struct uart_port * port)191 static void mvebu_uart_start_tx(struct uart_port *port)
192 {
193 unsigned int ctl;
194 struct circ_buf *xmit = &port->state->xmit;
195
196 if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) {
197 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
198 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
199 port->icount.tx++;
200 }
201
202 ctl = readl(port->membase + UART_INTR(port));
203 ctl |= CTRL_TX_RDY_INT(port);
204 writel(ctl, port->membase + UART_INTR(port));
205 }
206
mvebu_uart_stop_rx(struct uart_port * port)207 static void mvebu_uart_stop_rx(struct uart_port *port)
208 {
209 unsigned int ctl;
210
211 ctl = readl(port->membase + UART_CTRL(port));
212 ctl &= ~CTRL_BRK_INT;
213 writel(ctl, port->membase + UART_CTRL(port));
214
215 ctl = readl(port->membase + UART_INTR(port));
216 ctl &= ~CTRL_RX_RDY_INT(port);
217 writel(ctl, port->membase + UART_INTR(port));
218 }
219
mvebu_uart_break_ctl(struct uart_port * port,int brk)220 static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
221 {
222 unsigned int ctl;
223 unsigned long flags;
224
225 spin_lock_irqsave(&port->lock, flags);
226 ctl = readl(port->membase + UART_CTRL(port));
227 if (brk == -1)
228 ctl |= CTRL_SND_BRK_SEQ;
229 else
230 ctl &= ~CTRL_SND_BRK_SEQ;
231 writel(ctl, port->membase + UART_CTRL(port));
232 spin_unlock_irqrestore(&port->lock, flags);
233 }
234
mvebu_uart_rx_chars(struct uart_port * port,unsigned int status)235 static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
236 {
237 struct tty_port *tport = &port->state->port;
238 unsigned char ch = 0;
239 char flag = 0;
240
241 do {
242 if (status & STAT_RX_RDY(port)) {
243 ch = readl(port->membase + UART_RBR(port));
244 ch &= 0xff;
245 flag = TTY_NORMAL;
246 port->icount.rx++;
247
248 if (status & STAT_PAR_ERR)
249 port->icount.parity++;
250 }
251
252 if (status & STAT_BRK_DET) {
253 port->icount.brk++;
254 status &= ~(STAT_FRM_ERR | STAT_PAR_ERR);
255 if (uart_handle_break(port))
256 goto ignore_char;
257 }
258
259 if (status & STAT_OVR_ERR)
260 port->icount.overrun++;
261
262 if (status & STAT_FRM_ERR)
263 port->icount.frame++;
264
265 if (uart_handle_sysrq_char(port, ch))
266 goto ignore_char;
267
268 if (status & port->ignore_status_mask & STAT_PAR_ERR)
269 status &= ~STAT_RX_RDY(port);
270
271 status &= port->read_status_mask;
272
273 if (status & STAT_PAR_ERR)
274 flag = TTY_PARITY;
275
276 status &= ~port->ignore_status_mask;
277
278 if (status & STAT_RX_RDY(port))
279 tty_insert_flip_char(tport, ch, flag);
280
281 if (status & STAT_BRK_DET)
282 tty_insert_flip_char(tport, 0, TTY_BREAK);
283
284 if (status & STAT_FRM_ERR)
285 tty_insert_flip_char(tport, 0, TTY_FRAME);
286
287 if (status & STAT_OVR_ERR)
288 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
289
290 ignore_char:
291 status = readl(port->membase + UART_STAT);
292 } while (status & (STAT_RX_RDY(port) | STAT_BRK_DET));
293
294 tty_flip_buffer_push(tport);
295 }
296
mvebu_uart_tx_chars(struct uart_port * port,unsigned int status)297 static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
298 {
299 struct circ_buf *xmit = &port->state->xmit;
300 unsigned int count;
301 unsigned int st;
302
303 if (port->x_char) {
304 writel(port->x_char, port->membase + UART_TSH(port));
305 port->icount.tx++;
306 port->x_char = 0;
307 return;
308 }
309
310 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
311 mvebu_uart_stop_tx(port);
312 return;
313 }
314
315 for (count = 0; count < port->fifosize; count++) {
316 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
317 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
318 port->icount.tx++;
319
320 if (uart_circ_empty(xmit))
321 break;
322
323 st = readl(port->membase + UART_STAT);
324 if (st & STAT_TX_FIFO_FUL)
325 break;
326 }
327
328 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
329 uart_write_wakeup(port);
330
331 if (uart_circ_empty(xmit))
332 mvebu_uart_stop_tx(port);
333 }
334
mvebu_uart_isr(int irq,void * dev_id)335 static irqreturn_t mvebu_uart_isr(int irq, void *dev_id)
336 {
337 struct uart_port *port = (struct uart_port *)dev_id;
338 unsigned int st = readl(port->membase + UART_STAT);
339
340 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
341 STAT_BRK_DET))
342 mvebu_uart_rx_chars(port, st);
343
344 if (st & STAT_TX_RDY(port))
345 mvebu_uart_tx_chars(port, st);
346
347 return IRQ_HANDLED;
348 }
349
mvebu_uart_rx_isr(int irq,void * dev_id)350 static irqreturn_t mvebu_uart_rx_isr(int irq, void *dev_id)
351 {
352 struct uart_port *port = (struct uart_port *)dev_id;
353 unsigned int st = readl(port->membase + UART_STAT);
354
355 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
356 STAT_BRK_DET))
357 mvebu_uart_rx_chars(port, st);
358
359 return IRQ_HANDLED;
360 }
361
mvebu_uart_tx_isr(int irq,void * dev_id)362 static irqreturn_t mvebu_uart_tx_isr(int irq, void *dev_id)
363 {
364 struct uart_port *port = (struct uart_port *)dev_id;
365 unsigned int st = readl(port->membase + UART_STAT);
366
367 if (st & STAT_TX_RDY(port))
368 mvebu_uart_tx_chars(port, st);
369
370 return IRQ_HANDLED;
371 }
372
mvebu_uart_startup(struct uart_port * port)373 static int mvebu_uart_startup(struct uart_port *port)
374 {
375 struct mvebu_uart *mvuart = to_mvuart(port);
376 unsigned int ctl;
377 int ret;
378
379 writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST,
380 port->membase + UART_CTRL(port));
381 udelay(1);
382
383 /* Clear the error bits of state register before IRQ request */
384 ret = readl(port->membase + UART_STAT);
385 ret |= STAT_BRK_ERR;
386 writel(ret, port->membase + UART_STAT);
387
388 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));
389
390 ctl = readl(port->membase + UART_INTR(port));
391 ctl |= CTRL_RX_RDY_INT(port);
392 writel(ctl, port->membase + UART_INTR(port));
393
394 if (!mvuart->irq[UART_TX_IRQ]) {
395 /* Old bindings with just one interrupt (UART0 only) */
396 ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM],
397 mvebu_uart_isr, port->irqflags,
398 dev_name(port->dev), port);
399 if (ret) {
400 dev_err(port->dev, "unable to request IRQ %d\n",
401 mvuart->irq[UART_IRQ_SUM]);
402 return ret;
403 }
404 } else {
405 /* New bindings with an IRQ for RX and TX (both UART) */
406 ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ],
407 mvebu_uart_rx_isr, port->irqflags,
408 dev_name(port->dev), port);
409 if (ret) {
410 dev_err(port->dev, "unable to request IRQ %d\n",
411 mvuart->irq[UART_RX_IRQ]);
412 return ret;
413 }
414
415 ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ],
416 mvebu_uart_tx_isr, port->irqflags,
417 dev_name(port->dev),
418 port);
419 if (ret) {
420 dev_err(port->dev, "unable to request IRQ %d\n",
421 mvuart->irq[UART_TX_IRQ]);
422 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ],
423 port);
424 return ret;
425 }
426 }
427
428 return 0;
429 }
430
mvebu_uart_shutdown(struct uart_port * port)431 static void mvebu_uart_shutdown(struct uart_port *port)
432 {
433 struct mvebu_uart *mvuart = to_mvuart(port);
434
435 writel(0, port->membase + UART_INTR(port));
436
437 if (!mvuart->irq[UART_TX_IRQ]) {
438 devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port);
439 } else {
440 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port);
441 devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port);
442 }
443 }
444
mvebu_uart_baud_rate_set(struct uart_port * port,unsigned int baud)445 static int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud)
446 {
447 unsigned int d_divisor, m_divisor;
448 u32 brdv, osamp;
449
450 if (!port->uartclk)
451 return -EOPNOTSUPP;
452
453 /*
454 * The baudrate is derived from the UART clock thanks to two divisors:
455 * > D ("baud generator"): can divide the clock from 2 to 2^10 - 1.
456 * > M ("fractional divisor"): allows a better accuracy for
457 * baudrates higher than 230400.
458 *
459 * As the derivation of M is rather complicated, the code sticks to its
460 * default value (x16) when all the prescalers are zeroed, and only
461 * makes use of D to configure the desired baudrate.
462 */
463 m_divisor = OSAMP_DEFAULT_DIVISOR;
464 d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor);
465
466 brdv = readl(port->membase + UART_BRDV);
467 brdv &= ~BRDV_BAUD_MASK;
468 brdv |= d_divisor;
469 writel(brdv, port->membase + UART_BRDV);
470
471 osamp = readl(port->membase + UART_OSAMP);
472 osamp &= ~OSAMP_DIVISORS_MASK;
473 writel(osamp, port->membase + UART_OSAMP);
474
475 return 0;
476 }
477
mvebu_uart_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)478 static void mvebu_uart_set_termios(struct uart_port *port,
479 struct ktermios *termios,
480 struct ktermios *old)
481 {
482 unsigned long flags;
483 unsigned int baud, min_baud, max_baud;
484
485 spin_lock_irqsave(&port->lock, flags);
486
487 port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR |
488 STAT_TX_RDY(port) | STAT_TX_FIFO_FUL;
489
490 if (termios->c_iflag & INPCK)
491 port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR;
492
493 port->ignore_status_mask = 0;
494 if (termios->c_iflag & IGNPAR)
495 port->ignore_status_mask |=
496 STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR;
497
498 if ((termios->c_cflag & CREAD) == 0)
499 port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR;
500
501 /*
502 * Maximal divisor is 1023 * 16 when using default (x16) scheme.
503 * Maximum achievable frequency with simple baudrate divisor is 230400.
504 * Since the error per bit frame would be of more than 15%, achieving
505 * higher frequencies would require to implement the fractional divisor
506 * feature.
507 */
508 min_baud = DIV_ROUND_UP(port->uartclk, 1023 * 16);
509 max_baud = 230400;
510
511 baud = uart_get_baud_rate(port, termios, old, min_baud, max_baud);
512 if (mvebu_uart_baud_rate_set(port, baud)) {
513 /* No clock available, baudrate cannot be changed */
514 if (old)
515 baud = uart_get_baud_rate(port, old, NULL,
516 min_baud, max_baud);
517 } else {
518 tty_termios_encode_baud_rate(termios, baud, baud);
519 uart_update_timeout(port, termios->c_cflag, baud);
520 }
521
522 /* Only the following flag changes are supported */
523 if (old) {
524 termios->c_iflag &= INPCK | IGNPAR;
525 termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR);
526 termios->c_cflag &= CREAD | CBAUD;
527 termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD);
528 termios->c_cflag |= CS8;
529 }
530
531 spin_unlock_irqrestore(&port->lock, flags);
532 }
533
mvebu_uart_type(struct uart_port * port)534 static const char *mvebu_uart_type(struct uart_port *port)
535 {
536 return MVEBU_UART_TYPE;
537 }
538
mvebu_uart_release_port(struct uart_port * port)539 static void mvebu_uart_release_port(struct uart_port *port)
540 {
541 /* Nothing to do here */
542 }
543
mvebu_uart_request_port(struct uart_port * port)544 static int mvebu_uart_request_port(struct uart_port *port)
545 {
546 return 0;
547 }
548
549 #ifdef CONFIG_CONSOLE_POLL
mvebu_uart_get_poll_char(struct uart_port * port)550 static int mvebu_uart_get_poll_char(struct uart_port *port)
551 {
552 unsigned int st = readl(port->membase + UART_STAT);
553
554 if (!(st & STAT_RX_RDY(port)))
555 return NO_POLL_CHAR;
556
557 return readl(port->membase + UART_RBR(port));
558 }
559
mvebu_uart_put_poll_char(struct uart_port * port,unsigned char c)560 static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
561 {
562 unsigned int st;
563
564 for (;;) {
565 st = readl(port->membase + UART_STAT);
566
567 if (!(st & STAT_TX_FIFO_FUL))
568 break;
569
570 udelay(1);
571 }
572
573 writel(c, port->membase + UART_TSH(port));
574 }
575 #endif
576
577 static const struct uart_ops mvebu_uart_ops = {
578 .tx_empty = mvebu_uart_tx_empty,
579 .set_mctrl = mvebu_uart_set_mctrl,
580 .get_mctrl = mvebu_uart_get_mctrl,
581 .stop_tx = mvebu_uart_stop_tx,
582 .start_tx = mvebu_uart_start_tx,
583 .stop_rx = mvebu_uart_stop_rx,
584 .break_ctl = mvebu_uart_break_ctl,
585 .startup = mvebu_uart_startup,
586 .shutdown = mvebu_uart_shutdown,
587 .set_termios = mvebu_uart_set_termios,
588 .type = mvebu_uart_type,
589 .release_port = mvebu_uart_release_port,
590 .request_port = mvebu_uart_request_port,
591 #ifdef CONFIG_CONSOLE_POLL
592 .poll_get_char = mvebu_uart_get_poll_char,
593 .poll_put_char = mvebu_uart_put_poll_char,
594 #endif
595 };
596
597 /* Console Driver Operations */
598
599 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
600 /* Early Console */
mvebu_uart_putc(struct uart_port * port,int c)601 static void mvebu_uart_putc(struct uart_port *port, int c)
602 {
603 unsigned int st;
604
605 for (;;) {
606 st = readl(port->membase + UART_STAT);
607 if (!(st & STAT_TX_FIFO_FUL))
608 break;
609 }
610
611 /* At early stage, DT is not parsed yet, only use UART0 */
612 writel(c, port->membase + UART_STD_TSH);
613
614 for (;;) {
615 st = readl(port->membase + UART_STAT);
616 if (st & STAT_TX_FIFO_EMP)
617 break;
618 }
619 }
620
mvebu_uart_putc_early_write(struct console * con,const char * s,unsigned int n)621 static void mvebu_uart_putc_early_write(struct console *con,
622 const char *s,
623 unsigned int n)
624 {
625 struct earlycon_device *dev = con->data;
626
627 uart_console_write(&dev->port, s, n, mvebu_uart_putc);
628 }
629
630 static int __init
mvebu_uart_early_console_setup(struct earlycon_device * device,const char * opt)631 mvebu_uart_early_console_setup(struct earlycon_device *device,
632 const char *opt)
633 {
634 if (!device->port.membase)
635 return -ENODEV;
636
637 device->con->write = mvebu_uart_putc_early_write;
638
639 return 0;
640 }
641
642 EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup);
643 OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart",
644 mvebu_uart_early_console_setup);
645
wait_for_xmitr(struct uart_port * port)646 static void wait_for_xmitr(struct uart_port *port)
647 {
648 u32 val;
649
650 readl_poll_timeout_atomic(port->membase + UART_STAT, val,
651 (val & STAT_TX_RDY(port)), 1, 10000);
652 }
653
wait_for_xmite(struct uart_port * port)654 static void wait_for_xmite(struct uart_port *port)
655 {
656 u32 val;
657
658 readl_poll_timeout_atomic(port->membase + UART_STAT, val,
659 (val & STAT_TX_EMP), 1, 10000);
660 }
661
mvebu_uart_console_putchar(struct uart_port * port,int ch)662 static void mvebu_uart_console_putchar(struct uart_port *port, int ch)
663 {
664 wait_for_xmitr(port);
665 writel(ch, port->membase + UART_TSH(port));
666 }
667
mvebu_uart_console_write(struct console * co,const char * s,unsigned int count)668 static void mvebu_uart_console_write(struct console *co, const char *s,
669 unsigned int count)
670 {
671 struct uart_port *port = &mvebu_uart_ports[co->index];
672 unsigned long flags;
673 unsigned int ier, intr, ctl;
674 int locked = 1;
675
676 if (oops_in_progress)
677 locked = spin_trylock_irqsave(&port->lock, flags);
678 else
679 spin_lock_irqsave(&port->lock, flags);
680
681 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;
682 intr = readl(port->membase + UART_INTR(port)) &
683 (CTRL_RX_RDY_INT(port) | CTRL_TX_RDY_INT(port));
684 writel(0, port->membase + UART_CTRL(port));
685 writel(0, port->membase + UART_INTR(port));
686
687 uart_console_write(port, s, count, mvebu_uart_console_putchar);
688
689 wait_for_xmite(port);
690
691 if (ier)
692 writel(ier, port->membase + UART_CTRL(port));
693
694 if (intr) {
695 ctl = intr | readl(port->membase + UART_INTR(port));
696 writel(ctl, port->membase + UART_INTR(port));
697 }
698
699 if (locked)
700 spin_unlock_irqrestore(&port->lock, flags);
701 }
702
mvebu_uart_console_setup(struct console * co,char * options)703 static int mvebu_uart_console_setup(struct console *co, char *options)
704 {
705 struct uart_port *port;
706 int baud = 9600;
707 int bits = 8;
708 int parity = 'n';
709 int flow = 'n';
710
711 if (co->index < 0 || co->index >= MVEBU_NR_UARTS)
712 return -EINVAL;
713
714 port = &mvebu_uart_ports[co->index];
715
716 if (!port->mapbase || !port->membase) {
717 pr_debug("console on ttyMV%i not present\n", co->index);
718 return -ENODEV;
719 }
720
721 if (options)
722 uart_parse_options(options, &baud, &parity, &bits, &flow);
723
724 return uart_set_options(port, co, baud, parity, bits, flow);
725 }
726
727 static struct uart_driver mvebu_uart_driver;
728
729 static struct console mvebu_uart_console = {
730 .name = "ttyMV",
731 .write = mvebu_uart_console_write,
732 .device = uart_console_device,
733 .setup = mvebu_uart_console_setup,
734 .flags = CON_PRINTBUFFER,
735 .index = -1,
736 .data = &mvebu_uart_driver,
737 };
738
mvebu_uart_console_init(void)739 static int __init mvebu_uart_console_init(void)
740 {
741 register_console(&mvebu_uart_console);
742 return 0;
743 }
744
745 console_initcall(mvebu_uart_console_init);
746
747
748 #endif /* CONFIG_SERIAL_MVEBU_CONSOLE */
749
750 static struct uart_driver mvebu_uart_driver = {
751 .owner = THIS_MODULE,
752 .driver_name = DRIVER_NAME,
753 .dev_name = "ttyMV",
754 .nr = MVEBU_NR_UARTS,
755 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
756 .cons = &mvebu_uart_console,
757 #endif
758 };
759
760 #if defined(CONFIG_PM)
mvebu_uart_suspend(struct device * dev)761 static int mvebu_uart_suspend(struct device *dev)
762 {
763 struct mvebu_uart *mvuart = dev_get_drvdata(dev);
764 struct uart_port *port = mvuart->port;
765
766 uart_suspend_port(&mvebu_uart_driver, port);
767
768 mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port));
769 mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port));
770 mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port));
771 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port));
772 mvuart->pm_regs.stat = readl(port->membase + UART_STAT);
773 mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV);
774 mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP);
775
776 device_set_wakeup_enable(dev, true);
777
778 return 0;
779 }
780
mvebu_uart_resume(struct device * dev)781 static int mvebu_uart_resume(struct device *dev)
782 {
783 struct mvebu_uart *mvuart = dev_get_drvdata(dev);
784 struct uart_port *port = mvuart->port;
785
786 writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port));
787 writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port));
788 writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port));
789 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port));
790 writel(mvuart->pm_regs.stat, port->membase + UART_STAT);
791 writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV);
792 writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP);
793
794 uart_resume_port(&mvebu_uart_driver, port);
795
796 return 0;
797 }
798
799 static const struct dev_pm_ops mvebu_uart_pm_ops = {
800 .suspend = mvebu_uart_suspend,
801 .resume = mvebu_uart_resume,
802 };
803 #endif /* CONFIG_PM */
804
805 static const struct of_device_id mvebu_uart_of_match[];
806
807 /* Counter to keep track of each UART port id when not using CONFIG_OF */
808 static int uart_num_counter;
809
mvebu_uart_probe(struct platform_device * pdev)810 static int mvebu_uart_probe(struct platform_device *pdev)
811 {
812 struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
813 const struct of_device_id *match = of_match_device(mvebu_uart_of_match,
814 &pdev->dev);
815 struct uart_port *port;
816 struct mvebu_uart *mvuart;
817 int id, irq;
818
819 if (!reg) {
820 dev_err(&pdev->dev, "no registers defined\n");
821 return -EINVAL;
822 }
823
824 /* Assume that all UART ports have a DT alias or none has */
825 id = of_alias_get_id(pdev->dev.of_node, "serial");
826 if (!pdev->dev.of_node || id < 0)
827 pdev->id = uart_num_counter++;
828 else
829 pdev->id = id;
830
831 if (pdev->id >= MVEBU_NR_UARTS) {
832 dev_err(&pdev->dev, "cannot have more than %d UART ports\n",
833 MVEBU_NR_UARTS);
834 return -EINVAL;
835 }
836
837 port = &mvebu_uart_ports[pdev->id];
838
839 spin_lock_init(&port->lock);
840
841 port->dev = &pdev->dev;
842 port->type = PORT_MVEBU;
843 port->ops = &mvebu_uart_ops;
844 port->regshift = 0;
845
846 port->fifosize = 32;
847 port->iotype = UPIO_MEM32;
848 port->flags = UPF_FIXED_PORT;
849 port->line = pdev->id;
850
851 /*
852 * IRQ number is not stored in this structure because we may have two of
853 * them per port (RX and TX). Instead, use the driver UART structure
854 * array so called ->irq[].
855 */
856 port->irq = 0;
857 port->irqflags = 0;
858 port->mapbase = reg->start;
859
860 port->membase = devm_ioremap_resource(&pdev->dev, reg);
861 if (IS_ERR(port->membase))
862 return PTR_ERR(port->membase);
863
864 mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart),
865 GFP_KERNEL);
866 if (!mvuart)
867 return -ENOMEM;
868
869 /* Get controller data depending on the compatible string */
870 mvuart->data = (struct mvebu_uart_driver_data *)match->data;
871 mvuart->port = port;
872
873 port->private_data = mvuart;
874 platform_set_drvdata(pdev, mvuart);
875
876 /* Get fixed clock frequency */
877 mvuart->clk = devm_clk_get(&pdev->dev, NULL);
878 if (IS_ERR(mvuart->clk)) {
879 if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER)
880 return PTR_ERR(mvuart->clk);
881
882 if (IS_EXTENDED(port)) {
883 dev_err(&pdev->dev, "unable to get UART clock\n");
884 return PTR_ERR(mvuart->clk);
885 }
886 } else {
887 if (!clk_prepare_enable(mvuart->clk))
888 port->uartclk = clk_get_rate(mvuart->clk);
889 }
890
891 /* Manage interrupts */
892 if (platform_irq_count(pdev) == 1) {
893 /* Old bindings: no name on the single unamed UART0 IRQ */
894 irq = platform_get_irq(pdev, 0);
895 if (irq < 0)
896 return irq;
897
898 mvuart->irq[UART_IRQ_SUM] = irq;
899 } else {
900 /*
901 * New bindings: named interrupts (RX, TX) for both UARTS,
902 * only make use of uart-rx and uart-tx interrupts, do not use
903 * uart-sum of UART0 port.
904 */
905 irq = platform_get_irq_byname(pdev, "uart-rx");
906 if (irq < 0)
907 return irq;
908
909 mvuart->irq[UART_RX_IRQ] = irq;
910
911 irq = platform_get_irq_byname(pdev, "uart-tx");
912 if (irq < 0)
913 return irq;
914
915 mvuart->irq[UART_TX_IRQ] = irq;
916 }
917
918 /* UART Soft Reset*/
919 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));
920 udelay(1);
921 writel(0, port->membase + UART_CTRL(port));
922
923 return uart_add_one_port(&mvebu_uart_driver, port);
924 }
925
926 static struct mvebu_uart_driver_data uart_std_driver_data = {
927 .is_ext = false,
928 .regs.rbr = UART_STD_RBR,
929 .regs.tsh = UART_STD_TSH,
930 .regs.ctrl = UART_STD_CTRL1,
931 .regs.intr = UART_STD_CTRL2,
932 .flags.ctrl_tx_rdy_int = CTRL_STD_TX_RDY_INT,
933 .flags.ctrl_rx_rdy_int = CTRL_STD_RX_RDY_INT,
934 .flags.stat_tx_rdy = STAT_STD_TX_RDY,
935 .flags.stat_rx_rdy = STAT_STD_RX_RDY,
936 };
937
938 static struct mvebu_uart_driver_data uart_ext_driver_data = {
939 .is_ext = true,
940 .regs.rbr = UART_EXT_RBR,
941 .regs.tsh = UART_EXT_TSH,
942 .regs.ctrl = UART_EXT_CTRL1,
943 .regs.intr = UART_EXT_CTRL2,
944 .flags.ctrl_tx_rdy_int = CTRL_EXT_TX_RDY_INT,
945 .flags.ctrl_rx_rdy_int = CTRL_EXT_RX_RDY_INT,
946 .flags.stat_tx_rdy = STAT_EXT_TX_RDY,
947 .flags.stat_rx_rdy = STAT_EXT_RX_RDY,
948 };
949
950 /* Match table for of_platform binding */
951 static const struct of_device_id mvebu_uart_of_match[] = {
952 {
953 .compatible = "marvell,armada-3700-uart",
954 .data = (void *)&uart_std_driver_data,
955 },
956 {
957 .compatible = "marvell,armada-3700-uart-ext",
958 .data = (void *)&uart_ext_driver_data,
959 },
960 {}
961 };
962
963 static struct platform_driver mvebu_uart_platform_driver = {
964 .probe = mvebu_uart_probe,
965 .driver = {
966 .name = "mvebu-uart",
967 .of_match_table = of_match_ptr(mvebu_uart_of_match),
968 .suppress_bind_attrs = true,
969 #if defined(CONFIG_PM)
970 .pm = &mvebu_uart_pm_ops,
971 #endif /* CONFIG_PM */
972 },
973 };
974
mvebu_uart_init(void)975 static int __init mvebu_uart_init(void)
976 {
977 int ret;
978
979 ret = uart_register_driver(&mvebu_uart_driver);
980 if (ret)
981 return ret;
982
983 ret = platform_driver_register(&mvebu_uart_platform_driver);
984 if (ret)
985 uart_unregister_driver(&mvebu_uart_driver);
986
987 return ret;
988 }
989 arch_initcall(mvebu_uart_init);
990
