1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_device.h>
16 #include <linux/of_address.h>
17 #include <linux/phy/phy.h>
18 #include <linux/platform_device.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22
23 #include <dt-bindings/phy/phy.h>
24
25 #include "phy-qcom-qmp.h"
26
27 /* QPHY_SW_RESET bit */
28 #define SW_RESET BIT(0)
29 /* QPHY_POWER_DOWN_CONTROL */
30 #define SW_PWRDN BIT(0)
31 #define REFCLK_DRV_DSBL BIT(1)
32 /* QPHY_START_CONTROL bits */
33 #define SERDES_START BIT(0)
34 #define PCS_START BIT(1)
35 #define PLL_READY_GATE_EN BIT(3)
36 /* QPHY_PCS_STATUS bit */
37 #define PHYSTATUS BIT(6)
38 #define PHYSTATUS_4_20 BIT(7)
39 /* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
40 #define PCS_READY BIT(0)
41
42 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
43 /* DP PHY soft reset */
44 #define SW_DPPHY_RESET BIT(0)
45 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
46 #define SW_DPPHY_RESET_MUX BIT(1)
47 /* USB3 PHY soft reset */
48 #define SW_USB3PHY_RESET BIT(2)
49 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
50 #define SW_USB3PHY_RESET_MUX BIT(3)
51
52 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
53 #define USB3_MODE BIT(0) /* enables USB3 mode */
54 #define DP_MODE BIT(1) /* enables DP mode */
55
56 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
57 #define ARCVR_DTCT_EN BIT(0)
58 #define ALFPS_DTCT_EN BIT(1)
59 #define ARCVR_DTCT_EVENT_SEL BIT(4)
60
61 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
62 #define IRQ_CLEAR BIT(0)
63
64 /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
65 #define RCVR_DETECT BIT(0)
66
67 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
68 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */
69
70 #define PHY_INIT_COMPLETE_TIMEOUT 10000
71 #define POWER_DOWN_DELAY_US_MIN 10
72 #define POWER_DOWN_DELAY_US_MAX 11
73
74 #define MAX_PROP_NAME 32
75
76 /* Define the assumed distance between lanes for underspecified device trees. */
77 #define QMP_PHY_LEGACY_LANE_STRIDE 0x400
78
79 struct qmp_phy_init_tbl {
80 unsigned int offset;
81 unsigned int val;
82 /*
83 * register part of layout ?
84 * if yes, then offset gives index in the reg-layout
85 */
86 bool in_layout;
87 /*
88 * mask of lanes for which this register is written
89 * for cases when second lane needs different values
90 */
91 u8 lane_mask;
92 };
93
94 #define QMP_PHY_INIT_CFG(o, v) \
95 { \
96 .offset = o, \
97 .val = v, \
98 .lane_mask = 0xff, \
99 }
100
101 #define QMP_PHY_INIT_CFG_L(o, v) \
102 { \
103 .offset = o, \
104 .val = v, \
105 .in_layout = true, \
106 .lane_mask = 0xff, \
107 }
108
109 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \
110 { \
111 .offset = o, \
112 .val = v, \
113 .lane_mask = l, \
114 }
115
116 /* set of registers with offsets different per-PHY */
117 enum qphy_reg_layout {
118 /* Common block control registers */
119 QPHY_COM_SW_RESET,
120 QPHY_COM_POWER_DOWN_CONTROL,
121 QPHY_COM_START_CONTROL,
122 QPHY_COM_PCS_READY_STATUS,
123 /* PCS registers */
124 QPHY_PLL_LOCK_CHK_DLY_TIME,
125 QPHY_FLL_CNTRL1,
126 QPHY_FLL_CNTRL2,
127 QPHY_FLL_CNT_VAL_L,
128 QPHY_FLL_CNT_VAL_H_TOL,
129 QPHY_FLL_MAN_CODE,
130 QPHY_SW_RESET,
131 QPHY_START_CTRL,
132 QPHY_PCS_READY_STATUS,
133 QPHY_PCS_STATUS,
134 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
135 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
136 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
137 QPHY_PCS_POWER_DOWN_CONTROL,
138 /* Keep last to ensure regs_layout arrays are properly initialized */
139 QPHY_LAYOUT_SIZE
140 };
141
142 static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
143 [QPHY_START_CTRL] = 0x00,
144 [QPHY_PCS_READY_STATUS] = 0x168,
145 };
146
147 static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
148 [QPHY_SW_RESET] = 0x00,
149 [QPHY_START_CTRL] = 0x44,
150 [QPHY_PCS_STATUS] = 0x14,
151 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
152 };
153
154 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
155 [QPHY_COM_SW_RESET] = 0x400,
156 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
157 [QPHY_COM_START_CONTROL] = 0x408,
158 [QPHY_COM_PCS_READY_STATUS] = 0x448,
159 [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
160 [QPHY_FLL_CNTRL1] = 0xc4,
161 [QPHY_FLL_CNTRL2] = 0xc8,
162 [QPHY_FLL_CNT_VAL_L] = 0xcc,
163 [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
164 [QPHY_FLL_MAN_CODE] = 0xd4,
165 [QPHY_SW_RESET] = 0x00,
166 [QPHY_START_CTRL] = 0x08,
167 [QPHY_PCS_STATUS] = 0x174,
168 };
169
170 static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
171 [QPHY_FLL_CNTRL1] = 0xc0,
172 [QPHY_FLL_CNTRL2] = 0xc4,
173 [QPHY_FLL_CNT_VAL_L] = 0xc8,
174 [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
175 [QPHY_FLL_MAN_CODE] = 0xd0,
176 [QPHY_SW_RESET] = 0x00,
177 [QPHY_START_CTRL] = 0x08,
178 [QPHY_PCS_STATUS] = 0x17c,
179 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
180 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
181 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
182 };
183
184 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
185 [QPHY_SW_RESET] = 0x00,
186 [QPHY_START_CTRL] = 0x08,
187 [QPHY_PCS_STATUS] = 0x174,
188 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
189 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
190 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
191 };
192
193 static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
194 [QPHY_SW_RESET] = 0x00,
195 [QPHY_START_CTRL] = 0x08,
196 [QPHY_PCS_STATUS] = 0x174,
197 };
198
199 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
200 [QPHY_SW_RESET] = 0x00,
201 [QPHY_START_CTRL] = 0x08,
202 [QPHY_PCS_STATUS] = 0x2ac,
203 };
204
205 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
206 [QPHY_SW_RESET] = 0x00,
207 [QPHY_START_CTRL] = 0x44,
208 [QPHY_PCS_STATUS] = 0x14,
209 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
210 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
211 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
212 };
213
214 static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
215 [QPHY_SW_RESET] = 0x00,
216 [QPHY_START_CTRL] = 0x44,
217 [QPHY_PCS_STATUS] = 0x14,
218 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
219 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
220 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
221 };
222
223 static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
224 [QPHY_SW_RESET] = 0x00,
225 [QPHY_START_CTRL] = 0x44,
226 [QPHY_PCS_STATUS] = 0x14,
227 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
228 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
229 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
230 };
231
232 static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
233 [QPHY_START_CTRL] = 0x00,
234 [QPHY_PCS_READY_STATUS] = 0x160,
235 };
236
237 static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
238 [QPHY_START_CTRL] = 0x00,
239 [QPHY_PCS_READY_STATUS] = 0x168,
240 };
241
242 static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
243 [QPHY_SW_RESET] = 0x00,
244 [QPHY_START_CTRL] = 0x44,
245 [QPHY_PCS_STATUS] = 0x14,
246 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
247 };
248
249 static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
250 [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
251 [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
252 [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
253 };
254
255 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
256 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
257 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
258 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
259 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
260 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
261 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
262 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
263 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
264 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
265 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
266 /* PLL and Loop filter settings */
267 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
268 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
269 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
270 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
271 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
272 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
273 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
274 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
275 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
276 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
277 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
278 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
279 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
280 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
281 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
282 /* SSC settings */
283 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
284 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
285 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
286 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
287 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
288 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
289 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
290 };
291
292 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
293 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
294 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
295 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
296 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
297 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
298 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
299 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
300 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
301 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
302 };
303
304 static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
305 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
306 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
307 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
308 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
309 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
310 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
311 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
312 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
313 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
314 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
315 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
316 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
317 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
318 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
319 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
320 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
321 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
322 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
323 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
324 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
325 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
326 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
327 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
328 };
329
330 static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
331 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
332 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
333 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
334 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
335 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
336 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
337 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
338 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
339 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
340 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
341 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
342 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
343 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
344 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
345 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
346 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
347 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
348 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
349 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
350 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
351 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
352 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
353 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
354 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
355 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
356 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
357 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
358 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
359 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
360 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
361 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
362 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
363 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
364 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
365 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
366 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
367 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
368 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
369 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
370 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
371 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
372 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
373 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
374 };
375
376 static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
377 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
378 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
379 };
380
381 static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
382 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
383 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
384 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
385 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
386 QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
387 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
388 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
389 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
390 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
391 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
392 };
393
394 static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
395 QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
396 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
397 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
398
399 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
400
401 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
402 QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
403 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
404 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
405 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
406 };
407
408 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
409 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
410 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
411 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
412 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
413 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
414 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
415 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
416 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
417 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
418 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
419 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
420 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
422 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
423 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
424 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
425 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
426 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
427 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
428 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
429 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
430 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
431 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
432 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
433 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
434 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
435 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
436 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
437 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
438 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
439 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
440 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
441 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
442 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
443 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
444 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
445 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
446 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
447 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
448 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
449 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
450 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
451 };
452
453 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
454 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
455 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
456 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
457 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
458 };
459
460 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
461 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
462 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
463 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
464 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
465 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
466 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
467 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
468 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
469 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
470 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
471 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
472 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
473 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
474 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
475 };
476
477 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
478 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
479 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
480 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
481 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
482 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
483 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
484 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
485 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
486 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
487 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
488 };
489
490 static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
491 QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
492 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
493 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
494 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
495 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
496 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
497 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
498 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
499 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
500 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
501 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
502 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
503 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
504 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
505 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
506 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
507 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
508 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
509 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
510 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
511 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
512 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
513 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
514 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
515 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
516 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
517 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
518 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
519 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
520 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
521 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
522 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
523 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
524 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
525 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
526 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
527 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
528 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
529 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
530 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
531 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
532 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
533 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
534 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
535 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
536 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
537 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
538 };
539
540 static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
541 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
542 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
543 };
544
545 static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
546 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
547 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
548 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
549 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
550 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
551 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
552 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
553 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
554 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
555 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
556 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
557 };
558
559 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
560 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
561 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
562 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
563 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
564 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
565 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
566 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
567 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
568 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
569 /* PLL and Loop filter settings */
570 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
571 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
572 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
573 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
574 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
575 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
576 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
577 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
578 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
579 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
580 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
581 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
582 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
583 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
584 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
585 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
586 /* SSC settings */
587 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
588 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
589 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
590 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
591 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
592 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
593 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
594 };
595
596 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
597 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
598 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
599 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
600 };
601
602 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
603 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
604 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
605 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
606 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
607 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
608 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
609 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
610 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
611 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
612 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
613 };
614
615 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
616 /* FLL settings */
617 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
618 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
619 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
620 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
621 QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
622
623 /* Lock Det settings */
624 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
625 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
626 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
627 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
628 };
629
630 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
631 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
632 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
633 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
634 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
635 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
636 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
637 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
638 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
639 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
640 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
641 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
642 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
643 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
644 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
645 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
646 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
647 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
648 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
649 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
650 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
651 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
652 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
653 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
654 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
655 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
656 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
657 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
658 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
659 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
660 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
661 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
662 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
663 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
664 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
665 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
666 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
667 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
668 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
669 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
670 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
671 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
672 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
673 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
674 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
675 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
676 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
677 };
678
679 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
680 QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
681 QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
682 QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
683 };
684
685 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
686 QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
687 QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
688 QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
689 QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
690 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
691 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
692 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
693 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
694 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
695 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
696 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
697 QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
698 QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
699 QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
700 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
701 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
702 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
703 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
704 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
705 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
706 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
707 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
708 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
709 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
710 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
711 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
712 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
713 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
714 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
715 QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
716 };
717
718 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
719 QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
720 QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
721 QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
722 QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
723 QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
724 QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
725 QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
726 QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
727 QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
728 QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
729 QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
730 QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
731 QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
732 QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
733 QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
734 QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
735 };
736
737 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
738 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
739 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
740 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
741 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
742 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
743 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
744 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
745 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
746 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
747 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
748 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
749 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
750 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
751 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
752 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
753 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
754 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
755 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
756 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
757 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
758 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
759 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
760 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
761 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
762 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
763 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
764 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
765 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
766 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
767 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
768 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
769 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
770 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
771 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
772 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
773 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
774 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
775 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
776 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
777 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
778 };
779
780 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
781 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
782 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
783 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
784 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
785 QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
786 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
787 };
788
789 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
790 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
791 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
792 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
793 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
794 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
795 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
796 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
797 };
798
799 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
800 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
801 QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
802 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
803 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
804 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
805 QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
806 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
807 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
808 QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
809 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
810 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
811 QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
812 QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
813 };
814
815 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
816 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
817 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
818 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
819 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
820 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
821 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
822 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
823 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
824 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
825 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
826 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
827 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
828 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
829 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
830 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
831 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
832 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
833 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
834 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
835 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
836 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
837 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
838 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
839 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
840 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
841 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
842 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
843 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
844 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
845 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
846 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
847 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
848 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
849 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
850 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
851 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
852 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
853 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
854 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
855 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
856 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
857 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
858 };
859
860 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
861 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
862 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
863 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
864 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
865 };
866
867 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
868 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
869 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
870 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
871 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
872 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
873 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
874 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
875 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
876 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
877 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
878 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
879 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
880 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
881 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
882 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
883 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
884 };
885
886 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
887 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
888
889 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
890 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
891 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
892 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
893 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
894
895 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
896 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
897 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
898 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
899 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
900 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
901 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
902
903 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
904 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
905 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
906
907 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
908 };
909
910 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
911 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
912 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
913 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
914 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
915 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
916 };
917
918 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
919 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
920 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
921 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
922 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
923 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
924 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
925 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
926 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
927 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
928 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
929 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
930 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
931 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
932 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
933 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
934 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
935 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
936 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
937 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
938 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
939 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
940 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
941 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
942 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
943 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
944 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
945 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
946 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
947 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
948 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
949 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
950 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
951 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
952 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
953 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
954 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
955 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
956 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
957 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
958 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
959 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
960 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
961 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
962 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
963 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
964 };
965
966 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
967 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
968 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
969 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
970 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
971 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
972 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
973 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
974 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
975 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
976 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
977 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
978 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
979 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
980 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
981 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
982 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
983 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
984 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
985 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
986 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
987 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
988 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
989 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
990 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
991 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
992 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
993 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
994 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
995 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
996 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
997 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
998 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
999 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
1000 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
1001 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
1002 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
1003 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
1004 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
1005 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
1006 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
1007 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
1008 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
1009 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
1010 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
1011 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
1012 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
1013 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
1014 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
1015 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
1016 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
1017 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
1018 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
1019 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
1020 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
1021 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
1022 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
1023 };
1024
1025 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
1026 };
1027
1028 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
1029 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
1030 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
1031 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
1032 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
1033 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
1034 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
1035 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
1036 };
1037
1038 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
1039 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1040 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1041 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
1042 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1043 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1044 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1045 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
1046 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1047 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1048 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1049 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1050 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1051 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1052 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1053 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1054 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1055 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1056 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1057 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1058 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1059 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1060 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1061 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1062 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1063 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1064 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1065 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1066 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1067 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
1068 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1069 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1070 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1071 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1072 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1073 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1074 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1075 };
1076
1077 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
1078 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1079 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1080 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
1081 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
1082 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1083 };
1084
1085 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
1086 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1087 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
1088 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1089 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
1090 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
1091 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1092 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
1093 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
1094 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1095 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1096 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1097 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1098 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1099 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1100 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
1101 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
1102 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
1103 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1104 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1105 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1106 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1107 };
1108
1109 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
1110 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
1111 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1112 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1113 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1114 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
1115 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
1116 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1117 };
1118
1119 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
1120 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
1121 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1122 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
1125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
1126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1127 };
1128
1129 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
1130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
1132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
1133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
1134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
1135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
1136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1137 };
1138
1139 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
1140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
1141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
1145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
1146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
1147 };
1148
1149 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
1150 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
1151 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
1152 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
1153 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
1154 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
1155 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
1156 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
1157 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1158 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
1159 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
1160 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
1161 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
1162 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
1163 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1164 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1165 };
1166
1167 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
1168 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1169 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1170 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1171 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1172 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1173 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1174 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1175 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
1176 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1177 };
1178
1179 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
1180 /* FLL settings */
1181 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1182 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1183 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1184 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1185 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1186
1187 /* Lock Det settings */
1188 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1189 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1190 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1191 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1192
1193 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
1194 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1195 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1196 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1197 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1198 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1199 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1200 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1201 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1202 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
1203 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1204 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1205 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1206 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1207 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
1208 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1209 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1210 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1211 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1212
1213 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1214 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1215 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1216 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1217 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1218 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1219 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1220 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1221 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1222 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1223 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1224 };
1225
1226 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
1227 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1228 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1229 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1230 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1231 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1232 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1233 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1234 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1235 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1236 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1237 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1238 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1239 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1240 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1241 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1242 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1243 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1244 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1245 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1246 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1247 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1248 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1249 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1250 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1251 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1252 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1253 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1254 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1255 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
1256 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1257 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1258 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1259 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1260 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1261 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1262 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1263 };
1264
1265 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
1266 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1267 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1268 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
1269 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
1270 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1271 };
1272
1273 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
1274 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
1275 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
1276 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1277 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1278 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1279 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1280 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1281 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1282 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1283 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1284 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1285 };
1286
1287 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
1288 /* FLL settings */
1289 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1290 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1291 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1292 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1293 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1294
1295 /* Lock Det settings */
1296 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1297 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1298 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1299 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1300
1301 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
1302 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1303 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1304 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
1305 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
1306 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
1307 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
1308 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1309 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1310 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
1311 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1312 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1313 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1314 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1315 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
1316 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1317 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1318 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1319 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1320
1321 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1322 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1323 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1324 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1325 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1326 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1327 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1328 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1329 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1330 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1331 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1332
1333 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
1334 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
1335 };
1336
1337 static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
1338 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
1339 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
1340 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
1341 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
1342 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
1343 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
1344 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
1345 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
1346 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
1347 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
1348 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
1349 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
1350 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
1351 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
1352 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
1353 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
1354 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
1355 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
1356 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
1357 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
1358 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
1359 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
1360 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
1361 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
1362 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
1363 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
1364 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1365 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
1366 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
1367 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
1368 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
1369 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
1370 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
1371 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
1372 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
1373 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
1374 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
1375 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
1376 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
1377 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
1378 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
1379 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
1380 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
1381 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
1382 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
1383 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
1384 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
1385 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
1386 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
1387 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
1388
1389 /* Rate B */
1390 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
1391 };
1392
1393 static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
1394 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
1395 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
1396 };
1397
1398 static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
1399 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
1400 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
1401 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
1402 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
1403 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
1404 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
1405 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
1406 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
1407 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
1408 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
1409 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
1410 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
1411 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
1412 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
1413 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
1414 };
1415
1416 static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
1417 QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
1418 QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
1419 QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
1420 QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
1421 QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
1422 QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
1423 QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
1424 QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
1425 QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
1426 };
1427
1428 static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
1429 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1430 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1431 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1432 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1433 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1434 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
1435 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
1436 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1437 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1438 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
1439 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
1440 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1441 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
1442 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
1443 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
1444 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
1445 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1446 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1447 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1448 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1449 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1450 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1451 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
1452 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1453 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
1454 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
1455 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
1456 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
1457 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
1458 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
1459 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
1460 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
1461 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
1462 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
1463 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
1464 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
1465
1466 /* Rate B */
1467 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
1468 };
1469
1470 static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
1471 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
1472 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
1473 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1474 };
1475
1476 static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
1477 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
1478 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
1479 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1480 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
1481 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1482 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
1483 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1484 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1485 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
1486 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
1487 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
1488 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
1489 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1490 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
1491 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1492 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
1493 };
1494
1495 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
1496 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
1497 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1498 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
1499 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
1500 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
1501 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
1502 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
1503 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
1504 };
1505
1506 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
1507 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1508 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1509 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1510 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
1511 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
1537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
1538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1545 };
1546
1547 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
1548 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1549 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1550 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
1551 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
1552 };
1553
1554 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
1555 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1556 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1557 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1558 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1559 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
1560 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1561 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
1562 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1563 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1564 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1565 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1566 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
1567 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
1568 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
1569 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
1570 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
1571 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
1572 };
1573
1574 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
1575 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1576 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1577 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1578 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1579 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1580 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1581 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1582 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1583 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1584 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1585 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1586 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1587 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1588 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1589 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1591 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
1593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
1598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1607 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1608 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1609 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
1610 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1611 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1612 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1613 };
1614
1615 static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
1616 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
1617 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
1618 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1619 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
1620 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1621 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1622 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
1623 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1624 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1625 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1626 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1627 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1628 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
1629 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
1630 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
1631 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1632 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
1633 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1634 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1635 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1636 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
1637 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
1638 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
1639 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
1640
1641 /* Rate B */
1642 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
1643 };
1644
1645 static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
1646 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
1647 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
1648 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
1649 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
1650 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
1651 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
1652 };
1653
1654 static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
1655 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
1656 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
1657 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1658 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
1659 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
1660 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1661 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
1662 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1663 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
1664 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1665 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1666 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
1667 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1668 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1669 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
1670 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
1671 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
1672 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1673 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1674 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
1675 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
1676 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
1677 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
1678 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
1679 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
1680 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
1681 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
1682 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1683 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
1684 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
1685 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
1686 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
1687 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1688 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
1689
1690 };
1691
1692 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
1693 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
1694 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1695 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
1696 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
1697 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
1698 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
1699 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
1700 };
1701
1702 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
1703 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1704 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1705 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1706 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1707 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1708 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1709 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1710 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1711 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1712 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1713 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1714 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1715 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1716 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1717 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1718 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1719 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1720 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1721 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1722 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1723 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1724 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1725 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1726 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1727 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1728 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1729 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1730 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1731 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1732 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1733 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1734 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1735 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1736 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1737 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1738 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1739 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1740 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1741 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1742 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1743 };
1744
1745 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
1746 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
1747 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
1748 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1749 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1750 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1751 };
1752
1753 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
1754 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
1755 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1756 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1757 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1758 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1759 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1760 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1761 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1762 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1763 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1764 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1765 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
1766 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1767 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1768 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1769 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1770 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1771 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1772 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1773 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1774 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
1775 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
1776 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
1777 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1778 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
1779 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1780 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1781 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1782 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1783 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1784 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1785 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1786 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1787 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1788 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1789 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1790 };
1791
1792 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
1793 /* Lock Det settings */
1794 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1795 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1796 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1797
1798 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1799 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1800 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1801 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1802 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1803 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1804 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1805 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1806 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1807 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1808 };
1809
1810 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
1811 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1812 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1813 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1814 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1815 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1816 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1817 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1818 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1819 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1820 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1821 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1822 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1823 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1824 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1825 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1826 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1827 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1828 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1829 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1830 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1831 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1832 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1833 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1834 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1835 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1836 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1837 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1838 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1839 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1840 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1841 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1842 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1843 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1844 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1845 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1846 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1847 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1848 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1849 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1850 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1851 };
1852
1853 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
1854 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1855 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
1856 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
1857 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
1858 };
1859
1860 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
1861 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
1862 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1863 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
1864 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
1865 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
1866 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1867 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1868 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1869 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1870 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1871 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1872 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1873 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1874 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1875 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1876 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1877 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1878 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1879 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1880 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
1881 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1882 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1883 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1884 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1885 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1886 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1887 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1888 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1889 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1890 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1891 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1892 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1893 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1894 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
1895 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1896 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1897 };
1898
1899 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
1900 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1901 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1902 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1903 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1904 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1905 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1906 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1907 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
1908 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1909 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
1910 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1911 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1912 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1913 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1914 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1915 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1916 };
1917
1918 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
1919 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
1920 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
1921 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1922 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
1923 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1924 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1925 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
1926 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
1927 };
1928
1929 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
1930 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
1931 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1932 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1933 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1934 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1935 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1936 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1937 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1938 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1939 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1940 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1941 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1942 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1943 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1944 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1945 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1946 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1947 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1948 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1949 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1950 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
1951 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
1952 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
1953 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
1954 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
1955 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1956 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
1957 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1958 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1959 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1960 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
1961 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
1962 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1963 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1964 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1965 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1966 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1967 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1968 };
1969
1970 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
1971 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1972 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1973 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1974 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1975 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1976 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
1977 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1978 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1979 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1980 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1981 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1982 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1983 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1984 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1985 };
1986
1987 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
1988 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1989 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1990 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
1991 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
1992 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1993 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
1994 };
1995
1996 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
1997 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
1998 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
1999 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
2000 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
2001 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
2002 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
2003 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
2004 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
2005 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
2006 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
2007 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
2008 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
2009 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
2010 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
2011 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
2012 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2013 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2014 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2015 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2016 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
2017 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
2018 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
2019 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2020 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2021 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2022 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2023 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2024 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2025 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
2026 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2027 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2028 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2029 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2030 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
2031 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2032 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
2033 };
2034
2035 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
2036 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
2037 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
2038 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
2039 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
2040 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2041 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2042 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
2043 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
2044 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
2045 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
2046 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
2047 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
2048 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
2049 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
2050 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
2051 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
2052 };
2053
2054 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
2055 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
2056 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
2057 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
2058 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
2059 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
2060 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
2061 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2062 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
2063 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
2064 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
2065 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
2066 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
2067 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
2068 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
2069 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
2070 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
2071 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
2072 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
2073 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
2074 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
2075 };
2076
2077 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
2078 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
2079 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
2080 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
2081 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
2082 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
2083 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
2084 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
2085 };
2086
2087 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
2088 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
2089 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
2090 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
2091 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
2092 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
2093 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
2094 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
2095 };
2096
2097 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
2098 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
2099 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
2100 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
2101 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
2102 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
2103 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
2104 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
2105 };
2106
2107 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
2108 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
2109 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
2110 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
2111 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
2112 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
2113 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
2114 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
2115 };
2116
2117 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
2118 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
2119 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
2120 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
2121 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
2122 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
2123 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
2124 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
2125 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
2126 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
2127 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
2128 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
2129 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
2130 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
2131 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
2132 };
2133
2134 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
2135 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
2136 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
2137 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
2138 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2139 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
2140 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
2141 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
2142 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
2143 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
2144 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2145 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
2146 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
2147 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
2148 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
2149 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
2150 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
2151 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
2152 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
2153 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
2154 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
2155 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
2156 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
2157 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
2158 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
2159 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
2160 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
2161 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
2162 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
2163 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
2164 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2165 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
2166 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
2167 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
2168 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
2169 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
2170 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
2171 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
2172 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2173 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2174 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
2175 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
2176 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
2177 };
2178
2179 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
2180 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2181 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
2182 };
2183
2184 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
2185 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
2186 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
2187 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
2188 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
2189 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
2190 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
2191 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
2192 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2193 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2194 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
2195 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
2196 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
2197 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
2198 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
2199 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
2200 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
2201 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
2202 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
2203 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
2204 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
2205 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
2206 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
2207 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
2208 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
2209 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
2210 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
2211 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
2212 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
2213 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2214 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2215 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
2216 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
2217 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2218 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
2219 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
2220 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
2221 };
2222
2223 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
2224 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2225 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
2226 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
2227 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
2228 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
2229 };
2230
2231 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
2232 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2233 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2234 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2235 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
2236 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
2237 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
2238 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2239 };
2240
2241 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
2242 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
2243 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
2244 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
2245 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2246 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
2247 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
2248 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
2249 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
2250 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
2251 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2252 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
2253 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
2254 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
2255 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
2256 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
2257 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
2258 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
2259 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
2260 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
2261 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
2262 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
2263 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
2264 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
2265 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
2266 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
2267 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
2268 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
2269 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
2270 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
2271 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2272 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
2273 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
2274 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
2275 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
2276 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
2277 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
2278 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2279 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2280 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
2281 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
2282 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
2283 };
2284
2285 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
2286 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
2287 };
2288
2289 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
2290 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2291 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
2292 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
2293 };
2294
2295 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
2296 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
2297 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
2298 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
2299 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2300 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2301 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
2302 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
2303 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
2304 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2305 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
2306 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
2307 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2308 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
2309 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
2310 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
2311 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
2312 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
2313 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
2314 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
2315 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
2316 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
2317 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
2318 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
2319 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
2320 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
2321 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2322 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
2323 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
2324 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
2325 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
2326 };
2327
2328 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
2329 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
2330 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
2331 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2332 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
2333 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
2334 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
2335 };
2336
2337 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
2338 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2339 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
2340 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
2341 };
2342
2343 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
2344 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
2345 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
2346 };
2347
2348 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
2349 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2350 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2351 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2352 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
2353 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
2354 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
2355 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2356 };
2357
2358 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
2359 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
2360 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
2361 };
2362
2363 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
2364 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
2365 };
2366
2367 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
2368 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
2369 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
2370 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
2371 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2372 };
2373
2374 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
2375 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
2376 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
2377 };
2378
2379 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
2380 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
2381 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
2382 };
2383
2384 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
2385 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2386 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
2387 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
2388 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
2389 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
2390 };
2391
2392 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
2393 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
2394 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
2395 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
2396 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
2397 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
2398 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
2399 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
2400 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
2401 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
2402 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
2403 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
2404 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
2405 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
2406 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
2407 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
2408 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2409 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2410 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2411 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2412 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
2413 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
2414 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
2415 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2416 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2417 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2418 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2419 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2420 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2421 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
2422 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2423 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2424 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2425 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2426 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
2427 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2428 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
2429 };
2430
2431 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
2432 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
2433 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
2434 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
2435 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2436 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
2437 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
2438 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
2439 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
2440 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
2441 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
2442 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
2443 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
2444 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
2445 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
2446 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
2447 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
2448 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
2449 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
2450 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
2451 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
2452 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
2453 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
2454 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
2455 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
2456 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
2457 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
2458 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2459 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
2460 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
2461 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
2462 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
2463 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
2464 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
2465 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
2466 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
2467 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
2468 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
2469 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
2470 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
2471 };
2472
2473 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
2474 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
2475 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
2476 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
2477 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
2478 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
2479 };
2480
2481 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
2482 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
2483 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
2484 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
2485 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
2486 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
2487 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
2488 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
2489 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
2490 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
2491 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
2492 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
2493 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
2494 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
2495 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
2496 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
2497 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
2498 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
2499 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
2500 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
2501 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
2502 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
2503 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
2504 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
2505 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2506 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
2507 };
2508
2509 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
2510 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
2511 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
2512 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
2513 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
2514 };
2515
2516 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
2517 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
2518 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
2519 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
2520 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
2521 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
2522 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
2523 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
2524 };
2525
2526 static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
2527 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
2528 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
2529 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2530 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
2531 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2532 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2533 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
2534 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2535 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2536 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
2537 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
2538 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
2539 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
2540 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
2541 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
2542 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2543 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
2544 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
2545 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
2546 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
2547 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
2548 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
2549 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
2550 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
2551
2552 /* Rate B */
2553 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
2554 };
2555
2556 static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
2557 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
2558 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
2559 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
2560 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
2561 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
2562 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2563 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
2564 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
2565 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
2566 };
2567
2568 static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
2569 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
2570 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
2571 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
2572 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
2573 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
2574 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
2575 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
2576 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
2577 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
2578 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
2579 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
2580 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
2581 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
2582 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
2583 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
2584 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
2585 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
2586 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
2587 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
2588 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2589 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2590 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
2591 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
2592 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
2593 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
2594 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
2595 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
2596 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
2597 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
2598 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
2599 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
2600 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
2601 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
2602 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
2603 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
2604 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
2605 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
2606 };
2607
2608 static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
2609 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
2610 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
2611 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
2612 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
2613 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
2614 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
2615 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
2616 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
2617 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
2618 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
2619 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
2620 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
2621 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
2622 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
2623 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
2624 };
2625
2626 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
2627 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
2628 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
2629 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
2630 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
2631 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
2632 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2633 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
2634 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
2635 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
2636 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
2637 };
2638
2639 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
2640 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
2641 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
2642 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2643 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2644 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2645 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2646 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
2647 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
2648 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
2649 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
2650 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
2651 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
2652 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
2653 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2654 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2655 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2656 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2657 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2658 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2659 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
2660 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2661 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
2662 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
2663 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
2664 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
2665 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
2666 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
2667 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
2668 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
2669 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
2670 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
2671 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
2672 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
2673 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2674 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
2675 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
2676 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
2677 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
2678 };
2679
2680 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
2681 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
2682 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
2683 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2684 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2685 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
2686 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
2687 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
2688 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
2689 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
2690 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
2691 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
2692 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
2693 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
2694 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
2695 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
2696 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
2697 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
2698 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
2699 };
2700
2701 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
2702 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
2703 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
2704 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2705 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
2706 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
2707 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
2708 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
2709 };
2710
2711 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
2712 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
2713 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
2714 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
2715 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
2716 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
2717 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
2718 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
2719 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
2720 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
2721 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
2722 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
2723 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
2724 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
2725 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
2726 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
2727 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2728 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2729 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2730 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
2731 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
2732 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
2733 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2734 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2735 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2736 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2737 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
2738 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2739 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2740 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
2741 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
2742 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
2743 };
2744
2745 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
2746 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
2747 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
2748 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
2749 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
2750 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2751 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2752 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
2753 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
2754 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
2755 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
2756 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
2757 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
2758 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
2759 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
2760 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
2761 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
2762 };
2763
2764 struct qmp_phy;
2765
2766 /* struct qmp_phy_cfg - per-PHY initialization config */
2767 struct qmp_phy_cfg {
2768 /* phy-type - PCIE/UFS/USB */
2769 unsigned int type;
2770 /* number of lanes provided by phy */
2771 int nlanes;
2772
2773 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
2774 const struct qmp_phy_init_tbl *serdes_tbl;
2775 int serdes_tbl_num;
2776 const struct qmp_phy_init_tbl *serdes_tbl_sec;
2777 int serdes_tbl_num_sec;
2778 const struct qmp_phy_init_tbl *tx_tbl;
2779 int tx_tbl_num;
2780 const struct qmp_phy_init_tbl *tx_tbl_sec;
2781 int tx_tbl_num_sec;
2782 const struct qmp_phy_init_tbl *rx_tbl;
2783 int rx_tbl_num;
2784 const struct qmp_phy_init_tbl *rx_tbl_sec;
2785 int rx_tbl_num_sec;
2786 const struct qmp_phy_init_tbl *pcs_tbl;
2787 int pcs_tbl_num;
2788 const struct qmp_phy_init_tbl *pcs_tbl_sec;
2789 int pcs_tbl_num_sec;
2790 const struct qmp_phy_init_tbl *pcs_misc_tbl;
2791 int pcs_misc_tbl_num;
2792 const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
2793 int pcs_misc_tbl_num_sec;
2794
2795 /* Init sequence for DP PHY block link rates */
2796 const struct qmp_phy_init_tbl *serdes_tbl_rbr;
2797 int serdes_tbl_rbr_num;
2798 const struct qmp_phy_init_tbl *serdes_tbl_hbr;
2799 int serdes_tbl_hbr_num;
2800 const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
2801 int serdes_tbl_hbr2_num;
2802 const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
2803 int serdes_tbl_hbr3_num;
2804
2805 /* DP PHY callbacks */
2806 int (*configure_dp_phy)(struct qmp_phy *qphy);
2807 void (*configure_dp_tx)(struct qmp_phy *qphy);
2808 int (*calibrate_dp_phy)(struct qmp_phy *qphy);
2809 void (*dp_aux_init)(struct qmp_phy *qphy);
2810
2811 /* clock ids to be requested */
2812 const char * const *clk_list;
2813 int num_clks;
2814 /* resets to be requested */
2815 const char * const *reset_list;
2816 int num_resets;
2817 /* regulators to be requested */
2818 const char * const *vreg_list;
2819 int num_vregs;
2820
2821 /* array of registers with different offsets */
2822 const unsigned int *regs;
2823
2824 unsigned int start_ctrl;
2825 unsigned int pwrdn_ctrl;
2826 unsigned int mask_com_pcs_ready;
2827 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
2828 unsigned int phy_status;
2829
2830 /* true, if PHY has a separate PHY_COM control block */
2831 bool has_phy_com_ctrl;
2832 /* true, if PHY has a reset for individual lanes */
2833 bool has_lane_rst;
2834 /* true, if PHY needs delay after POWER_DOWN */
2835 bool has_pwrdn_delay;
2836 /* power_down delay in usec */
2837 int pwrdn_delay_min;
2838 int pwrdn_delay_max;
2839
2840 /* true, if PHY has a separate DP_COM control block */
2841 bool has_phy_dp_com_ctrl;
2842 /* true, if PHY has secondary tx/rx lanes to be configured */
2843 bool is_dual_lane_phy;
2844
2845 /* true, if PCS block has no separate SW_RESET register */
2846 bool no_pcs_sw_reset;
2847 };
2848
2849 struct qmp_phy_combo_cfg {
2850 const struct qmp_phy_cfg *usb_cfg;
2851 const struct qmp_phy_cfg *dp_cfg;
2852 };
2853
2854 /**
2855 * struct qmp_phy - per-lane phy descriptor
2856 *
2857 * @phy: generic phy
2858 * @cfg: phy specific configuration
2859 * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
2860 * @tx: iomapped memory space for lane's tx
2861 * @rx: iomapped memory space for lane's rx
2862 * @pcs: iomapped memory space for lane's pcs
2863 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
2864 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
2865 * @pcs_misc: iomapped memory space for lane's pcs_misc
2866 * @pipe_clk: pipe lock
2867 * @index: lane index
2868 * @qmp: QMP phy to which this lane belongs
2869 * @lane_rst: lane's reset controller
2870 * @mode: current PHY mode
2871 */
2872 struct qmp_phy {
2873 struct phy *phy;
2874 const struct qmp_phy_cfg *cfg;
2875 void __iomem *serdes;
2876 void __iomem *tx;
2877 void __iomem *rx;
2878 void __iomem *pcs;
2879 void __iomem *tx2;
2880 void __iomem *rx2;
2881 void __iomem *pcs_misc;
2882 struct clk *pipe_clk;
2883 unsigned int index;
2884 struct qcom_qmp *qmp;
2885 struct reset_control *lane_rst;
2886 enum phy_mode mode;
2887 unsigned int dp_aux_cfg;
2888 struct phy_configure_opts_dp dp_opts;
2889 struct qmp_phy_dp_clks *dp_clks;
2890 };
2891
2892 struct qmp_phy_dp_clks {
2893 struct qmp_phy *qphy;
2894 struct clk_hw dp_link_hw;
2895 struct clk_hw dp_pixel_hw;
2896 };
2897
2898 /**
2899 * struct qcom_qmp - structure holding QMP phy block attributes
2900 *
2901 * @dev: device
2902 * @dp_com: iomapped memory space for phy's dp_com control block
2903 *
2904 * @clks: array of clocks required by phy
2905 * @resets: array of resets required by phy
2906 * @vregs: regulator supplies bulk data
2907 *
2908 * @phys: array of per-lane phy descriptors
2909 * @phy_mutex: mutex lock for PHY common block initialization
2910 * @init_count: phy common block initialization count
2911 * @ufs_reset: optional UFS PHY reset handle
2912 */
2913 struct qcom_qmp {
2914 struct device *dev;
2915 void __iomem *dp_com;
2916
2917 struct clk_bulk_data *clks;
2918 struct reset_control **resets;
2919 struct regulator_bulk_data *vregs;
2920
2921 struct qmp_phy **phys;
2922
2923 struct mutex phy_mutex;
2924 int init_count;
2925
2926 struct reset_control *ufs_reset;
2927 };
2928
2929 static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
2930 static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
2931 static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
2932 static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
2933
2934 static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
2935 static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
2936 static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
2937 static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
2938
qphy_setbits(void __iomem * base,u32 offset,u32 val)2939 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
2940 {
2941 u32 reg;
2942
2943 reg = readl(base + offset);
2944 reg |= val;
2945 writel(reg, base + offset);
2946
2947 /* ensure that above write is through */
2948 readl(base + offset);
2949 }
2950
qphy_clrbits(void __iomem * base,u32 offset,u32 val)2951 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
2952 {
2953 u32 reg;
2954
2955 reg = readl(base + offset);
2956 reg &= ~val;
2957 writel(reg, base + offset);
2958
2959 /* ensure that above write is through */
2960 readl(base + offset);
2961 }
2962
2963 /* list of clocks required by phy */
2964 static const char * const msm8996_phy_clk_l[] = {
2965 "aux", "cfg_ahb", "ref",
2966 };
2967
2968 static const char * const msm8996_ufs_phy_clk_l[] = {
2969 "ref",
2970 };
2971
2972 static const char * const qmp_v3_phy_clk_l[] = {
2973 "aux", "cfg_ahb", "ref", "com_aux",
2974 };
2975
2976 static const char * const sdm845_pciephy_clk_l[] = {
2977 "aux", "cfg_ahb", "ref", "refgen",
2978 };
2979
2980 static const char * const qmp_v4_phy_clk_l[] = {
2981 "aux", "ref_clk_src", "ref", "com_aux",
2982 };
2983
2984 /* the primary usb3 phy on sm8250 doesn't have a ref clock */
2985 static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
2986 "aux", "ref_clk_src", "com_aux"
2987 };
2988
2989 static const char * const sdm845_ufs_phy_clk_l[] = {
2990 "ref", "ref_aux",
2991 };
2992
2993 /* usb3 phy on sdx55 doesn't have com_aux clock */
2994 static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
2995 "aux", "cfg_ahb", "ref"
2996 };
2997
2998 /* list of resets */
2999 static const char * const msm8996_pciephy_reset_l[] = {
3000 "phy", "common", "cfg",
3001 };
3002
3003 static const char * const msm8996_usb3phy_reset_l[] = {
3004 "phy", "common",
3005 };
3006
3007 static const char * const sc7180_usb3phy_reset_l[] = {
3008 "phy",
3009 };
3010
3011 static const char * const sdm845_pciephy_reset_l[] = {
3012 "phy",
3013 };
3014
3015 /* list of regulators */
3016 static const char * const qmp_phy_vreg_l[] = {
3017 "vdda-phy", "vdda-pll",
3018 };
3019
3020 static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
3021 .type = PHY_TYPE_USB3,
3022 .nlanes = 1,
3023
3024 .serdes_tbl = ipq8074_usb3_serdes_tbl,
3025 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
3026 .tx_tbl = msm8996_usb3_tx_tbl,
3027 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
3028 .rx_tbl = ipq8074_usb3_rx_tbl,
3029 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
3030 .pcs_tbl = ipq8074_usb3_pcs_tbl,
3031 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
3032 .clk_list = msm8996_phy_clk_l,
3033 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
3034 .reset_list = msm8996_usb3phy_reset_l,
3035 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3036 .vreg_list = qmp_phy_vreg_l,
3037 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3038 .regs = usb3phy_regs_layout,
3039
3040 .start_ctrl = SERDES_START | PCS_START,
3041 .pwrdn_ctrl = SW_PWRDN,
3042 .phy_status = PHYSTATUS,
3043 };
3044
3045 static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
3046 .type = PHY_TYPE_PCIE,
3047 .nlanes = 3,
3048
3049 .serdes_tbl = msm8996_pcie_serdes_tbl,
3050 .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
3051 .tx_tbl = msm8996_pcie_tx_tbl,
3052 .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
3053 .rx_tbl = msm8996_pcie_rx_tbl,
3054 .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
3055 .pcs_tbl = msm8996_pcie_pcs_tbl,
3056 .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
3057 .clk_list = msm8996_phy_clk_l,
3058 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
3059 .reset_list = msm8996_pciephy_reset_l,
3060 .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
3061 .vreg_list = qmp_phy_vreg_l,
3062 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3063 .regs = pciephy_regs_layout,
3064
3065 .start_ctrl = PCS_START | PLL_READY_GATE_EN,
3066 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3067 .mask_com_pcs_ready = PCS_READY,
3068 .phy_status = PHYSTATUS,
3069
3070 .has_phy_com_ctrl = true,
3071 .has_lane_rst = true,
3072 .has_pwrdn_delay = true,
3073 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3074 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3075 };
3076
3077 static const struct qmp_phy_cfg msm8996_ufs_cfg = {
3078 .type = PHY_TYPE_UFS,
3079 .nlanes = 1,
3080
3081 .serdes_tbl = msm8996_ufs_serdes_tbl,
3082 .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
3083 .tx_tbl = msm8996_ufs_tx_tbl,
3084 .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
3085 .rx_tbl = msm8996_ufs_rx_tbl,
3086 .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
3087
3088 .clk_list = msm8996_ufs_phy_clk_l,
3089 .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
3090
3091 .vreg_list = qmp_phy_vreg_l,
3092 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3093
3094 .regs = msm8996_ufsphy_regs_layout,
3095
3096 .start_ctrl = SERDES_START,
3097 .pwrdn_ctrl = SW_PWRDN,
3098 .phy_status = PHYSTATUS,
3099
3100 .no_pcs_sw_reset = true,
3101 };
3102
3103 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
3104 .type = PHY_TYPE_USB3,
3105 .nlanes = 1,
3106
3107 .serdes_tbl = msm8996_usb3_serdes_tbl,
3108 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
3109 .tx_tbl = msm8996_usb3_tx_tbl,
3110 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
3111 .rx_tbl = msm8996_usb3_rx_tbl,
3112 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
3113 .pcs_tbl = msm8996_usb3_pcs_tbl,
3114 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
3115 .clk_list = msm8996_phy_clk_l,
3116 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
3117 .reset_list = msm8996_usb3phy_reset_l,
3118 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3119 .vreg_list = qmp_phy_vreg_l,
3120 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3121 .regs = usb3phy_regs_layout,
3122
3123 .start_ctrl = SERDES_START | PCS_START,
3124 .pwrdn_ctrl = SW_PWRDN,
3125 .phy_status = PHYSTATUS,
3126 };
3127
3128 static const char * const ipq8074_pciephy_clk_l[] = {
3129 "aux", "cfg_ahb",
3130 };
3131 /* list of resets */
3132 static const char * const ipq8074_pciephy_reset_l[] = {
3133 "phy", "common",
3134 };
3135
3136 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
3137 .type = PHY_TYPE_PCIE,
3138 .nlanes = 1,
3139
3140 .serdes_tbl = ipq8074_pcie_serdes_tbl,
3141 .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
3142 .tx_tbl = ipq8074_pcie_tx_tbl,
3143 .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
3144 .rx_tbl = ipq8074_pcie_rx_tbl,
3145 .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
3146 .pcs_tbl = ipq8074_pcie_pcs_tbl,
3147 .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
3148 .clk_list = ipq8074_pciephy_clk_l,
3149 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
3150 .reset_list = ipq8074_pciephy_reset_l,
3151 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3152 .vreg_list = NULL,
3153 .num_vregs = 0,
3154 .regs = pciephy_regs_layout,
3155
3156 .start_ctrl = SERDES_START | PCS_START,
3157 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3158 .phy_status = PHYSTATUS,
3159
3160 .has_phy_com_ctrl = false,
3161 .has_lane_rst = false,
3162 .has_pwrdn_delay = true,
3163 .pwrdn_delay_min = 995, /* us */
3164 .pwrdn_delay_max = 1005, /* us */
3165 };
3166
3167 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
3168 .type = PHY_TYPE_PCIE,
3169 .nlanes = 1,
3170
3171 .serdes_tbl = ipq6018_pcie_serdes_tbl,
3172 .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
3173 .tx_tbl = ipq6018_pcie_tx_tbl,
3174 .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
3175 .rx_tbl = ipq6018_pcie_rx_tbl,
3176 .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
3177 .pcs_tbl = ipq6018_pcie_pcs_tbl,
3178 .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
3179 .clk_list = ipq8074_pciephy_clk_l,
3180 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
3181 .reset_list = ipq8074_pciephy_reset_l,
3182 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3183 .vreg_list = NULL,
3184 .num_vregs = 0,
3185 .regs = ipq_pciephy_gen3_regs_layout,
3186
3187 .start_ctrl = SERDES_START | PCS_START,
3188 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3189
3190 .has_phy_com_ctrl = false,
3191 .has_lane_rst = false,
3192 .has_pwrdn_delay = true,
3193 .pwrdn_delay_min = 995, /* us */
3194 .pwrdn_delay_max = 1005, /* us */
3195 };
3196
3197 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
3198 .type = PHY_TYPE_PCIE,
3199 .nlanes = 1,
3200
3201 .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
3202 .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
3203 .tx_tbl = sdm845_qmp_pcie_tx_tbl,
3204 .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
3205 .rx_tbl = sdm845_qmp_pcie_rx_tbl,
3206 .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
3207 .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
3208 .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
3209 .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
3210 .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
3211 .clk_list = sdm845_pciephy_clk_l,
3212 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
3213 .reset_list = sdm845_pciephy_reset_l,
3214 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3215 .vreg_list = qmp_phy_vreg_l,
3216 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3217 .regs = sdm845_qmp_pciephy_regs_layout,
3218
3219 .start_ctrl = PCS_START | SERDES_START,
3220 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3221 .phy_status = PHYSTATUS,
3222
3223 .has_pwrdn_delay = true,
3224 .pwrdn_delay_min = 995, /* us */
3225 .pwrdn_delay_max = 1005, /* us */
3226 };
3227
3228 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
3229 .type = PHY_TYPE_PCIE,
3230 .nlanes = 1,
3231
3232 .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
3233 .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
3234 .tx_tbl = sdm845_qhp_pcie_tx_tbl,
3235 .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
3236 .rx_tbl = sdm845_qhp_pcie_rx_tbl,
3237 .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
3238 .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
3239 .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
3240 .clk_list = sdm845_pciephy_clk_l,
3241 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
3242 .reset_list = sdm845_pciephy_reset_l,
3243 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3244 .vreg_list = qmp_phy_vreg_l,
3245 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3246 .regs = sdm845_qhp_pciephy_regs_layout,
3247
3248 .start_ctrl = PCS_START | SERDES_START,
3249 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3250 .phy_status = PHYSTATUS,
3251
3252 .has_pwrdn_delay = true,
3253 .pwrdn_delay_min = 995, /* us */
3254 .pwrdn_delay_max = 1005, /* us */
3255 };
3256
3257 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
3258 .type = PHY_TYPE_PCIE,
3259 .nlanes = 1,
3260
3261 .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
3262 .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
3263 .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
3264 .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
3265 .tx_tbl = sm8250_qmp_pcie_tx_tbl,
3266 .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
3267 .rx_tbl = sm8250_qmp_pcie_rx_tbl,
3268 .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
3269 .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
3270 .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
3271 .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
3272 .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
3273 .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
3274 .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
3275 .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
3276 .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
3277 .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
3278 .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
3279 .clk_list = sdm845_pciephy_clk_l,
3280 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
3281 .reset_list = sdm845_pciephy_reset_l,
3282 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3283 .vreg_list = qmp_phy_vreg_l,
3284 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3285 .regs = sm8250_pcie_regs_layout,
3286
3287 .start_ctrl = PCS_START | SERDES_START,
3288 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3289 .phy_status = PHYSTATUS,
3290
3291 .has_pwrdn_delay = true,
3292 .pwrdn_delay_min = 995, /* us */
3293 .pwrdn_delay_max = 1005, /* us */
3294 };
3295
3296 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
3297 .type = PHY_TYPE_PCIE,
3298 .nlanes = 2,
3299
3300 .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
3301 .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
3302 .tx_tbl = sm8250_qmp_pcie_tx_tbl,
3303 .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
3304 .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
3305 .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
3306 .rx_tbl = sm8250_qmp_pcie_rx_tbl,
3307 .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
3308 .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
3309 .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
3310 .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
3311 .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
3312 .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
3313 .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
3314 .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
3315 .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
3316 .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
3317 .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
3318 .clk_list = sdm845_pciephy_clk_l,
3319 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
3320 .reset_list = sdm845_pciephy_reset_l,
3321 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3322 .vreg_list = qmp_phy_vreg_l,
3323 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3324 .regs = sm8250_pcie_regs_layout,
3325
3326 .start_ctrl = PCS_START | SERDES_START,
3327 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3328 .phy_status = PHYSTATUS,
3329
3330 .is_dual_lane_phy = true,
3331 .has_pwrdn_delay = true,
3332 .pwrdn_delay_min = 995, /* us */
3333 .pwrdn_delay_max = 1005, /* us */
3334 };
3335
3336 static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
3337 .type = PHY_TYPE_USB3,
3338 .nlanes = 1,
3339
3340 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
3341 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
3342 .tx_tbl = qmp_v3_usb3_tx_tbl,
3343 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
3344 .rx_tbl = qmp_v3_usb3_rx_tbl,
3345 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
3346 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
3347 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
3348 .clk_list = qmp_v3_phy_clk_l,
3349 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
3350 .reset_list = msm8996_usb3phy_reset_l,
3351 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3352 .vreg_list = qmp_phy_vreg_l,
3353 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3354 .regs = qmp_v3_usb3phy_regs_layout,
3355
3356 .start_ctrl = SERDES_START | PCS_START,
3357 .pwrdn_ctrl = SW_PWRDN,
3358 .phy_status = PHYSTATUS,
3359
3360 .has_pwrdn_delay = true,
3361 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3362 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3363
3364 .has_phy_dp_com_ctrl = true,
3365 .is_dual_lane_phy = true,
3366 };
3367
3368 static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
3369 .type = PHY_TYPE_USB3,
3370 .nlanes = 1,
3371
3372 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
3373 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
3374 .tx_tbl = qmp_v3_usb3_tx_tbl,
3375 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
3376 .rx_tbl = qmp_v3_usb3_rx_tbl,
3377 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
3378 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
3379 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
3380 .clk_list = qmp_v3_phy_clk_l,
3381 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
3382 .reset_list = sc7180_usb3phy_reset_l,
3383 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
3384 .vreg_list = qmp_phy_vreg_l,
3385 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3386 .regs = qmp_v3_usb3phy_regs_layout,
3387
3388 .start_ctrl = SERDES_START | PCS_START,
3389 .pwrdn_ctrl = SW_PWRDN,
3390 .phy_status = PHYSTATUS,
3391
3392 .has_pwrdn_delay = true,
3393 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3394 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3395
3396 .has_phy_dp_com_ctrl = true,
3397 .is_dual_lane_phy = true,
3398 };
3399
3400 static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
3401 .type = PHY_TYPE_DP,
3402 .nlanes = 1,
3403
3404 .serdes_tbl = qmp_v3_dp_serdes_tbl,
3405 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
3406 .tx_tbl = qmp_v3_dp_tx_tbl,
3407 .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
3408
3409 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
3410 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
3411 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
3412 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
3413 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
3414 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
3415 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
3416 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
3417
3418 .clk_list = qmp_v3_phy_clk_l,
3419 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
3420 .reset_list = sc7180_usb3phy_reset_l,
3421 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
3422 .vreg_list = qmp_phy_vreg_l,
3423 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3424 .regs = qmp_v3_usb3phy_regs_layout,
3425
3426 .has_phy_dp_com_ctrl = true,
3427 .is_dual_lane_phy = true,
3428
3429 .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
3430 .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
3431 .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
3432 .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
3433 };
3434
3435 static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
3436 .usb_cfg = &sc7180_usb3phy_cfg,
3437 .dp_cfg = &sc7180_dpphy_cfg,
3438 };
3439
3440 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
3441 .type = PHY_TYPE_USB3,
3442 .nlanes = 1,
3443
3444 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
3445 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
3446 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
3447 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
3448 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
3449 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
3450 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
3451 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
3452 .clk_list = qmp_v3_phy_clk_l,
3453 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
3454 .reset_list = msm8996_usb3phy_reset_l,
3455 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3456 .vreg_list = qmp_phy_vreg_l,
3457 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3458 .regs = qmp_v3_usb3phy_regs_layout,
3459
3460 .start_ctrl = SERDES_START | PCS_START,
3461 .pwrdn_ctrl = SW_PWRDN,
3462 .phy_status = PHYSTATUS,
3463
3464 .has_pwrdn_delay = true,
3465 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3466 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3467 };
3468
3469 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
3470 .type = PHY_TYPE_UFS,
3471 .nlanes = 2,
3472
3473 .serdes_tbl = sdm845_ufsphy_serdes_tbl,
3474 .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
3475 .tx_tbl = sdm845_ufsphy_tx_tbl,
3476 .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
3477 .rx_tbl = sdm845_ufsphy_rx_tbl,
3478 .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
3479 .pcs_tbl = sdm845_ufsphy_pcs_tbl,
3480 .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
3481 .clk_list = sdm845_ufs_phy_clk_l,
3482 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3483 .vreg_list = qmp_phy_vreg_l,
3484 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3485 .regs = sdm845_ufsphy_regs_layout,
3486
3487 .start_ctrl = SERDES_START,
3488 .pwrdn_ctrl = SW_PWRDN,
3489 .phy_status = PHYSTATUS,
3490
3491 .is_dual_lane_phy = true,
3492 .no_pcs_sw_reset = true,
3493 };
3494
3495 static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
3496 .type = PHY_TYPE_UFS,
3497 .nlanes = 1,
3498
3499 .serdes_tbl = sm6115_ufsphy_serdes_tbl,
3500 .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
3501 .tx_tbl = sm6115_ufsphy_tx_tbl,
3502 .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
3503 .rx_tbl = sm6115_ufsphy_rx_tbl,
3504 .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
3505 .pcs_tbl = sm6115_ufsphy_pcs_tbl,
3506 .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
3507 .clk_list = sdm845_ufs_phy_clk_l,
3508 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3509 .vreg_list = qmp_phy_vreg_l,
3510 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3511 .regs = sm6115_ufsphy_regs_layout,
3512
3513 .start_ctrl = SERDES_START,
3514 .pwrdn_ctrl = SW_PWRDN,
3515
3516 .is_dual_lane_phy = false,
3517 .no_pcs_sw_reset = true,
3518 };
3519
3520 static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
3521 .type = PHY_TYPE_PCIE,
3522 .nlanes = 1,
3523
3524 .serdes_tbl = msm8998_pcie_serdes_tbl,
3525 .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
3526 .tx_tbl = msm8998_pcie_tx_tbl,
3527 .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
3528 .rx_tbl = msm8998_pcie_rx_tbl,
3529 .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
3530 .pcs_tbl = msm8998_pcie_pcs_tbl,
3531 .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
3532 .clk_list = msm8996_phy_clk_l,
3533 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
3534 .reset_list = ipq8074_pciephy_reset_l,
3535 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3536 .vreg_list = qmp_phy_vreg_l,
3537 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3538 .regs = pciephy_regs_layout,
3539
3540 .start_ctrl = SERDES_START | PCS_START,
3541 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3542 .phy_status = PHYSTATUS,
3543 };
3544
3545 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
3546 .type = PHY_TYPE_USB3,
3547 .nlanes = 1,
3548
3549 .serdes_tbl = msm8998_usb3_serdes_tbl,
3550 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
3551 .tx_tbl = msm8998_usb3_tx_tbl,
3552 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
3553 .rx_tbl = msm8998_usb3_rx_tbl,
3554 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
3555 .pcs_tbl = msm8998_usb3_pcs_tbl,
3556 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
3557 .clk_list = msm8996_phy_clk_l,
3558 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
3559 .reset_list = msm8996_usb3phy_reset_l,
3560 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3561 .vreg_list = qmp_phy_vreg_l,
3562 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3563 .regs = qmp_v3_usb3phy_regs_layout,
3564
3565 .start_ctrl = SERDES_START | PCS_START,
3566 .pwrdn_ctrl = SW_PWRDN,
3567 .phy_status = PHYSTATUS,
3568
3569 .is_dual_lane_phy = true,
3570 };
3571
3572 static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
3573 .type = PHY_TYPE_UFS,
3574 .nlanes = 2,
3575
3576 .serdes_tbl = sm8150_ufsphy_serdes_tbl,
3577 .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
3578 .tx_tbl = sm8150_ufsphy_tx_tbl,
3579 .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
3580 .rx_tbl = sm8150_ufsphy_rx_tbl,
3581 .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
3582 .pcs_tbl = sm8150_ufsphy_pcs_tbl,
3583 .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
3584 .clk_list = sdm845_ufs_phy_clk_l,
3585 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3586 .vreg_list = qmp_phy_vreg_l,
3587 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3588 .regs = sm8150_ufsphy_regs_layout,
3589
3590 .start_ctrl = SERDES_START,
3591 .pwrdn_ctrl = SW_PWRDN,
3592 .phy_status = PHYSTATUS,
3593
3594 .is_dual_lane_phy = true,
3595 };
3596
3597 static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
3598 .type = PHY_TYPE_USB3,
3599 .nlanes = 1,
3600
3601 .serdes_tbl = sm8150_usb3_serdes_tbl,
3602 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
3603 .tx_tbl = sm8150_usb3_tx_tbl,
3604 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
3605 .rx_tbl = sm8150_usb3_rx_tbl,
3606 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
3607 .pcs_tbl = sm8150_usb3_pcs_tbl,
3608 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
3609 .clk_list = qmp_v4_phy_clk_l,
3610 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
3611 .reset_list = msm8996_usb3phy_reset_l,
3612 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3613 .vreg_list = qmp_phy_vreg_l,
3614 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3615 .regs = qmp_v4_usb3phy_regs_layout,
3616
3617 .start_ctrl = SERDES_START | PCS_START,
3618 .pwrdn_ctrl = SW_PWRDN,
3619 .phy_status = PHYSTATUS,
3620
3621
3622 .has_pwrdn_delay = true,
3623 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3624 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3625
3626 .has_phy_dp_com_ctrl = true,
3627 .is_dual_lane_phy = true,
3628 };
3629
3630 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
3631 .type = PHY_TYPE_PCIE,
3632 .nlanes = 1,
3633
3634 .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
3635 .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
3636 .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
3637 .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
3638 .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
3639 .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
3640 .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
3641 .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
3642 .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
3643 .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
3644 .clk_list = sdm845_pciephy_clk_l,
3645 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
3646 .reset_list = sdm845_pciephy_reset_l,
3647 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3648 .vreg_list = qmp_phy_vreg_l,
3649 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3650 .regs = sm8250_pcie_regs_layout,
3651
3652 .start_ctrl = PCS_START | SERDES_START,
3653 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3654
3655 .has_pwrdn_delay = true,
3656 .pwrdn_delay_min = 995, /* us */
3657 .pwrdn_delay_max = 1005, /* us */
3658 };
3659
3660 static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
3661 .type = PHY_TYPE_DP,
3662 .nlanes = 1,
3663
3664 .serdes_tbl = qmp_v4_dp_serdes_tbl,
3665 .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
3666 .tx_tbl = qmp_v4_dp_tx_tbl,
3667 .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
3668
3669 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
3670 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
3671 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
3672 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
3673 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
3674 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
3675 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
3676 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
3677
3678 .clk_list = qmp_v3_phy_clk_l,
3679 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
3680 .reset_list = sc7180_usb3phy_reset_l,
3681 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
3682 .vreg_list = qmp_phy_vreg_l,
3683 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3684 .regs = qmp_v3_usb3phy_regs_layout,
3685
3686 .has_phy_dp_com_ctrl = true,
3687 .is_dual_lane_phy = true,
3688
3689 .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
3690 .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
3691 .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
3692 .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
3693 };
3694
3695 static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
3696 .usb_cfg = &sm8150_usb3phy_cfg,
3697 .dp_cfg = &sc8180x_dpphy_cfg,
3698 };
3699
3700 static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
3701 .type = PHY_TYPE_USB3,
3702 .nlanes = 1,
3703
3704 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
3705 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
3706 .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
3707 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
3708 .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
3709 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
3710 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
3711 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
3712 .clk_list = qmp_v4_phy_clk_l,
3713 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
3714 .reset_list = msm8996_usb3phy_reset_l,
3715 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3716 .vreg_list = qmp_phy_vreg_l,
3717 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3718 .regs = qmp_v4_usb3_uniphy_regs_layout,
3719
3720 .start_ctrl = SERDES_START | PCS_START,
3721 .pwrdn_ctrl = SW_PWRDN,
3722 .phy_status = PHYSTATUS,
3723
3724 .has_pwrdn_delay = true,
3725 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3726 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3727 };
3728
3729 static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
3730 .type = PHY_TYPE_USB3,
3731 .nlanes = 1,
3732
3733 .serdes_tbl = sm8150_usb3_serdes_tbl,
3734 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
3735 .tx_tbl = sm8250_usb3_tx_tbl,
3736 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
3737 .rx_tbl = sm8250_usb3_rx_tbl,
3738 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
3739 .pcs_tbl = sm8250_usb3_pcs_tbl,
3740 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
3741 .clk_list = qmp_v4_sm8250_usbphy_clk_l,
3742 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
3743 .reset_list = msm8996_usb3phy_reset_l,
3744 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3745 .vreg_list = qmp_phy_vreg_l,
3746 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3747 .regs = qmp_v4_usb3phy_regs_layout,
3748
3749 .start_ctrl = SERDES_START | PCS_START,
3750 .pwrdn_ctrl = SW_PWRDN,
3751 .phy_status = PHYSTATUS,
3752
3753 .has_pwrdn_delay = true,
3754 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3755 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3756
3757 .has_phy_dp_com_ctrl = true,
3758 .is_dual_lane_phy = true,
3759 };
3760
3761 static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
3762 .type = PHY_TYPE_USB3,
3763 .nlanes = 1,
3764
3765 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
3766 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
3767 .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
3768 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
3769 .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
3770 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
3771 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
3772 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
3773 .clk_list = qmp_v4_phy_clk_l,
3774 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
3775 .reset_list = msm8996_usb3phy_reset_l,
3776 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3777 .vreg_list = qmp_phy_vreg_l,
3778 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3779 .regs = qmp_v4_usb3_uniphy_regs_layout,
3780
3781 .start_ctrl = SERDES_START | PCS_START,
3782 .pwrdn_ctrl = SW_PWRDN,
3783 .phy_status = PHYSTATUS,
3784
3785 .has_pwrdn_delay = true,
3786 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3787 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3788 };
3789
3790 static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
3791 .type = PHY_TYPE_DP,
3792 .nlanes = 1,
3793
3794 .serdes_tbl = qmp_v4_dp_serdes_tbl,
3795 .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
3796 .tx_tbl = qmp_v4_dp_tx_tbl,
3797 .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
3798
3799 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
3800 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
3801 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
3802 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
3803 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
3804 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
3805 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
3806 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
3807
3808 .clk_list = qmp_v4_phy_clk_l,
3809 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
3810 .reset_list = msm8996_usb3phy_reset_l,
3811 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3812 .vreg_list = qmp_phy_vreg_l,
3813 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3814 .regs = qmp_v4_usb3phy_regs_layout,
3815
3816 .has_phy_dp_com_ctrl = true,
3817 .is_dual_lane_phy = true,
3818
3819 .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
3820 .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
3821 .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
3822 .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
3823 };
3824
3825 static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
3826 .usb_cfg = &sm8250_usb3phy_cfg,
3827 .dp_cfg = &sm8250_dpphy_cfg,
3828 };
3829
3830 static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
3831 .type = PHY_TYPE_USB3,
3832 .nlanes = 1,
3833
3834 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
3835 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
3836 .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
3837 .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
3838 .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
3839 .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
3840 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
3841 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
3842 .clk_list = qmp_v4_sdx55_usbphy_clk_l,
3843 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
3844 .reset_list = msm8996_usb3phy_reset_l,
3845 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3846 .vreg_list = qmp_phy_vreg_l,
3847 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3848 .regs = qmp_v4_usb3_uniphy_regs_layout,
3849
3850 .start_ctrl = SERDES_START | PCS_START,
3851 .pwrdn_ctrl = SW_PWRDN,
3852 .phy_status = PHYSTATUS,
3853
3854 .has_pwrdn_delay = true,
3855 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3856 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3857 };
3858
3859 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
3860 .type = PHY_TYPE_PCIE,
3861 .nlanes = 2,
3862
3863 .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
3864 .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
3865 .tx_tbl = sdx55_qmp_pcie_tx_tbl,
3866 .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
3867 .rx_tbl = sdx55_qmp_pcie_rx_tbl,
3868 .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
3869 .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
3870 .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
3871 .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
3872 .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
3873 .clk_list = sdm845_pciephy_clk_l,
3874 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
3875 .reset_list = sdm845_pciephy_reset_l,
3876 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3877 .vreg_list = qmp_phy_vreg_l,
3878 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3879 .regs = sm8250_pcie_regs_layout,
3880
3881 .start_ctrl = PCS_START | SERDES_START,
3882 .pwrdn_ctrl = SW_PWRDN,
3883 .phy_status = PHYSTATUS_4_20,
3884
3885 .is_dual_lane_phy = true,
3886 .has_pwrdn_delay = true,
3887 .pwrdn_delay_min = 995, /* us */
3888 .pwrdn_delay_max = 1005, /* us */
3889 };
3890
3891 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
3892 .type = PHY_TYPE_UFS,
3893 .nlanes = 2,
3894
3895 .serdes_tbl = sm8350_ufsphy_serdes_tbl,
3896 .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
3897 .tx_tbl = sm8350_ufsphy_tx_tbl,
3898 .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
3899 .rx_tbl = sm8350_ufsphy_rx_tbl,
3900 .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
3901 .pcs_tbl = sm8350_ufsphy_pcs_tbl,
3902 .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
3903 .clk_list = sdm845_ufs_phy_clk_l,
3904 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3905 .vreg_list = qmp_phy_vreg_l,
3906 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3907 .regs = sm8150_ufsphy_regs_layout,
3908
3909 .start_ctrl = SERDES_START,
3910 .pwrdn_ctrl = SW_PWRDN,
3911 .phy_status = PHYSTATUS,
3912
3913 .is_dual_lane_phy = true,
3914 };
3915
3916 static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
3917 .type = PHY_TYPE_USB3,
3918 .nlanes = 1,
3919
3920 .serdes_tbl = sm8150_usb3_serdes_tbl,
3921 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
3922 .tx_tbl = sm8350_usb3_tx_tbl,
3923 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
3924 .rx_tbl = sm8350_usb3_rx_tbl,
3925 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
3926 .pcs_tbl = sm8350_usb3_pcs_tbl,
3927 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
3928 .clk_list = qmp_v4_sm8250_usbphy_clk_l,
3929 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
3930 .reset_list = msm8996_usb3phy_reset_l,
3931 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3932 .vreg_list = qmp_phy_vreg_l,
3933 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3934 .regs = qmp_v4_usb3phy_regs_layout,
3935
3936 .start_ctrl = SERDES_START | PCS_START,
3937 .pwrdn_ctrl = SW_PWRDN,
3938 .phy_status = PHYSTATUS,
3939
3940 .has_pwrdn_delay = true,
3941 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3942 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3943
3944 .has_phy_dp_com_ctrl = true,
3945 .is_dual_lane_phy = true,
3946 };
3947
3948 static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
3949 .type = PHY_TYPE_USB3,
3950 .nlanes = 1,
3951
3952 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
3953 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
3954 .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
3955 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
3956 .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
3957 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
3958 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
3959 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
3960 .clk_list = qmp_v4_phy_clk_l,
3961 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
3962 .reset_list = msm8996_usb3phy_reset_l,
3963 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3964 .vreg_list = qmp_phy_vreg_l,
3965 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3966 .regs = sm8350_usb3_uniphy_regs_layout,
3967
3968 .start_ctrl = SERDES_START | PCS_START,
3969 .pwrdn_ctrl = SW_PWRDN,
3970 .phy_status = PHYSTATUS,
3971
3972 .has_pwrdn_delay = true,
3973 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3974 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3975 };
3976
qcom_qmp_phy_configure_lane(void __iomem * base,const unsigned int * regs,const struct qmp_phy_init_tbl tbl[],int num,u8 lane_mask)3977 static void qcom_qmp_phy_configure_lane(void __iomem *base,
3978 const unsigned int *regs,
3979 const struct qmp_phy_init_tbl tbl[],
3980 int num,
3981 u8 lane_mask)
3982 {
3983 int i;
3984 const struct qmp_phy_init_tbl *t = tbl;
3985
3986 if (!t)
3987 return;
3988
3989 for (i = 0; i < num; i++, t++) {
3990 if (!(t->lane_mask & lane_mask))
3991 continue;
3992
3993 if (t->in_layout)
3994 writel(t->val, base + regs[t->offset]);
3995 else
3996 writel(t->val, base + t->offset);
3997 }
3998 }
3999
qcom_qmp_phy_configure(void __iomem * base,const unsigned int * regs,const struct qmp_phy_init_tbl tbl[],int num)4000 static void qcom_qmp_phy_configure(void __iomem *base,
4001 const unsigned int *regs,
4002 const struct qmp_phy_init_tbl tbl[],
4003 int num)
4004 {
4005 qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
4006 }
4007
qcom_qmp_phy_serdes_init(struct qmp_phy * qphy)4008 static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
4009 {
4010 struct qcom_qmp *qmp = qphy->qmp;
4011 const struct qmp_phy_cfg *cfg = qphy->cfg;
4012 void __iomem *serdes = qphy->serdes;
4013 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4014 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
4015 int serdes_tbl_num = cfg->serdes_tbl_num;
4016 int ret;
4017
4018 qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
4019 if (cfg->serdes_tbl_sec)
4020 qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
4021 cfg->serdes_tbl_num_sec);
4022
4023 if (cfg->type == PHY_TYPE_DP) {
4024 switch (dp_opts->link_rate) {
4025 case 1620:
4026 qcom_qmp_phy_configure(serdes, cfg->regs,
4027 cfg->serdes_tbl_rbr,
4028 cfg->serdes_tbl_rbr_num);
4029 break;
4030 case 2700:
4031 qcom_qmp_phy_configure(serdes, cfg->regs,
4032 cfg->serdes_tbl_hbr,
4033 cfg->serdes_tbl_hbr_num);
4034 break;
4035 case 5400:
4036 qcom_qmp_phy_configure(serdes, cfg->regs,
4037 cfg->serdes_tbl_hbr2,
4038 cfg->serdes_tbl_hbr2_num);
4039 break;
4040 case 8100:
4041 qcom_qmp_phy_configure(serdes, cfg->regs,
4042 cfg->serdes_tbl_hbr3,
4043 cfg->serdes_tbl_hbr3_num);
4044 break;
4045 default:
4046 /* Other link rates aren't supported */
4047 return -EINVAL;
4048 }
4049 }
4050
4051
4052 if (cfg->has_phy_com_ctrl) {
4053 void __iomem *status;
4054 unsigned int mask, val;
4055
4056 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
4057 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
4058 SERDES_START | PCS_START);
4059
4060 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
4061 mask = cfg->mask_com_pcs_ready;
4062
4063 ret = readl_poll_timeout(status, val, (val & mask), 10,
4064 PHY_INIT_COMPLETE_TIMEOUT);
4065 if (ret) {
4066 dev_err(qmp->dev,
4067 "phy common block init timed-out\n");
4068 return ret;
4069 }
4070 }
4071
4072 return 0;
4073 }
4074
qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy * qphy)4075 static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
4076 {
4077 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4078 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
4079 qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4080
4081 /* Turn on BIAS current for PHY/PLL */
4082 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
4083 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
4084 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
4085
4086 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4087
4088 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4089 DP_PHY_PD_CTL_LANE_0_1_PWRDN |
4090 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
4091 DP_PHY_PD_CTL_DP_CLAMP_EN,
4092 qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4093
4094 writel(QSERDES_V3_COM_BIAS_EN |
4095 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
4096 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
4097 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
4098 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
4099
4100 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
4101 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4102 writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4103 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
4104 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
4105 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
4106 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
4107 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
4108 writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
4109 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
4110 qphy->dp_aux_cfg = 0;
4111
4112 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
4113 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
4114 PHY_AUX_REQ_ERR_MASK,
4115 qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
4116 }
4117
4118 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
4119 { 0x00, 0x0c, 0x15, 0x1a },
4120 { 0x02, 0x0e, 0x16, 0xff },
4121 { 0x02, 0x11, 0xff, 0xff },
4122 { 0x04, 0xff, 0xff, 0xff }
4123 };
4124
4125 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
4126 { 0x02, 0x12, 0x16, 0x1a },
4127 { 0x09, 0x19, 0x1f, 0xff },
4128 { 0x10, 0x1f, 0xff, 0xff },
4129 { 0x1f, 0xff, 0xff, 0xff }
4130 };
4131
4132 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
4133 { 0x00, 0x0c, 0x14, 0x19 },
4134 { 0x00, 0x0b, 0x12, 0xff },
4135 { 0x00, 0x0b, 0xff, 0xff },
4136 { 0x04, 0xff, 0xff, 0xff }
4137 };
4138
4139 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
4140 { 0x08, 0x0f, 0x16, 0x1f },
4141 { 0x11, 0x1e, 0x1f, 0xff },
4142 { 0x19, 0x1f, 0xff, 0xff },
4143 { 0x1f, 0xff, 0xff, 0xff }
4144 };
4145
qcom_qmp_phy_configure_dp_swing(struct qmp_phy * qphy,unsigned int drv_lvl_reg,unsigned int emp_post_reg)4146 static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
4147 unsigned int drv_lvl_reg, unsigned int emp_post_reg)
4148 {
4149 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4150 unsigned int v_level = 0, p_level = 0;
4151 u8 voltage_swing_cfg, pre_emphasis_cfg;
4152 int i;
4153
4154 for (i = 0; i < dp_opts->lanes; i++) {
4155 v_level = max(v_level, dp_opts->voltage[i]);
4156 p_level = max(p_level, dp_opts->pre[i]);
4157 }
4158
4159 if (dp_opts->link_rate <= 2700) {
4160 voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
4161 pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
4162 } else {
4163 voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
4164 pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
4165 }
4166
4167 /* TODO: Move check to config check */
4168 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
4169 return -EINVAL;
4170
4171 /* Enable MUX to use Cursor values from these registers */
4172 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
4173 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
4174
4175 writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
4176 writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
4177 writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
4178 writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
4179
4180 return 0;
4181 }
4182
qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy * qphy)4183 static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
4184 {
4185 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4186 u32 bias_en, drvr_en;
4187
4188 if (qcom_qmp_phy_configure_dp_swing(qphy,
4189 QSERDES_V3_TX_TX_DRV_LVL,
4190 QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
4191 return;
4192
4193 if (dp_opts->lanes == 1) {
4194 bias_en = 0x3e;
4195 drvr_en = 0x13;
4196 } else {
4197 bias_en = 0x3f;
4198 drvr_en = 0x10;
4199 }
4200
4201 writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
4202 writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
4203 writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
4204 writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
4205 }
4206
qcom_qmp_phy_configure_dp_mode(struct qmp_phy * qphy)4207 static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
4208 {
4209 u32 val;
4210 bool reverse = false;
4211
4212 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4213 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
4214
4215 /*
4216 * TODO: Assume orientation is CC1 for now and two lanes, need to
4217 * use type-c connector to understand orientation and lanes.
4218 *
4219 * Otherwise val changes to be like below if this code understood
4220 * the orientation of the type-c cable.
4221 *
4222 * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
4223 * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
4224 * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
4225 * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
4226 * if (orientation == ORIENTATION_CC2)
4227 * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
4228 */
4229 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
4230 writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4231
4232 writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
4233
4234 return reverse;
4235 }
4236
qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy * qphy)4237 static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
4238 {
4239 const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
4240 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4241 u32 phy_vco_div, status;
4242 unsigned long pixel_freq;
4243
4244 qcom_qmp_phy_configure_dp_mode(qphy);
4245
4246 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
4247 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
4248
4249 switch (dp_opts->link_rate) {
4250 case 1620:
4251 phy_vco_div = 0x1;
4252 pixel_freq = 1620000000UL / 2;
4253 break;
4254 case 2700:
4255 phy_vco_div = 0x1;
4256 pixel_freq = 2700000000UL / 2;
4257 break;
4258 case 5400:
4259 phy_vco_div = 0x2;
4260 pixel_freq = 5400000000UL / 4;
4261 break;
4262 case 8100:
4263 phy_vco_div = 0x0;
4264 pixel_freq = 8100000000UL / 6;
4265 break;
4266 default:
4267 /* Other link rates aren't supported */
4268 return -EINVAL;
4269 }
4270 writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
4271
4272 clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
4273 clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
4274
4275 writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4276 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4277 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
4278 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4279 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
4280
4281 writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
4282
4283 if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
4284 status,
4285 ((status & BIT(0)) > 0),
4286 500,
4287 10000))
4288 return -ETIMEDOUT;
4289
4290 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4291
4292 if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
4293 status,
4294 ((status & BIT(1)) > 0),
4295 500,
4296 10000))
4297 return -ETIMEDOUT;
4298
4299 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
4300 udelay(2000);
4301 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4302
4303 return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
4304 status,
4305 ((status & BIT(1)) > 0),
4306 500,
4307 10000);
4308 }
4309
4310 /*
4311 * We need to calibrate the aux setting here as many times
4312 * as the caller tries
4313 */
qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy * qphy)4314 static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
4315 {
4316 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
4317 u8 val;
4318
4319 qphy->dp_aux_cfg++;
4320 qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
4321 val = cfg1_settings[qphy->dp_aux_cfg];
4322
4323 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4324
4325 return 0;
4326 }
4327
qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy * qphy)4328 static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
4329 {
4330 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4331 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
4332 qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4333
4334 /* Turn on BIAS current for PHY/PLL */
4335 writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
4336
4337 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
4338 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4339 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4340 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
4341 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
4342 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
4343 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
4344 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
4345 writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
4346 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
4347 qphy->dp_aux_cfg = 0;
4348
4349 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
4350 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
4351 PHY_AUX_REQ_ERR_MASK,
4352 qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
4353 }
4354
qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy * qphy)4355 static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
4356 {
4357 /* Program default values before writing proper values */
4358 writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
4359 writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
4360
4361 writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4362 writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4363
4364 qcom_qmp_phy_configure_dp_swing(qphy,
4365 QSERDES_V4_TX_TX_DRV_LVL,
4366 QSERDES_V4_TX_TX_EMP_POST1_LVL);
4367 }
4368
qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy * qphy)4369 static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
4370 {
4371 const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
4372 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4373 u32 phy_vco_div, status;
4374 unsigned long pixel_freq;
4375 u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
4376 bool reverse;
4377
4378 writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
4379
4380 reverse = qcom_qmp_phy_configure_dp_mode(qphy);
4381
4382 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4383 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4384
4385 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
4386 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
4387
4388 switch (dp_opts->link_rate) {
4389 case 1620:
4390 phy_vco_div = 0x1;
4391 pixel_freq = 1620000000UL / 2;
4392 break;
4393 case 2700:
4394 phy_vco_div = 0x1;
4395 pixel_freq = 2700000000UL / 2;
4396 break;
4397 case 5400:
4398 phy_vco_div = 0x2;
4399 pixel_freq = 5400000000UL / 4;
4400 break;
4401 case 8100:
4402 phy_vco_div = 0x0;
4403 pixel_freq = 8100000000UL / 6;
4404 break;
4405 default:
4406 /* Other link rates aren't supported */
4407 return -EINVAL;
4408 }
4409 writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
4410
4411 clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
4412 clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
4413
4414 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4415 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
4416 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4417 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
4418
4419 writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
4420
4421 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
4422 status,
4423 ((status & BIT(0)) > 0),
4424 500,
4425 10000))
4426 return -ETIMEDOUT;
4427
4428 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
4429 status,
4430 ((status & BIT(0)) > 0),
4431 500,
4432 10000))
4433 return -ETIMEDOUT;
4434
4435 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
4436 status,
4437 ((status & BIT(1)) > 0),
4438 500,
4439 10000))
4440 return -ETIMEDOUT;
4441
4442 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4443
4444 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
4445 status,
4446 ((status & BIT(0)) > 0),
4447 500,
4448 10000))
4449 return -ETIMEDOUT;
4450
4451 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
4452 status,
4453 ((status & BIT(1)) > 0),
4454 500,
4455 10000))
4456 return -ETIMEDOUT;
4457
4458 /*
4459 * At least for 7nm DP PHY this has to be done after enabling link
4460 * clock.
4461 */
4462
4463 if (dp_opts->lanes == 1) {
4464 bias0_en = reverse ? 0x3e : 0x15;
4465 bias1_en = reverse ? 0x15 : 0x3e;
4466 drvr0_en = reverse ? 0x13 : 0x10;
4467 drvr1_en = reverse ? 0x10 : 0x13;
4468 } else if (dp_opts->lanes == 2) {
4469 bias0_en = reverse ? 0x3f : 0x15;
4470 bias1_en = reverse ? 0x15 : 0x3f;
4471 drvr0_en = 0x10;
4472 drvr1_en = 0x10;
4473 } else {
4474 bias0_en = 0x3f;
4475 bias1_en = 0x3f;
4476 drvr0_en = 0x10;
4477 drvr1_en = 0x10;
4478 }
4479
4480 writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
4481 writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
4482 writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
4483 writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
4484
4485 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
4486 udelay(2000);
4487 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4488
4489 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
4490 status,
4491 ((status & BIT(1)) > 0),
4492 500,
4493 10000))
4494 return -ETIMEDOUT;
4495
4496 writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
4497 writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
4498
4499 writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
4500 writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
4501
4502 writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4503 writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4504
4505 return 0;
4506 }
4507
4508 /*
4509 * We need to calibrate the aux setting here as many times
4510 * as the caller tries
4511 */
qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy * qphy)4512 static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
4513 {
4514 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
4515 u8 val;
4516
4517 qphy->dp_aux_cfg++;
4518 qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
4519 val = cfg1_settings[qphy->dp_aux_cfg];
4520
4521 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4522
4523 return 0;
4524 }
4525
qcom_qmp_dp_phy_configure(struct phy * phy,union phy_configure_opts * opts)4526 static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
4527 {
4528 const struct phy_configure_opts_dp *dp_opts = &opts->dp;
4529 struct qmp_phy *qphy = phy_get_drvdata(phy);
4530 const struct qmp_phy_cfg *cfg = qphy->cfg;
4531
4532 memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
4533 if (qphy->dp_opts.set_voltages) {
4534 cfg->configure_dp_tx(qphy);
4535 qphy->dp_opts.set_voltages = 0;
4536 }
4537
4538 return 0;
4539 }
4540
qcom_qmp_dp_phy_calibrate(struct phy * phy)4541 static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
4542 {
4543 struct qmp_phy *qphy = phy_get_drvdata(phy);
4544 const struct qmp_phy_cfg *cfg = qphy->cfg;
4545
4546 if (cfg->calibrate_dp_phy)
4547 return cfg->calibrate_dp_phy(qphy);
4548
4549 return 0;
4550 }
4551
qcom_qmp_phy_com_init(struct qmp_phy * qphy)4552 static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
4553 {
4554 struct qcom_qmp *qmp = qphy->qmp;
4555 const struct qmp_phy_cfg *cfg = qphy->cfg;
4556 void __iomem *serdes = qphy->serdes;
4557 void __iomem *pcs = qphy->pcs;
4558 void __iomem *dp_com = qmp->dp_com;
4559 int ret, i;
4560
4561 mutex_lock(&qmp->phy_mutex);
4562 if (qmp->init_count++) {
4563 mutex_unlock(&qmp->phy_mutex);
4564 return 0;
4565 }
4566
4567 /* turn on regulator supplies */
4568 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
4569 if (ret) {
4570 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
4571 goto err_reg_enable;
4572 }
4573
4574 for (i = 0; i < cfg->num_resets; i++) {
4575 ret = reset_control_assert(qmp->resets[i]);
4576 if (ret) {
4577 dev_err(qmp->dev, "%s reset assert failed\n",
4578 cfg->reset_list[i]);
4579 goto err_rst_assert;
4580 }
4581 }
4582
4583 for (i = cfg->num_resets - 1; i >= 0; i--) {
4584 ret = reset_control_deassert(qmp->resets[i]);
4585 if (ret) {
4586 dev_err(qmp->dev, "%s reset deassert failed\n",
4587 qphy->cfg->reset_list[i]);
4588 goto err_rst;
4589 }
4590 }
4591
4592 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
4593 if (ret)
4594 goto err_rst;
4595
4596 if (cfg->has_phy_dp_com_ctrl) {
4597 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
4598 SW_PWRDN);
4599 /* override hardware control for reset of qmp phy */
4600 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
4601 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
4602 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
4603
4604 /* Default type-c orientation, i.e CC1 */
4605 qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
4606
4607 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
4608 USB3_MODE | DP_MODE);
4609
4610 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
4611 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
4612 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
4613 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
4614
4615 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
4616 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
4617 }
4618
4619 if (cfg->has_phy_com_ctrl) {
4620 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
4621 SW_PWRDN);
4622 } else {
4623 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
4624 qphy_setbits(pcs,
4625 cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
4626 cfg->pwrdn_ctrl);
4627 else
4628 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
4629 cfg->pwrdn_ctrl);
4630 }
4631
4632 mutex_unlock(&qmp->phy_mutex);
4633
4634 return 0;
4635
4636 err_rst:
4637 while (++i < cfg->num_resets)
4638 reset_control_assert(qmp->resets[i]);
4639 err_rst_assert:
4640 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
4641 err_reg_enable:
4642 mutex_unlock(&qmp->phy_mutex);
4643
4644 return ret;
4645 }
4646
qcom_qmp_phy_com_exit(struct qmp_phy * qphy)4647 static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
4648 {
4649 struct qcom_qmp *qmp = qphy->qmp;
4650 const struct qmp_phy_cfg *cfg = qphy->cfg;
4651 void __iomem *serdes = qphy->serdes;
4652 int i = cfg->num_resets;
4653
4654 mutex_lock(&qmp->phy_mutex);
4655 if (--qmp->init_count) {
4656 mutex_unlock(&qmp->phy_mutex);
4657 return 0;
4658 }
4659
4660 reset_control_assert(qmp->ufs_reset);
4661 if (cfg->has_phy_com_ctrl) {
4662 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
4663 SERDES_START | PCS_START);
4664 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
4665 SW_RESET);
4666 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
4667 SW_PWRDN);
4668 }
4669
4670 while (--i >= 0)
4671 reset_control_assert(qmp->resets[i]);
4672
4673 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
4674
4675 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
4676
4677 mutex_unlock(&qmp->phy_mutex);
4678
4679 return 0;
4680 }
4681
qcom_qmp_phy_init(struct phy * phy)4682 static int qcom_qmp_phy_init(struct phy *phy)
4683 {
4684 struct qmp_phy *qphy = phy_get_drvdata(phy);
4685 struct qcom_qmp *qmp = qphy->qmp;
4686 const struct qmp_phy_cfg *cfg = qphy->cfg;
4687 int ret;
4688 dev_vdbg(qmp->dev, "Initializing QMP phy\n");
4689
4690 if (cfg->no_pcs_sw_reset) {
4691 /*
4692 * Get UFS reset, which is delayed until now to avoid a
4693 * circular dependency where UFS needs its PHY, but the PHY
4694 * needs this UFS reset.
4695 */
4696 if (!qmp->ufs_reset) {
4697 qmp->ufs_reset =
4698 devm_reset_control_get_exclusive(qmp->dev,
4699 "ufsphy");
4700
4701 if (IS_ERR(qmp->ufs_reset)) {
4702 ret = PTR_ERR(qmp->ufs_reset);
4703 dev_err(qmp->dev,
4704 "failed to get UFS reset: %d\n",
4705 ret);
4706
4707 qmp->ufs_reset = NULL;
4708 return ret;
4709 }
4710 }
4711
4712 ret = reset_control_assert(qmp->ufs_reset);
4713 if (ret)
4714 return ret;
4715 }
4716
4717 ret = qcom_qmp_phy_com_init(qphy);
4718 if (ret)
4719 return ret;
4720
4721 if (cfg->type == PHY_TYPE_DP)
4722 cfg->dp_aux_init(qphy);
4723
4724 return 0;
4725 }
4726
qcom_qmp_phy_power_on(struct phy * phy)4727 static int qcom_qmp_phy_power_on(struct phy *phy)
4728 {
4729 struct qmp_phy *qphy = phy_get_drvdata(phy);
4730 struct qcom_qmp *qmp = qphy->qmp;
4731 const struct qmp_phy_cfg *cfg = qphy->cfg;
4732 void __iomem *tx = qphy->tx;
4733 void __iomem *rx = qphy->rx;
4734 void __iomem *pcs = qphy->pcs;
4735 void __iomem *pcs_misc = qphy->pcs_misc;
4736 void __iomem *status;
4737 unsigned int mask, val, ready;
4738 int ret;
4739
4740 qcom_qmp_phy_serdes_init(qphy);
4741
4742 if (cfg->has_lane_rst) {
4743 ret = reset_control_deassert(qphy->lane_rst);
4744 if (ret) {
4745 dev_err(qmp->dev, "lane%d reset deassert failed\n",
4746 qphy->index);
4747 goto err_lane_rst;
4748 }
4749 }
4750
4751 ret = clk_prepare_enable(qphy->pipe_clk);
4752 if (ret) {
4753 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
4754 goto err_clk_enable;
4755 }
4756
4757 /* Tx, Rx, and PCS configurations */
4758 qcom_qmp_phy_configure_lane(tx, cfg->regs,
4759 cfg->tx_tbl, cfg->tx_tbl_num, 1);
4760 if (cfg->tx_tbl_sec)
4761 qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
4762 cfg->tx_tbl_num_sec, 1);
4763
4764 /* Configuration for other LANE for USB-DP combo PHY */
4765 if (cfg->is_dual_lane_phy) {
4766 qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
4767 cfg->tx_tbl, cfg->tx_tbl_num, 2);
4768 if (cfg->tx_tbl_sec)
4769 qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
4770 cfg->tx_tbl_sec,
4771 cfg->tx_tbl_num_sec, 2);
4772 }
4773
4774 /* Configure special DP tx tunings */
4775 if (cfg->type == PHY_TYPE_DP)
4776 cfg->configure_dp_tx(qphy);
4777
4778 qcom_qmp_phy_configure_lane(rx, cfg->regs,
4779 cfg->rx_tbl, cfg->rx_tbl_num, 1);
4780 if (cfg->rx_tbl_sec)
4781 qcom_qmp_phy_configure_lane(rx, cfg->regs,
4782 cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
4783
4784 if (cfg->is_dual_lane_phy) {
4785 qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
4786 cfg->rx_tbl, cfg->rx_tbl_num, 2);
4787 if (cfg->rx_tbl_sec)
4788 qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
4789 cfg->rx_tbl_sec,
4790 cfg->rx_tbl_num_sec, 2);
4791 }
4792
4793 /* Configure link rate, swing, etc. */
4794 if (cfg->type == PHY_TYPE_DP) {
4795 cfg->configure_dp_phy(qphy);
4796 } else {
4797 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
4798 if (cfg->pcs_tbl_sec)
4799 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
4800 cfg->pcs_tbl_num_sec);
4801 }
4802
4803 ret = reset_control_deassert(qmp->ufs_reset);
4804 if (ret)
4805 goto err_lane_rst;
4806
4807 qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
4808 cfg->pcs_misc_tbl_num);
4809 if (cfg->pcs_misc_tbl_sec)
4810 qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
4811 cfg->pcs_misc_tbl_num_sec);
4812
4813 /*
4814 * Pull out PHY from POWER DOWN state.
4815 * This is active low enable signal to power-down PHY.
4816 */
4817 if(cfg->type == PHY_TYPE_PCIE)
4818 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
4819
4820 if (cfg->has_pwrdn_delay)
4821 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
4822
4823 if (cfg->type != PHY_TYPE_DP) {
4824 /* Pull PHY out of reset state */
4825 if (!cfg->no_pcs_sw_reset)
4826 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
4827 /* start SerDes and Phy-Coding-Sublayer */
4828 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
4829
4830 if (cfg->type == PHY_TYPE_UFS) {
4831 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
4832 mask = PCS_READY;
4833 ready = PCS_READY;
4834 } else {
4835 status = pcs + cfg->regs[QPHY_PCS_STATUS];
4836 mask = cfg->phy_status;
4837 ready = 0;
4838 }
4839
4840 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
4841 PHY_INIT_COMPLETE_TIMEOUT);
4842 if (ret) {
4843 dev_err(qmp->dev, "phy initialization timed-out\n");
4844 goto err_pcs_ready;
4845 }
4846 }
4847 return 0;
4848
4849 err_pcs_ready:
4850 clk_disable_unprepare(qphy->pipe_clk);
4851 err_clk_enable:
4852 if (cfg->has_lane_rst)
4853 reset_control_assert(qphy->lane_rst);
4854 err_lane_rst:
4855 return ret;
4856 }
4857
qcom_qmp_phy_power_off(struct phy * phy)4858 static int qcom_qmp_phy_power_off(struct phy *phy)
4859 {
4860 struct qmp_phy *qphy = phy_get_drvdata(phy);
4861 const struct qmp_phy_cfg *cfg = qphy->cfg;
4862
4863 clk_disable_unprepare(qphy->pipe_clk);
4864
4865 if (cfg->type == PHY_TYPE_DP) {
4866 /* Assert DP PHY power down */
4867 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4868 } else {
4869 /* PHY reset */
4870 if (!cfg->no_pcs_sw_reset)
4871 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
4872
4873 /* stop SerDes and Phy-Coding-Sublayer */
4874 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
4875
4876 /* Put PHY into POWER DOWN state: active low */
4877 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
4878 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
4879 cfg->pwrdn_ctrl);
4880 } else {
4881 qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
4882 cfg->pwrdn_ctrl);
4883 }
4884 }
4885
4886 return 0;
4887 }
4888
qcom_qmp_phy_exit(struct phy * phy)4889 static int qcom_qmp_phy_exit(struct phy *phy)
4890 {
4891 struct qmp_phy *qphy = phy_get_drvdata(phy);
4892 const struct qmp_phy_cfg *cfg = qphy->cfg;
4893
4894 if (cfg->has_lane_rst)
4895 reset_control_assert(qphy->lane_rst);
4896
4897 qcom_qmp_phy_com_exit(qphy);
4898
4899 return 0;
4900 }
4901
qcom_qmp_phy_enable(struct phy * phy)4902 static int qcom_qmp_phy_enable(struct phy *phy)
4903 {
4904 int ret;
4905
4906 ret = qcom_qmp_phy_init(phy);
4907 if (ret)
4908 return ret;
4909
4910 ret = qcom_qmp_phy_power_on(phy);
4911 if (ret)
4912 qcom_qmp_phy_exit(phy);
4913
4914 return ret;
4915 }
4916
qcom_qmp_phy_disable(struct phy * phy)4917 static int qcom_qmp_phy_disable(struct phy *phy)
4918 {
4919 int ret;
4920
4921 ret = qcom_qmp_phy_power_off(phy);
4922 if (ret)
4923 return ret;
4924 return qcom_qmp_phy_exit(phy);
4925 }
4926
qcom_qmp_phy_set_mode(struct phy * phy,enum phy_mode mode,int submode)4927 static int qcom_qmp_phy_set_mode(struct phy *phy,
4928 enum phy_mode mode, int submode)
4929 {
4930 struct qmp_phy *qphy = phy_get_drvdata(phy);
4931
4932 qphy->mode = mode;
4933
4934 return 0;
4935 }
4936
qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy * qphy)4937 static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
4938 {
4939 const struct qmp_phy_cfg *cfg = qphy->cfg;
4940 void __iomem *pcs = qphy->pcs;
4941 void __iomem *pcs_misc = qphy->pcs_misc;
4942 u32 intr_mask;
4943
4944 if (qphy->mode == PHY_MODE_USB_HOST_SS ||
4945 qphy->mode == PHY_MODE_USB_DEVICE_SS)
4946 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
4947 else
4948 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
4949
4950 /* Clear any pending interrupts status */
4951 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
4952 /* Writing 1 followed by 0 clears the interrupt */
4953 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
4954
4955 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
4956 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
4957
4958 /* Enable required PHY autonomous mode interrupts */
4959 qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
4960
4961 /* Enable i/o clamp_n for autonomous mode */
4962 if (pcs_misc)
4963 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
4964 }
4965
qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy * qphy)4966 static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
4967 {
4968 const struct qmp_phy_cfg *cfg = qphy->cfg;
4969 void __iomem *pcs = qphy->pcs;
4970 void __iomem *pcs_misc = qphy->pcs_misc;
4971
4972 /* Disable i/o clamp_n on resume for normal mode */
4973 if (pcs_misc)
4974 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
4975
4976 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
4977 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
4978
4979 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
4980 /* Writing 1 followed by 0 clears the interrupt */
4981 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
4982 }
4983
qcom_qmp_phy_runtime_suspend(struct device * dev)4984 static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
4985 {
4986 struct qcom_qmp *qmp = dev_get_drvdata(dev);
4987 struct qmp_phy *qphy = qmp->phys[0];
4988 const struct qmp_phy_cfg *cfg = qphy->cfg;
4989
4990 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
4991
4992 /* Supported only for USB3 PHY and luckily USB3 is the first phy */
4993 if (cfg->type != PHY_TYPE_USB3)
4994 return 0;
4995
4996 if (!qmp->init_count) {
4997 dev_vdbg(dev, "PHY not initialized, bailing out\n");
4998 return 0;
4999 }
5000
5001 qcom_qmp_phy_enable_autonomous_mode(qphy);
5002
5003 clk_disable_unprepare(qphy->pipe_clk);
5004 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
5005
5006 return 0;
5007 }
5008
qcom_qmp_phy_runtime_resume(struct device * dev)5009 static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
5010 {
5011 struct qcom_qmp *qmp = dev_get_drvdata(dev);
5012 struct qmp_phy *qphy = qmp->phys[0];
5013 const struct qmp_phy_cfg *cfg = qphy->cfg;
5014 int ret = 0;
5015
5016 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
5017
5018 /* Supported only for USB3 PHY and luckily USB3 is the first phy */
5019 if (cfg->type != PHY_TYPE_USB3)
5020 return 0;
5021
5022 if (!qmp->init_count) {
5023 dev_vdbg(dev, "PHY not initialized, bailing out\n");
5024 return 0;
5025 }
5026
5027 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
5028 if (ret)
5029 return ret;
5030
5031 ret = clk_prepare_enable(qphy->pipe_clk);
5032 if (ret) {
5033 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
5034 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
5035 return ret;
5036 }
5037
5038 qcom_qmp_phy_disable_autonomous_mode(qphy);
5039
5040 return 0;
5041 }
5042
qcom_qmp_phy_vreg_init(struct device * dev,const struct qmp_phy_cfg * cfg)5043 static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
5044 {
5045 struct qcom_qmp *qmp = dev_get_drvdata(dev);
5046 int num = cfg->num_vregs;
5047 int i;
5048
5049 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
5050 if (!qmp->vregs)
5051 return -ENOMEM;
5052
5053 for (i = 0; i < num; i++)
5054 qmp->vregs[i].supply = cfg->vreg_list[i];
5055
5056 return devm_regulator_bulk_get(dev, num, qmp->vregs);
5057 }
5058
qcom_qmp_phy_reset_init(struct device * dev,const struct qmp_phy_cfg * cfg)5059 static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
5060 {
5061 struct qcom_qmp *qmp = dev_get_drvdata(dev);
5062 int i;
5063
5064 qmp->resets = devm_kcalloc(dev, cfg->num_resets,
5065 sizeof(*qmp->resets), GFP_KERNEL);
5066 if (!qmp->resets)
5067 return -ENOMEM;
5068
5069 for (i = 0; i < cfg->num_resets; i++) {
5070 struct reset_control *rst;
5071 const char *name = cfg->reset_list[i];
5072
5073 rst = devm_reset_control_get(dev, name);
5074 if (IS_ERR(rst)) {
5075 dev_err(dev, "failed to get %s reset\n", name);
5076 return PTR_ERR(rst);
5077 }
5078 qmp->resets[i] = rst;
5079 }
5080
5081 return 0;
5082 }
5083
qcom_qmp_phy_clk_init(struct device * dev,const struct qmp_phy_cfg * cfg)5084 static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
5085 {
5086 struct qcom_qmp *qmp = dev_get_drvdata(dev);
5087 int num = cfg->num_clks;
5088 int i;
5089
5090 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
5091 if (!qmp->clks)
5092 return -ENOMEM;
5093
5094 for (i = 0; i < num; i++)
5095 qmp->clks[i].id = cfg->clk_list[i];
5096
5097 return devm_clk_bulk_get(dev, num, qmp->clks);
5098 }
5099
phy_clk_release_provider(void * res)5100 static void phy_clk_release_provider(void *res)
5101 {
5102 of_clk_del_provider(res);
5103 }
5104
5105 /*
5106 * Register a fixed rate pipe clock.
5107 *
5108 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
5109 * controls it. The <s>_pipe_clk coming out of the GCC is requested
5110 * by the PHY driver for its operations.
5111 * We register the <s>_pipe_clksrc here. The gcc driver takes care
5112 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
5113 * Below picture shows this relationship.
5114 *
5115 * +---------------+
5116 * | PHY block |<<---------------------------------------+
5117 * | | |
5118 * | +-------+ | +-----+ |
5119 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
5120 * clk | +-------+ | +-----+
5121 * +---------------+
5122 */
phy_pipe_clk_register(struct qcom_qmp * qmp,struct device_node * np)5123 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
5124 {
5125 struct clk_fixed_rate *fixed;
5126 struct clk_init_data init = { };
5127 int ret;
5128
5129 ret = of_property_read_string(np, "clock-output-names", &init.name);
5130 if (ret) {
5131 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
5132 return ret;
5133 }
5134
5135 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
5136 if (!fixed)
5137 return -ENOMEM;
5138
5139 init.ops = &clk_fixed_rate_ops;
5140
5141 /* controllers using QMP phys use 125MHz pipe clock interface */
5142 fixed->fixed_rate = 125000000;
5143 fixed->hw.init = &init;
5144
5145 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
5146 if (ret)
5147 return ret;
5148
5149 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
5150 if (ret)
5151 return ret;
5152
5153 /*
5154 * Roll a devm action because the clock provider is the child node, but
5155 * the child node is not actually a device.
5156 */
5157 ret = devm_add_action(qmp->dev, phy_clk_release_provider, np);
5158 if (ret)
5159 phy_clk_release_provider(np);
5160
5161 return ret;
5162 }
5163
5164 /*
5165 * Display Port PLL driver block diagram for branch clocks
5166 *
5167 * +------------------------------+
5168 * | DP_VCO_CLK |
5169 * | |
5170 * | +-------------------+ |
5171 * | | (DP PLL/VCO) | |
5172 * | +---------+---------+ |
5173 * | v |
5174 * | +----------+-----------+ |
5175 * | | hsclk_divsel_clk_src | |
5176 * | +----------+-----------+ |
5177 * +------------------------------+
5178 * |
5179 * +---------<---------v------------>----------+
5180 * | |
5181 * +--------v----------------+ |
5182 * | dp_phy_pll_link_clk | |
5183 * | link_clk | |
5184 * +--------+----------------+ |
5185 * | |
5186 * | |
5187 * v v
5188 * Input to DISPCC block |
5189 * for link clk, crypto clk |
5190 * and interface clock |
5191 * |
5192 * |
5193 * +--------<------------+-----------------+---<---+
5194 * | | |
5195 * +----v---------+ +--------v-----+ +--------v------+
5196 * | vco_divided | | vco_divided | | vco_divided |
5197 * | _clk_src | | _clk_src | | _clk_src |
5198 * | | | | | |
5199 * |divsel_six | | divsel_two | | divsel_four |
5200 * +-------+------+ +-----+--------+ +--------+------+
5201 * | | |
5202 * v---->----------v-------------<------v
5203 * |
5204 * +----------+-----------------+
5205 * | dp_phy_pll_vco_div_clk |
5206 * +---------+------------------+
5207 * |
5208 * v
5209 * Input to DISPCC block
5210 * for DP pixel clock
5211 *
5212 */
qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)5213 static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
5214 struct clk_rate_request *req)
5215 {
5216 switch (req->rate) {
5217 case 1620000000UL / 2:
5218 case 2700000000UL / 2:
5219 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
5220 return 0;
5221 default:
5222 return -EINVAL;
5223 }
5224 }
5225
5226 static unsigned long
qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)5227 qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
5228 {
5229 const struct qmp_phy_dp_clks *dp_clks;
5230 const struct qmp_phy *qphy;
5231 const struct phy_configure_opts_dp *dp_opts;
5232
5233 dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
5234 qphy = dp_clks->qphy;
5235 dp_opts = &qphy->dp_opts;
5236
5237 switch (dp_opts->link_rate) {
5238 case 1620:
5239 return 1620000000UL / 2;
5240 case 2700:
5241 return 2700000000UL / 2;
5242 case 5400:
5243 return 5400000000UL / 4;
5244 case 8100:
5245 return 8100000000UL / 6;
5246 default:
5247 return 0;
5248 }
5249 }
5250
5251 static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
5252 .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
5253 .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
5254 };
5255
qcom_qmp_dp_link_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)5256 static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
5257 struct clk_rate_request *req)
5258 {
5259 switch (req->rate) {
5260 case 162000000:
5261 case 270000000:
5262 case 540000000:
5263 case 810000000:
5264 return 0;
5265 default:
5266 return -EINVAL;
5267 }
5268 }
5269
5270 static unsigned long
qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)5271 qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
5272 {
5273 const struct qmp_phy_dp_clks *dp_clks;
5274 const struct qmp_phy *qphy;
5275 const struct phy_configure_opts_dp *dp_opts;
5276
5277 dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
5278 qphy = dp_clks->qphy;
5279 dp_opts = &qphy->dp_opts;
5280
5281 switch (dp_opts->link_rate) {
5282 case 1620:
5283 case 2700:
5284 case 5400:
5285 case 8100:
5286 return dp_opts->link_rate * 100000;
5287 default:
5288 return 0;
5289 }
5290 }
5291
5292 static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
5293 .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
5294 .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
5295 };
5296
5297 static struct clk_hw *
qcom_qmp_dp_clks_hw_get(struct of_phandle_args * clkspec,void * data)5298 qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
5299 {
5300 struct qmp_phy_dp_clks *dp_clks = data;
5301 unsigned int idx = clkspec->args[0];
5302
5303 if (idx >= 2) {
5304 pr_err("%s: invalid index %u\n", __func__, idx);
5305 return ERR_PTR(-EINVAL);
5306 }
5307
5308 if (idx == 0)
5309 return &dp_clks->dp_link_hw;
5310
5311 return &dp_clks->dp_pixel_hw;
5312 }
5313
phy_dp_clks_register(struct qcom_qmp * qmp,struct qmp_phy * qphy,struct device_node * np)5314 static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
5315 struct device_node *np)
5316 {
5317 struct clk_init_data init = { };
5318 struct qmp_phy_dp_clks *dp_clks;
5319 char name[64];
5320 int ret;
5321
5322 dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
5323 if (!dp_clks)
5324 return -ENOMEM;
5325
5326 dp_clks->qphy = qphy;
5327 qphy->dp_clks = dp_clks;
5328
5329 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
5330 init.ops = &qcom_qmp_dp_link_clk_ops;
5331 init.name = name;
5332 dp_clks->dp_link_hw.init = &init;
5333 ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
5334 if (ret)
5335 return ret;
5336
5337 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
5338 init.ops = &qcom_qmp_dp_pixel_clk_ops;
5339 init.name = name;
5340 dp_clks->dp_pixel_hw.init = &init;
5341 ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
5342 if (ret)
5343 return ret;
5344
5345 ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
5346 if (ret)
5347 return ret;
5348
5349 /*
5350 * Roll a devm action because the clock provider is the child node, but
5351 * the child node is not actually a device.
5352 */
5353 ret = devm_add_action(qmp->dev, phy_clk_release_provider, np);
5354 if (ret)
5355 phy_clk_release_provider(np);
5356
5357 return ret;
5358 }
5359
5360 static const struct phy_ops qcom_qmp_phy_gen_ops = {
5361 .init = qcom_qmp_phy_enable,
5362 .exit = qcom_qmp_phy_disable,
5363 .set_mode = qcom_qmp_phy_set_mode,
5364 .owner = THIS_MODULE,
5365 };
5366
5367 static const struct phy_ops qcom_qmp_phy_dp_ops = {
5368 .init = qcom_qmp_phy_init,
5369 .configure = qcom_qmp_dp_phy_configure,
5370 .power_on = qcom_qmp_phy_power_on,
5371 .calibrate = qcom_qmp_dp_phy_calibrate,
5372 .power_off = qcom_qmp_phy_power_off,
5373 .exit = qcom_qmp_phy_exit,
5374 .set_mode = qcom_qmp_phy_set_mode,
5375 .owner = THIS_MODULE,
5376 };
5377
5378 static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
5379 .power_on = qcom_qmp_phy_enable,
5380 .power_off = qcom_qmp_phy_disable,
5381 .set_mode = qcom_qmp_phy_set_mode,
5382 .owner = THIS_MODULE,
5383 };
5384
5385 static
qcom_qmp_phy_create(struct device * dev,struct device_node * np,int id,void __iomem * serdes,const struct qmp_phy_cfg * cfg)5386 int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
5387 void __iomem *serdes, const struct qmp_phy_cfg *cfg)
5388 {
5389 struct qcom_qmp *qmp = dev_get_drvdata(dev);
5390 struct phy *generic_phy;
5391 struct qmp_phy *qphy;
5392 const struct phy_ops *ops;
5393 char prop_name[MAX_PROP_NAME];
5394 int ret;
5395
5396 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
5397 if (!qphy)
5398 return -ENOMEM;
5399
5400 qphy->cfg = cfg;
5401 qphy->serdes = serdes;
5402 /*
5403 * Get memory resources for each phy lane:
5404 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
5405 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
5406 * For single lane PHYs: pcs_misc (optional) -> 3.
5407 */
5408 qphy->tx = of_iomap(np, 0);
5409 if (!qphy->tx)
5410 return -ENOMEM;
5411
5412 qphy->rx = of_iomap(np, 1);
5413 if (!qphy->rx)
5414 return -ENOMEM;
5415
5416 qphy->pcs = of_iomap(np, 2);
5417 if (!qphy->pcs)
5418 return -ENOMEM;
5419
5420 /*
5421 * If this is a dual-lane PHY, then there should be registers for the
5422 * second lane. Some old device trees did not specify this, so fall
5423 * back to old legacy behavior of assuming they can be reached at an
5424 * offset from the first lane.
5425 */
5426 if (cfg->is_dual_lane_phy) {
5427 qphy->tx2 = of_iomap(np, 3);
5428 qphy->rx2 = of_iomap(np, 4);
5429 if (!qphy->tx2 || !qphy->rx2) {
5430 dev_warn(dev,
5431 "Underspecified device tree, falling back to legacy register regions\n");
5432
5433 /* In the old version, pcs_misc is at index 3. */
5434 qphy->pcs_misc = qphy->tx2;
5435 qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
5436 qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
5437
5438 } else {
5439 qphy->pcs_misc = of_iomap(np, 5);
5440 }
5441
5442 } else {
5443 qphy->pcs_misc = of_iomap(np, 3);
5444 }
5445
5446 if (!qphy->pcs_misc)
5447 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
5448
5449 /*
5450 * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
5451 * based phys, so they essentially have pipe clock. So,
5452 * we return error in case phy is USB3 or PIPE type.
5453 * Otherwise, we initialize pipe clock to NULL for
5454 * all phys that don't need this.
5455 */
5456 snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
5457 qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
5458 if (IS_ERR(qphy->pipe_clk)) {
5459 if (cfg->type == PHY_TYPE_PCIE ||
5460 cfg->type == PHY_TYPE_USB3) {
5461 ret = PTR_ERR(qphy->pipe_clk);
5462 if (ret != -EPROBE_DEFER)
5463 dev_err(dev,
5464 "failed to get lane%d pipe_clk, %d\n",
5465 id, ret);
5466 return ret;
5467 }
5468 qphy->pipe_clk = NULL;
5469 }
5470
5471 /* Get lane reset, if any */
5472 if (cfg->has_lane_rst) {
5473 snprintf(prop_name, sizeof(prop_name), "lane%d", id);
5474 qphy->lane_rst = of_reset_control_get(np, prop_name);
5475 if (IS_ERR(qphy->lane_rst)) {
5476 dev_err(dev, "failed to get lane%d reset\n", id);
5477 return PTR_ERR(qphy->lane_rst);
5478 }
5479 }
5480
5481 if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
5482 ops = &qcom_qmp_pcie_ufs_ops;
5483 else if (cfg->type == PHY_TYPE_DP)
5484 ops = &qcom_qmp_phy_dp_ops;
5485 else
5486 ops = &qcom_qmp_phy_gen_ops;
5487
5488 generic_phy = devm_phy_create(dev, np, ops);
5489 if (IS_ERR(generic_phy)) {
5490 ret = PTR_ERR(generic_phy);
5491 dev_err(dev, "failed to create qphy %d\n", ret);
5492 return ret;
5493 }
5494
5495 qphy->phy = generic_phy;
5496 qphy->index = id;
5497 qphy->qmp = qmp;
5498 qmp->phys[id] = qphy;
5499 phy_set_drvdata(generic_phy, qphy);
5500
5501 return 0;
5502 }
5503
5504 static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
5505 {
5506 .compatible = "qcom,ipq8074-qmp-usb3-phy",
5507 .data = &ipq8074_usb3phy_cfg,
5508 }, {
5509 .compatible = "qcom,msm8996-qmp-pcie-phy",
5510 .data = &msm8996_pciephy_cfg,
5511 }, {
5512 .compatible = "qcom,msm8996-qmp-ufs-phy",
5513 .data = &msm8996_ufs_cfg,
5514 }, {
5515 .compatible = "qcom,msm8996-qmp-usb3-phy",
5516 .data = &msm8996_usb3phy_cfg,
5517 }, {
5518 .compatible = "qcom,msm8998-qmp-pcie-phy",
5519 .data = &msm8998_pciephy_cfg,
5520 }, {
5521 .compatible = "qcom,msm8998-qmp-ufs-phy",
5522 .data = &sdm845_ufsphy_cfg,
5523 }, {
5524 .compatible = "qcom,ipq8074-qmp-pcie-phy",
5525 .data = &ipq8074_pciephy_cfg,
5526 }, {
5527 .compatible = "qcom,ipq6018-qmp-pcie-phy",
5528 .data = &ipq6018_pciephy_cfg,
5529 }, {
5530 .compatible = "qcom,ipq6018-qmp-usb3-phy",
5531 .data = &ipq8074_usb3phy_cfg,
5532 }, {
5533 .compatible = "qcom,sc7180-qmp-usb3-phy",
5534 .data = &sc7180_usb3phy_cfg,
5535 }, {
5536 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
5537 /* It's a combo phy */
5538 }, {
5539 .compatible = "qcom,sc8180x-qmp-pcie-phy",
5540 .data = &sc8180x_pciephy_cfg,
5541 }, {
5542 .compatible = "qcom,sc8180x-qmp-ufs-phy",
5543 .data = &sm8150_ufsphy_cfg,
5544 }, {
5545 .compatible = "qcom,sc8180x-qmp-usb3-phy",
5546 .data = &sm8150_usb3phy_cfg,
5547 }, {
5548 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
5549 /* It's a combo phy */
5550 }, {
5551 .compatible = "qcom,sdm845-qhp-pcie-phy",
5552 .data = &sdm845_qhp_pciephy_cfg,
5553 }, {
5554 .compatible = "qcom,sdm845-qmp-pcie-phy",
5555 .data = &sdm845_qmp_pciephy_cfg,
5556 }, {
5557 .compatible = "qcom,sdm845-qmp-usb3-phy",
5558 .data = &qmp_v3_usb3phy_cfg,
5559 }, {
5560 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
5561 .data = &qmp_v3_usb3_uniphy_cfg,
5562 }, {
5563 .compatible = "qcom,sdm845-qmp-ufs-phy",
5564 .data = &sdm845_ufsphy_cfg,
5565 }, {
5566 .compatible = "qcom,msm8998-qmp-usb3-phy",
5567 .data = &msm8998_usb3phy_cfg,
5568 }, {
5569 .compatible = "qcom,sm6115-qmp-ufs-phy",
5570 .data = &sm6115_ufsphy_cfg,
5571 }, {
5572 .compatible = "qcom,sm8150-qmp-ufs-phy",
5573 .data = &sm8150_ufsphy_cfg,
5574 }, {
5575 .compatible = "qcom,sm8250-qmp-ufs-phy",
5576 .data = &sm8150_ufsphy_cfg,
5577 }, {
5578 .compatible = "qcom,sm8150-qmp-usb3-phy",
5579 .data = &sm8150_usb3phy_cfg,
5580 }, {
5581 .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
5582 .data = &sm8150_usb3_uniphy_cfg,
5583 }, {
5584 .compatible = "qcom,sm8250-qmp-usb3-phy",
5585 .data = &sm8250_usb3phy_cfg,
5586 }, {
5587 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
5588 /* It's a combo phy */
5589 }, {
5590 .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
5591 .data = &sm8250_usb3_uniphy_cfg,
5592 }, {
5593 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
5594 .data = &sm8250_qmp_gen3x1_pciephy_cfg,
5595 }, {
5596 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
5597 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
5598 }, {
5599 .compatible = "qcom,sm8350-qmp-ufs-phy",
5600 .data = &sm8350_ufsphy_cfg,
5601 }, {
5602 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
5603 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
5604 }, {
5605 .compatible = "qcom,sdx55-qmp-pcie-phy",
5606 .data = &sdx55_qmp_pciephy_cfg,
5607 }, {
5608 .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
5609 .data = &sdx55_usb3_uniphy_cfg,
5610 }, {
5611 .compatible = "qcom,sm8350-qmp-usb3-phy",
5612 .data = &sm8350_usb3phy_cfg,
5613 }, {
5614 .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
5615 .data = &sm8350_usb3_uniphy_cfg,
5616 },
5617 { },
5618 };
5619 MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
5620
5621 static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
5622 {
5623 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
5624 .data = &sc7180_usb3dpphy_cfg,
5625 },
5626 {
5627 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
5628 .data = &sm8250_usb3dpphy_cfg,
5629 },
5630 {
5631 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
5632 .data = &sc8180x_usb3dpphy_cfg,
5633 },
5634 { }
5635 };
5636
5637 static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
5638 SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
5639 qcom_qmp_phy_runtime_resume, NULL)
5640 };
5641
qcom_qmp_phy_probe(struct platform_device * pdev)5642 static int qcom_qmp_phy_probe(struct platform_device *pdev)
5643 {
5644 struct qcom_qmp *qmp;
5645 struct device *dev = &pdev->dev;
5646 struct device_node *child;
5647 struct phy_provider *phy_provider;
5648 void __iomem *serdes;
5649 void __iomem *usb_serdes;
5650 void __iomem *dp_serdes = NULL;
5651 const struct qmp_phy_combo_cfg *combo_cfg = NULL;
5652 const struct qmp_phy_cfg *cfg = NULL;
5653 const struct qmp_phy_cfg *usb_cfg = NULL;
5654 const struct qmp_phy_cfg *dp_cfg = NULL;
5655 int num, id, expected_phys;
5656 int ret;
5657
5658 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
5659 if (!qmp)
5660 return -ENOMEM;
5661
5662 qmp->dev = dev;
5663 dev_set_drvdata(dev, qmp);
5664
5665 /* Get the specific init parameters of QMP phy */
5666 cfg = of_device_get_match_data(dev);
5667 if (!cfg) {
5668 const struct of_device_id *match;
5669
5670 match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
5671 if (!match)
5672 return -EINVAL;
5673
5674 combo_cfg = match->data;
5675 if (!combo_cfg)
5676 return -EINVAL;
5677
5678 usb_cfg = combo_cfg->usb_cfg;
5679 cfg = usb_cfg; /* Setup clks and regulators */
5680 }
5681
5682 /* per PHY serdes; usually located at base address */
5683 usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
5684 if (IS_ERR(serdes))
5685 return PTR_ERR(serdes);
5686
5687 /* per PHY dp_com; if PHY has dp_com control block */
5688 if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
5689 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
5690 if (IS_ERR(qmp->dp_com))
5691 return PTR_ERR(qmp->dp_com);
5692 }
5693
5694 if (combo_cfg) {
5695 /* Only two serdes for combo PHY */
5696 dp_serdes = devm_platform_ioremap_resource(pdev, 2);
5697 if (IS_ERR(dp_serdes))
5698 return PTR_ERR(dp_serdes);
5699
5700 dp_cfg = combo_cfg->dp_cfg;
5701 expected_phys = 2;
5702 } else {
5703 expected_phys = cfg->nlanes;
5704 }
5705
5706 mutex_init(&qmp->phy_mutex);
5707
5708 ret = qcom_qmp_phy_clk_init(dev, cfg);
5709 if (ret)
5710 return ret;
5711
5712 ret = qcom_qmp_phy_reset_init(dev, cfg);
5713 if (ret)
5714 return ret;
5715
5716 ret = qcom_qmp_phy_vreg_init(dev, cfg);
5717 if (ret) {
5718 if (ret != -EPROBE_DEFER)
5719 dev_err(dev, "failed to get regulator supplies: %d\n",
5720 ret);
5721 return ret;
5722 }
5723
5724 num = of_get_available_child_count(dev->of_node);
5725 /* do we have a rogue child node ? */
5726 if (num > expected_phys)
5727 return -EINVAL;
5728
5729 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
5730 if (!qmp->phys)
5731 return -ENOMEM;
5732
5733 pm_runtime_set_active(dev);
5734 pm_runtime_enable(dev);
5735 /*
5736 * Prevent runtime pm from being ON by default. Users can enable
5737 * it using power/control in sysfs.
5738 */
5739 pm_runtime_forbid(dev);
5740
5741 id = 0;
5742 for_each_available_child_of_node(dev->of_node, child) {
5743 if (of_node_name_eq(child, "dp-phy")) {
5744 cfg = dp_cfg;
5745 serdes = dp_serdes;
5746 } else if (of_node_name_eq(child, "usb3-phy")) {
5747 cfg = usb_cfg;
5748 serdes = usb_serdes;
5749 }
5750
5751 /* Create per-lane phy */
5752 ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
5753 if (ret) {
5754 dev_err(dev, "failed to create lane%d phy, %d\n",
5755 id, ret);
5756 goto err_node_put;
5757 }
5758
5759 /*
5760 * Register the pipe clock provided by phy.
5761 * See function description to see details of this pipe clock.
5762 */
5763 if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
5764 ret = phy_pipe_clk_register(qmp, child);
5765 if (ret) {
5766 dev_err(qmp->dev,
5767 "failed to register pipe clock source\n");
5768 goto err_node_put;
5769 }
5770 } else if (cfg->type == PHY_TYPE_DP) {
5771 ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
5772 if (ret) {
5773 dev_err(qmp->dev,
5774 "failed to register DP clock source\n");
5775 goto err_node_put;
5776 }
5777 }
5778 id++;
5779 }
5780
5781 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
5782 if (!IS_ERR(phy_provider))
5783 dev_info(dev, "Registered Qcom-QMP phy\n");
5784 else
5785 pm_runtime_disable(dev);
5786
5787 return PTR_ERR_OR_ZERO(phy_provider);
5788
5789 err_node_put:
5790 pm_runtime_disable(dev);
5791 of_node_put(child);
5792 return ret;
5793 }
5794
5795 static struct platform_driver qcom_qmp_phy_driver = {
5796 .probe = qcom_qmp_phy_probe,
5797 .driver = {
5798 .name = "qcom-qmp-phy",
5799 .pm = &qcom_qmp_phy_pm_ops,
5800 .of_match_table = qcom_qmp_phy_of_match_table,
5801 },
5802 };
5803
5804 module_platform_driver(qcom_qmp_phy_driver);
5805
5806 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
5807 MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
5808 MODULE_LICENSE("GPL v2");
5809
