1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30
31 #include <drm/drm_atomic_helper.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_edid.h>
34 #include <drm/drm_probe_helper.h>
35
36 #include "i915_drv.h"
37 #include "i915_irq.h"
38 #include "i915_reg.h"
39 #include "intel_connector.h"
40 #include "intel_crt.h"
41 #include "intel_crtc.h"
42 #include "intel_ddi.h"
43 #include "intel_ddi_buf_trans.h"
44 #include "intel_de.h"
45 #include "intel_display_types.h"
46 #include "intel_fdi.h"
47 #include "intel_fdi_regs.h"
48 #include "intel_fifo_underrun.h"
49 #include "intel_gmbus.h"
50 #include "intel_hotplug.h"
51 #include "intel_hotplug_irq.h"
52 #include "intel_load_detect.h"
53 #include "intel_pch_display.h"
54 #include "intel_pch_refclk.h"
55
56 /* Here's the desired hotplug mode */
57 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
58 ADPA_CRT_HOTPLUG_WARMUP_10MS | \
59 ADPA_CRT_HOTPLUG_SAMPLE_4S | \
60 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
61 ADPA_CRT_HOTPLUG_VOLREF_325MV | \
62 ADPA_CRT_HOTPLUG_ENABLE)
63
64 struct intel_crt {
65 struct intel_encoder base;
66 /* DPMS state is stored in the connector, which we need in the
67 * encoder's enable/disable callbacks */
68 struct intel_connector *connector;
69 bool force_hotplug_required;
70 i915_reg_t adpa_reg;
71 };
72
intel_encoder_to_crt(struct intel_encoder * encoder)73 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
74 {
75 return container_of(encoder, struct intel_crt, base);
76 }
77
intel_attached_crt(struct intel_connector * connector)78 static struct intel_crt *intel_attached_crt(struct intel_connector *connector)
79 {
80 return intel_encoder_to_crt(intel_attached_encoder(connector));
81 }
82
intel_crt_port_enabled(struct drm_i915_private * dev_priv,i915_reg_t adpa_reg,enum pipe * pipe)83 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
84 i915_reg_t adpa_reg, enum pipe *pipe)
85 {
86 u32 val;
87
88 val = intel_de_read(dev_priv, adpa_reg);
89
90 /* asserts want to know the pipe even if the port is disabled */
91 if (HAS_PCH_CPT(dev_priv))
92 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
93 else
94 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
95
96 return val & ADPA_DAC_ENABLE;
97 }
98
intel_crt_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)99 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
100 enum pipe *pipe)
101 {
102 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
103 struct intel_crt *crt = intel_encoder_to_crt(encoder);
104 intel_wakeref_t wakeref;
105 bool ret;
106
107 wakeref = intel_display_power_get_if_enabled(dev_priv,
108 encoder->power_domain);
109 if (!wakeref)
110 return false;
111
112 ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
113
114 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
115
116 return ret;
117 }
118
intel_crt_get_flags(struct intel_encoder * encoder)119 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
120 {
121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
122 struct intel_crt *crt = intel_encoder_to_crt(encoder);
123 u32 tmp, flags = 0;
124
125 tmp = intel_de_read(dev_priv, crt->adpa_reg);
126
127 if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
128 flags |= DRM_MODE_FLAG_PHSYNC;
129 else
130 flags |= DRM_MODE_FLAG_NHSYNC;
131
132 if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
133 flags |= DRM_MODE_FLAG_PVSYNC;
134 else
135 flags |= DRM_MODE_FLAG_NVSYNC;
136
137 return flags;
138 }
139
intel_crt_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)140 static void intel_crt_get_config(struct intel_encoder *encoder,
141 struct intel_crtc_state *pipe_config)
142 {
143 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
144
145 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
146
147 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
148 }
149
hsw_crt_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)150 static void hsw_crt_get_config(struct intel_encoder *encoder,
151 struct intel_crtc_state *pipe_config)
152 {
153 lpt_pch_get_config(pipe_config);
154
155 hsw_ddi_get_config(encoder, pipe_config);
156
157 pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
158 DRM_MODE_FLAG_NHSYNC |
159 DRM_MODE_FLAG_PVSYNC |
160 DRM_MODE_FLAG_NVSYNC);
161 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
162 }
163
164 /* Note: The caller is required to filter out dpms modes not supported by the
165 * platform. */
intel_crt_set_dpms(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int mode)166 static void intel_crt_set_dpms(struct intel_encoder *encoder,
167 const struct intel_crtc_state *crtc_state,
168 int mode)
169 {
170 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
171 struct intel_crt *crt = intel_encoder_to_crt(encoder);
172 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
173 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
174 u32 adpa;
175
176 if (DISPLAY_VER(dev_priv) >= 5)
177 adpa = ADPA_HOTPLUG_BITS;
178 else
179 adpa = 0;
180
181 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
182 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
183 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
184 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
185
186 /* For CPT allow 3 pipe config, for others just use A or B */
187 if (HAS_PCH_LPT(dev_priv))
188 ; /* Those bits don't exist here */
189 else if (HAS_PCH_CPT(dev_priv))
190 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
191 else
192 adpa |= ADPA_PIPE_SEL(crtc->pipe);
193
194 if (!HAS_PCH_SPLIT(dev_priv))
195 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
196
197 switch (mode) {
198 case DRM_MODE_DPMS_ON:
199 adpa |= ADPA_DAC_ENABLE;
200 break;
201 case DRM_MODE_DPMS_STANDBY:
202 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
203 break;
204 case DRM_MODE_DPMS_SUSPEND:
205 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
206 break;
207 case DRM_MODE_DPMS_OFF:
208 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
209 break;
210 }
211
212 intel_de_write(dev_priv, crt->adpa_reg, adpa);
213 }
214
intel_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)215 static void intel_disable_crt(struct intel_atomic_state *state,
216 struct intel_encoder *encoder,
217 const struct intel_crtc_state *old_crtc_state,
218 const struct drm_connector_state *old_conn_state)
219 {
220 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
221 }
222
pch_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)223 static void pch_disable_crt(struct intel_atomic_state *state,
224 struct intel_encoder *encoder,
225 const struct intel_crtc_state *old_crtc_state,
226 const struct drm_connector_state *old_conn_state)
227 {
228 }
229
pch_post_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)230 static void pch_post_disable_crt(struct intel_atomic_state *state,
231 struct intel_encoder *encoder,
232 const struct intel_crtc_state *old_crtc_state,
233 const struct drm_connector_state *old_conn_state)
234 {
235 intel_disable_crt(state, encoder, old_crtc_state, old_conn_state);
236 }
237
hsw_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)238 static void hsw_disable_crt(struct intel_atomic_state *state,
239 struct intel_encoder *encoder,
240 const struct intel_crtc_state *old_crtc_state,
241 const struct drm_connector_state *old_conn_state)
242 {
243 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
244
245 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
246
247 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
248 }
249
hsw_post_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)250 static void hsw_post_disable_crt(struct intel_atomic_state *state,
251 struct intel_encoder *encoder,
252 const struct intel_crtc_state *old_crtc_state,
253 const struct drm_connector_state *old_conn_state)
254 {
255 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
256 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
257
258 intel_crtc_vblank_off(old_crtc_state);
259
260 intel_disable_transcoder(old_crtc_state);
261
262 intel_ddi_disable_transcoder_func(old_crtc_state);
263
264 ilk_pfit_disable(old_crtc_state);
265
266 intel_ddi_disable_transcoder_clock(old_crtc_state);
267
268 pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state);
269
270 lpt_pch_disable(state, crtc);
271
272 hsw_fdi_disable(encoder);
273
274 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
275
276 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
277 }
278
hsw_pre_pll_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)279 static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state,
280 struct intel_encoder *encoder,
281 const struct intel_crtc_state *crtc_state,
282 const struct drm_connector_state *conn_state)
283 {
284 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
285
286 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
287
288 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
289 }
290
hsw_pre_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)291 static void hsw_pre_enable_crt(struct intel_atomic_state *state,
292 struct intel_encoder *encoder,
293 const struct intel_crtc_state *crtc_state,
294 const struct drm_connector_state *conn_state)
295 {
296 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
297 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
298 enum pipe pipe = crtc->pipe;
299
300 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
301
302 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
303
304 hsw_fdi_link_train(encoder, crtc_state);
305
306 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
307 }
308
hsw_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)309 static void hsw_enable_crt(struct intel_atomic_state *state,
310 struct intel_encoder *encoder,
311 const struct intel_crtc_state *crtc_state,
312 const struct drm_connector_state *conn_state)
313 {
314 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
315 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
316 enum pipe pipe = crtc->pipe;
317
318 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
319
320 intel_ddi_enable_transcoder_func(encoder, crtc_state);
321
322 intel_enable_transcoder(crtc_state);
323
324 lpt_pch_enable(state, crtc);
325
326 intel_crtc_vblank_on(crtc_state);
327
328 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
329
330 intel_crtc_wait_for_next_vblank(crtc);
331 intel_crtc_wait_for_next_vblank(crtc);
332 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
333 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
334 }
335
intel_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)336 static void intel_enable_crt(struct intel_atomic_state *state,
337 struct intel_encoder *encoder,
338 const struct intel_crtc_state *crtc_state,
339 const struct drm_connector_state *conn_state)
340 {
341 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
342 }
343
344 static enum drm_mode_status
intel_crt_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)345 intel_crt_mode_valid(struct drm_connector *connector,
346 struct drm_display_mode *mode)
347 {
348 struct drm_device *dev = connector->dev;
349 struct drm_i915_private *dev_priv = to_i915(dev);
350 int max_dotclk = dev_priv->max_dotclk_freq;
351 int max_clock;
352
353 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
354 return MODE_NO_DBLESCAN;
355
356 if (mode->clock < 25000)
357 return MODE_CLOCK_LOW;
358
359 if (HAS_PCH_LPT(dev_priv))
360 max_clock = 180000;
361 else if (IS_VALLEYVIEW(dev_priv))
362 /*
363 * 270 MHz due to current DPLL limits,
364 * DAC limit supposedly 355 MHz.
365 */
366 max_clock = 270000;
367 else if (IS_DISPLAY_VER(dev_priv, 3, 4))
368 max_clock = 400000;
369 else
370 max_clock = 350000;
371 if (mode->clock > max_clock)
372 return MODE_CLOCK_HIGH;
373
374 if (mode->clock > max_dotclk)
375 return MODE_CLOCK_HIGH;
376
377 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
378 if (HAS_PCH_LPT(dev_priv) &&
379 ilk_get_lanes_required(mode->clock, 270000, 24) > 2)
380 return MODE_CLOCK_HIGH;
381
382 /* HSW/BDW FDI limited to 4k */
383 if (mode->hdisplay > 4096)
384 return MODE_H_ILLEGAL;
385
386 return MODE_OK;
387 }
388
intel_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)389 static int intel_crt_compute_config(struct intel_encoder *encoder,
390 struct intel_crtc_state *pipe_config,
391 struct drm_connector_state *conn_state)
392 {
393 struct drm_display_mode *adjusted_mode =
394 &pipe_config->hw.adjusted_mode;
395
396 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
397 return -EINVAL;
398
399 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
400 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
401
402 return 0;
403 }
404
pch_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)405 static int pch_crt_compute_config(struct intel_encoder *encoder,
406 struct intel_crtc_state *pipe_config,
407 struct drm_connector_state *conn_state)
408 {
409 struct drm_display_mode *adjusted_mode =
410 &pipe_config->hw.adjusted_mode;
411
412 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
413 return -EINVAL;
414
415 pipe_config->has_pch_encoder = true;
416 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
417
418 return 0;
419 }
420
hsw_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)421 static int hsw_crt_compute_config(struct intel_encoder *encoder,
422 struct intel_crtc_state *pipe_config,
423 struct drm_connector_state *conn_state)
424 {
425 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
426 struct drm_display_mode *adjusted_mode =
427 &pipe_config->hw.adjusted_mode;
428
429 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
430 return -EINVAL;
431
432 /* HSW/BDW FDI limited to 4k */
433 if (adjusted_mode->crtc_hdisplay > 4096 ||
434 adjusted_mode->crtc_hblank_start > 4096)
435 return -EINVAL;
436
437 pipe_config->has_pch_encoder = true;
438 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
439
440 /* LPT FDI RX only supports 8bpc. */
441 if (HAS_PCH_LPT(dev_priv)) {
442 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
443 drm_dbg_kms(&dev_priv->drm,
444 "LPT only supports 24bpp\n");
445 return -EINVAL;
446 }
447
448 pipe_config->pipe_bpp = 24;
449 }
450
451 /* FDI must always be 2.7 GHz */
452 pipe_config->port_clock = 135000 * 2;
453
454 adjusted_mode->crtc_clock = lpt_iclkip(pipe_config);
455
456 return 0;
457 }
458
ilk_crt_detect_hotplug(struct drm_connector * connector)459 static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
460 {
461 struct drm_device *dev = connector->dev;
462 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
463 struct drm_i915_private *dev_priv = to_i915(dev);
464 u32 adpa;
465 bool ret;
466
467 /* The first time through, trigger an explicit detection cycle */
468 if (crt->force_hotplug_required) {
469 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
470 u32 save_adpa;
471
472 crt->force_hotplug_required = false;
473
474 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
475 drm_dbg_kms(&dev_priv->drm,
476 "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
477
478 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
479 if (turn_off_dac)
480 adpa &= ~ADPA_DAC_ENABLE;
481
482 intel_de_write(dev_priv, crt->adpa_reg, adpa);
483
484 if (intel_de_wait_for_clear(dev_priv,
485 crt->adpa_reg,
486 ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
487 1000))
488 drm_dbg_kms(&dev_priv->drm,
489 "timed out waiting for FORCE_TRIGGER");
490
491 if (turn_off_dac) {
492 intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
493 intel_de_posting_read(dev_priv, crt->adpa_reg);
494 }
495 }
496
497 /* Check the status to see if both blue and green are on now */
498 adpa = intel_de_read(dev_priv, crt->adpa_reg);
499 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
500 ret = true;
501 else
502 ret = false;
503 drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n",
504 adpa, ret);
505
506 return ret;
507 }
508
valleyview_crt_detect_hotplug(struct drm_connector * connector)509 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
510 {
511 struct drm_device *dev = connector->dev;
512 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
513 struct drm_i915_private *dev_priv = to_i915(dev);
514 bool reenable_hpd;
515 u32 adpa;
516 bool ret;
517 u32 save_adpa;
518
519 /*
520 * Doing a force trigger causes a hpd interrupt to get sent, which can
521 * get us stuck in a loop if we're polling:
522 * - We enable power wells and reset the ADPA
523 * - output_poll_exec does force probe on VGA, triggering a hpd
524 * - HPD handler waits for poll to unlock dev->mode_config.mutex
525 * - output_poll_exec shuts off the ADPA, unlocks
526 * dev->mode_config.mutex
527 * - HPD handler runs, resets ADPA and brings us back to the start
528 *
529 * Just disable HPD interrupts here to prevent this
530 */
531 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
532
533 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
534 drm_dbg_kms(&dev_priv->drm,
535 "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
536
537 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
538
539 intel_de_write(dev_priv, crt->adpa_reg, adpa);
540
541 if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
542 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
543 drm_dbg_kms(&dev_priv->drm,
544 "timed out waiting for FORCE_TRIGGER");
545 intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
546 }
547
548 /* Check the status to see if both blue and green are on now */
549 adpa = intel_de_read(dev_priv, crt->adpa_reg);
550 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
551 ret = true;
552 else
553 ret = false;
554
555 drm_dbg_kms(&dev_priv->drm,
556 "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
557
558 if (reenable_hpd)
559 intel_hpd_enable(dev_priv, crt->base.hpd_pin);
560
561 return ret;
562 }
563
intel_crt_detect_hotplug(struct drm_connector * connector)564 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
565 {
566 struct drm_device *dev = connector->dev;
567 struct drm_i915_private *dev_priv = to_i915(dev);
568 u32 stat;
569 bool ret = false;
570 int i, tries = 0;
571
572 if (HAS_PCH_SPLIT(dev_priv))
573 return ilk_crt_detect_hotplug(connector);
574
575 if (IS_VALLEYVIEW(dev_priv))
576 return valleyview_crt_detect_hotplug(connector);
577
578 /*
579 * On 4 series desktop, CRT detect sequence need to be done twice
580 * to get a reliable result.
581 */
582
583 if (IS_G45(dev_priv))
584 tries = 2;
585 else
586 tries = 1;
587
588 for (i = 0; i < tries ; i++) {
589 /* turn on the FORCE_DETECT */
590 i915_hotplug_interrupt_update(dev_priv,
591 CRT_HOTPLUG_FORCE_DETECT,
592 CRT_HOTPLUG_FORCE_DETECT);
593 /* wait for FORCE_DETECT to go off */
594 if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN,
595 CRT_HOTPLUG_FORCE_DETECT, 1000))
596 drm_dbg_kms(&dev_priv->drm,
597 "timed out waiting for FORCE_DETECT to go off");
598 }
599
600 stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT);
601 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
602 ret = true;
603
604 /* clear the interrupt we just generated, if any */
605 intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
606
607 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
608
609 return ret;
610 }
611
intel_crt_get_edid(struct drm_connector * connector,struct i2c_adapter * i2c)612 static const struct drm_edid *intel_crt_get_edid(struct drm_connector *connector,
613 struct i2c_adapter *i2c)
614 {
615 const struct drm_edid *drm_edid;
616
617 drm_edid = drm_edid_read_ddc(connector, i2c);
618
619 if (!drm_edid && !intel_gmbus_is_forced_bit(i2c)) {
620 drm_dbg_kms(connector->dev,
621 "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
622 intel_gmbus_force_bit(i2c, true);
623 drm_edid = drm_edid_read_ddc(connector, i2c);
624 intel_gmbus_force_bit(i2c, false);
625 }
626
627 return drm_edid;
628 }
629
630 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
intel_crt_ddc_get_modes(struct drm_connector * connector,struct i2c_adapter * adapter)631 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
632 struct i2c_adapter *adapter)
633 {
634 const struct drm_edid *drm_edid;
635 int ret;
636
637 drm_edid = intel_crt_get_edid(connector, adapter);
638 if (!drm_edid)
639 return 0;
640
641 ret = intel_connector_update_modes(connector, drm_edid);
642
643 drm_edid_free(drm_edid);
644
645 return ret;
646 }
647
intel_crt_detect_ddc(struct drm_connector * connector)648 static bool intel_crt_detect_ddc(struct drm_connector *connector)
649 {
650 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
651 struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
652 const struct drm_edid *drm_edid;
653 struct i2c_adapter *i2c;
654 bool ret = false;
655
656 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin);
657 drm_edid = intel_crt_get_edid(connector, i2c);
658
659 if (drm_edid) {
660 const struct edid *edid = drm_edid_raw(drm_edid);
661 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
662
663 /*
664 * This may be a DVI-I connector with a shared DDC
665 * link between analog and digital outputs, so we
666 * have to check the EDID input spec of the attached device.
667 */
668 if (!is_digital) {
669 drm_dbg_kms(&dev_priv->drm,
670 "CRT detected via DDC:0x50 [EDID]\n");
671 ret = true;
672 } else {
673 drm_dbg_kms(&dev_priv->drm,
674 "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
675 }
676 } else {
677 drm_dbg_kms(&dev_priv->drm,
678 "CRT not detected via DDC:0x50 [no valid EDID found]\n");
679 }
680
681 drm_edid_free(drm_edid);
682
683 return ret;
684 }
685
686 static enum drm_connector_status
intel_crt_load_detect(struct intel_crt * crt,enum pipe pipe)687 intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
688 {
689 struct drm_device *dev = crt->base.base.dev;
690 struct drm_i915_private *dev_priv = to_i915(dev);
691 enum transcoder cpu_transcoder = (enum transcoder)pipe;
692 u32 save_bclrpat;
693 u32 save_vtotal;
694 u32 vtotal, vactive;
695 u32 vsample;
696 u32 vblank, vblank_start, vblank_end;
697 u32 dsl;
698 u8 st00;
699 enum drm_connector_status status;
700
701 drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
702
703 save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder));
704 save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
705 vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
706
707 vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
708 vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
709
710 vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1;
711 vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
712
713 /* Set the border color to purple. */
714 intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), 0x500050);
715
716 if (DISPLAY_VER(dev_priv) != 2) {
717 u32 transconf = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
718
719 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder),
720 transconf | TRANSCONF_FORCE_BORDER);
721 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
722 /* Wait for next Vblank to substitue
723 * border color for Color info */
724 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
725 st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
726 status = ((st00 & (1 << 4)) != 0) ?
727 connector_status_connected :
728 connector_status_disconnected;
729
730 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), transconf);
731 } else {
732 bool restore_vblank = false;
733 int count, detect;
734
735 /*
736 * If there isn't any border, add some.
737 * Yes, this will flicker
738 */
739 if (vblank_start <= vactive && vblank_end >= vtotal) {
740 u32 vsync = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
741 u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
742
743 vblank_start = vsync_start;
744 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
745 VBLANK_START(vblank_start - 1) |
746 VBLANK_END(vblank_end - 1));
747 restore_vblank = true;
748 }
749 /* sample in the vertical border, selecting the larger one */
750 if (vblank_start - vactive >= vtotal - vblank_end)
751 vsample = (vblank_start + vactive) >> 1;
752 else
753 vsample = (vtotal + vblank_end) >> 1;
754
755 /*
756 * Wait for the border to be displayed
757 */
758 while (intel_de_read(dev_priv, PIPEDSL(pipe)) >= vactive)
759 ;
760 while ((dsl = intel_de_read(dev_priv, PIPEDSL(pipe))) <= vsample)
761 ;
762 /*
763 * Watch ST00 for an entire scanline
764 */
765 detect = 0;
766 count = 0;
767 do {
768 count++;
769 /* Read the ST00 VGA status register */
770 st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
771 if (st00 & (1 << 4))
772 detect++;
773 } while ((intel_de_read(dev_priv, PIPEDSL(pipe)) == dsl));
774
775 /* restore vblank if necessary */
776 if (restore_vblank)
777 intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), vblank);
778 /*
779 * If more than 3/4 of the scanline detected a monitor,
780 * then it is assumed to be present. This works even on i830,
781 * where there isn't any way to force the border color across
782 * the screen
783 */
784 status = detect * 4 > count * 3 ?
785 connector_status_connected :
786 connector_status_disconnected;
787 }
788
789 /* Restore previous settings */
790 intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), save_bclrpat);
791
792 return status;
793 }
794
intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id * id)795 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
796 {
797 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
798 return 1;
799 }
800
801 static const struct dmi_system_id intel_spurious_crt_detect[] = {
802 {
803 .callback = intel_spurious_crt_detect_dmi_callback,
804 .ident = "ACER ZGB",
805 .matches = {
806 DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
807 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
808 },
809 },
810 {
811 .callback = intel_spurious_crt_detect_dmi_callback,
812 .ident = "Intel DZ77BH-55K",
813 .matches = {
814 DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
815 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
816 },
817 },
818 { }
819 };
820
821 static int
intel_crt_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)822 intel_crt_detect(struct drm_connector *connector,
823 struct drm_modeset_acquire_ctx *ctx,
824 bool force)
825 {
826 struct drm_i915_private *dev_priv = to_i915(connector->dev);
827 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
828 struct intel_encoder *intel_encoder = &crt->base;
829 struct drm_atomic_state *state;
830 intel_wakeref_t wakeref;
831 int status;
832
833 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n",
834 connector->base.id, connector->name,
835 force);
836
837 if (!INTEL_DISPLAY_ENABLED(dev_priv))
838 return connector_status_disconnected;
839
840 if (dev_priv->params.load_detect_test) {
841 wakeref = intel_display_power_get(dev_priv,
842 intel_encoder->power_domain);
843 goto load_detect;
844 }
845
846 /* Skip machines without VGA that falsely report hotplug events */
847 if (dmi_check_system(intel_spurious_crt_detect))
848 return connector_status_disconnected;
849
850 wakeref = intel_display_power_get(dev_priv,
851 intel_encoder->power_domain);
852
853 if (I915_HAS_HOTPLUG(dev_priv)) {
854 /* We can not rely on the HPD pin always being correctly wired
855 * up, for example many KVM do not pass it through, and so
856 * only trust an assertion that the monitor is connected.
857 */
858 if (intel_crt_detect_hotplug(connector)) {
859 drm_dbg_kms(&dev_priv->drm,
860 "CRT detected via hotplug\n");
861 status = connector_status_connected;
862 goto out;
863 } else
864 drm_dbg_kms(&dev_priv->drm,
865 "CRT not detected via hotplug\n");
866 }
867
868 if (intel_crt_detect_ddc(connector)) {
869 status = connector_status_connected;
870 goto out;
871 }
872
873 /* Load detection is broken on HPD capable machines. Whoever wants a
874 * broken monitor (without edid) to work behind a broken kvm (that fails
875 * to have the right resistors for HP detection) needs to fix this up.
876 * For now just bail out. */
877 if (I915_HAS_HOTPLUG(dev_priv)) {
878 status = connector_status_disconnected;
879 goto out;
880 }
881
882 load_detect:
883 if (!force) {
884 status = connector->status;
885 goto out;
886 }
887
888 /* for pre-945g platforms use load detect */
889 state = intel_load_detect_get_pipe(connector, ctx);
890 if (IS_ERR(state)) {
891 status = PTR_ERR(state);
892 } else if (!state) {
893 status = connector_status_unknown;
894 } else {
895 if (intel_crt_detect_ddc(connector))
896 status = connector_status_connected;
897 else if (DISPLAY_VER(dev_priv) < 4)
898 status = intel_crt_load_detect(crt,
899 to_intel_crtc(connector->state->crtc)->pipe);
900 else if (dev_priv->params.load_detect_test)
901 status = connector_status_disconnected;
902 else
903 status = connector_status_unknown;
904 intel_load_detect_release_pipe(connector, state, ctx);
905 }
906
907 out:
908 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
909
910 /*
911 * Make sure the refs for power wells enabled during detect are
912 * dropped to avoid a new detect cycle triggered by HPD polling.
913 */
914 intel_display_power_flush_work(dev_priv);
915
916 return status;
917 }
918
intel_crt_get_modes(struct drm_connector * connector)919 static int intel_crt_get_modes(struct drm_connector *connector)
920 {
921 struct drm_device *dev = connector->dev;
922 struct drm_i915_private *dev_priv = to_i915(dev);
923 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
924 struct intel_encoder *intel_encoder = &crt->base;
925 intel_wakeref_t wakeref;
926 struct i2c_adapter *i2c;
927 int ret;
928
929 wakeref = intel_display_power_get(dev_priv,
930 intel_encoder->power_domain);
931
932 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin);
933 ret = intel_crt_ddc_get_modes(connector, i2c);
934 if (ret || !IS_G4X(dev_priv))
935 goto out;
936
937 /* Try to probe digital port for output in DVI-I -> VGA mode. */
938 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
939 ret = intel_crt_ddc_get_modes(connector, i2c);
940
941 out:
942 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
943
944 return ret;
945 }
946
intel_crt_reset(struct drm_encoder * encoder)947 void intel_crt_reset(struct drm_encoder *encoder)
948 {
949 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
950 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
951
952 if (DISPLAY_VER(dev_priv) >= 5) {
953 u32 adpa;
954
955 adpa = intel_de_read(dev_priv, crt->adpa_reg);
956 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
957 adpa |= ADPA_HOTPLUG_BITS;
958 intel_de_write(dev_priv, crt->adpa_reg, adpa);
959 intel_de_posting_read(dev_priv, crt->adpa_reg);
960
961 drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa);
962 crt->force_hotplug_required = true;
963 }
964
965 }
966
967 /*
968 * Routines for controlling stuff on the analog port
969 */
970
971 static const struct drm_connector_funcs intel_crt_connector_funcs = {
972 .fill_modes = drm_helper_probe_single_connector_modes,
973 .late_register = intel_connector_register,
974 .early_unregister = intel_connector_unregister,
975 .destroy = intel_connector_destroy,
976 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
977 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
978 };
979
980 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
981 .detect_ctx = intel_crt_detect,
982 .mode_valid = intel_crt_mode_valid,
983 .get_modes = intel_crt_get_modes,
984 };
985
986 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
987 .reset = intel_crt_reset,
988 .destroy = intel_encoder_destroy,
989 };
990
intel_crt_init(struct drm_i915_private * dev_priv)991 void intel_crt_init(struct drm_i915_private *dev_priv)
992 {
993 struct drm_connector *connector;
994 struct intel_crt *crt;
995 struct intel_connector *intel_connector;
996 i915_reg_t adpa_reg;
997 u32 adpa;
998
999 if (HAS_PCH_SPLIT(dev_priv))
1000 adpa_reg = PCH_ADPA;
1001 else if (IS_VALLEYVIEW(dev_priv))
1002 adpa_reg = VLV_ADPA;
1003 else
1004 adpa_reg = ADPA;
1005
1006 adpa = intel_de_read(dev_priv, adpa_reg);
1007 if ((adpa & ADPA_DAC_ENABLE) == 0) {
1008 /*
1009 * On some machines (some IVB at least) CRT can be
1010 * fused off, but there's no known fuse bit to
1011 * indicate that. On these machine the ADPA register
1012 * works normally, except the DAC enable bit won't
1013 * take. So the only way to tell is attempt to enable
1014 * it and see what happens.
1015 */
1016 intel_de_write(dev_priv, adpa_reg,
1017 adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
1018 if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0)
1019 return;
1020 intel_de_write(dev_priv, adpa_reg, adpa);
1021 }
1022
1023 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
1024 if (!crt)
1025 return;
1026
1027 intel_connector = intel_connector_alloc();
1028 if (!intel_connector) {
1029 kfree(crt);
1030 return;
1031 }
1032
1033 connector = &intel_connector->base;
1034 crt->connector = intel_connector;
1035 drm_connector_init(&dev_priv->drm, &intel_connector->base,
1036 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1037
1038 drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
1039 DRM_MODE_ENCODER_DAC, "CRT");
1040
1041 intel_connector_attach_encoder(intel_connector, &crt->base);
1042
1043 crt->base.type = INTEL_OUTPUT_ANALOG;
1044 crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI);
1045 if (IS_I830(dev_priv))
1046 crt->base.pipe_mask = BIT(PIPE_A);
1047 else
1048 crt->base.pipe_mask = ~0;
1049
1050 if (DISPLAY_VER(dev_priv) != 2)
1051 connector->interlace_allowed = true;
1052
1053 crt->adpa_reg = adpa_reg;
1054
1055 crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
1056
1057 if (I915_HAS_HOTPLUG(dev_priv) &&
1058 !dmi_check_system(intel_spurious_crt_detect)) {
1059 crt->base.hpd_pin = HPD_CRT;
1060 crt->base.hotplug = intel_encoder_hotplug;
1061 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
1062 } else {
1063 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1064 }
1065
1066 if (HAS_DDI(dev_priv)) {
1067 assert_port_valid(dev_priv, PORT_E);
1068
1069 crt->base.port = PORT_E;
1070 crt->base.get_config = hsw_crt_get_config;
1071 crt->base.get_hw_state = intel_ddi_get_hw_state;
1072 crt->base.compute_config = hsw_crt_compute_config;
1073 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1074 crt->base.pre_enable = hsw_pre_enable_crt;
1075 crt->base.enable = hsw_enable_crt;
1076 crt->base.disable = hsw_disable_crt;
1077 crt->base.post_disable = hsw_post_disable_crt;
1078 crt->base.enable_clock = hsw_ddi_enable_clock;
1079 crt->base.disable_clock = hsw_ddi_disable_clock;
1080 crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled;
1081
1082 intel_ddi_buf_trans_init(&crt->base);
1083 } else {
1084 if (HAS_PCH_SPLIT(dev_priv)) {
1085 crt->base.compute_config = pch_crt_compute_config;
1086 crt->base.disable = pch_disable_crt;
1087 crt->base.post_disable = pch_post_disable_crt;
1088 } else {
1089 crt->base.compute_config = intel_crt_compute_config;
1090 crt->base.disable = intel_disable_crt;
1091 }
1092 crt->base.port = PORT_NONE;
1093 crt->base.get_config = intel_crt_get_config;
1094 crt->base.get_hw_state = intel_crt_get_hw_state;
1095 crt->base.enable = intel_enable_crt;
1096 }
1097 intel_connector->get_hw_state = intel_connector_get_hw_state;
1098
1099 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
1100
1101 /*
1102 * TODO: find a proper way to discover whether we need to set the the
1103 * polarity and link reversal bits or not, instead of relying on the
1104 * BIOS.
1105 */
1106 if (HAS_PCH_LPT(dev_priv)) {
1107 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1108 FDI_RX_LINK_REVERSAL_OVERRIDE;
1109
1110 dev_priv->display.fdi.rx_config = intel_de_read(dev_priv,
1111 FDI_RX_CTL(PIPE_A)) & fdi_config;
1112 }
1113
1114 intel_crt_reset(&crt->base.base);
1115 }
1116
