1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * arch/arm/mach-at91/pm.c
4 * AT91 Power Management
5 *
6 * Copyright (C) 2005 David Brownell
7 */
8
9 #include <linux/genalloc.h>
10 #include <linux/io.h>
11 #include <linux/of_address.h>
12 #include <linux/of.h>
13 #include <linux/of_fdt.h>
14 #include <linux/of_platform.h>
15 #include <linux/parser.h>
16 #include <linux/suspend.h>
17
18 #include <linux/clk/at91_pmc.h>
19 #include <linux/platform_data/atmel.h>
20
21 #include <soc/at91/pm.h>
22
23 #include <asm/cacheflush.h>
24 #include <asm/fncpy.h>
25 #include <asm/system_misc.h>
26 #include <asm/suspend.h>
27
28 #include "generic.h"
29 #include "pm.h"
30
31 #define BACKUP_DDR_PHY_CALIBRATION (9)
32
33 /**
34 * struct at91_pm_bu - AT91 power management backup unit data structure
35 * @suspended: true if suspended to backup mode
36 * @reserved: reserved
37 * @canary: canary data for memory checking after exit from backup mode
38 * @resume: resume API
39 * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words
40 * of the memory
41 */
42 struct at91_pm_bu {
43 int suspended;
44 unsigned long reserved;
45 phys_addr_t canary;
46 phys_addr_t resume;
47 unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION];
48 };
49
50 /*
51 * struct at91_pm_sfrbu_offsets: registers mapping for SFRBU
52 * @pswbu: power switch BU control registers
53 */
54 struct at91_pm_sfrbu_regs {
55 struct {
56 u32 key;
57 u32 ctrl;
58 u32 state;
59 u32 softsw;
60 } pswbu;
61 };
62
63 /**
64 * struct at91_soc_pm - AT91 SoC power management data structure
65 * @config_shdwc_ws: wakeup sources configuration function for SHDWC
66 * @config_pmc_ws: wakeup srouces configuration function for PMC
67 * @ws_ids: wakup sources of_device_id array
68 * @data: PM data to be used on last phase of suspend
69 * @sfrbu_regs: SFRBU registers mapping
70 * @bu: backup unit mapped data (for backup mode)
71 * @memcs: memory chip select
72 */
73 struct at91_soc_pm {
74 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
75 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
76 const struct of_device_id *ws_ids;
77 struct at91_pm_bu *bu;
78 struct at91_pm_data data;
79 struct at91_pm_sfrbu_regs sfrbu_regs;
80 void *memcs;
81 };
82
83 /**
84 * enum at91_pm_iomaps: IOs that needs to be mapped for different PM modes
85 * @AT91_PM_IOMAP_SHDWC: SHDWC controller
86 * @AT91_PM_IOMAP_SFRBU: SFRBU controller
87 */
88 enum at91_pm_iomaps {
89 AT91_PM_IOMAP_SHDWC,
90 AT91_PM_IOMAP_SFRBU,
91 };
92
93 #define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name)
94
95 static struct at91_soc_pm soc_pm = {
96 .data = {
97 .standby_mode = AT91_PM_STANDBY,
98 .suspend_mode = AT91_PM_ULP0,
99 },
100 };
101
102 static const match_table_t pm_modes __initconst = {
103 { AT91_PM_STANDBY, "standby" },
104 { AT91_PM_ULP0, "ulp0" },
105 { AT91_PM_ULP0_FAST, "ulp0-fast" },
106 { AT91_PM_ULP1, "ulp1" },
107 { AT91_PM_BACKUP, "backup" },
108 { -1, NULL },
109 };
110
111 #define at91_ramc_read(id, field) \
112 __raw_readl(soc_pm.data.ramc[id] + field)
113
114 #define at91_ramc_write(id, field, value) \
115 __raw_writel(value, soc_pm.data.ramc[id] + field)
116
at91_pm_valid_state(suspend_state_t state)117 static int at91_pm_valid_state(suspend_state_t state)
118 {
119 switch (state) {
120 case PM_SUSPEND_ON:
121 case PM_SUSPEND_STANDBY:
122 case PM_SUSPEND_MEM:
123 return 1;
124
125 default:
126 return 0;
127 }
128 }
129
130 static int canary = 0xA5A5A5A5;
131
132 struct wakeup_source_info {
133 unsigned int pmc_fsmr_bit;
134 unsigned int shdwc_mr_bit;
135 bool set_polarity;
136 };
137
138 static const struct wakeup_source_info ws_info[] = {
139 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
140 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
141 { .pmc_fsmr_bit = AT91_PMC_USBAL },
142 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
143 { .pmc_fsmr_bit = AT91_PMC_RTTAL },
144 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
145 };
146
147 static const struct of_device_id sama5d2_ws_ids[] = {
148 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
149 { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] },
150 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
151 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
152 { .compatible = "usb-ohci", .data = &ws_info[2] },
153 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
154 { .compatible = "usb-ehci", .data = &ws_info[2] },
155 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
156 { /* sentinel */ }
157 };
158
159 static const struct of_device_id sam9x60_ws_ids[] = {
160 { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] },
161 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
162 { .compatible = "usb-ohci", .data = &ws_info[2] },
163 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
164 { .compatible = "usb-ehci", .data = &ws_info[2] },
165 { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] },
166 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
167 { /* sentinel */ }
168 };
169
170 static const struct of_device_id sama7g5_ws_ids[] = {
171 { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] },
172 { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] },
173 { .compatible = "usb-ohci", .data = &ws_info[2] },
174 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
175 { .compatible = "usb-ehci", .data = &ws_info[2] },
176 { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] },
177 { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] },
178 { /* sentinel */ }
179 };
180
at91_pm_config_ws(unsigned int pm_mode,bool set)181 static int at91_pm_config_ws(unsigned int pm_mode, bool set)
182 {
183 const struct wakeup_source_info *wsi;
184 const struct of_device_id *match;
185 struct platform_device *pdev;
186 struct device_node *np;
187 unsigned int mode = 0, polarity = 0, val = 0;
188
189 if (pm_mode != AT91_PM_ULP1)
190 return 0;
191
192 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
193 return -EPERM;
194
195 if (!set) {
196 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
197 return 0;
198 }
199
200 if (soc_pm.config_shdwc_ws)
201 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
202
203 /* SHDWC.MR */
204 val = readl(soc_pm.data.shdwc + 0x04);
205
206 /* Loop through defined wakeup sources. */
207 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
208 pdev = of_find_device_by_node(np);
209 if (!pdev)
210 continue;
211
212 if (device_may_wakeup(&pdev->dev)) {
213 wsi = match->data;
214
215 /* Check if enabled on SHDWC. */
216 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
217 goto put_device;
218
219 mode |= wsi->pmc_fsmr_bit;
220 if (wsi->set_polarity)
221 polarity |= wsi->pmc_fsmr_bit;
222 }
223
224 put_device:
225 put_device(&pdev->dev);
226 }
227
228 if (mode) {
229 if (soc_pm.config_pmc_ws)
230 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
231 } else {
232 pr_err("AT91: PM: no ULP1 wakeup sources found!");
233 }
234
235 return mode ? 0 : -EPERM;
236 }
237
at91_sama5d2_config_shdwc_ws(void __iomem * shdwc,u32 * mode,u32 * polarity)238 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
239 u32 *polarity)
240 {
241 u32 val;
242
243 /* SHDWC.WUIR */
244 val = readl(shdwc + 0x0c);
245 *mode |= (val & 0x3ff);
246 *polarity |= ((val >> 16) & 0x3ff);
247
248 return 0;
249 }
250
at91_sama5d2_config_pmc_ws(void __iomem * pmc,u32 mode,u32 polarity)251 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
252 {
253 writel(mode, pmc + AT91_PMC_FSMR);
254 writel(polarity, pmc + AT91_PMC_FSPR);
255
256 return 0;
257 }
258
at91_sam9x60_config_pmc_ws(void __iomem * pmc,u32 mode,u32 polarity)259 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
260 {
261 writel(mode, pmc + AT91_PMC_FSMR);
262
263 return 0;
264 }
265
266 /*
267 * Called after processes are frozen, but before we shutdown devices.
268 */
at91_pm_begin(suspend_state_t state)269 static int at91_pm_begin(suspend_state_t state)
270 {
271 int ret;
272
273 switch (state) {
274 case PM_SUSPEND_MEM:
275 soc_pm.data.mode = soc_pm.data.suspend_mode;
276 break;
277
278 case PM_SUSPEND_STANDBY:
279 soc_pm.data.mode = soc_pm.data.standby_mode;
280 break;
281
282 default:
283 soc_pm.data.mode = -1;
284 }
285
286 ret = at91_pm_config_ws(soc_pm.data.mode, true);
287 if (ret)
288 return ret;
289
290 if (soc_pm.data.mode == AT91_PM_BACKUP)
291 soc_pm.bu->suspended = 1;
292 else if (soc_pm.bu)
293 soc_pm.bu->suspended = 0;
294
295 return 0;
296 }
297
298 /*
299 * Verify that all the clocks are correct before entering
300 * slow-clock mode.
301 */
at91_pm_verify_clocks(void)302 static int at91_pm_verify_clocks(void)
303 {
304 unsigned long scsr;
305 int i;
306
307 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
308
309 /* USB must not be using PLLB */
310 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
311 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
312 return 0;
313 }
314
315 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
316 for (i = 0; i < 4; i++) {
317 u32 css;
318
319 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
320 continue;
321 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
322 if (css != AT91_PMC_CSS_SLOW) {
323 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
324 return 0;
325 }
326 }
327
328 return 1;
329 }
330
331 /*
332 * Call this from platform driver suspend() to see how deeply to suspend.
333 * For example, some controllers (like OHCI) need one of the PLL clocks
334 * in order to act as a wakeup source, and those are not available when
335 * going into slow clock mode.
336 *
337 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
338 * the very same problem (but not using at91 main_clk), and it'd be better
339 * to add one generic API rather than lots of platform-specific ones.
340 */
at91_suspend_entering_slow_clock(void)341 int at91_suspend_entering_slow_clock(void)
342 {
343 return (soc_pm.data.mode >= AT91_PM_ULP0);
344 }
345 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
346
347 static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
348 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
349 extern u32 at91_pm_suspend_in_sram_sz;
350
at91_suspend_finish(unsigned long val)351 static int at91_suspend_finish(unsigned long val)
352 {
353 int i;
354
355 if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) {
356 /*
357 * The 1st 8 words of memory might get corrupted in the process
358 * of DDR PHY recalibration; it is saved here in securam and it
359 * will be restored later, after recalibration, by bootloader
360 */
361 for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++)
362 soc_pm.bu->ddr_phy_calibration[i] =
363 *((unsigned int *)soc_pm.memcs + (i - 1));
364 }
365
366 flush_cache_all();
367 outer_disable();
368
369 at91_suspend_sram_fn(&soc_pm.data);
370
371 return 0;
372 }
373
at91_pm_switch_ba_to_vbat(void)374 static void at91_pm_switch_ba_to_vbat(void)
375 {
376 unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu);
377 unsigned int val;
378
379 /* Just for safety. */
380 if (!soc_pm.data.sfrbu)
381 return;
382
383 val = readl(soc_pm.data.sfrbu + offset);
384
385 /* Already on VBAT. */
386 if (!(val & soc_pm.sfrbu_regs.pswbu.state))
387 return;
388
389 val &= ~soc_pm.sfrbu_regs.pswbu.softsw;
390 val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl;
391 writel(val, soc_pm.data.sfrbu + offset);
392
393 /* Wait for update. */
394 val = readl(soc_pm.data.sfrbu + offset);
395 while (val & soc_pm.sfrbu_regs.pswbu.state)
396 val = readl(soc_pm.data.sfrbu + offset);
397 }
398
at91_pm_suspend(suspend_state_t state)399 static void at91_pm_suspend(suspend_state_t state)
400 {
401 if (soc_pm.data.mode == AT91_PM_BACKUP) {
402 at91_pm_switch_ba_to_vbat();
403
404 cpu_suspend(0, at91_suspend_finish);
405
406 /* The SRAM is lost between suspend cycles */
407 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
408 &at91_pm_suspend_in_sram,
409 at91_pm_suspend_in_sram_sz);
410 } else {
411 at91_suspend_finish(0);
412 }
413
414 outer_resume();
415 }
416
417 /*
418 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
419 * event sources; and reduces DRAM power. But otherwise it's identical to
420 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
421 *
422 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
423 * suspend more deeply, the master clock switches to the clk32k and turns off
424 * the main oscillator
425 *
426 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
427 */
at91_pm_enter(suspend_state_t state)428 static int at91_pm_enter(suspend_state_t state)
429 {
430 #ifdef CONFIG_PINCTRL_AT91
431 /*
432 * FIXME: this is needed to communicate between the pinctrl driver and
433 * the PM implementation in the machine. Possibly part of the PM
434 * implementation should be moved down into the pinctrl driver and get
435 * called as part of the generic suspend/resume path.
436 */
437 at91_pinctrl_gpio_suspend();
438 #endif
439
440 switch (state) {
441 case PM_SUSPEND_MEM:
442 case PM_SUSPEND_STANDBY:
443 /*
444 * Ensure that clocks are in a valid state.
445 */
446 if (soc_pm.data.mode >= AT91_PM_ULP0 &&
447 !at91_pm_verify_clocks())
448 goto error;
449
450 at91_pm_suspend(state);
451
452 break;
453
454 case PM_SUSPEND_ON:
455 cpu_do_idle();
456 break;
457
458 default:
459 pr_debug("AT91: PM - bogus suspend state %d\n", state);
460 goto error;
461 }
462
463 error:
464 #ifdef CONFIG_PINCTRL_AT91
465 at91_pinctrl_gpio_resume();
466 #endif
467 return 0;
468 }
469
470 /*
471 * Called right prior to thawing processes.
472 */
at91_pm_end(void)473 static void at91_pm_end(void)
474 {
475 at91_pm_config_ws(soc_pm.data.mode, false);
476 }
477
478
479 static const struct platform_suspend_ops at91_pm_ops = {
480 .valid = at91_pm_valid_state,
481 .begin = at91_pm_begin,
482 .enter = at91_pm_enter,
483 .end = at91_pm_end,
484 };
485
486 static struct platform_device at91_cpuidle_device = {
487 .name = "cpuidle-at91",
488 };
489
490 /*
491 * The AT91RM9200 goes into self-refresh mode with this command, and will
492 * terminate self-refresh automatically on the next SDRAM access.
493 *
494 * Self-refresh mode is exited as soon as a memory access is made, but we don't
495 * know for sure when that happens. However, we need to restore the low-power
496 * mode if it was enabled before going idle. Restoring low-power mode while
497 * still in self-refresh is "not recommended", but seems to work.
498 */
at91rm9200_standby(void)499 static void at91rm9200_standby(void)
500 {
501 asm volatile(
502 "b 1f\n\t"
503 ".align 5\n\t"
504 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
505 " str %2, [%1, %3]\n\t"
506 " mcr p15, 0, %0, c7, c0, 4\n\t"
507 :
508 : "r" (0), "r" (soc_pm.data.ramc[0]),
509 "r" (1), "r" (AT91_MC_SDRAMC_SRR));
510 }
511
512 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
513 * remember.
514 */
at91_ddr_standby(void)515 static void at91_ddr_standby(void)
516 {
517 /* Those two values allow us to delay self-refresh activation
518 * to the maximum. */
519 u32 lpr0, lpr1 = 0;
520 u32 mdr, saved_mdr0, saved_mdr1 = 0;
521 u32 saved_lpr0, saved_lpr1 = 0;
522
523 /* LPDDR1 --> force DDR2 mode during self-refresh */
524 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
525 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
526 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
527 mdr |= AT91_DDRSDRC_MD_DDR2;
528 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
529 }
530
531 if (soc_pm.data.ramc[1]) {
532 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
533 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
534 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
535 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
536 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
537 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
538 mdr |= AT91_DDRSDRC_MD_DDR2;
539 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
540 }
541 }
542
543 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
544 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
545 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
546
547 /* self-refresh mode now */
548 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
549 if (soc_pm.data.ramc[1])
550 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
551
552 cpu_do_idle();
553
554 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
555 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
556 if (soc_pm.data.ramc[1]) {
557 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
558 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
559 }
560 }
561
sama5d3_ddr_standby(void)562 static void sama5d3_ddr_standby(void)
563 {
564 u32 lpr0;
565 u32 saved_lpr0;
566
567 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
568 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
569 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
570
571 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
572
573 cpu_do_idle();
574
575 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
576 }
577
578 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
579 * remember.
580 */
at91sam9_sdram_standby(void)581 static void at91sam9_sdram_standby(void)
582 {
583 u32 lpr0, lpr1 = 0;
584 u32 saved_lpr0, saved_lpr1 = 0;
585
586 if (soc_pm.data.ramc[1]) {
587 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
588 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
589 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
590 }
591
592 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
593 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
594 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
595
596 /* self-refresh mode now */
597 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
598 if (soc_pm.data.ramc[1])
599 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
600
601 cpu_do_idle();
602
603 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
604 if (soc_pm.data.ramc[1])
605 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
606 }
607
608 struct ramc_info {
609 void (*idle)(void);
610 unsigned int memctrl;
611 };
612
613 static const struct ramc_info ramc_infos[] __initconst = {
614 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
615 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
616 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
617 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
618 };
619
620 static const struct of_device_id ramc_ids[] __initconst = {
621 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
622 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
623 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
624 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
625 { .compatible = "microchip,sama7g5-uddrc", },
626 { /*sentinel*/ }
627 };
628
629 static const struct of_device_id ramc_phy_ids[] __initconst = {
630 { .compatible = "microchip,sama7g5-ddr3phy", },
631 { /* Sentinel. */ },
632 };
633
at91_dt_ramc(bool phy_mandatory)634 static __init int at91_dt_ramc(bool phy_mandatory)
635 {
636 struct device_node *np;
637 const struct of_device_id *of_id;
638 int idx = 0;
639 void *standby = NULL;
640 const struct ramc_info *ramc;
641 int ret;
642
643 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
644 soc_pm.data.ramc[idx] = of_iomap(np, 0);
645 if (!soc_pm.data.ramc[idx]) {
646 pr_err("unable to map ramc[%d] cpu registers\n", idx);
647 ret = -ENOMEM;
648 goto unmap_ramc;
649 }
650
651 ramc = of_id->data;
652 if (ramc) {
653 if (!standby)
654 standby = ramc->idle;
655 soc_pm.data.memctrl = ramc->memctrl;
656 }
657
658 idx++;
659 }
660
661 if (!idx) {
662 pr_err("unable to find compatible ram controller node in dtb\n");
663 ret = -ENODEV;
664 goto unmap_ramc;
665 }
666
667 /* Lookup for DDR PHY node, if any. */
668 for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) {
669 soc_pm.data.ramc_phy = of_iomap(np, 0);
670 if (!soc_pm.data.ramc_phy) {
671 pr_err("unable to map ramc phy cpu registers\n");
672 ret = -ENOMEM;
673 goto unmap_ramc;
674 }
675 }
676
677 if (phy_mandatory && !soc_pm.data.ramc_phy) {
678 pr_err("DDR PHY is mandatory!\n");
679 ret = -ENODEV;
680 goto unmap_ramc;
681 }
682
683 if (!standby) {
684 pr_warn("ramc no standby function available\n");
685 return 0;
686 }
687
688 at91_cpuidle_device.dev.platform_data = standby;
689
690 return 0;
691
692 unmap_ramc:
693 while (idx)
694 iounmap(soc_pm.data.ramc[--idx]);
695
696 return ret;
697 }
698
at91rm9200_idle(void)699 static void at91rm9200_idle(void)
700 {
701 /*
702 * Disable the processor clock. The processor will be automatically
703 * re-enabled by an interrupt or by a reset.
704 */
705 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
706 }
707
at91sam9_idle(void)708 static void at91sam9_idle(void)
709 {
710 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
711 cpu_do_idle();
712 }
713
at91_pm_sram_init(void)714 static void __init at91_pm_sram_init(void)
715 {
716 struct gen_pool *sram_pool;
717 phys_addr_t sram_pbase;
718 unsigned long sram_base;
719 struct device_node *node;
720 struct platform_device *pdev = NULL;
721
722 for_each_compatible_node(node, NULL, "mmio-sram") {
723 pdev = of_find_device_by_node(node);
724 if (pdev) {
725 of_node_put(node);
726 break;
727 }
728 }
729
730 if (!pdev) {
731 pr_warn("%s: failed to find sram device!\n", __func__);
732 return;
733 }
734
735 sram_pool = gen_pool_get(&pdev->dev, NULL);
736 if (!sram_pool) {
737 pr_warn("%s: sram pool unavailable!\n", __func__);
738 goto out_put_device;
739 }
740
741 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
742 if (!sram_base) {
743 pr_warn("%s: unable to alloc sram!\n", __func__);
744 goto out_put_device;
745 }
746
747 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
748 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
749 at91_pm_suspend_in_sram_sz, false);
750 if (!at91_suspend_sram_fn) {
751 pr_warn("SRAM: Could not map\n");
752 goto out_put_device;
753 }
754
755 /* Copy the pm suspend handler to SRAM */
756 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
757 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
758 return;
759
760 out_put_device:
761 put_device(&pdev->dev);
762 return;
763 }
764
at91_is_pm_mode_active(int pm_mode)765 static bool __init at91_is_pm_mode_active(int pm_mode)
766 {
767 return (soc_pm.data.standby_mode == pm_mode ||
768 soc_pm.data.suspend_mode == pm_mode);
769 }
770
at91_pm_backup_scan_memcs(unsigned long node,const char * uname,int depth,void * data)771 static int __init at91_pm_backup_scan_memcs(unsigned long node,
772 const char *uname, int depth,
773 void *data)
774 {
775 const char *type;
776 const __be32 *reg;
777 int *located = data;
778 int size;
779
780 /* Memory node already located. */
781 if (*located)
782 return 0;
783
784 type = of_get_flat_dt_prop(node, "device_type", NULL);
785
786 /* We are scanning "memory" nodes only. */
787 if (!type || strcmp(type, "memory"))
788 return 0;
789
790 reg = of_get_flat_dt_prop(node, "reg", &size);
791 if (reg) {
792 soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg));
793 *located = 1;
794 }
795
796 return 0;
797 }
798
at91_pm_backup_init(void)799 static int __init at91_pm_backup_init(void)
800 {
801 struct gen_pool *sram_pool;
802 struct device_node *np;
803 struct platform_device *pdev;
804 int ret = -ENODEV, located = 0;
805
806 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) &&
807 !IS_ENABLED(CONFIG_SOC_SAMA7G5))
808 return -EPERM;
809
810 if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
811 return 0;
812
813 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
814 if (!np)
815 return ret;
816
817 pdev = of_find_device_by_node(np);
818 of_node_put(np);
819 if (!pdev) {
820 pr_warn("%s: failed to find securam device!\n", __func__);
821 return ret;
822 }
823
824 sram_pool = gen_pool_get(&pdev->dev, NULL);
825 if (!sram_pool) {
826 pr_warn("%s: securam pool unavailable!\n", __func__);
827 goto securam_fail;
828 }
829
830 soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
831 if (!soc_pm.bu) {
832 pr_warn("%s: unable to alloc securam!\n", __func__);
833 ret = -ENOMEM;
834 goto securam_fail;
835 }
836
837 soc_pm.bu->suspended = 0;
838 soc_pm.bu->canary = __pa_symbol(&canary);
839 soc_pm.bu->resume = __pa_symbol(cpu_resume);
840 if (soc_pm.data.ramc_phy) {
841 of_scan_flat_dt(at91_pm_backup_scan_memcs, &located);
842 if (!located)
843 goto securam_fail;
844
845 /* DDR3PHY_ZQ0SR0 */
846 soc_pm.bu->ddr_phy_calibration[0] = readl(soc_pm.data.ramc_phy +
847 0x188);
848 }
849
850 return 0;
851
852 securam_fail:
853 put_device(&pdev->dev);
854 return ret;
855 }
856
857 static const struct of_device_id atmel_shdwc_ids[] = {
858 { .compatible = "atmel,sama5d2-shdwc" },
859 { .compatible = "microchip,sam9x60-shdwc" },
860 { .compatible = "microchip,sama7g5-shdwc" },
861 { /* sentinel. */ }
862 };
863
at91_pm_modes_init(const u32 * maps,int len)864 static void __init at91_pm_modes_init(const u32 *maps, int len)
865 {
866 struct device_node *np;
867 int ret, mode;
868
869 ret = at91_pm_backup_init();
870 if (ret) {
871 if (soc_pm.data.standby_mode == AT91_PM_BACKUP)
872 soc_pm.data.standby_mode = AT91_PM_ULP0;
873 if (soc_pm.data.suspend_mode == AT91_PM_BACKUP)
874 soc_pm.data.suspend_mode = AT91_PM_ULP0;
875 }
876
877 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
878 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) {
879 np = of_find_matching_node(NULL, atmel_shdwc_ids);
880 if (!np) {
881 pr_warn("%s: failed to find shdwc!\n", __func__);
882
883 /* Use ULP0 if it doesn't needs SHDWC.*/
884 if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)))
885 mode = AT91_PM_ULP0;
886 else
887 mode = AT91_PM_STANDBY;
888
889 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC))
890 soc_pm.data.standby_mode = mode;
891 if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))
892 soc_pm.data.suspend_mode = mode;
893 } else {
894 soc_pm.data.shdwc = of_iomap(np, 0);
895 of_node_put(np);
896 }
897 }
898
899 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
900 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) {
901 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
902 if (!np) {
903 pr_warn("%s: failed to find sfrbu!\n", __func__);
904
905 /*
906 * Use ULP0 if it doesn't need SHDWC or if SHDWC
907 * was already located.
908 */
909 if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)) ||
910 soc_pm.data.shdwc)
911 mode = AT91_PM_ULP0;
912 else
913 mode = AT91_PM_STANDBY;
914
915 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU))
916 soc_pm.data.standby_mode = mode;
917 if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))
918 soc_pm.data.suspend_mode = mode;
919 } else {
920 soc_pm.data.sfrbu = of_iomap(np, 0);
921 of_node_put(np);
922 }
923 }
924
925 /* Unmap all unnecessary. */
926 if (soc_pm.data.shdwc &&
927 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
928 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) {
929 iounmap(soc_pm.data.shdwc);
930 soc_pm.data.shdwc = NULL;
931 }
932
933 if (soc_pm.data.sfrbu &&
934 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
935 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) {
936 iounmap(soc_pm.data.sfrbu);
937 soc_pm.data.sfrbu = NULL;
938 }
939
940 return;
941 }
942
943 struct pmc_info {
944 unsigned long uhp_udp_mask;
945 unsigned long mckr;
946 unsigned long version;
947 };
948
949 static const struct pmc_info pmc_infos[] __initconst = {
950 {
951 .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
952 .mckr = 0x30,
953 .version = AT91_PMC_V1,
954 },
955
956 {
957 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
958 .mckr = 0x30,
959 .version = AT91_PMC_V1,
960 },
961 {
962 .uhp_udp_mask = AT91SAM926x_PMC_UHP,
963 .mckr = 0x30,
964 .version = AT91_PMC_V1,
965 },
966 { .uhp_udp_mask = 0,
967 .mckr = 0x30,
968 .version = AT91_PMC_V1,
969 },
970 {
971 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
972 .mckr = 0x28,
973 .version = AT91_PMC_V2,
974 },
975 {
976 .mckr = 0x28,
977 .version = AT91_PMC_V2,
978 },
979
980 };
981
982 static const struct of_device_id atmel_pmc_ids[] __initconst = {
983 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
984 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
985 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
986 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
987 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
988 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
989 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
990 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
991 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
992 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
993 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
994 { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
995 { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
996 { /* sentinel */ },
997 };
998
at91_pm_modes_validate(const int * modes,int len)999 static void __init at91_pm_modes_validate(const int *modes, int len)
1000 {
1001 u8 i, standby = 0, suspend = 0;
1002 int mode;
1003
1004 for (i = 0; i < len; i++) {
1005 if (standby && suspend)
1006 break;
1007
1008 if (modes[i] == soc_pm.data.standby_mode && !standby) {
1009 standby = 1;
1010 continue;
1011 }
1012
1013 if (modes[i] == soc_pm.data.suspend_mode && !suspend) {
1014 suspend = 1;
1015 continue;
1016 }
1017 }
1018
1019 if (!standby) {
1020 if (soc_pm.data.suspend_mode == AT91_PM_STANDBY)
1021 mode = AT91_PM_ULP0;
1022 else
1023 mode = AT91_PM_STANDBY;
1024
1025 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
1026 pm_modes[soc_pm.data.standby_mode].pattern,
1027 pm_modes[mode].pattern);
1028 soc_pm.data.standby_mode = mode;
1029 }
1030
1031 if (!suspend) {
1032 if (soc_pm.data.standby_mode == AT91_PM_ULP0)
1033 mode = AT91_PM_STANDBY;
1034 else
1035 mode = AT91_PM_ULP0;
1036
1037 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
1038 pm_modes[soc_pm.data.suspend_mode].pattern,
1039 pm_modes[mode].pattern);
1040 soc_pm.data.suspend_mode = mode;
1041 }
1042 }
1043
at91_pm_init(void (* pm_idle)(void))1044 static void __init at91_pm_init(void (*pm_idle)(void))
1045 {
1046 struct device_node *pmc_np;
1047 const struct of_device_id *of_id;
1048 const struct pmc_info *pmc;
1049
1050 if (at91_cpuidle_device.dev.platform_data)
1051 platform_device_register(&at91_cpuidle_device);
1052
1053 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
1054 soc_pm.data.pmc = of_iomap(pmc_np, 0);
1055 of_node_put(pmc_np);
1056 if (!soc_pm.data.pmc) {
1057 pr_err("AT91: PM not supported, PMC not found\n");
1058 return;
1059 }
1060
1061 pmc = of_id->data;
1062 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
1063 soc_pm.data.pmc_mckr_offset = pmc->mckr;
1064 soc_pm.data.pmc_version = pmc->version;
1065
1066 if (pm_idle)
1067 arm_pm_idle = pm_idle;
1068
1069 at91_pm_sram_init();
1070
1071 if (at91_suspend_sram_fn) {
1072 suspend_set_ops(&at91_pm_ops);
1073 pr_info("AT91: PM: standby: %s, suspend: %s\n",
1074 pm_modes[soc_pm.data.standby_mode].pattern,
1075 pm_modes[soc_pm.data.suspend_mode].pattern);
1076 } else {
1077 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
1078 }
1079 }
1080
at91rm9200_pm_init(void)1081 void __init at91rm9200_pm_init(void)
1082 {
1083 int ret;
1084
1085 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
1086 return;
1087
1088 /*
1089 * Force STANDBY and ULP0 mode to avoid calling
1090 * at91_pm_modes_validate() which may increase booting time.
1091 * Platform supports anyway only STANDBY and ULP0 modes.
1092 */
1093 soc_pm.data.standby_mode = AT91_PM_STANDBY;
1094 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1095
1096 ret = at91_dt_ramc(false);
1097 if (ret)
1098 return;
1099
1100 /*
1101 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
1102 */
1103 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
1104
1105 at91_pm_init(at91rm9200_idle);
1106 }
1107
sam9x60_pm_init(void)1108 void __init sam9x60_pm_init(void)
1109 {
1110 static const int modes[] __initconst = {
1111 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
1112 };
1113 static const int iomaps[] __initconst = {
1114 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
1115 };
1116 int ret;
1117
1118 if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
1119 return;
1120
1121 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1122 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1123 ret = at91_dt_ramc(false);
1124 if (ret)
1125 return;
1126
1127 at91_pm_init(NULL);
1128
1129 soc_pm.ws_ids = sam9x60_ws_ids;
1130 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
1131 }
1132
at91sam9_pm_init(void)1133 void __init at91sam9_pm_init(void)
1134 {
1135 int ret;
1136
1137 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
1138 return;
1139
1140 /*
1141 * Force STANDBY and ULP0 mode to avoid calling
1142 * at91_pm_modes_validate() which may increase booting time.
1143 * Platform supports anyway only STANDBY and ULP0 modes.
1144 */
1145 soc_pm.data.standby_mode = AT91_PM_STANDBY;
1146 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1147
1148 ret = at91_dt_ramc(false);
1149 if (ret)
1150 return;
1151
1152 at91_pm_init(at91sam9_idle);
1153 }
1154
sama5_pm_init(void)1155 void __init sama5_pm_init(void)
1156 {
1157 static const int modes[] __initconst = {
1158 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST,
1159 };
1160 int ret;
1161
1162 if (!IS_ENABLED(CONFIG_SOC_SAMA5))
1163 return;
1164
1165 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1166 ret = at91_dt_ramc(false);
1167 if (ret)
1168 return;
1169
1170 at91_pm_init(NULL);
1171 }
1172
sama5d2_pm_init(void)1173 void __init sama5d2_pm_init(void)
1174 {
1175 static const int modes[] __initconst = {
1176 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
1177 AT91_PM_BACKUP,
1178 };
1179 static const u32 iomaps[] __initconst = {
1180 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
1181 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) |
1182 AT91_PM_IOMAP(SFRBU),
1183 };
1184 int ret;
1185
1186 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
1187 return;
1188
1189 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1190 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1191 ret = at91_dt_ramc(false);
1192 if (ret)
1193 return;
1194
1195 at91_pm_init(NULL);
1196
1197 soc_pm.ws_ids = sama5d2_ws_ids;
1198 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
1199 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
1200
1201 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
1202 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
1203 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
1204 soc_pm.sfrbu_regs.pswbu.state = BIT(3);
1205 }
1206
sama7_pm_init(void)1207 void __init sama7_pm_init(void)
1208 {
1209 static const int modes[] __initconst = {
1210 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
1211 };
1212 static const u32 iomaps[] __initconst = {
1213 [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU),
1214 [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) |
1215 AT91_PM_IOMAP(SHDWC),
1216 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) |
1217 AT91_PM_IOMAP(SHDWC),
1218 };
1219 int ret;
1220
1221 if (!IS_ENABLED(CONFIG_SOC_SAMA7))
1222 return;
1223
1224 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1225
1226 ret = at91_dt_ramc(true);
1227 if (ret)
1228 return;
1229
1230 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1231 at91_pm_init(NULL);
1232
1233 soc_pm.ws_ids = sama7g5_ws_ids;
1234 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
1235
1236 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
1237 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
1238 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
1239 soc_pm.sfrbu_regs.pswbu.state = BIT(2);
1240 }
1241
at91_pm_modes_select(char * str)1242 static int __init at91_pm_modes_select(char *str)
1243 {
1244 char *s;
1245 substring_t args[MAX_OPT_ARGS];
1246 int standby, suspend;
1247
1248 if (!str)
1249 return 0;
1250
1251 s = strsep(&str, ",");
1252 standby = match_token(s, pm_modes, args);
1253 if (standby < 0)
1254 return 0;
1255
1256 suspend = match_token(str, pm_modes, args);
1257 if (suspend < 0)
1258 return 0;
1259
1260 soc_pm.data.standby_mode = standby;
1261 soc_pm.data.suspend_mode = suspend;
1262
1263 return 0;
1264 }
1265 early_param("atmel.pm_modes", at91_pm_modes_select);
1266
