1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Texas Instruments ADS7950 SPI ADC driver
4 *
5 * Copyright 2016 David Lechner <david@lechnology.com>
6 *
7 * Based on iio/ad7923.c:
8 * Copyright 2011 Analog Devices Inc
9 * Copyright 2012 CS Systemes d'Information
10 *
11 * And also on hwmon/ads79xx.c
12 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
13 * Nishanth Menon
14 */
15
16 #include <linux/acpi.h>
17 #include <linux/bitops.h>
18 #include <linux/device.h>
19 #include <linux/err.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/slab.h>
25 #include <linux/spi/spi.h>
26
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/iio.h>
29 #include <linux/iio/sysfs.h>
30 #include <linux/iio/trigger_consumer.h>
31 #include <linux/iio/triggered_buffer.h>
32
33 /*
34 * In case of ACPI, we use the 5000 mV as default for the reference pin.
35 * Device tree users encode that via the vref-supply regulator.
36 */
37 #define TI_ADS7950_VA_MV_ACPI_DEFAULT 5000
38
39 #define TI_ADS7950_CR_MANUAL BIT(12)
40 #define TI_ADS7950_CR_WRITE BIT(11)
41 #define TI_ADS7950_CR_CHAN(ch) ((ch) << 7)
42 #define TI_ADS7950_CR_RANGE_5V BIT(6)
43
44 #define TI_ADS7950_MAX_CHAN 16
45
46 #define TI_ADS7950_TIMESTAMP_SIZE (sizeof(int64_t) / sizeof(__be16))
47
48 /* val = value, dec = left shift, bits = number of bits of the mask */
49 #define TI_ADS7950_EXTRACT(val, dec, bits) \
50 (((val) >> (dec)) & ((1 << (bits)) - 1))
51
52 struct ti_ads7950_state {
53 struct spi_device *spi;
54 struct spi_transfer ring_xfer[TI_ADS7950_MAX_CHAN + 2];
55 struct spi_transfer scan_single_xfer[3];
56 struct spi_message ring_msg;
57 struct spi_message scan_single_msg;
58
59 struct regulator *reg;
60 unsigned int vref_mv;
61
62 unsigned int settings;
63
64 /*
65 * DMA (thus cache coherency maintenance) requires the
66 * transfer buffers to live in their own cache lines.
67 */
68 __be16 rx_buf[TI_ADS7950_MAX_CHAN + TI_ADS7950_TIMESTAMP_SIZE]
69 ____cacheline_aligned;
70 __be16 tx_buf[TI_ADS7950_MAX_CHAN];
71 __be16 single_tx;
72 __be16 single_rx;
73
74 };
75
76 struct ti_ads7950_chip_info {
77 const struct iio_chan_spec *channels;
78 unsigned int num_channels;
79 };
80
81 enum ti_ads7950_id {
82 TI_ADS7950,
83 TI_ADS7951,
84 TI_ADS7952,
85 TI_ADS7953,
86 TI_ADS7954,
87 TI_ADS7955,
88 TI_ADS7956,
89 TI_ADS7957,
90 TI_ADS7958,
91 TI_ADS7959,
92 TI_ADS7960,
93 TI_ADS7961,
94 };
95
96 #define TI_ADS7950_V_CHAN(index, bits) \
97 { \
98 .type = IIO_VOLTAGE, \
99 .indexed = 1, \
100 .channel = index, \
101 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
102 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
103 .address = index, \
104 .datasheet_name = "CH##index", \
105 .scan_index = index, \
106 .scan_type = { \
107 .sign = 'u', \
108 .realbits = bits, \
109 .storagebits = 16, \
110 .shift = 12 - (bits), \
111 .endianness = IIO_BE, \
112 }, \
113 }
114
115 #define DECLARE_TI_ADS7950_4_CHANNELS(name, bits) \
116 const struct iio_chan_spec name ## _channels[] = { \
117 TI_ADS7950_V_CHAN(0, bits), \
118 TI_ADS7950_V_CHAN(1, bits), \
119 TI_ADS7950_V_CHAN(2, bits), \
120 TI_ADS7950_V_CHAN(3, bits), \
121 IIO_CHAN_SOFT_TIMESTAMP(4), \
122 }
123
124 #define DECLARE_TI_ADS7950_8_CHANNELS(name, bits) \
125 const struct iio_chan_spec name ## _channels[] = { \
126 TI_ADS7950_V_CHAN(0, bits), \
127 TI_ADS7950_V_CHAN(1, bits), \
128 TI_ADS7950_V_CHAN(2, bits), \
129 TI_ADS7950_V_CHAN(3, bits), \
130 TI_ADS7950_V_CHAN(4, bits), \
131 TI_ADS7950_V_CHAN(5, bits), \
132 TI_ADS7950_V_CHAN(6, bits), \
133 TI_ADS7950_V_CHAN(7, bits), \
134 IIO_CHAN_SOFT_TIMESTAMP(8), \
135 }
136
137 #define DECLARE_TI_ADS7950_12_CHANNELS(name, bits) \
138 const struct iio_chan_spec name ## _channels[] = { \
139 TI_ADS7950_V_CHAN(0, bits), \
140 TI_ADS7950_V_CHAN(1, bits), \
141 TI_ADS7950_V_CHAN(2, bits), \
142 TI_ADS7950_V_CHAN(3, bits), \
143 TI_ADS7950_V_CHAN(4, bits), \
144 TI_ADS7950_V_CHAN(5, bits), \
145 TI_ADS7950_V_CHAN(6, bits), \
146 TI_ADS7950_V_CHAN(7, bits), \
147 TI_ADS7950_V_CHAN(8, bits), \
148 TI_ADS7950_V_CHAN(9, bits), \
149 TI_ADS7950_V_CHAN(10, bits), \
150 TI_ADS7950_V_CHAN(11, bits), \
151 IIO_CHAN_SOFT_TIMESTAMP(12), \
152 }
153
154 #define DECLARE_TI_ADS7950_16_CHANNELS(name, bits) \
155 const struct iio_chan_spec name ## _channels[] = { \
156 TI_ADS7950_V_CHAN(0, bits), \
157 TI_ADS7950_V_CHAN(1, bits), \
158 TI_ADS7950_V_CHAN(2, bits), \
159 TI_ADS7950_V_CHAN(3, bits), \
160 TI_ADS7950_V_CHAN(4, bits), \
161 TI_ADS7950_V_CHAN(5, bits), \
162 TI_ADS7950_V_CHAN(6, bits), \
163 TI_ADS7950_V_CHAN(7, bits), \
164 TI_ADS7950_V_CHAN(8, bits), \
165 TI_ADS7950_V_CHAN(9, bits), \
166 TI_ADS7950_V_CHAN(10, bits), \
167 TI_ADS7950_V_CHAN(11, bits), \
168 TI_ADS7950_V_CHAN(12, bits), \
169 TI_ADS7950_V_CHAN(13, bits), \
170 TI_ADS7950_V_CHAN(14, bits), \
171 TI_ADS7950_V_CHAN(15, bits), \
172 IIO_CHAN_SOFT_TIMESTAMP(16), \
173 }
174
175 static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7950, 12);
176 static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7951, 12);
177 static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7952, 12);
178 static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7953, 12);
179 static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7954, 10);
180 static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7955, 10);
181 static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7956, 10);
182 static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7957, 10);
183 static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7958, 8);
184 static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7959, 8);
185 static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7960, 8);
186 static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7961, 8);
187
188 static const struct ti_ads7950_chip_info ti_ads7950_chip_info[] = {
189 [TI_ADS7950] = {
190 .channels = ti_ads7950_channels,
191 .num_channels = ARRAY_SIZE(ti_ads7950_channels),
192 },
193 [TI_ADS7951] = {
194 .channels = ti_ads7951_channels,
195 .num_channels = ARRAY_SIZE(ti_ads7951_channels),
196 },
197 [TI_ADS7952] = {
198 .channels = ti_ads7952_channels,
199 .num_channels = ARRAY_SIZE(ti_ads7952_channels),
200 },
201 [TI_ADS7953] = {
202 .channels = ti_ads7953_channels,
203 .num_channels = ARRAY_SIZE(ti_ads7953_channels),
204 },
205 [TI_ADS7954] = {
206 .channels = ti_ads7954_channels,
207 .num_channels = ARRAY_SIZE(ti_ads7954_channels),
208 },
209 [TI_ADS7955] = {
210 .channels = ti_ads7955_channels,
211 .num_channels = ARRAY_SIZE(ti_ads7955_channels),
212 },
213 [TI_ADS7956] = {
214 .channels = ti_ads7956_channels,
215 .num_channels = ARRAY_SIZE(ti_ads7956_channels),
216 },
217 [TI_ADS7957] = {
218 .channels = ti_ads7957_channels,
219 .num_channels = ARRAY_SIZE(ti_ads7957_channels),
220 },
221 [TI_ADS7958] = {
222 .channels = ti_ads7958_channels,
223 .num_channels = ARRAY_SIZE(ti_ads7958_channels),
224 },
225 [TI_ADS7959] = {
226 .channels = ti_ads7959_channels,
227 .num_channels = ARRAY_SIZE(ti_ads7959_channels),
228 },
229 [TI_ADS7960] = {
230 .channels = ti_ads7960_channels,
231 .num_channels = ARRAY_SIZE(ti_ads7960_channels),
232 },
233 [TI_ADS7961] = {
234 .channels = ti_ads7961_channels,
235 .num_channels = ARRAY_SIZE(ti_ads7961_channels),
236 },
237 };
238
239 /*
240 * ti_ads7950_update_scan_mode() setup the spi transfer buffer for the new
241 * scan mask
242 */
ti_ads7950_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * active_scan_mask)243 static int ti_ads7950_update_scan_mode(struct iio_dev *indio_dev,
244 const unsigned long *active_scan_mask)
245 {
246 struct ti_ads7950_state *st = iio_priv(indio_dev);
247 int i, cmd, len;
248
249 len = 0;
250 for_each_set_bit(i, active_scan_mask, indio_dev->num_channels) {
251 cmd = TI_ADS7950_CR_WRITE | TI_ADS7950_CR_CHAN(i) | st->settings;
252 st->tx_buf[len++] = cpu_to_be16(cmd);
253 }
254
255 /* Data for the 1st channel is not returned until the 3rd transfer */
256 len += 2;
257 for (i = 0; i < len; i++) {
258 if ((i + 2) < len)
259 st->ring_xfer[i].tx_buf = &st->tx_buf[i];
260 if (i >= 2)
261 st->ring_xfer[i].rx_buf = &st->rx_buf[i - 2];
262 st->ring_xfer[i].len = 2;
263 st->ring_xfer[i].cs_change = 1;
264 }
265 /* make sure last transfer's cs_change is not set */
266 st->ring_xfer[len - 1].cs_change = 0;
267
268 spi_message_init_with_transfers(&st->ring_msg, st->ring_xfer, len);
269
270 return 0;
271 }
272
ti_ads7950_trigger_handler(int irq,void * p)273 static irqreturn_t ti_ads7950_trigger_handler(int irq, void *p)
274 {
275 struct iio_poll_func *pf = p;
276 struct iio_dev *indio_dev = pf->indio_dev;
277 struct ti_ads7950_state *st = iio_priv(indio_dev);
278 int ret;
279
280 ret = spi_sync(st->spi, &st->ring_msg);
281 if (ret < 0)
282 goto out;
283
284 iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
285 iio_get_time_ns(indio_dev));
286
287 out:
288 iio_trigger_notify_done(indio_dev->trig);
289
290 return IRQ_HANDLED;
291 }
292
ti_ads7950_scan_direct(struct iio_dev * indio_dev,unsigned int ch)293 static int ti_ads7950_scan_direct(struct iio_dev *indio_dev, unsigned int ch)
294 {
295 struct ti_ads7950_state *st = iio_priv(indio_dev);
296 int ret, cmd;
297
298 mutex_lock(&indio_dev->mlock);
299
300 cmd = TI_ADS7950_CR_WRITE | TI_ADS7950_CR_CHAN(ch) | st->settings;
301 st->single_tx = cpu_to_be16(cmd);
302
303 ret = spi_sync(st->spi, &st->scan_single_msg);
304 if (ret)
305 goto out;
306
307 ret = be16_to_cpu(st->single_rx);
308
309 out:
310 mutex_unlock(&indio_dev->mlock);
311
312 return ret;
313 }
314
ti_ads7950_get_range(struct ti_ads7950_state * st)315 static int ti_ads7950_get_range(struct ti_ads7950_state *st)
316 {
317 int vref;
318
319 if (st->vref_mv) {
320 vref = st->vref_mv;
321 } else {
322 vref = regulator_get_voltage(st->reg);
323 if (vref < 0)
324 return vref;
325
326 vref /= 1000;
327 }
328
329 if (st->settings & TI_ADS7950_CR_RANGE_5V)
330 vref *= 2;
331
332 return vref;
333 }
334
ti_ads7950_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)335 static int ti_ads7950_read_raw(struct iio_dev *indio_dev,
336 struct iio_chan_spec const *chan,
337 int *val, int *val2, long m)
338 {
339 struct ti_ads7950_state *st = iio_priv(indio_dev);
340 int ret;
341
342 switch (m) {
343 case IIO_CHAN_INFO_RAW:
344 ret = ti_ads7950_scan_direct(indio_dev, chan->address);
345 if (ret < 0)
346 return ret;
347
348 if (chan->address != TI_ADS7950_EXTRACT(ret, 12, 4))
349 return -EIO;
350
351 *val = TI_ADS7950_EXTRACT(ret, chan->scan_type.shift,
352 chan->scan_type.realbits);
353
354 return IIO_VAL_INT;
355 case IIO_CHAN_INFO_SCALE:
356 ret = ti_ads7950_get_range(st);
357 if (ret < 0)
358 return ret;
359
360 *val = ret;
361 *val2 = (1 << chan->scan_type.realbits) - 1;
362
363 return IIO_VAL_FRACTIONAL;
364 }
365
366 return -EINVAL;
367 }
368
369 static const struct iio_info ti_ads7950_info = {
370 .read_raw = &ti_ads7950_read_raw,
371 .update_scan_mode = ti_ads7950_update_scan_mode,
372 };
373
ti_ads7950_probe(struct spi_device * spi)374 static int ti_ads7950_probe(struct spi_device *spi)
375 {
376 struct ti_ads7950_state *st;
377 struct iio_dev *indio_dev;
378 const struct ti_ads7950_chip_info *info;
379 int ret;
380
381 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
382 if (!indio_dev)
383 return -ENOMEM;
384
385 st = iio_priv(indio_dev);
386
387 spi_set_drvdata(spi, indio_dev);
388
389 st->spi = spi;
390 st->settings = TI_ADS7950_CR_MANUAL | TI_ADS7950_CR_RANGE_5V;
391
392 info = &ti_ads7950_chip_info[spi_get_device_id(spi)->driver_data];
393
394 indio_dev->name = spi_get_device_id(spi)->name;
395 indio_dev->dev.parent = &spi->dev;
396 indio_dev->modes = INDIO_DIRECT_MODE;
397 indio_dev->channels = info->channels;
398 indio_dev->num_channels = info->num_channels;
399 indio_dev->info = &ti_ads7950_info;
400
401 /*
402 * Setup default message. The sample is read at the end of the first
403 * transfer, then it takes one full cycle to convert the sample and one
404 * more cycle to send the value. The conversion process is driven by
405 * the SPI clock, which is why we have 3 transfers. The middle one is
406 * just dummy data sent while the chip is converting the sample that
407 * was read at the end of the first transfer.
408 */
409
410 st->scan_single_xfer[0].tx_buf = &st->single_tx;
411 st->scan_single_xfer[0].len = 2;
412 st->scan_single_xfer[0].cs_change = 1;
413 st->scan_single_xfer[1].tx_buf = &st->single_tx;
414 st->scan_single_xfer[1].len = 2;
415 st->scan_single_xfer[1].cs_change = 1;
416 st->scan_single_xfer[2].rx_buf = &st->single_rx;
417 st->scan_single_xfer[2].len = 2;
418
419 spi_message_init_with_transfers(&st->scan_single_msg,
420 st->scan_single_xfer, 3);
421
422 /* Use hard coded value for reference voltage in ACPI case */
423 if (ACPI_COMPANION(&spi->dev))
424 st->vref_mv = TI_ADS7950_VA_MV_ACPI_DEFAULT;
425
426 st->reg = devm_regulator_get(&spi->dev, "vref");
427 if (IS_ERR(st->reg)) {
428 dev_err(&spi->dev, "Failed get get regulator \"vref\"\n");
429 return PTR_ERR(st->reg);
430 }
431
432 ret = regulator_enable(st->reg);
433 if (ret) {
434 dev_err(&spi->dev, "Failed to enable regulator \"vref\"\n");
435 return ret;
436 }
437
438 ret = iio_triggered_buffer_setup(indio_dev, NULL,
439 &ti_ads7950_trigger_handler, NULL);
440 if (ret) {
441 dev_err(&spi->dev, "Failed to setup triggered buffer\n");
442 goto error_disable_reg;
443 }
444
445 ret = iio_device_register(indio_dev);
446 if (ret) {
447 dev_err(&spi->dev, "Failed to register iio device\n");
448 goto error_cleanup_ring;
449 }
450
451 return 0;
452
453 error_cleanup_ring:
454 iio_triggered_buffer_cleanup(indio_dev);
455 error_disable_reg:
456 regulator_disable(st->reg);
457
458 return ret;
459 }
460
ti_ads7950_remove(struct spi_device * spi)461 static int ti_ads7950_remove(struct spi_device *spi)
462 {
463 struct iio_dev *indio_dev = spi_get_drvdata(spi);
464 struct ti_ads7950_state *st = iio_priv(indio_dev);
465
466 iio_device_unregister(indio_dev);
467 iio_triggered_buffer_cleanup(indio_dev);
468 regulator_disable(st->reg);
469
470 return 0;
471 }
472
473 static const struct spi_device_id ti_ads7950_id[] = {
474 { "ads7950", TI_ADS7950 },
475 { "ads7951", TI_ADS7951 },
476 { "ads7952", TI_ADS7952 },
477 { "ads7953", TI_ADS7953 },
478 { "ads7954", TI_ADS7954 },
479 { "ads7955", TI_ADS7955 },
480 { "ads7956", TI_ADS7956 },
481 { "ads7957", TI_ADS7957 },
482 { "ads7958", TI_ADS7958 },
483 { "ads7959", TI_ADS7959 },
484 { "ads7960", TI_ADS7960 },
485 { "ads7961", TI_ADS7961 },
486 { }
487 };
488 MODULE_DEVICE_TABLE(spi, ti_ads7950_id);
489
490 static const struct of_device_id ads7950_of_table[] = {
491 { .compatible = "ti,ads7950", .data = &ti_ads7950_chip_info[TI_ADS7950] },
492 { .compatible = "ti,ads7951", .data = &ti_ads7950_chip_info[TI_ADS7951] },
493 { .compatible = "ti,ads7952", .data = &ti_ads7950_chip_info[TI_ADS7952] },
494 { .compatible = "ti,ads7953", .data = &ti_ads7950_chip_info[TI_ADS7953] },
495 { .compatible = "ti,ads7954", .data = &ti_ads7950_chip_info[TI_ADS7954] },
496 { .compatible = "ti,ads7955", .data = &ti_ads7950_chip_info[TI_ADS7955] },
497 { .compatible = "ti,ads7956", .data = &ti_ads7950_chip_info[TI_ADS7956] },
498 { .compatible = "ti,ads7957", .data = &ti_ads7950_chip_info[TI_ADS7957] },
499 { .compatible = "ti,ads7958", .data = &ti_ads7950_chip_info[TI_ADS7958] },
500 { .compatible = "ti,ads7959", .data = &ti_ads7950_chip_info[TI_ADS7959] },
501 { .compatible = "ti,ads7960", .data = &ti_ads7950_chip_info[TI_ADS7960] },
502 { .compatible = "ti,ads7961", .data = &ti_ads7950_chip_info[TI_ADS7961] },
503 { },
504 };
505 MODULE_DEVICE_TABLE(of, ads7950_of_table);
506
507 static struct spi_driver ti_ads7950_driver = {
508 .driver = {
509 .name = "ads7950",
510 .of_match_table = ads7950_of_table,
511 },
512 .probe = ti_ads7950_probe,
513 .remove = ti_ads7950_remove,
514 .id_table = ti_ads7950_id,
515 };
516 module_spi_driver(ti_ads7950_driver);
517
518 MODULE_AUTHOR("David Lechner <david@lechnology.com>");
519 MODULE_DESCRIPTION("TI TI_ADS7950 ADC");
520 MODULE_LICENSE("GPL v2");
521
