1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18 #undef DEBUG
19
20 #include <linux/clk.h>
21 #include <linux/console.h>
22 #include <linux/ctype.h>
23 #include <linux/cpufreq.h>
24 #include <linux/delay.h>
25 #include <linux/dmaengine.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/err.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/ioport.h>
32 #include <linux/ktime.h>
33 #include <linux/major.h>
34 #include <linux/module.h>
35 #include <linux/mm.h>
36 #include <linux/of.h>
37 #include <linux/of_device.h>
38 #include <linux/platform_device.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/reset.h>
41 #include <linux/scatterlist.h>
42 #include <linux/serial.h>
43 #include <linux/serial_sci.h>
44 #include <linux/sh_dma.h>
45 #include <linux/slab.h>
46 #include <linux/string.h>
47 #include <linux/sysrq.h>
48 #include <linux/timer.h>
49 #include <linux/tty.h>
50 #include <linux/tty_flip.h>
51
52 #ifdef CONFIG_SUPERH
53 #include <asm/sh_bios.h>
54 #include <asm/platform_early.h>
55 #endif
56
57 #include "serial_mctrl_gpio.h"
58 #include "sh-sci.h"
59
60 /* Offsets into the sci_port->irqs array */
61 enum {
62 SCIx_ERI_IRQ,
63 SCIx_RXI_IRQ,
64 SCIx_TXI_IRQ,
65 SCIx_BRI_IRQ,
66 SCIx_DRI_IRQ,
67 SCIx_TEI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71 };
72
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
79 enum SCI_CLKS {
80 SCI_FCK, /* Functional Clock */
81 SCI_SCK, /* Optional External Clock */
82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
84 SCI_NUM_CLKS
85 };
86
87 /* Bit x set means sampling rate x + 1 is supported */
88 #define SCI_SR(x) BIT((x) - 1)
89 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
90
91 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
93 SCI_SR(19) | SCI_SR(27)
94
95 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
96 #define max_sr(_port) fls((_port)->sampling_rate_mask)
97
98 /* Iterate over all supported sampling rates, from high to low */
99 #define for_each_sr(_sr, _port) \
100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
101 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
102
103 struct plat_sci_reg {
104 u8 offset, size;
105 };
106
107 struct sci_port_params {
108 const struct plat_sci_reg regs[SCIx_NR_REGS];
109 unsigned int fifosize;
110 unsigned int overrun_reg;
111 unsigned int overrun_mask;
112 unsigned int sampling_rate_mask;
113 unsigned int error_mask;
114 unsigned int error_clear;
115 };
116
117 struct sci_port {
118 struct uart_port port;
119
120 /* Platform configuration */
121 const struct sci_port_params *params;
122 const struct plat_sci_port *cfg;
123 unsigned int sampling_rate_mask;
124 resource_size_t reg_size;
125 struct mctrl_gpios *gpios;
126
127 /* Clocks */
128 struct clk *clks[SCI_NUM_CLKS];
129 unsigned long clk_rates[SCI_NUM_CLKS];
130
131 int irqs[SCIx_NR_IRQS];
132 char *irqstr[SCIx_NR_IRQS];
133
134 struct dma_chan *chan_tx;
135 struct dma_chan *chan_rx;
136
137 #ifdef CONFIG_SERIAL_SH_SCI_DMA
138 struct dma_chan *chan_tx_saved;
139 struct dma_chan *chan_rx_saved;
140 dma_cookie_t cookie_tx;
141 dma_cookie_t cookie_rx[2];
142 dma_cookie_t active_rx;
143 dma_addr_t tx_dma_addr;
144 unsigned int tx_dma_len;
145 struct scatterlist sg_rx[2];
146 void *rx_buf[2];
147 size_t buf_len_rx;
148 struct work_struct work_tx;
149 struct hrtimer rx_timer;
150 unsigned int rx_timeout; /* microseconds */
151 #endif
152 unsigned int rx_frame;
153 int rx_trigger;
154 struct timer_list rx_fifo_timer;
155 int rx_fifo_timeout;
156 u16 hscif_tot;
157
158 bool has_rtscts;
159 bool autorts;
160 };
161
162 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
163
164 static struct sci_port sci_ports[SCI_NPORTS];
165 static unsigned long sci_ports_in_use;
166 static struct uart_driver sci_uart_driver;
167
168 static inline struct sci_port *
to_sci_port(struct uart_port * uart)169 to_sci_port(struct uart_port *uart)
170 {
171 return container_of(uart, struct sci_port, port);
172 }
173
174 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
175 /*
176 * Common SCI definitions, dependent on the port's regshift
177 * value.
178 */
179 [SCIx_SCI_REGTYPE] = {
180 .regs = {
181 [SCSMR] = { 0x00, 8 },
182 [SCBRR] = { 0x01, 8 },
183 [SCSCR] = { 0x02, 8 },
184 [SCxTDR] = { 0x03, 8 },
185 [SCxSR] = { 0x04, 8 },
186 [SCxRDR] = { 0x05, 8 },
187 },
188 .fifosize = 1,
189 .overrun_reg = SCxSR,
190 .overrun_mask = SCI_ORER,
191 .sampling_rate_mask = SCI_SR(32),
192 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
193 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
194 },
195
196 /*
197 * Common definitions for legacy IrDA ports.
198 */
199 [SCIx_IRDA_REGTYPE] = {
200 .regs = {
201 [SCSMR] = { 0x00, 8 },
202 [SCBRR] = { 0x02, 8 },
203 [SCSCR] = { 0x04, 8 },
204 [SCxTDR] = { 0x06, 8 },
205 [SCxSR] = { 0x08, 16 },
206 [SCxRDR] = { 0x0a, 8 },
207 [SCFCR] = { 0x0c, 8 },
208 [SCFDR] = { 0x0e, 16 },
209 },
210 .fifosize = 1,
211 .overrun_reg = SCxSR,
212 .overrun_mask = SCI_ORER,
213 .sampling_rate_mask = SCI_SR(32),
214 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
215 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
216 },
217
218 /*
219 * Common SCIFA definitions.
220 */
221 [SCIx_SCIFA_REGTYPE] = {
222 .regs = {
223 [SCSMR] = { 0x00, 16 },
224 [SCBRR] = { 0x04, 8 },
225 [SCSCR] = { 0x08, 16 },
226 [SCxTDR] = { 0x20, 8 },
227 [SCxSR] = { 0x14, 16 },
228 [SCxRDR] = { 0x24, 8 },
229 [SCFCR] = { 0x18, 16 },
230 [SCFDR] = { 0x1c, 16 },
231 [SCPCR] = { 0x30, 16 },
232 [SCPDR] = { 0x34, 16 },
233 },
234 .fifosize = 64,
235 .overrun_reg = SCxSR,
236 .overrun_mask = SCIFA_ORER,
237 .sampling_rate_mask = SCI_SR_SCIFAB,
238 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
239 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
240 },
241
242 /*
243 * Common SCIFB definitions.
244 */
245 [SCIx_SCIFB_REGTYPE] = {
246 .regs = {
247 [SCSMR] = { 0x00, 16 },
248 [SCBRR] = { 0x04, 8 },
249 [SCSCR] = { 0x08, 16 },
250 [SCxTDR] = { 0x40, 8 },
251 [SCxSR] = { 0x14, 16 },
252 [SCxRDR] = { 0x60, 8 },
253 [SCFCR] = { 0x18, 16 },
254 [SCTFDR] = { 0x38, 16 },
255 [SCRFDR] = { 0x3c, 16 },
256 [SCPCR] = { 0x30, 16 },
257 [SCPDR] = { 0x34, 16 },
258 },
259 .fifosize = 256,
260 .overrun_reg = SCxSR,
261 .overrun_mask = SCIFA_ORER,
262 .sampling_rate_mask = SCI_SR_SCIFAB,
263 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
264 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
265 },
266
267 /*
268 * Common SH-2(A) SCIF definitions for ports with FIFO data
269 * count registers.
270 */
271 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
272 .regs = {
273 [SCSMR] = { 0x00, 16 },
274 [SCBRR] = { 0x04, 8 },
275 [SCSCR] = { 0x08, 16 },
276 [SCxTDR] = { 0x0c, 8 },
277 [SCxSR] = { 0x10, 16 },
278 [SCxRDR] = { 0x14, 8 },
279 [SCFCR] = { 0x18, 16 },
280 [SCFDR] = { 0x1c, 16 },
281 [SCSPTR] = { 0x20, 16 },
282 [SCLSR] = { 0x24, 16 },
283 },
284 .fifosize = 16,
285 .overrun_reg = SCLSR,
286 .overrun_mask = SCLSR_ORER,
287 .sampling_rate_mask = SCI_SR(32),
288 .error_mask = SCIF_DEFAULT_ERROR_MASK,
289 .error_clear = SCIF_ERROR_CLEAR,
290 },
291
292 /*
293 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
294 * It looks like a normal SCIF with FIFO data, but with a
295 * compressed address space. Also, the break out of interrupts
296 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
297 */
298 [SCIx_RZ_SCIFA_REGTYPE] = {
299 .regs = {
300 [SCSMR] = { 0x00, 16 },
301 [SCBRR] = { 0x02, 8 },
302 [SCSCR] = { 0x04, 16 },
303 [SCxTDR] = { 0x06, 8 },
304 [SCxSR] = { 0x08, 16 },
305 [SCxRDR] = { 0x0A, 8 },
306 [SCFCR] = { 0x0C, 16 },
307 [SCFDR] = { 0x0E, 16 },
308 [SCSPTR] = { 0x10, 16 },
309 [SCLSR] = { 0x12, 16 },
310 [SEMR] = { 0x14, 8 },
311 },
312 .fifosize = 16,
313 .overrun_reg = SCLSR,
314 .overrun_mask = SCLSR_ORER,
315 .sampling_rate_mask = SCI_SR(32),
316 .error_mask = SCIF_DEFAULT_ERROR_MASK,
317 .error_clear = SCIF_ERROR_CLEAR,
318 },
319
320 /*
321 * Common SH-3 SCIF definitions.
322 */
323 [SCIx_SH3_SCIF_REGTYPE] = {
324 .regs = {
325 [SCSMR] = { 0x00, 8 },
326 [SCBRR] = { 0x02, 8 },
327 [SCSCR] = { 0x04, 8 },
328 [SCxTDR] = { 0x06, 8 },
329 [SCxSR] = { 0x08, 16 },
330 [SCxRDR] = { 0x0a, 8 },
331 [SCFCR] = { 0x0c, 8 },
332 [SCFDR] = { 0x0e, 16 },
333 },
334 .fifosize = 16,
335 .overrun_reg = SCLSR,
336 .overrun_mask = SCLSR_ORER,
337 .sampling_rate_mask = SCI_SR(32),
338 .error_mask = SCIF_DEFAULT_ERROR_MASK,
339 .error_clear = SCIF_ERROR_CLEAR,
340 },
341
342 /*
343 * Common SH-4(A) SCIF(B) definitions.
344 */
345 [SCIx_SH4_SCIF_REGTYPE] = {
346 .regs = {
347 [SCSMR] = { 0x00, 16 },
348 [SCBRR] = { 0x04, 8 },
349 [SCSCR] = { 0x08, 16 },
350 [SCxTDR] = { 0x0c, 8 },
351 [SCxSR] = { 0x10, 16 },
352 [SCxRDR] = { 0x14, 8 },
353 [SCFCR] = { 0x18, 16 },
354 [SCFDR] = { 0x1c, 16 },
355 [SCSPTR] = { 0x20, 16 },
356 [SCLSR] = { 0x24, 16 },
357 },
358 .fifosize = 16,
359 .overrun_reg = SCLSR,
360 .overrun_mask = SCLSR_ORER,
361 .sampling_rate_mask = SCI_SR(32),
362 .error_mask = SCIF_DEFAULT_ERROR_MASK,
363 .error_clear = SCIF_ERROR_CLEAR,
364 },
365
366 /*
367 * Common SCIF definitions for ports with a Baud Rate Generator for
368 * External Clock (BRG).
369 */
370 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
371 .regs = {
372 [SCSMR] = { 0x00, 16 },
373 [SCBRR] = { 0x04, 8 },
374 [SCSCR] = { 0x08, 16 },
375 [SCxTDR] = { 0x0c, 8 },
376 [SCxSR] = { 0x10, 16 },
377 [SCxRDR] = { 0x14, 8 },
378 [SCFCR] = { 0x18, 16 },
379 [SCFDR] = { 0x1c, 16 },
380 [SCSPTR] = { 0x20, 16 },
381 [SCLSR] = { 0x24, 16 },
382 [SCDL] = { 0x30, 16 },
383 [SCCKS] = { 0x34, 16 },
384 },
385 .fifosize = 16,
386 .overrun_reg = SCLSR,
387 .overrun_mask = SCLSR_ORER,
388 .sampling_rate_mask = SCI_SR(32),
389 .error_mask = SCIF_DEFAULT_ERROR_MASK,
390 .error_clear = SCIF_ERROR_CLEAR,
391 },
392
393 /*
394 * Common HSCIF definitions.
395 */
396 [SCIx_HSCIF_REGTYPE] = {
397 .regs = {
398 [SCSMR] = { 0x00, 16 },
399 [SCBRR] = { 0x04, 8 },
400 [SCSCR] = { 0x08, 16 },
401 [SCxTDR] = { 0x0c, 8 },
402 [SCxSR] = { 0x10, 16 },
403 [SCxRDR] = { 0x14, 8 },
404 [SCFCR] = { 0x18, 16 },
405 [SCFDR] = { 0x1c, 16 },
406 [SCSPTR] = { 0x20, 16 },
407 [SCLSR] = { 0x24, 16 },
408 [HSSRR] = { 0x40, 16 },
409 [SCDL] = { 0x30, 16 },
410 [SCCKS] = { 0x34, 16 },
411 [HSRTRGR] = { 0x54, 16 },
412 [HSTTRGR] = { 0x58, 16 },
413 },
414 .fifosize = 128,
415 .overrun_reg = SCLSR,
416 .overrun_mask = SCLSR_ORER,
417 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
418 .error_mask = SCIF_DEFAULT_ERROR_MASK,
419 .error_clear = SCIF_ERROR_CLEAR,
420 },
421
422 /*
423 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
424 * register.
425 */
426 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
427 .regs = {
428 [SCSMR] = { 0x00, 16 },
429 [SCBRR] = { 0x04, 8 },
430 [SCSCR] = { 0x08, 16 },
431 [SCxTDR] = { 0x0c, 8 },
432 [SCxSR] = { 0x10, 16 },
433 [SCxRDR] = { 0x14, 8 },
434 [SCFCR] = { 0x18, 16 },
435 [SCFDR] = { 0x1c, 16 },
436 [SCLSR] = { 0x24, 16 },
437 },
438 .fifosize = 16,
439 .overrun_reg = SCLSR,
440 .overrun_mask = SCLSR_ORER,
441 .sampling_rate_mask = SCI_SR(32),
442 .error_mask = SCIF_DEFAULT_ERROR_MASK,
443 .error_clear = SCIF_ERROR_CLEAR,
444 },
445
446 /*
447 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
448 * count registers.
449 */
450 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
451 .regs = {
452 [SCSMR] = { 0x00, 16 },
453 [SCBRR] = { 0x04, 8 },
454 [SCSCR] = { 0x08, 16 },
455 [SCxTDR] = { 0x0c, 8 },
456 [SCxSR] = { 0x10, 16 },
457 [SCxRDR] = { 0x14, 8 },
458 [SCFCR] = { 0x18, 16 },
459 [SCFDR] = { 0x1c, 16 },
460 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
461 [SCRFDR] = { 0x20, 16 },
462 [SCSPTR] = { 0x24, 16 },
463 [SCLSR] = { 0x28, 16 },
464 },
465 .fifosize = 16,
466 .overrun_reg = SCLSR,
467 .overrun_mask = SCLSR_ORER,
468 .sampling_rate_mask = SCI_SR(32),
469 .error_mask = SCIF_DEFAULT_ERROR_MASK,
470 .error_clear = SCIF_ERROR_CLEAR,
471 },
472
473 /*
474 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
475 * registers.
476 */
477 [SCIx_SH7705_SCIF_REGTYPE] = {
478 .regs = {
479 [SCSMR] = { 0x00, 16 },
480 [SCBRR] = { 0x04, 8 },
481 [SCSCR] = { 0x08, 16 },
482 [SCxTDR] = { 0x20, 8 },
483 [SCxSR] = { 0x14, 16 },
484 [SCxRDR] = { 0x24, 8 },
485 [SCFCR] = { 0x18, 16 },
486 [SCFDR] = { 0x1c, 16 },
487 },
488 .fifosize = 64,
489 .overrun_reg = SCxSR,
490 .overrun_mask = SCIFA_ORER,
491 .sampling_rate_mask = SCI_SR(16),
492 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
493 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
494 },
495 };
496
497 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
498
499 /*
500 * The "offset" here is rather misleading, in that it refers to an enum
501 * value relative to the port mapping rather than the fixed offset
502 * itself, which needs to be manually retrieved from the platform's
503 * register map for the given port.
504 */
sci_serial_in(struct uart_port * p,int offset)505 static unsigned int sci_serial_in(struct uart_port *p, int offset)
506 {
507 const struct plat_sci_reg *reg = sci_getreg(p, offset);
508
509 if (reg->size == 8)
510 return ioread8(p->membase + (reg->offset << p->regshift));
511 else if (reg->size == 16)
512 return ioread16(p->membase + (reg->offset << p->regshift));
513 else
514 WARN(1, "Invalid register access\n");
515
516 return 0;
517 }
518
sci_serial_out(struct uart_port * p,int offset,int value)519 static void sci_serial_out(struct uart_port *p, int offset, int value)
520 {
521 const struct plat_sci_reg *reg = sci_getreg(p, offset);
522
523 if (reg->size == 8)
524 iowrite8(value, p->membase + (reg->offset << p->regshift));
525 else if (reg->size == 16)
526 iowrite16(value, p->membase + (reg->offset << p->regshift));
527 else
528 WARN(1, "Invalid register access\n");
529 }
530
sci_port_enable(struct sci_port * sci_port)531 static void sci_port_enable(struct sci_port *sci_port)
532 {
533 unsigned int i;
534
535 if (!sci_port->port.dev)
536 return;
537
538 pm_runtime_get_sync(sci_port->port.dev);
539
540 for (i = 0; i < SCI_NUM_CLKS; i++) {
541 clk_prepare_enable(sci_port->clks[i]);
542 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
543 }
544 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
545 }
546
sci_port_disable(struct sci_port * sci_port)547 static void sci_port_disable(struct sci_port *sci_port)
548 {
549 unsigned int i;
550
551 if (!sci_port->port.dev)
552 return;
553
554 for (i = SCI_NUM_CLKS; i-- > 0; )
555 clk_disable_unprepare(sci_port->clks[i]);
556
557 pm_runtime_put_sync(sci_port->port.dev);
558 }
559
port_rx_irq_mask(struct uart_port * port)560 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
561 {
562 /*
563 * Not all ports (such as SCIFA) will support REIE. Rather than
564 * special-casing the port type, we check the port initialization
565 * IRQ enable mask to see whether the IRQ is desired at all. If
566 * it's unset, it's logically inferred that there's no point in
567 * testing for it.
568 */
569 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
570 }
571
sci_start_tx(struct uart_port * port)572 static void sci_start_tx(struct uart_port *port)
573 {
574 struct sci_port *s = to_sci_port(port);
575 unsigned short ctrl;
576
577 #ifdef CONFIG_SERIAL_SH_SCI_DMA
578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
579 u16 new, scr = serial_port_in(port, SCSCR);
580 if (s->chan_tx)
581 new = scr | SCSCR_TDRQE;
582 else
583 new = scr & ~SCSCR_TDRQE;
584 if (new != scr)
585 serial_port_out(port, SCSCR, new);
586 }
587
588 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
589 dma_submit_error(s->cookie_tx)) {
590 s->cookie_tx = 0;
591 schedule_work(&s->work_tx);
592 }
593 #endif
594
595 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
596 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
597 ctrl = serial_port_in(port, SCSCR);
598 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
599 }
600 }
601
sci_stop_tx(struct uart_port * port)602 static void sci_stop_tx(struct uart_port *port)
603 {
604 unsigned short ctrl;
605
606 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
607 ctrl = serial_port_in(port, SCSCR);
608
609 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
610 ctrl &= ~SCSCR_TDRQE;
611
612 ctrl &= ~SCSCR_TIE;
613
614 serial_port_out(port, SCSCR, ctrl);
615
616 #ifdef CONFIG_SERIAL_SH_SCI_DMA
617 if (to_sci_port(port)->chan_tx &&
618 !dma_submit_error(to_sci_port(port)->cookie_tx)) {
619 dmaengine_terminate_async(to_sci_port(port)->chan_tx);
620 to_sci_port(port)->cookie_tx = -EINVAL;
621 }
622 #endif
623 }
624
sci_start_rx(struct uart_port * port)625 static void sci_start_rx(struct uart_port *port)
626 {
627 unsigned short ctrl;
628
629 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
630
631 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
632 ctrl &= ~SCSCR_RDRQE;
633
634 serial_port_out(port, SCSCR, ctrl);
635 }
636
sci_stop_rx(struct uart_port * port)637 static void sci_stop_rx(struct uart_port *port)
638 {
639 unsigned short ctrl;
640
641 ctrl = serial_port_in(port, SCSCR);
642
643 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
644 ctrl &= ~SCSCR_RDRQE;
645
646 ctrl &= ~port_rx_irq_mask(port);
647
648 serial_port_out(port, SCSCR, ctrl);
649 }
650
sci_clear_SCxSR(struct uart_port * port,unsigned int mask)651 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
652 {
653 if (port->type == PORT_SCI) {
654 /* Just store the mask */
655 serial_port_out(port, SCxSR, mask);
656 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
657 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
658 /* Only clear the status bits we want to clear */
659 serial_port_out(port, SCxSR,
660 serial_port_in(port, SCxSR) & mask);
661 } else {
662 /* Store the mask, clear parity/framing errors */
663 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
664 }
665 }
666
667 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
668 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
669
670 #ifdef CONFIG_CONSOLE_POLL
sci_poll_get_char(struct uart_port * port)671 static int sci_poll_get_char(struct uart_port *port)
672 {
673 unsigned short status;
674 int c;
675
676 do {
677 status = serial_port_in(port, SCxSR);
678 if (status & SCxSR_ERRORS(port)) {
679 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
680 continue;
681 }
682 break;
683 } while (1);
684
685 if (!(status & SCxSR_RDxF(port)))
686 return NO_POLL_CHAR;
687
688 c = serial_port_in(port, SCxRDR);
689
690 /* Dummy read */
691 serial_port_in(port, SCxSR);
692 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
693
694 return c;
695 }
696 #endif
697
sci_poll_put_char(struct uart_port * port,unsigned char c)698 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
699 {
700 unsigned short status;
701
702 do {
703 status = serial_port_in(port, SCxSR);
704 } while (!(status & SCxSR_TDxE(port)));
705
706 serial_port_out(port, SCxTDR, c);
707 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
708 }
709 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
710 CONFIG_SERIAL_SH_SCI_EARLYCON */
711
sci_init_pins(struct uart_port * port,unsigned int cflag)712 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
713 {
714 struct sci_port *s = to_sci_port(port);
715
716 /*
717 * Use port-specific handler if provided.
718 */
719 if (s->cfg->ops && s->cfg->ops->init_pins) {
720 s->cfg->ops->init_pins(port, cflag);
721 return;
722 }
723
724 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
725 u16 data = serial_port_in(port, SCPDR);
726 u16 ctrl = serial_port_in(port, SCPCR);
727
728 /* Enable RXD and TXD pin functions */
729 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
730 if (to_sci_port(port)->has_rtscts) {
731 /* RTS# is output, active low, unless autorts */
732 if (!(port->mctrl & TIOCM_RTS)) {
733 ctrl |= SCPCR_RTSC;
734 data |= SCPDR_RTSD;
735 } else if (!s->autorts) {
736 ctrl |= SCPCR_RTSC;
737 data &= ~SCPDR_RTSD;
738 } else {
739 /* Enable RTS# pin function */
740 ctrl &= ~SCPCR_RTSC;
741 }
742 /* Enable CTS# pin function */
743 ctrl &= ~SCPCR_CTSC;
744 }
745 serial_port_out(port, SCPDR, data);
746 serial_port_out(port, SCPCR, ctrl);
747 } else if (sci_getreg(port, SCSPTR)->size) {
748 u16 status = serial_port_in(port, SCSPTR);
749
750 /* RTS# is always output; and active low, unless autorts */
751 status |= SCSPTR_RTSIO;
752 if (!(port->mctrl & TIOCM_RTS))
753 status |= SCSPTR_RTSDT;
754 else if (!s->autorts)
755 status &= ~SCSPTR_RTSDT;
756 /* CTS# and SCK are inputs */
757 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
758 serial_port_out(port, SCSPTR, status);
759 }
760 }
761
sci_txfill(struct uart_port * port)762 static int sci_txfill(struct uart_port *port)
763 {
764 struct sci_port *s = to_sci_port(port);
765 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
766 const struct plat_sci_reg *reg;
767
768 reg = sci_getreg(port, SCTFDR);
769 if (reg->size)
770 return serial_port_in(port, SCTFDR) & fifo_mask;
771
772 reg = sci_getreg(port, SCFDR);
773 if (reg->size)
774 return serial_port_in(port, SCFDR) >> 8;
775
776 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
777 }
778
sci_txroom(struct uart_port * port)779 static int sci_txroom(struct uart_port *port)
780 {
781 return port->fifosize - sci_txfill(port);
782 }
783
sci_rxfill(struct uart_port * port)784 static int sci_rxfill(struct uart_port *port)
785 {
786 struct sci_port *s = to_sci_port(port);
787 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
788 const struct plat_sci_reg *reg;
789
790 reg = sci_getreg(port, SCRFDR);
791 if (reg->size)
792 return serial_port_in(port, SCRFDR) & fifo_mask;
793
794 reg = sci_getreg(port, SCFDR);
795 if (reg->size)
796 return serial_port_in(port, SCFDR) & fifo_mask;
797
798 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
799 }
800
801 /* ********************************************************************** *
802 * the interrupt related routines *
803 * ********************************************************************** */
804
sci_transmit_chars(struct uart_port * port)805 static void sci_transmit_chars(struct uart_port *port)
806 {
807 struct circ_buf *xmit = &port->state->xmit;
808 unsigned int stopped = uart_tx_stopped(port);
809 unsigned short status;
810 unsigned short ctrl;
811 int count;
812
813 status = serial_port_in(port, SCxSR);
814 if (!(status & SCxSR_TDxE(port))) {
815 ctrl = serial_port_in(port, SCSCR);
816 if (uart_circ_empty(xmit))
817 ctrl &= ~SCSCR_TIE;
818 else
819 ctrl |= SCSCR_TIE;
820 serial_port_out(port, SCSCR, ctrl);
821 return;
822 }
823
824 count = sci_txroom(port);
825
826 do {
827 unsigned char c;
828
829 if (port->x_char) {
830 c = port->x_char;
831 port->x_char = 0;
832 } else if (!uart_circ_empty(xmit) && !stopped) {
833 c = xmit->buf[xmit->tail];
834 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
835 } else {
836 break;
837 }
838
839 serial_port_out(port, SCxTDR, c);
840
841 port->icount.tx++;
842 } while (--count > 0);
843
844 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
845
846 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
847 uart_write_wakeup(port);
848 if (uart_circ_empty(xmit))
849 sci_stop_tx(port);
850
851 }
852
sci_receive_chars(struct uart_port * port)853 static void sci_receive_chars(struct uart_port *port)
854 {
855 struct tty_port *tport = &port->state->port;
856 int i, count, copied = 0;
857 unsigned short status;
858 unsigned char flag;
859
860 status = serial_port_in(port, SCxSR);
861 if (!(status & SCxSR_RDxF(port)))
862 return;
863
864 while (1) {
865 /* Don't copy more bytes than there is room for in the buffer */
866 count = tty_buffer_request_room(tport, sci_rxfill(port));
867
868 /* If for any reason we can't copy more data, we're done! */
869 if (count == 0)
870 break;
871
872 if (port->type == PORT_SCI) {
873 char c = serial_port_in(port, SCxRDR);
874 if (uart_handle_sysrq_char(port, c))
875 count = 0;
876 else
877 tty_insert_flip_char(tport, c, TTY_NORMAL);
878 } else {
879 for (i = 0; i < count; i++) {
880 char c;
881
882 if (port->type == PORT_SCIF ||
883 port->type == PORT_HSCIF) {
884 status = serial_port_in(port, SCxSR);
885 c = serial_port_in(port, SCxRDR);
886 } else {
887 c = serial_port_in(port, SCxRDR);
888 status = serial_port_in(port, SCxSR);
889 }
890 if (uart_handle_sysrq_char(port, c)) {
891 count--; i--;
892 continue;
893 }
894
895 /* Store data and status */
896 if (status & SCxSR_FER(port)) {
897 flag = TTY_FRAME;
898 port->icount.frame++;
899 } else if (status & SCxSR_PER(port)) {
900 flag = TTY_PARITY;
901 port->icount.parity++;
902 } else
903 flag = TTY_NORMAL;
904
905 tty_insert_flip_char(tport, c, flag);
906 }
907 }
908
909 serial_port_in(port, SCxSR); /* dummy read */
910 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
911
912 copied += count;
913 port->icount.rx += count;
914 }
915
916 if (copied) {
917 /* Tell the rest of the system the news. New characters! */
918 tty_flip_buffer_push(tport);
919 } else {
920 /* TTY buffers full; read from RX reg to prevent lockup */
921 serial_port_in(port, SCxRDR);
922 serial_port_in(port, SCxSR); /* dummy read */
923 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
924 }
925 }
926
sci_handle_errors(struct uart_port * port)927 static int sci_handle_errors(struct uart_port *port)
928 {
929 int copied = 0;
930 unsigned short status = serial_port_in(port, SCxSR);
931 struct tty_port *tport = &port->state->port;
932 struct sci_port *s = to_sci_port(port);
933
934 /* Handle overruns */
935 if (status & s->params->overrun_mask) {
936 port->icount.overrun++;
937
938 /* overrun error */
939 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
940 copied++;
941 }
942
943 if (status & SCxSR_FER(port)) {
944 /* frame error */
945 port->icount.frame++;
946
947 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
948 copied++;
949 }
950
951 if (status & SCxSR_PER(port)) {
952 /* parity error */
953 port->icount.parity++;
954
955 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
956 copied++;
957 }
958
959 if (copied)
960 tty_flip_buffer_push(tport);
961
962 return copied;
963 }
964
sci_handle_fifo_overrun(struct uart_port * port)965 static int sci_handle_fifo_overrun(struct uart_port *port)
966 {
967 struct tty_port *tport = &port->state->port;
968 struct sci_port *s = to_sci_port(port);
969 const struct plat_sci_reg *reg;
970 int copied = 0;
971 u16 status;
972
973 reg = sci_getreg(port, s->params->overrun_reg);
974 if (!reg->size)
975 return 0;
976
977 status = serial_port_in(port, s->params->overrun_reg);
978 if (status & s->params->overrun_mask) {
979 status &= ~s->params->overrun_mask;
980 serial_port_out(port, s->params->overrun_reg, status);
981
982 port->icount.overrun++;
983
984 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
985 tty_flip_buffer_push(tport);
986 copied++;
987 }
988
989 return copied;
990 }
991
sci_handle_breaks(struct uart_port * port)992 static int sci_handle_breaks(struct uart_port *port)
993 {
994 int copied = 0;
995 unsigned short status = serial_port_in(port, SCxSR);
996 struct tty_port *tport = &port->state->port;
997
998 if (uart_handle_break(port))
999 return 0;
1000
1001 if (status & SCxSR_BRK(port)) {
1002 port->icount.brk++;
1003
1004 /* Notify of BREAK */
1005 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1006 copied++;
1007 }
1008
1009 if (copied)
1010 tty_flip_buffer_push(tport);
1011
1012 copied += sci_handle_fifo_overrun(port);
1013
1014 return copied;
1015 }
1016
scif_set_rtrg(struct uart_port * port,int rx_trig)1017 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1018 {
1019 unsigned int bits;
1020
1021 if (rx_trig >= port->fifosize)
1022 rx_trig = port->fifosize - 1;
1023 if (rx_trig < 1)
1024 rx_trig = 1;
1025
1026 /* HSCIF can be set to an arbitrary level. */
1027 if (sci_getreg(port, HSRTRGR)->size) {
1028 serial_port_out(port, HSRTRGR, rx_trig);
1029 return rx_trig;
1030 }
1031
1032 switch (port->type) {
1033 case PORT_SCIF:
1034 if (rx_trig < 4) {
1035 bits = 0;
1036 rx_trig = 1;
1037 } else if (rx_trig < 8) {
1038 bits = SCFCR_RTRG0;
1039 rx_trig = 4;
1040 } else if (rx_trig < 14) {
1041 bits = SCFCR_RTRG1;
1042 rx_trig = 8;
1043 } else {
1044 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1045 rx_trig = 14;
1046 }
1047 break;
1048 case PORT_SCIFA:
1049 case PORT_SCIFB:
1050 if (rx_trig < 16) {
1051 bits = 0;
1052 rx_trig = 1;
1053 } else if (rx_trig < 32) {
1054 bits = SCFCR_RTRG0;
1055 rx_trig = 16;
1056 } else if (rx_trig < 48) {
1057 bits = SCFCR_RTRG1;
1058 rx_trig = 32;
1059 } else {
1060 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1061 rx_trig = 48;
1062 }
1063 break;
1064 default:
1065 WARN(1, "unknown FIFO configuration");
1066 return 1;
1067 }
1068
1069 serial_port_out(port, SCFCR,
1070 (serial_port_in(port, SCFCR) &
1071 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1072
1073 return rx_trig;
1074 }
1075
scif_rtrg_enabled(struct uart_port * port)1076 static int scif_rtrg_enabled(struct uart_port *port)
1077 {
1078 if (sci_getreg(port, HSRTRGR)->size)
1079 return serial_port_in(port, HSRTRGR) != 0;
1080 else
1081 return (serial_port_in(port, SCFCR) &
1082 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1083 }
1084
rx_fifo_timer_fn(struct timer_list * t)1085 static void rx_fifo_timer_fn(struct timer_list *t)
1086 {
1087 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1088 struct uart_port *port = &s->port;
1089
1090 dev_dbg(port->dev, "Rx timed out\n");
1091 scif_set_rtrg(port, 1);
1092 }
1093
rx_fifo_trigger_show(struct device * dev,struct device_attribute * attr,char * buf)1094 static ssize_t rx_fifo_trigger_show(struct device *dev,
1095 struct device_attribute *attr, char *buf)
1096 {
1097 struct uart_port *port = dev_get_drvdata(dev);
1098 struct sci_port *sci = to_sci_port(port);
1099
1100 return sprintf(buf, "%d\n", sci->rx_trigger);
1101 }
1102
rx_fifo_trigger_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1103 static ssize_t rx_fifo_trigger_store(struct device *dev,
1104 struct device_attribute *attr,
1105 const char *buf, size_t count)
1106 {
1107 struct uart_port *port = dev_get_drvdata(dev);
1108 struct sci_port *sci = to_sci_port(port);
1109 int ret;
1110 long r;
1111
1112 ret = kstrtol(buf, 0, &r);
1113 if (ret)
1114 return ret;
1115
1116 sci->rx_trigger = scif_set_rtrg(port, r);
1117 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1118 scif_set_rtrg(port, 1);
1119
1120 return count;
1121 }
1122
1123 static DEVICE_ATTR_RW(rx_fifo_trigger);
1124
rx_fifo_timeout_show(struct device * dev,struct device_attribute * attr,char * buf)1125 static ssize_t rx_fifo_timeout_show(struct device *dev,
1126 struct device_attribute *attr,
1127 char *buf)
1128 {
1129 struct uart_port *port = dev_get_drvdata(dev);
1130 struct sci_port *sci = to_sci_port(port);
1131 int v;
1132
1133 if (port->type == PORT_HSCIF)
1134 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1135 else
1136 v = sci->rx_fifo_timeout;
1137
1138 return sprintf(buf, "%d\n", v);
1139 }
1140
rx_fifo_timeout_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1141 static ssize_t rx_fifo_timeout_store(struct device *dev,
1142 struct device_attribute *attr,
1143 const char *buf,
1144 size_t count)
1145 {
1146 struct uart_port *port = dev_get_drvdata(dev);
1147 struct sci_port *sci = to_sci_port(port);
1148 int ret;
1149 long r;
1150
1151 ret = kstrtol(buf, 0, &r);
1152 if (ret)
1153 return ret;
1154
1155 if (port->type == PORT_HSCIF) {
1156 if (r < 0 || r > 3)
1157 return -EINVAL;
1158 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1159 } else {
1160 sci->rx_fifo_timeout = r;
1161 scif_set_rtrg(port, 1);
1162 if (r > 0)
1163 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1164 }
1165
1166 return count;
1167 }
1168
1169 static DEVICE_ATTR_RW(rx_fifo_timeout);
1170
1171
1172 #ifdef CONFIG_SERIAL_SH_SCI_DMA
sci_dma_tx_complete(void * arg)1173 static void sci_dma_tx_complete(void *arg)
1174 {
1175 struct sci_port *s = arg;
1176 struct uart_port *port = &s->port;
1177 struct circ_buf *xmit = &port->state->xmit;
1178 unsigned long flags;
1179
1180 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1181
1182 spin_lock_irqsave(&port->lock, flags);
1183
1184 xmit->tail += s->tx_dma_len;
1185 xmit->tail &= UART_XMIT_SIZE - 1;
1186
1187 port->icount.tx += s->tx_dma_len;
1188
1189 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1190 uart_write_wakeup(port);
1191
1192 if (!uart_circ_empty(xmit)) {
1193 s->cookie_tx = 0;
1194 schedule_work(&s->work_tx);
1195 } else {
1196 s->cookie_tx = -EINVAL;
1197 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1198 u16 ctrl = serial_port_in(port, SCSCR);
1199 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1200 }
1201 }
1202
1203 spin_unlock_irqrestore(&port->lock, flags);
1204 }
1205
1206 /* Locking: called with port lock held */
sci_dma_rx_push(struct sci_port * s,void * buf,size_t count)1207 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1208 {
1209 struct uart_port *port = &s->port;
1210 struct tty_port *tport = &port->state->port;
1211 int copied;
1212
1213 copied = tty_insert_flip_string(tport, buf, count);
1214 if (copied < count)
1215 port->icount.buf_overrun++;
1216
1217 port->icount.rx += copied;
1218
1219 return copied;
1220 }
1221
sci_dma_rx_find_active(struct sci_port * s)1222 static int sci_dma_rx_find_active(struct sci_port *s)
1223 {
1224 unsigned int i;
1225
1226 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1227 if (s->active_rx == s->cookie_rx[i])
1228 return i;
1229
1230 return -1;
1231 }
1232
sci_dma_rx_chan_invalidate(struct sci_port * s)1233 static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1234 {
1235 unsigned int i;
1236
1237 s->chan_rx = NULL;
1238 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1239 s->cookie_rx[i] = -EINVAL;
1240 s->active_rx = 0;
1241 }
1242
sci_dma_rx_release(struct sci_port * s)1243 static void sci_dma_rx_release(struct sci_port *s)
1244 {
1245 struct dma_chan *chan = s->chan_rx_saved;
1246
1247 s->chan_rx_saved = NULL;
1248 sci_dma_rx_chan_invalidate(s);
1249 dmaengine_terminate_sync(chan);
1250 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1251 sg_dma_address(&s->sg_rx[0]));
1252 dma_release_channel(chan);
1253 }
1254
start_hrtimer_us(struct hrtimer * hrt,unsigned long usec)1255 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1256 {
1257 long sec = usec / 1000000;
1258 long nsec = (usec % 1000000) * 1000;
1259 ktime_t t = ktime_set(sec, nsec);
1260
1261 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1262 }
1263
sci_dma_rx_reenable_irq(struct sci_port * s)1264 static void sci_dma_rx_reenable_irq(struct sci_port *s)
1265 {
1266 struct uart_port *port = &s->port;
1267 u16 scr;
1268
1269 /* Direct new serial port interrupts back to CPU */
1270 scr = serial_port_in(port, SCSCR);
1271 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1272 scr &= ~SCSCR_RDRQE;
1273 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1274 }
1275 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1276 }
1277
sci_dma_rx_complete(void * arg)1278 static void sci_dma_rx_complete(void *arg)
1279 {
1280 struct sci_port *s = arg;
1281 struct dma_chan *chan = s->chan_rx;
1282 struct uart_port *port = &s->port;
1283 struct dma_async_tx_descriptor *desc;
1284 unsigned long flags;
1285 int active, count = 0;
1286
1287 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1288 s->active_rx);
1289
1290 spin_lock_irqsave(&port->lock, flags);
1291
1292 active = sci_dma_rx_find_active(s);
1293 if (active >= 0)
1294 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1295
1296 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1297
1298 if (count)
1299 tty_flip_buffer_push(&port->state->port);
1300
1301 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1302 DMA_DEV_TO_MEM,
1303 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1304 if (!desc)
1305 goto fail;
1306
1307 desc->callback = sci_dma_rx_complete;
1308 desc->callback_param = s;
1309 s->cookie_rx[active] = dmaengine_submit(desc);
1310 if (dma_submit_error(s->cookie_rx[active]))
1311 goto fail;
1312
1313 s->active_rx = s->cookie_rx[!active];
1314
1315 dma_async_issue_pending(chan);
1316
1317 spin_unlock_irqrestore(&port->lock, flags);
1318 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1319 __func__, s->cookie_rx[active], active, s->active_rx);
1320 return;
1321
1322 fail:
1323 spin_unlock_irqrestore(&port->lock, flags);
1324 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1325 /* Switch to PIO */
1326 spin_lock_irqsave(&port->lock, flags);
1327 dmaengine_terminate_async(chan);
1328 sci_dma_rx_chan_invalidate(s);
1329 sci_dma_rx_reenable_irq(s);
1330 spin_unlock_irqrestore(&port->lock, flags);
1331 }
1332
sci_dma_tx_release(struct sci_port * s)1333 static void sci_dma_tx_release(struct sci_port *s)
1334 {
1335 struct dma_chan *chan = s->chan_tx_saved;
1336
1337 cancel_work_sync(&s->work_tx);
1338 s->chan_tx_saved = s->chan_tx = NULL;
1339 s->cookie_tx = -EINVAL;
1340 dmaengine_terminate_sync(chan);
1341 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1342 DMA_TO_DEVICE);
1343 dma_release_channel(chan);
1344 }
1345
sci_dma_rx_submit(struct sci_port * s,bool port_lock_held)1346 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1347 {
1348 struct dma_chan *chan = s->chan_rx;
1349 struct uart_port *port = &s->port;
1350 unsigned long flags;
1351 int i;
1352
1353 for (i = 0; i < 2; i++) {
1354 struct scatterlist *sg = &s->sg_rx[i];
1355 struct dma_async_tx_descriptor *desc;
1356
1357 desc = dmaengine_prep_slave_sg(chan,
1358 sg, 1, DMA_DEV_TO_MEM,
1359 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1360 if (!desc)
1361 goto fail;
1362
1363 desc->callback = sci_dma_rx_complete;
1364 desc->callback_param = s;
1365 s->cookie_rx[i] = dmaengine_submit(desc);
1366 if (dma_submit_error(s->cookie_rx[i]))
1367 goto fail;
1368
1369 }
1370
1371 s->active_rx = s->cookie_rx[0];
1372
1373 dma_async_issue_pending(chan);
1374 return 0;
1375
1376 fail:
1377 /* Switch to PIO */
1378 if (!port_lock_held)
1379 spin_lock_irqsave(&port->lock, flags);
1380 if (i)
1381 dmaengine_terminate_async(chan);
1382 sci_dma_rx_chan_invalidate(s);
1383 sci_start_rx(port);
1384 if (!port_lock_held)
1385 spin_unlock_irqrestore(&port->lock, flags);
1386 return -EAGAIN;
1387 }
1388
sci_dma_tx_work_fn(struct work_struct * work)1389 static void sci_dma_tx_work_fn(struct work_struct *work)
1390 {
1391 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1392 struct dma_async_tx_descriptor *desc;
1393 struct dma_chan *chan = s->chan_tx;
1394 struct uart_port *port = &s->port;
1395 struct circ_buf *xmit = &port->state->xmit;
1396 unsigned long flags;
1397 dma_addr_t buf;
1398 int head, tail;
1399
1400 /*
1401 * DMA is idle now.
1402 * Port xmit buffer is already mapped, and it is one page... Just adjust
1403 * offsets and lengths. Since it is a circular buffer, we have to
1404 * transmit till the end, and then the rest. Take the port lock to get a
1405 * consistent xmit buffer state.
1406 */
1407 spin_lock_irq(&port->lock);
1408 head = xmit->head;
1409 tail = xmit->tail;
1410 buf = s->tx_dma_addr + tail;
1411 s->tx_dma_len = CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE);
1412 if (!s->tx_dma_len) {
1413 /* Transmit buffer has been flushed */
1414 spin_unlock_irq(&port->lock);
1415 return;
1416 }
1417
1418 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1419 DMA_MEM_TO_DEV,
1420 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1421 if (!desc) {
1422 spin_unlock_irq(&port->lock);
1423 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1424 goto switch_to_pio;
1425 }
1426
1427 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1428 DMA_TO_DEVICE);
1429
1430 desc->callback = sci_dma_tx_complete;
1431 desc->callback_param = s;
1432 s->cookie_tx = dmaengine_submit(desc);
1433 if (dma_submit_error(s->cookie_tx)) {
1434 spin_unlock_irq(&port->lock);
1435 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1436 goto switch_to_pio;
1437 }
1438
1439 spin_unlock_irq(&port->lock);
1440 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1441 __func__, xmit->buf, tail, head, s->cookie_tx);
1442
1443 dma_async_issue_pending(chan);
1444 return;
1445
1446 switch_to_pio:
1447 spin_lock_irqsave(&port->lock, flags);
1448 s->chan_tx = NULL;
1449 sci_start_tx(port);
1450 spin_unlock_irqrestore(&port->lock, flags);
1451 return;
1452 }
1453
sci_dma_rx_timer_fn(struct hrtimer * t)1454 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1455 {
1456 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1457 struct dma_chan *chan = s->chan_rx;
1458 struct uart_port *port = &s->port;
1459 struct dma_tx_state state;
1460 enum dma_status status;
1461 unsigned long flags;
1462 unsigned int read;
1463 int active, count;
1464
1465 dev_dbg(port->dev, "DMA Rx timed out\n");
1466
1467 spin_lock_irqsave(&port->lock, flags);
1468
1469 active = sci_dma_rx_find_active(s);
1470 if (active < 0) {
1471 spin_unlock_irqrestore(&port->lock, flags);
1472 return HRTIMER_NORESTART;
1473 }
1474
1475 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1476 if (status == DMA_COMPLETE) {
1477 spin_unlock_irqrestore(&port->lock, flags);
1478 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1479 s->active_rx, active);
1480
1481 /* Let packet complete handler take care of the packet */
1482 return HRTIMER_NORESTART;
1483 }
1484
1485 dmaengine_pause(chan);
1486
1487 /*
1488 * sometimes DMA transfer doesn't stop even if it is stopped and
1489 * data keeps on coming until transaction is complete so check
1490 * for DMA_COMPLETE again
1491 * Let packet complete handler take care of the packet
1492 */
1493 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1494 if (status == DMA_COMPLETE) {
1495 spin_unlock_irqrestore(&port->lock, flags);
1496 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1497 return HRTIMER_NORESTART;
1498 }
1499
1500 /* Handle incomplete DMA receive */
1501 dmaengine_terminate_async(s->chan_rx);
1502 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1503
1504 if (read) {
1505 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1506 if (count)
1507 tty_flip_buffer_push(&port->state->port);
1508 }
1509
1510 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1511 sci_dma_rx_submit(s, true);
1512
1513 sci_dma_rx_reenable_irq(s);
1514
1515 spin_unlock_irqrestore(&port->lock, flags);
1516
1517 return HRTIMER_NORESTART;
1518 }
1519
sci_request_dma_chan(struct uart_port * port,enum dma_transfer_direction dir)1520 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1521 enum dma_transfer_direction dir)
1522 {
1523 struct dma_chan *chan;
1524 struct dma_slave_config cfg;
1525 int ret;
1526
1527 chan = dma_request_slave_channel(port->dev,
1528 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1529 if (!chan) {
1530 dev_dbg(port->dev, "dma_request_slave_channel failed\n");
1531 return NULL;
1532 }
1533
1534 memset(&cfg, 0, sizeof(cfg));
1535 cfg.direction = dir;
1536 if (dir == DMA_MEM_TO_DEV) {
1537 cfg.dst_addr = port->mapbase +
1538 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1539 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1540 } else {
1541 cfg.src_addr = port->mapbase +
1542 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1543 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1544 }
1545
1546 ret = dmaengine_slave_config(chan, &cfg);
1547 if (ret) {
1548 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1549 dma_release_channel(chan);
1550 return NULL;
1551 }
1552
1553 return chan;
1554 }
1555
sci_request_dma(struct uart_port * port)1556 static void sci_request_dma(struct uart_port *port)
1557 {
1558 struct sci_port *s = to_sci_port(port);
1559 struct dma_chan *chan;
1560
1561 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1562
1563 /*
1564 * DMA on console may interfere with Kernel log messages which use
1565 * plain putchar(). So, simply don't use it with a console.
1566 */
1567 if (uart_console(port))
1568 return;
1569
1570 if (!port->dev->of_node)
1571 return;
1572
1573 s->cookie_tx = -EINVAL;
1574
1575 /*
1576 * Don't request a dma channel if no channel was specified
1577 * in the device tree.
1578 */
1579 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1580 return;
1581
1582 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1583 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1584 if (chan) {
1585 /* UART circular tx buffer is an aligned page. */
1586 s->tx_dma_addr = dma_map_single(chan->device->dev,
1587 port->state->xmit.buf,
1588 UART_XMIT_SIZE,
1589 DMA_TO_DEVICE);
1590 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1591 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1592 dma_release_channel(chan);
1593 } else {
1594 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1595 __func__, UART_XMIT_SIZE,
1596 port->state->xmit.buf, &s->tx_dma_addr);
1597
1598 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1599 s->chan_tx_saved = s->chan_tx = chan;
1600 }
1601 }
1602
1603 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1604 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1605 if (chan) {
1606 unsigned int i;
1607 dma_addr_t dma;
1608 void *buf;
1609
1610 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1611 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1612 &dma, GFP_KERNEL);
1613 if (!buf) {
1614 dev_warn(port->dev,
1615 "Failed to allocate Rx dma buffer, using PIO\n");
1616 dma_release_channel(chan);
1617 return;
1618 }
1619
1620 for (i = 0; i < 2; i++) {
1621 struct scatterlist *sg = &s->sg_rx[i];
1622
1623 sg_init_table(sg, 1);
1624 s->rx_buf[i] = buf;
1625 sg_dma_address(sg) = dma;
1626 sg_dma_len(sg) = s->buf_len_rx;
1627
1628 buf += s->buf_len_rx;
1629 dma += s->buf_len_rx;
1630 }
1631
1632 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1633 s->rx_timer.function = sci_dma_rx_timer_fn;
1634
1635 s->chan_rx_saved = s->chan_rx = chan;
1636
1637 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1638 sci_dma_rx_submit(s, false);
1639 }
1640 }
1641
sci_free_dma(struct uart_port * port)1642 static void sci_free_dma(struct uart_port *port)
1643 {
1644 struct sci_port *s = to_sci_port(port);
1645
1646 if (s->chan_tx_saved)
1647 sci_dma_tx_release(s);
1648 if (s->chan_rx_saved)
1649 sci_dma_rx_release(s);
1650 }
1651
sci_flush_buffer(struct uart_port * port)1652 static void sci_flush_buffer(struct uart_port *port)
1653 {
1654 struct sci_port *s = to_sci_port(port);
1655
1656 /*
1657 * In uart_flush_buffer(), the xmit circular buffer has just been
1658 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1659 * pending transfers
1660 */
1661 s->tx_dma_len = 0;
1662 if (s->chan_tx) {
1663 dmaengine_terminate_async(s->chan_tx);
1664 s->cookie_tx = -EINVAL;
1665 }
1666 }
1667 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
sci_request_dma(struct uart_port * port)1668 static inline void sci_request_dma(struct uart_port *port)
1669 {
1670 }
1671
sci_free_dma(struct uart_port * port)1672 static inline void sci_free_dma(struct uart_port *port)
1673 {
1674 }
1675
1676 #define sci_flush_buffer NULL
1677 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1678
sci_rx_interrupt(int irq,void * ptr)1679 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1680 {
1681 struct uart_port *port = ptr;
1682 struct sci_port *s = to_sci_port(port);
1683
1684 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1685 if (s->chan_rx) {
1686 u16 scr = serial_port_in(port, SCSCR);
1687 u16 ssr = serial_port_in(port, SCxSR);
1688
1689 /* Disable future Rx interrupts */
1690 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1691 disable_irq_nosync(irq);
1692 scr |= SCSCR_RDRQE;
1693 } else {
1694 if (sci_dma_rx_submit(s, false) < 0)
1695 goto handle_pio;
1696
1697 scr &= ~SCSCR_RIE;
1698 }
1699 serial_port_out(port, SCSCR, scr);
1700 /* Clear current interrupt */
1701 serial_port_out(port, SCxSR,
1702 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1703 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1704 jiffies, s->rx_timeout);
1705 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1706
1707 return IRQ_HANDLED;
1708 }
1709
1710 handle_pio:
1711 #endif
1712
1713 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1714 if (!scif_rtrg_enabled(port))
1715 scif_set_rtrg(port, s->rx_trigger);
1716
1717 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1718 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1719 }
1720
1721 /* I think sci_receive_chars has to be called irrespective
1722 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1723 * to be disabled?
1724 */
1725 sci_receive_chars(port);
1726
1727 return IRQ_HANDLED;
1728 }
1729
sci_tx_interrupt(int irq,void * ptr)1730 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1731 {
1732 struct uart_port *port = ptr;
1733 unsigned long flags;
1734
1735 spin_lock_irqsave(&port->lock, flags);
1736 sci_transmit_chars(port);
1737 spin_unlock_irqrestore(&port->lock, flags);
1738
1739 return IRQ_HANDLED;
1740 }
1741
sci_br_interrupt(int irq,void * ptr)1742 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1743 {
1744 struct uart_port *port = ptr;
1745
1746 /* Handle BREAKs */
1747 sci_handle_breaks(port);
1748
1749 /* drop invalid character received before break was detected */
1750 serial_port_in(port, SCxRDR);
1751
1752 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1753
1754 return IRQ_HANDLED;
1755 }
1756
sci_er_interrupt(int irq,void * ptr)1757 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1758 {
1759 struct uart_port *port = ptr;
1760 struct sci_port *s = to_sci_port(port);
1761
1762 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1763 /* Break and Error interrupts are muxed */
1764 unsigned short ssr_status = serial_port_in(port, SCxSR);
1765
1766 /* Break Interrupt */
1767 if (ssr_status & SCxSR_BRK(port))
1768 sci_br_interrupt(irq, ptr);
1769
1770 /* Break only? */
1771 if (!(ssr_status & SCxSR_ERRORS(port)))
1772 return IRQ_HANDLED;
1773 }
1774
1775 /* Handle errors */
1776 if (port->type == PORT_SCI) {
1777 if (sci_handle_errors(port)) {
1778 /* discard character in rx buffer */
1779 serial_port_in(port, SCxSR);
1780 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1781 }
1782 } else {
1783 sci_handle_fifo_overrun(port);
1784 if (!s->chan_rx)
1785 sci_receive_chars(port);
1786 }
1787
1788 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1789
1790 /* Kick the transmission */
1791 if (!s->chan_tx)
1792 sci_tx_interrupt(irq, ptr);
1793
1794 return IRQ_HANDLED;
1795 }
1796
sci_mpxed_interrupt(int irq,void * ptr)1797 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1798 {
1799 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1800 struct uart_port *port = ptr;
1801 struct sci_port *s = to_sci_port(port);
1802 irqreturn_t ret = IRQ_NONE;
1803
1804 ssr_status = serial_port_in(port, SCxSR);
1805 scr_status = serial_port_in(port, SCSCR);
1806 if (s->params->overrun_reg == SCxSR)
1807 orer_status = ssr_status;
1808 else if (sci_getreg(port, s->params->overrun_reg)->size)
1809 orer_status = serial_port_in(port, s->params->overrun_reg);
1810
1811 err_enabled = scr_status & port_rx_irq_mask(port);
1812
1813 /* Tx Interrupt */
1814 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1815 !s->chan_tx)
1816 ret = sci_tx_interrupt(irq, ptr);
1817
1818 /*
1819 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1820 * DR flags
1821 */
1822 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1823 (scr_status & SCSCR_RIE))
1824 ret = sci_rx_interrupt(irq, ptr);
1825
1826 /* Error Interrupt */
1827 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1828 ret = sci_er_interrupt(irq, ptr);
1829
1830 /* Break Interrupt */
1831 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
1832 (ssr_status & SCxSR_BRK(port)) && err_enabled)
1833 ret = sci_br_interrupt(irq, ptr);
1834
1835 /* Overrun Interrupt */
1836 if (orer_status & s->params->overrun_mask) {
1837 sci_handle_fifo_overrun(port);
1838 ret = IRQ_HANDLED;
1839 }
1840
1841 return ret;
1842 }
1843
1844 static const struct sci_irq_desc {
1845 const char *desc;
1846 irq_handler_t handler;
1847 } sci_irq_desc[] = {
1848 /*
1849 * Split out handlers, the default case.
1850 */
1851 [SCIx_ERI_IRQ] = {
1852 .desc = "rx err",
1853 .handler = sci_er_interrupt,
1854 },
1855
1856 [SCIx_RXI_IRQ] = {
1857 .desc = "rx full",
1858 .handler = sci_rx_interrupt,
1859 },
1860
1861 [SCIx_TXI_IRQ] = {
1862 .desc = "tx empty",
1863 .handler = sci_tx_interrupt,
1864 },
1865
1866 [SCIx_BRI_IRQ] = {
1867 .desc = "break",
1868 .handler = sci_br_interrupt,
1869 },
1870
1871 [SCIx_DRI_IRQ] = {
1872 .desc = "rx ready",
1873 .handler = sci_rx_interrupt,
1874 },
1875
1876 [SCIx_TEI_IRQ] = {
1877 .desc = "tx end",
1878 .handler = sci_tx_interrupt,
1879 },
1880
1881 /*
1882 * Special muxed handler.
1883 */
1884 [SCIx_MUX_IRQ] = {
1885 .desc = "mux",
1886 .handler = sci_mpxed_interrupt,
1887 },
1888 };
1889
sci_request_irq(struct sci_port * port)1890 static int sci_request_irq(struct sci_port *port)
1891 {
1892 struct uart_port *up = &port->port;
1893 int i, j, w, ret = 0;
1894
1895 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1896 const struct sci_irq_desc *desc;
1897 int irq;
1898
1899 /* Check if already registered (muxed) */
1900 for (w = 0; w < i; w++)
1901 if (port->irqs[w] == port->irqs[i])
1902 w = i + 1;
1903 if (w > i)
1904 continue;
1905
1906 if (SCIx_IRQ_IS_MUXED(port)) {
1907 i = SCIx_MUX_IRQ;
1908 irq = up->irq;
1909 } else {
1910 irq = port->irqs[i];
1911
1912 /*
1913 * Certain port types won't support all of the
1914 * available interrupt sources.
1915 */
1916 if (unlikely(irq < 0))
1917 continue;
1918 }
1919
1920 desc = sci_irq_desc + i;
1921 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1922 dev_name(up->dev), desc->desc);
1923 if (!port->irqstr[j]) {
1924 ret = -ENOMEM;
1925 goto out_nomem;
1926 }
1927
1928 ret = request_irq(irq, desc->handler, up->irqflags,
1929 port->irqstr[j], port);
1930 if (unlikely(ret)) {
1931 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1932 goto out_noirq;
1933 }
1934 }
1935
1936 return 0;
1937
1938 out_noirq:
1939 while (--i >= 0)
1940 free_irq(port->irqs[i], port);
1941
1942 out_nomem:
1943 while (--j >= 0)
1944 kfree(port->irqstr[j]);
1945
1946 return ret;
1947 }
1948
sci_free_irq(struct sci_port * port)1949 static void sci_free_irq(struct sci_port *port)
1950 {
1951 int i, j;
1952
1953 /*
1954 * Intentionally in reverse order so we iterate over the muxed
1955 * IRQ first.
1956 */
1957 for (i = 0; i < SCIx_NR_IRQS; i++) {
1958 int irq = port->irqs[i];
1959
1960 /*
1961 * Certain port types won't support all of the available
1962 * interrupt sources.
1963 */
1964 if (unlikely(irq < 0))
1965 continue;
1966
1967 /* Check if already freed (irq was muxed) */
1968 for (j = 0; j < i; j++)
1969 if (port->irqs[j] == irq)
1970 j = i + 1;
1971 if (j > i)
1972 continue;
1973
1974 free_irq(port->irqs[i], port);
1975 kfree(port->irqstr[i]);
1976
1977 if (SCIx_IRQ_IS_MUXED(port)) {
1978 /* If there's only one IRQ, we're done. */
1979 return;
1980 }
1981 }
1982 }
1983
sci_tx_empty(struct uart_port * port)1984 static unsigned int sci_tx_empty(struct uart_port *port)
1985 {
1986 unsigned short status = serial_port_in(port, SCxSR);
1987 unsigned short in_tx_fifo = sci_txfill(port);
1988
1989 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1990 }
1991
sci_set_rts(struct uart_port * port,bool state)1992 static void sci_set_rts(struct uart_port *port, bool state)
1993 {
1994 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1995 u16 data = serial_port_in(port, SCPDR);
1996
1997 /* Active low */
1998 if (state)
1999 data &= ~SCPDR_RTSD;
2000 else
2001 data |= SCPDR_RTSD;
2002 serial_port_out(port, SCPDR, data);
2003
2004 /* RTS# is output */
2005 serial_port_out(port, SCPCR,
2006 serial_port_in(port, SCPCR) | SCPCR_RTSC);
2007 } else if (sci_getreg(port, SCSPTR)->size) {
2008 u16 ctrl = serial_port_in(port, SCSPTR);
2009
2010 /* Active low */
2011 if (state)
2012 ctrl &= ~SCSPTR_RTSDT;
2013 else
2014 ctrl |= SCSPTR_RTSDT;
2015 serial_port_out(port, SCSPTR, ctrl);
2016 }
2017 }
2018
sci_get_cts(struct uart_port * port)2019 static bool sci_get_cts(struct uart_port *port)
2020 {
2021 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2022 /* Active low */
2023 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2024 } else if (sci_getreg(port, SCSPTR)->size) {
2025 /* Active low */
2026 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2027 }
2028
2029 return true;
2030 }
2031
2032 /*
2033 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2034 * CTS/RTS is supported in hardware by at least one port and controlled
2035 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2036 * handled via the ->init_pins() op, which is a bit of a one-way street,
2037 * lacking any ability to defer pin control -- this will later be
2038 * converted over to the GPIO framework).
2039 *
2040 * Other modes (such as loopback) are supported generically on certain
2041 * port types, but not others. For these it's sufficient to test for the
2042 * existence of the support register and simply ignore the port type.
2043 */
sci_set_mctrl(struct uart_port * port,unsigned int mctrl)2044 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2045 {
2046 struct sci_port *s = to_sci_port(port);
2047
2048 if (mctrl & TIOCM_LOOP) {
2049 const struct plat_sci_reg *reg;
2050
2051 /*
2052 * Standard loopback mode for SCFCR ports.
2053 */
2054 reg = sci_getreg(port, SCFCR);
2055 if (reg->size)
2056 serial_port_out(port, SCFCR,
2057 serial_port_in(port, SCFCR) |
2058 SCFCR_LOOP);
2059 }
2060
2061 mctrl_gpio_set(s->gpios, mctrl);
2062
2063 if (!s->has_rtscts)
2064 return;
2065
2066 if (!(mctrl & TIOCM_RTS)) {
2067 /* Disable Auto RTS */
2068 serial_port_out(port, SCFCR,
2069 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2070
2071 /* Clear RTS */
2072 sci_set_rts(port, 0);
2073 } else if (s->autorts) {
2074 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2075 /* Enable RTS# pin function */
2076 serial_port_out(port, SCPCR,
2077 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2078 }
2079
2080 /* Enable Auto RTS */
2081 serial_port_out(port, SCFCR,
2082 serial_port_in(port, SCFCR) | SCFCR_MCE);
2083 } else {
2084 /* Set RTS */
2085 sci_set_rts(port, 1);
2086 }
2087 }
2088
sci_get_mctrl(struct uart_port * port)2089 static unsigned int sci_get_mctrl(struct uart_port *port)
2090 {
2091 struct sci_port *s = to_sci_port(port);
2092 struct mctrl_gpios *gpios = s->gpios;
2093 unsigned int mctrl = 0;
2094
2095 mctrl_gpio_get(gpios, &mctrl);
2096
2097 /*
2098 * CTS/RTS is handled in hardware when supported, while nothing
2099 * else is wired up.
2100 */
2101 if (s->autorts) {
2102 if (sci_get_cts(port))
2103 mctrl |= TIOCM_CTS;
2104 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2105 mctrl |= TIOCM_CTS;
2106 }
2107 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2108 mctrl |= TIOCM_DSR;
2109 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2110 mctrl |= TIOCM_CAR;
2111
2112 return mctrl;
2113 }
2114
sci_enable_ms(struct uart_port * port)2115 static void sci_enable_ms(struct uart_port *port)
2116 {
2117 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2118 }
2119
sci_break_ctl(struct uart_port * port,int break_state)2120 static void sci_break_ctl(struct uart_port *port, int break_state)
2121 {
2122 unsigned short scscr, scsptr;
2123 unsigned long flags;
2124
2125 /* check whether the port has SCSPTR */
2126 if (!sci_getreg(port, SCSPTR)->size) {
2127 /*
2128 * Not supported by hardware. Most parts couple break and rx
2129 * interrupts together, with break detection always enabled.
2130 */
2131 return;
2132 }
2133
2134 spin_lock_irqsave(&port->lock, flags);
2135 scsptr = serial_port_in(port, SCSPTR);
2136 scscr = serial_port_in(port, SCSCR);
2137
2138 if (break_state == -1) {
2139 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2140 scscr &= ~SCSCR_TE;
2141 } else {
2142 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2143 scscr |= SCSCR_TE;
2144 }
2145
2146 serial_port_out(port, SCSPTR, scsptr);
2147 serial_port_out(port, SCSCR, scscr);
2148 spin_unlock_irqrestore(&port->lock, flags);
2149 }
2150
sci_startup(struct uart_port * port)2151 static int sci_startup(struct uart_port *port)
2152 {
2153 struct sci_port *s = to_sci_port(port);
2154 int ret;
2155
2156 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2157
2158 sci_request_dma(port);
2159
2160 ret = sci_request_irq(s);
2161 if (unlikely(ret < 0)) {
2162 sci_free_dma(port);
2163 return ret;
2164 }
2165
2166 return 0;
2167 }
2168
sci_shutdown(struct uart_port * port)2169 static void sci_shutdown(struct uart_port *port)
2170 {
2171 struct sci_port *s = to_sci_port(port);
2172 unsigned long flags;
2173 u16 scr;
2174
2175 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2176
2177 s->autorts = false;
2178 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2179
2180 spin_lock_irqsave(&port->lock, flags);
2181 sci_stop_rx(port);
2182 sci_stop_tx(port);
2183 /*
2184 * Stop RX and TX, disable related interrupts, keep clock source
2185 * and HSCIF TOT bits
2186 */
2187 scr = serial_port_in(port, SCSCR);
2188 serial_port_out(port, SCSCR, scr &
2189 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2190 spin_unlock_irqrestore(&port->lock, flags);
2191
2192 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2193 if (s->chan_rx_saved) {
2194 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2195 port->line);
2196 hrtimer_cancel(&s->rx_timer);
2197 }
2198 #endif
2199
2200 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2201 del_timer_sync(&s->rx_fifo_timer);
2202 sci_free_irq(s);
2203 sci_free_dma(port);
2204 }
2205
sci_sck_calc(struct sci_port * s,unsigned int bps,unsigned int * srr)2206 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2207 unsigned int *srr)
2208 {
2209 unsigned long freq = s->clk_rates[SCI_SCK];
2210 int err, min_err = INT_MAX;
2211 unsigned int sr;
2212
2213 if (s->port.type != PORT_HSCIF)
2214 freq *= 2;
2215
2216 for_each_sr(sr, s) {
2217 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2218 if (abs(err) >= abs(min_err))
2219 continue;
2220
2221 min_err = err;
2222 *srr = sr - 1;
2223
2224 if (!err)
2225 break;
2226 }
2227
2228 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2229 *srr + 1);
2230 return min_err;
2231 }
2232
sci_brg_calc(struct sci_port * s,unsigned int bps,unsigned long freq,unsigned int * dlr,unsigned int * srr)2233 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2234 unsigned long freq, unsigned int *dlr,
2235 unsigned int *srr)
2236 {
2237 int err, min_err = INT_MAX;
2238 unsigned int sr, dl;
2239
2240 if (s->port.type != PORT_HSCIF)
2241 freq *= 2;
2242
2243 for_each_sr(sr, s) {
2244 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2245 dl = clamp(dl, 1U, 65535U);
2246
2247 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2248 if (abs(err) >= abs(min_err))
2249 continue;
2250
2251 min_err = err;
2252 *dlr = dl;
2253 *srr = sr - 1;
2254
2255 if (!err)
2256 break;
2257 }
2258
2259 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2260 min_err, *dlr, *srr + 1);
2261 return min_err;
2262 }
2263
2264 /* calculate sample rate, BRR, and clock select */
sci_scbrr_calc(struct sci_port * s,unsigned int bps,unsigned int * brr,unsigned int * srr,unsigned int * cks)2265 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2266 unsigned int *brr, unsigned int *srr,
2267 unsigned int *cks)
2268 {
2269 unsigned long freq = s->clk_rates[SCI_FCK];
2270 unsigned int sr, br, prediv, scrate, c;
2271 int err, min_err = INT_MAX;
2272
2273 if (s->port.type != PORT_HSCIF)
2274 freq *= 2;
2275
2276 /*
2277 * Find the combination of sample rate and clock select with the
2278 * smallest deviation from the desired baud rate.
2279 * Prefer high sample rates to maximise the receive margin.
2280 *
2281 * M: Receive margin (%)
2282 * N: Ratio of bit rate to clock (N = sampling rate)
2283 * D: Clock duty (D = 0 to 1.0)
2284 * L: Frame length (L = 9 to 12)
2285 * F: Absolute value of clock frequency deviation
2286 *
2287 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2288 * (|D - 0.5| / N * (1 + F))|
2289 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2290 */
2291 for_each_sr(sr, s) {
2292 for (c = 0; c <= 3; c++) {
2293 /* integerized formulas from HSCIF documentation */
2294 prediv = sr << (2 * c + 1);
2295
2296 /*
2297 * We need to calculate:
2298 *
2299 * br = freq / (prediv * bps) clamped to [1..256]
2300 * err = freq / (br * prediv) - bps
2301 *
2302 * Watch out for overflow when calculating the desired
2303 * sampling clock rate!
2304 */
2305 if (bps > UINT_MAX / prediv)
2306 break;
2307
2308 scrate = prediv * bps;
2309 br = DIV_ROUND_CLOSEST(freq, scrate);
2310 br = clamp(br, 1U, 256U);
2311
2312 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2313 if (abs(err) >= abs(min_err))
2314 continue;
2315
2316 min_err = err;
2317 *brr = br - 1;
2318 *srr = sr - 1;
2319 *cks = c;
2320
2321 if (!err)
2322 goto found;
2323 }
2324 }
2325
2326 found:
2327 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2328 min_err, *brr, *srr + 1, *cks);
2329 return min_err;
2330 }
2331
sci_reset(struct uart_port * port)2332 static void sci_reset(struct uart_port *port)
2333 {
2334 const struct plat_sci_reg *reg;
2335 unsigned int status;
2336 struct sci_port *s = to_sci_port(port);
2337
2338 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2339
2340 reg = sci_getreg(port, SCFCR);
2341 if (reg->size)
2342 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2343
2344 sci_clear_SCxSR(port,
2345 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2346 SCxSR_BREAK_CLEAR(port));
2347 if (sci_getreg(port, SCLSR)->size) {
2348 status = serial_port_in(port, SCLSR);
2349 status &= ~(SCLSR_TO | SCLSR_ORER);
2350 serial_port_out(port, SCLSR, status);
2351 }
2352
2353 if (s->rx_trigger > 1) {
2354 if (s->rx_fifo_timeout) {
2355 scif_set_rtrg(port, 1);
2356 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2357 } else {
2358 if (port->type == PORT_SCIFA ||
2359 port->type == PORT_SCIFB)
2360 scif_set_rtrg(port, 1);
2361 else
2362 scif_set_rtrg(port, s->rx_trigger);
2363 }
2364 }
2365 }
2366
sci_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)2367 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2368 const struct ktermios *old)
2369 {
2370 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2371 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2372 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2373 struct sci_port *s = to_sci_port(port);
2374 const struct plat_sci_reg *reg;
2375 int min_err = INT_MAX, err;
2376 unsigned long max_freq = 0;
2377 int best_clk = -1;
2378 unsigned long flags;
2379
2380 if ((termios->c_cflag & CSIZE) == CS7) {
2381 smr_val |= SCSMR_CHR;
2382 } else {
2383 termios->c_cflag &= ~CSIZE;
2384 termios->c_cflag |= CS8;
2385 }
2386 if (termios->c_cflag & PARENB)
2387 smr_val |= SCSMR_PE;
2388 if (termios->c_cflag & PARODD)
2389 smr_val |= SCSMR_PE | SCSMR_ODD;
2390 if (termios->c_cflag & CSTOPB)
2391 smr_val |= SCSMR_STOP;
2392
2393 /*
2394 * earlyprintk comes here early on with port->uartclk set to zero.
2395 * the clock framework is not up and running at this point so here
2396 * we assume that 115200 is the maximum baud rate. please note that
2397 * the baud rate is not programmed during earlyprintk - it is assumed
2398 * that the previous boot loader has enabled required clocks and
2399 * setup the baud rate generator hardware for us already.
2400 */
2401 if (!port->uartclk) {
2402 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2403 goto done;
2404 }
2405
2406 for (i = 0; i < SCI_NUM_CLKS; i++)
2407 max_freq = max(max_freq, s->clk_rates[i]);
2408
2409 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2410 if (!baud)
2411 goto done;
2412
2413 /*
2414 * There can be multiple sources for the sampling clock. Find the one
2415 * that gives us the smallest deviation from the desired baud rate.
2416 */
2417
2418 /* Optional Undivided External Clock */
2419 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2420 port->type != PORT_SCIFB) {
2421 err = sci_sck_calc(s, baud, &srr1);
2422 if (abs(err) < abs(min_err)) {
2423 best_clk = SCI_SCK;
2424 scr_val = SCSCR_CKE1;
2425 sccks = SCCKS_CKS;
2426 min_err = err;
2427 srr = srr1;
2428 if (!err)
2429 goto done;
2430 }
2431 }
2432
2433 /* Optional BRG Frequency Divided External Clock */
2434 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2435 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2436 &srr1);
2437 if (abs(err) < abs(min_err)) {
2438 best_clk = SCI_SCIF_CLK;
2439 scr_val = SCSCR_CKE1;
2440 sccks = 0;
2441 min_err = err;
2442 dl = dl1;
2443 srr = srr1;
2444 if (!err)
2445 goto done;
2446 }
2447 }
2448
2449 /* Optional BRG Frequency Divided Internal Clock */
2450 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2451 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2452 &srr1);
2453 if (abs(err) < abs(min_err)) {
2454 best_clk = SCI_BRG_INT;
2455 scr_val = SCSCR_CKE1;
2456 sccks = SCCKS_XIN;
2457 min_err = err;
2458 dl = dl1;
2459 srr = srr1;
2460 if (!min_err)
2461 goto done;
2462 }
2463 }
2464
2465 /* Divided Functional Clock using standard Bit Rate Register */
2466 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2467 if (abs(err) < abs(min_err)) {
2468 best_clk = SCI_FCK;
2469 scr_val = 0;
2470 min_err = err;
2471 brr = brr1;
2472 srr = srr1;
2473 cks = cks1;
2474 }
2475
2476 done:
2477 if (best_clk >= 0)
2478 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2479 s->clks[best_clk], baud, min_err);
2480
2481 sci_port_enable(s);
2482
2483 /*
2484 * Program the optional External Baud Rate Generator (BRG) first.
2485 * It controls the mux to select (H)SCK or frequency divided clock.
2486 */
2487 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2488 serial_port_out(port, SCDL, dl);
2489 serial_port_out(port, SCCKS, sccks);
2490 }
2491
2492 spin_lock_irqsave(&port->lock, flags);
2493
2494 sci_reset(port);
2495
2496 uart_update_timeout(port, termios->c_cflag, baud);
2497
2498 /* byte size and parity */
2499 bits = tty_get_frame_size(termios->c_cflag);
2500
2501 if (sci_getreg(port, SEMR)->size)
2502 serial_port_out(port, SEMR, 0);
2503
2504 if (best_clk >= 0) {
2505 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2506 switch (srr + 1) {
2507 case 5: smr_val |= SCSMR_SRC_5; break;
2508 case 7: smr_val |= SCSMR_SRC_7; break;
2509 case 11: smr_val |= SCSMR_SRC_11; break;
2510 case 13: smr_val |= SCSMR_SRC_13; break;
2511 case 16: smr_val |= SCSMR_SRC_16; break;
2512 case 17: smr_val |= SCSMR_SRC_17; break;
2513 case 19: smr_val |= SCSMR_SRC_19; break;
2514 case 27: smr_val |= SCSMR_SRC_27; break;
2515 }
2516 smr_val |= cks;
2517 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2518 serial_port_out(port, SCSMR, smr_val);
2519 serial_port_out(port, SCBRR, brr);
2520 if (sci_getreg(port, HSSRR)->size) {
2521 unsigned int hssrr = srr | HSCIF_SRE;
2522 /* Calculate deviation from intended rate at the
2523 * center of the last stop bit in sampling clocks.
2524 */
2525 int last_stop = bits * 2 - 1;
2526 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2527 (int)(srr + 1),
2528 2 * (int)baud);
2529
2530 if (abs(deviation) >= 2) {
2531 /* At least two sampling clocks off at the
2532 * last stop bit; we can increase the error
2533 * margin by shifting the sampling point.
2534 */
2535 int shift = clamp(deviation / 2, -8, 7);
2536
2537 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2538 HSCIF_SRHP_MASK;
2539 hssrr |= HSCIF_SRDE;
2540 }
2541 serial_port_out(port, HSSRR, hssrr);
2542 }
2543
2544 /* Wait one bit interval */
2545 udelay((1000000 + (baud - 1)) / baud);
2546 } else {
2547 /* Don't touch the bit rate configuration */
2548 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2549 smr_val |= serial_port_in(port, SCSMR) &
2550 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2551 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2552 serial_port_out(port, SCSMR, smr_val);
2553 }
2554
2555 sci_init_pins(port, termios->c_cflag);
2556
2557 port->status &= ~UPSTAT_AUTOCTS;
2558 s->autorts = false;
2559 reg = sci_getreg(port, SCFCR);
2560 if (reg->size) {
2561 unsigned short ctrl = serial_port_in(port, SCFCR);
2562
2563 if ((port->flags & UPF_HARD_FLOW) &&
2564 (termios->c_cflag & CRTSCTS)) {
2565 /* There is no CTS interrupt to restart the hardware */
2566 port->status |= UPSTAT_AUTOCTS;
2567 /* MCE is enabled when RTS is raised */
2568 s->autorts = true;
2569 }
2570
2571 /*
2572 * As we've done a sci_reset() above, ensure we don't
2573 * interfere with the FIFOs while toggling MCE. As the
2574 * reset values could still be set, simply mask them out.
2575 */
2576 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2577
2578 serial_port_out(port, SCFCR, ctrl);
2579 }
2580 if (port->flags & UPF_HARD_FLOW) {
2581 /* Refresh (Auto) RTS */
2582 sci_set_mctrl(port, port->mctrl);
2583 }
2584
2585 scr_val |= SCSCR_RE | SCSCR_TE |
2586 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2587 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2588 if ((srr + 1 == 5) &&
2589 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2590 /*
2591 * In asynchronous mode, when the sampling rate is 1/5, first
2592 * received data may become invalid on some SCIFA and SCIFB.
2593 * To avoid this problem wait more than 1 serial data time (1
2594 * bit time x serial data number) after setting SCSCR.RE = 1.
2595 */
2596 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2597 }
2598
2599 /* Calculate delay for 2 DMA buffers (4 FIFO). */
2600 s->rx_frame = (10000 * bits) / (baud / 100);
2601 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2602 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2603 #endif
2604
2605 if ((termios->c_cflag & CREAD) != 0)
2606 sci_start_rx(port);
2607
2608 spin_unlock_irqrestore(&port->lock, flags);
2609
2610 sci_port_disable(s);
2611
2612 if (UART_ENABLE_MS(port, termios->c_cflag))
2613 sci_enable_ms(port);
2614 }
2615
sci_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)2616 static void sci_pm(struct uart_port *port, unsigned int state,
2617 unsigned int oldstate)
2618 {
2619 struct sci_port *sci_port = to_sci_port(port);
2620
2621 switch (state) {
2622 case UART_PM_STATE_OFF:
2623 sci_port_disable(sci_port);
2624 break;
2625 default:
2626 sci_port_enable(sci_port);
2627 break;
2628 }
2629 }
2630
sci_type(struct uart_port * port)2631 static const char *sci_type(struct uart_port *port)
2632 {
2633 switch (port->type) {
2634 case PORT_IRDA:
2635 return "irda";
2636 case PORT_SCI:
2637 return "sci";
2638 case PORT_SCIF:
2639 return "scif";
2640 case PORT_SCIFA:
2641 return "scifa";
2642 case PORT_SCIFB:
2643 return "scifb";
2644 case PORT_HSCIF:
2645 return "hscif";
2646 }
2647
2648 return NULL;
2649 }
2650
sci_remap_port(struct uart_port * port)2651 static int sci_remap_port(struct uart_port *port)
2652 {
2653 struct sci_port *sport = to_sci_port(port);
2654
2655 /*
2656 * Nothing to do if there's already an established membase.
2657 */
2658 if (port->membase)
2659 return 0;
2660
2661 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2662 port->membase = ioremap(port->mapbase, sport->reg_size);
2663 if (unlikely(!port->membase)) {
2664 dev_err(port->dev, "can't remap port#%d\n", port->line);
2665 return -ENXIO;
2666 }
2667 } else {
2668 /*
2669 * For the simple (and majority of) cases where we don't
2670 * need to do any remapping, just cast the cookie
2671 * directly.
2672 */
2673 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2674 }
2675
2676 return 0;
2677 }
2678
sci_release_port(struct uart_port * port)2679 static void sci_release_port(struct uart_port *port)
2680 {
2681 struct sci_port *sport = to_sci_port(port);
2682
2683 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2684 iounmap(port->membase);
2685 port->membase = NULL;
2686 }
2687
2688 release_mem_region(port->mapbase, sport->reg_size);
2689 }
2690
sci_request_port(struct uart_port * port)2691 static int sci_request_port(struct uart_port *port)
2692 {
2693 struct resource *res;
2694 struct sci_port *sport = to_sci_port(port);
2695 int ret;
2696
2697 res = request_mem_region(port->mapbase, sport->reg_size,
2698 dev_name(port->dev));
2699 if (unlikely(res == NULL)) {
2700 dev_err(port->dev, "request_mem_region failed.");
2701 return -EBUSY;
2702 }
2703
2704 ret = sci_remap_port(port);
2705 if (unlikely(ret != 0)) {
2706 release_resource(res);
2707 return ret;
2708 }
2709
2710 return 0;
2711 }
2712
sci_config_port(struct uart_port * port,int flags)2713 static void sci_config_port(struct uart_port *port, int flags)
2714 {
2715 if (flags & UART_CONFIG_TYPE) {
2716 struct sci_port *sport = to_sci_port(port);
2717
2718 port->type = sport->cfg->type;
2719 sci_request_port(port);
2720 }
2721 }
2722
sci_verify_port(struct uart_port * port,struct serial_struct * ser)2723 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2724 {
2725 if (ser->baud_base < 2400)
2726 /* No paper tape reader for Mitch.. */
2727 return -EINVAL;
2728
2729 return 0;
2730 }
2731
2732 static const struct uart_ops sci_uart_ops = {
2733 .tx_empty = sci_tx_empty,
2734 .set_mctrl = sci_set_mctrl,
2735 .get_mctrl = sci_get_mctrl,
2736 .start_tx = sci_start_tx,
2737 .stop_tx = sci_stop_tx,
2738 .stop_rx = sci_stop_rx,
2739 .enable_ms = sci_enable_ms,
2740 .break_ctl = sci_break_ctl,
2741 .startup = sci_startup,
2742 .shutdown = sci_shutdown,
2743 .flush_buffer = sci_flush_buffer,
2744 .set_termios = sci_set_termios,
2745 .pm = sci_pm,
2746 .type = sci_type,
2747 .release_port = sci_release_port,
2748 .request_port = sci_request_port,
2749 .config_port = sci_config_port,
2750 .verify_port = sci_verify_port,
2751 #ifdef CONFIG_CONSOLE_POLL
2752 .poll_get_char = sci_poll_get_char,
2753 .poll_put_char = sci_poll_put_char,
2754 #endif
2755 };
2756
sci_init_clocks(struct sci_port * sci_port,struct device * dev)2757 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2758 {
2759 const char *clk_names[] = {
2760 [SCI_FCK] = "fck",
2761 [SCI_SCK] = "sck",
2762 [SCI_BRG_INT] = "brg_int",
2763 [SCI_SCIF_CLK] = "scif_clk",
2764 };
2765 struct clk *clk;
2766 unsigned int i;
2767
2768 if (sci_port->cfg->type == PORT_HSCIF)
2769 clk_names[SCI_SCK] = "hsck";
2770
2771 for (i = 0; i < SCI_NUM_CLKS; i++) {
2772 clk = devm_clk_get_optional(dev, clk_names[i]);
2773 if (IS_ERR(clk))
2774 return PTR_ERR(clk);
2775
2776 if (!clk && i == SCI_FCK) {
2777 /*
2778 * Not all SH platforms declare a clock lookup entry
2779 * for SCI devices, in which case we need to get the
2780 * global "peripheral_clk" clock.
2781 */
2782 clk = devm_clk_get(dev, "peripheral_clk");
2783 if (IS_ERR(clk))
2784 return dev_err_probe(dev, PTR_ERR(clk),
2785 "failed to get %s\n",
2786 clk_names[i]);
2787 }
2788
2789 if (!clk)
2790 dev_dbg(dev, "failed to get %s\n", clk_names[i]);
2791 else
2792 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2793 clk, clk_get_rate(clk));
2794 sci_port->clks[i] = clk;
2795 }
2796 return 0;
2797 }
2798
2799 static const struct sci_port_params *
sci_probe_regmap(const struct plat_sci_port * cfg)2800 sci_probe_regmap(const struct plat_sci_port *cfg)
2801 {
2802 unsigned int regtype;
2803
2804 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2805 return &sci_port_params[cfg->regtype];
2806
2807 switch (cfg->type) {
2808 case PORT_SCI:
2809 regtype = SCIx_SCI_REGTYPE;
2810 break;
2811 case PORT_IRDA:
2812 regtype = SCIx_IRDA_REGTYPE;
2813 break;
2814 case PORT_SCIFA:
2815 regtype = SCIx_SCIFA_REGTYPE;
2816 break;
2817 case PORT_SCIFB:
2818 regtype = SCIx_SCIFB_REGTYPE;
2819 break;
2820 case PORT_SCIF:
2821 /*
2822 * The SH-4 is a bit of a misnomer here, although that's
2823 * where this particular port layout originated. This
2824 * configuration (or some slight variation thereof)
2825 * remains the dominant model for all SCIFs.
2826 */
2827 regtype = SCIx_SH4_SCIF_REGTYPE;
2828 break;
2829 case PORT_HSCIF:
2830 regtype = SCIx_HSCIF_REGTYPE;
2831 break;
2832 default:
2833 pr_err("Can't probe register map for given port\n");
2834 return NULL;
2835 }
2836
2837 return &sci_port_params[regtype];
2838 }
2839
sci_init_single(struct platform_device * dev,struct sci_port * sci_port,unsigned int index,const struct plat_sci_port * p,bool early)2840 static int sci_init_single(struct platform_device *dev,
2841 struct sci_port *sci_port, unsigned int index,
2842 const struct plat_sci_port *p, bool early)
2843 {
2844 struct uart_port *port = &sci_port->port;
2845 const struct resource *res;
2846 unsigned int i;
2847 int ret;
2848
2849 sci_port->cfg = p;
2850
2851 port->ops = &sci_uart_ops;
2852 port->iotype = UPIO_MEM;
2853 port->line = index;
2854 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
2855
2856 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2857 if (res == NULL)
2858 return -ENOMEM;
2859
2860 port->mapbase = res->start;
2861 sci_port->reg_size = resource_size(res);
2862
2863 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
2864 if (i)
2865 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
2866 else
2867 sci_port->irqs[i] = platform_get_irq(dev, i);
2868 }
2869
2870 /* The SCI generates several interrupts. They can be muxed together or
2871 * connected to different interrupt lines. In the muxed case only one
2872 * interrupt resource is specified as there is only one interrupt ID.
2873 * In the non-muxed case, up to 6 interrupt signals might be generated
2874 * from the SCI, however those signals might have their own individual
2875 * interrupt ID numbers, or muxed together with another interrupt.
2876 */
2877 if (sci_port->irqs[0] < 0)
2878 return -ENXIO;
2879
2880 if (sci_port->irqs[1] < 0)
2881 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2882 sci_port->irqs[i] = sci_port->irqs[0];
2883
2884 sci_port->params = sci_probe_regmap(p);
2885 if (unlikely(sci_port->params == NULL))
2886 return -EINVAL;
2887
2888 switch (p->type) {
2889 case PORT_SCIFB:
2890 sci_port->rx_trigger = 48;
2891 break;
2892 case PORT_HSCIF:
2893 sci_port->rx_trigger = 64;
2894 break;
2895 case PORT_SCIFA:
2896 sci_port->rx_trigger = 32;
2897 break;
2898 case PORT_SCIF:
2899 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2900 /* RX triggering not implemented for this IP */
2901 sci_port->rx_trigger = 1;
2902 else
2903 sci_port->rx_trigger = 8;
2904 break;
2905 default:
2906 sci_port->rx_trigger = 1;
2907 break;
2908 }
2909
2910 sci_port->rx_fifo_timeout = 0;
2911 sci_port->hscif_tot = 0;
2912
2913 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2914 * match the SoC datasheet, this should be investigated. Let platform
2915 * data override the sampling rate for now.
2916 */
2917 sci_port->sampling_rate_mask = p->sampling_rate
2918 ? SCI_SR(p->sampling_rate)
2919 : sci_port->params->sampling_rate_mask;
2920
2921 if (!early) {
2922 ret = sci_init_clocks(sci_port, &dev->dev);
2923 if (ret < 0)
2924 return ret;
2925
2926 port->dev = &dev->dev;
2927
2928 pm_runtime_enable(&dev->dev);
2929 }
2930
2931 port->type = p->type;
2932 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2933 port->fifosize = sci_port->params->fifosize;
2934
2935 if (port->type == PORT_SCI) {
2936 if (sci_port->reg_size >= 0x20)
2937 port->regshift = 2;
2938 else
2939 port->regshift = 1;
2940 }
2941
2942 /*
2943 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2944 * for the multi-IRQ ports, which is where we are primarily
2945 * concerned with the shutdown path synchronization.
2946 *
2947 * For the muxed case there's nothing more to do.
2948 */
2949 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2950 port->irqflags = 0;
2951
2952 port->serial_in = sci_serial_in;
2953 port->serial_out = sci_serial_out;
2954
2955 return 0;
2956 }
2957
sci_cleanup_single(struct sci_port * port)2958 static void sci_cleanup_single(struct sci_port *port)
2959 {
2960 pm_runtime_disable(port->port.dev);
2961 }
2962
2963 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2964 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
serial_console_putchar(struct uart_port * port,unsigned char ch)2965 static void serial_console_putchar(struct uart_port *port, unsigned char ch)
2966 {
2967 sci_poll_put_char(port, ch);
2968 }
2969
2970 /*
2971 * Print a string to the serial port trying not to disturb
2972 * any possible real use of the port...
2973 */
serial_console_write(struct console * co,const char * s,unsigned count)2974 static void serial_console_write(struct console *co, const char *s,
2975 unsigned count)
2976 {
2977 struct sci_port *sci_port = &sci_ports[co->index];
2978 struct uart_port *port = &sci_port->port;
2979 unsigned short bits, ctrl, ctrl_temp;
2980 unsigned long flags;
2981 int locked = 1;
2982
2983 if (port->sysrq)
2984 locked = 0;
2985 else if (oops_in_progress)
2986 locked = spin_trylock_irqsave(&port->lock, flags);
2987 else
2988 spin_lock_irqsave(&port->lock, flags);
2989
2990 /* first save SCSCR then disable interrupts, keep clock source */
2991 ctrl = serial_port_in(port, SCSCR);
2992 ctrl_temp = SCSCR_RE | SCSCR_TE |
2993 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2994 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2995 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
2996
2997 uart_console_write(port, s, count, serial_console_putchar);
2998
2999 /* wait until fifo is empty and last bit has been transmitted */
3000 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3001 while ((serial_port_in(port, SCxSR) & bits) != bits)
3002 cpu_relax();
3003
3004 /* restore the SCSCR */
3005 serial_port_out(port, SCSCR, ctrl);
3006
3007 if (locked)
3008 spin_unlock_irqrestore(&port->lock, flags);
3009 }
3010
serial_console_setup(struct console * co,char * options)3011 static int serial_console_setup(struct console *co, char *options)
3012 {
3013 struct sci_port *sci_port;
3014 struct uart_port *port;
3015 int baud = 115200;
3016 int bits = 8;
3017 int parity = 'n';
3018 int flow = 'n';
3019 int ret;
3020
3021 /*
3022 * Refuse to handle any bogus ports.
3023 */
3024 if (co->index < 0 || co->index >= SCI_NPORTS)
3025 return -ENODEV;
3026
3027 sci_port = &sci_ports[co->index];
3028 port = &sci_port->port;
3029
3030 /*
3031 * Refuse to handle uninitialized ports.
3032 */
3033 if (!port->ops)
3034 return -ENODEV;
3035
3036 ret = sci_remap_port(port);
3037 if (unlikely(ret != 0))
3038 return ret;
3039
3040 if (options)
3041 uart_parse_options(options, &baud, &parity, &bits, &flow);
3042
3043 return uart_set_options(port, co, baud, parity, bits, flow);
3044 }
3045
3046 static struct console serial_console = {
3047 .name = "ttySC",
3048 .device = uart_console_device,
3049 .write = serial_console_write,
3050 .setup = serial_console_setup,
3051 .flags = CON_PRINTBUFFER,
3052 .index = -1,
3053 .data = &sci_uart_driver,
3054 };
3055
3056 #ifdef CONFIG_SUPERH
3057 static struct console early_serial_console = {
3058 .name = "early_ttySC",
3059 .write = serial_console_write,
3060 .flags = CON_PRINTBUFFER,
3061 .index = -1,
3062 };
3063
3064 static char early_serial_buf[32];
3065
sci_probe_earlyprintk(struct platform_device * pdev)3066 static int sci_probe_earlyprintk(struct platform_device *pdev)
3067 {
3068 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3069
3070 if (early_serial_console.data)
3071 return -EEXIST;
3072
3073 early_serial_console.index = pdev->id;
3074
3075 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3076
3077 serial_console_setup(&early_serial_console, early_serial_buf);
3078
3079 if (!strstr(early_serial_buf, "keep"))
3080 early_serial_console.flags |= CON_BOOT;
3081
3082 register_console(&early_serial_console);
3083 return 0;
3084 }
3085 #endif
3086
3087 #define SCI_CONSOLE (&serial_console)
3088
3089 #else
sci_probe_earlyprintk(struct platform_device * pdev)3090 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3091 {
3092 return -EINVAL;
3093 }
3094
3095 #define SCI_CONSOLE NULL
3096
3097 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3098
3099 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3100
3101 static DEFINE_MUTEX(sci_uart_registration_lock);
3102 static struct uart_driver sci_uart_driver = {
3103 .owner = THIS_MODULE,
3104 .driver_name = "sci",
3105 .dev_name = "ttySC",
3106 .major = SCI_MAJOR,
3107 .minor = SCI_MINOR_START,
3108 .nr = SCI_NPORTS,
3109 .cons = SCI_CONSOLE,
3110 };
3111
sci_remove(struct platform_device * dev)3112 static int sci_remove(struct platform_device *dev)
3113 {
3114 struct sci_port *port = platform_get_drvdata(dev);
3115 unsigned int type = port->port.type; /* uart_remove_... clears it */
3116
3117 sci_ports_in_use &= ~BIT(port->port.line);
3118 uart_remove_one_port(&sci_uart_driver, &port->port);
3119
3120 sci_cleanup_single(port);
3121
3122 if (port->port.fifosize > 1)
3123 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3124 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3125 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3126
3127 return 0;
3128 }
3129
3130
3131 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3132 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3133 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3134
3135 static const struct of_device_id of_sci_match[] = {
3136 /* SoC-specific types */
3137 {
3138 .compatible = "renesas,scif-r7s72100",
3139 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3140 },
3141 {
3142 .compatible = "renesas,scif-r7s9210",
3143 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3144 },
3145 {
3146 .compatible = "renesas,scif-r9a07g044",
3147 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3148 },
3149 /* Family-specific types */
3150 {
3151 .compatible = "renesas,rcar-gen1-scif",
3152 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3153 }, {
3154 .compatible = "renesas,rcar-gen2-scif",
3155 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3156 }, {
3157 .compatible = "renesas,rcar-gen3-scif",
3158 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3159 }, {
3160 .compatible = "renesas,rcar-gen4-scif",
3161 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3162 },
3163 /* Generic types */
3164 {
3165 .compatible = "renesas,scif",
3166 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3167 }, {
3168 .compatible = "renesas,scifa",
3169 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3170 }, {
3171 .compatible = "renesas,scifb",
3172 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3173 }, {
3174 .compatible = "renesas,hscif",
3175 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3176 }, {
3177 .compatible = "renesas,sci",
3178 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3179 }, {
3180 /* Terminator */
3181 },
3182 };
3183 MODULE_DEVICE_TABLE(of, of_sci_match);
3184
sci_reset_control_assert(void * data)3185 static void sci_reset_control_assert(void *data)
3186 {
3187 reset_control_assert(data);
3188 }
3189
sci_parse_dt(struct platform_device * pdev,unsigned int * dev_id)3190 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3191 unsigned int *dev_id)
3192 {
3193 struct device_node *np = pdev->dev.of_node;
3194 struct reset_control *rstc;
3195 struct plat_sci_port *p;
3196 struct sci_port *sp;
3197 const void *data;
3198 int id, ret;
3199
3200 if (!IS_ENABLED(CONFIG_OF) || !np)
3201 return ERR_PTR(-EINVAL);
3202
3203 data = of_device_get_match_data(&pdev->dev);
3204
3205 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
3206 if (IS_ERR(rstc))
3207 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc),
3208 "failed to get reset ctrl\n"));
3209
3210 ret = reset_control_deassert(rstc);
3211 if (ret) {
3212 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret);
3213 return ERR_PTR(ret);
3214 }
3215
3216 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc);
3217 if (ret) {
3218 dev_err(&pdev->dev, "failed to register assert devm action, %d\n",
3219 ret);
3220 return ERR_PTR(ret);
3221 }
3222
3223 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3224 if (!p)
3225 return ERR_PTR(-ENOMEM);
3226
3227 /* Get the line number from the aliases node. */
3228 id = of_alias_get_id(np, "serial");
3229 if (id < 0 && ~sci_ports_in_use)
3230 id = ffz(sci_ports_in_use);
3231 if (id < 0) {
3232 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3233 return ERR_PTR(-EINVAL);
3234 }
3235 if (id >= ARRAY_SIZE(sci_ports)) {
3236 dev_err(&pdev->dev, "serial%d out of range\n", id);
3237 return ERR_PTR(-EINVAL);
3238 }
3239
3240 sp = &sci_ports[id];
3241 *dev_id = id;
3242
3243 p->type = SCI_OF_TYPE(data);
3244 p->regtype = SCI_OF_REGTYPE(data);
3245
3246 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3247
3248 return p;
3249 }
3250
sci_probe_single(struct platform_device * dev,unsigned int index,struct plat_sci_port * p,struct sci_port * sciport)3251 static int sci_probe_single(struct platform_device *dev,
3252 unsigned int index,
3253 struct plat_sci_port *p,
3254 struct sci_port *sciport)
3255 {
3256 int ret;
3257
3258 /* Sanity check */
3259 if (unlikely(index >= SCI_NPORTS)) {
3260 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3261 index+1, SCI_NPORTS);
3262 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3263 return -EINVAL;
3264 }
3265 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3266 if (sci_ports_in_use & BIT(index))
3267 return -EBUSY;
3268
3269 mutex_lock(&sci_uart_registration_lock);
3270 if (!sci_uart_driver.state) {
3271 ret = uart_register_driver(&sci_uart_driver);
3272 if (ret) {
3273 mutex_unlock(&sci_uart_registration_lock);
3274 return ret;
3275 }
3276 }
3277 mutex_unlock(&sci_uart_registration_lock);
3278
3279 ret = sci_init_single(dev, sciport, index, p, false);
3280 if (ret)
3281 return ret;
3282
3283 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3284 if (IS_ERR(sciport->gpios))
3285 return PTR_ERR(sciport->gpios);
3286
3287 if (sciport->has_rtscts) {
3288 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3289 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3290 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3291 return -EINVAL;
3292 }
3293 sciport->port.flags |= UPF_HARD_FLOW;
3294 }
3295
3296 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3297 if (ret) {
3298 sci_cleanup_single(sciport);
3299 return ret;
3300 }
3301
3302 return 0;
3303 }
3304
sci_probe(struct platform_device * dev)3305 static int sci_probe(struct platform_device *dev)
3306 {
3307 struct plat_sci_port *p;
3308 struct sci_port *sp;
3309 unsigned int dev_id;
3310 int ret;
3311
3312 /*
3313 * If we've come here via earlyprintk initialization, head off to
3314 * the special early probe. We don't have sufficient device state
3315 * to make it beyond this yet.
3316 */
3317 #ifdef CONFIG_SUPERH
3318 if (is_sh_early_platform_device(dev))
3319 return sci_probe_earlyprintk(dev);
3320 #endif
3321
3322 if (dev->dev.of_node) {
3323 p = sci_parse_dt(dev, &dev_id);
3324 if (IS_ERR(p))
3325 return PTR_ERR(p);
3326 } else {
3327 p = dev->dev.platform_data;
3328 if (p == NULL) {
3329 dev_err(&dev->dev, "no platform data supplied\n");
3330 return -EINVAL;
3331 }
3332
3333 dev_id = dev->id;
3334 }
3335
3336 sp = &sci_ports[dev_id];
3337 platform_set_drvdata(dev, sp);
3338
3339 ret = sci_probe_single(dev, dev_id, p, sp);
3340 if (ret)
3341 return ret;
3342
3343 if (sp->port.fifosize > 1) {
3344 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3345 if (ret)
3346 return ret;
3347 }
3348 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3349 sp->port.type == PORT_HSCIF) {
3350 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3351 if (ret) {
3352 if (sp->port.fifosize > 1) {
3353 device_remove_file(&dev->dev,
3354 &dev_attr_rx_fifo_trigger);
3355 }
3356 return ret;
3357 }
3358 }
3359
3360 #ifdef CONFIG_SH_STANDARD_BIOS
3361 sh_bios_gdb_detach();
3362 #endif
3363
3364 sci_ports_in_use |= BIT(dev_id);
3365 return 0;
3366 }
3367
sci_suspend(struct device * dev)3368 static __maybe_unused int sci_suspend(struct device *dev)
3369 {
3370 struct sci_port *sport = dev_get_drvdata(dev);
3371
3372 if (sport)
3373 uart_suspend_port(&sci_uart_driver, &sport->port);
3374
3375 return 0;
3376 }
3377
sci_resume(struct device * dev)3378 static __maybe_unused int sci_resume(struct device *dev)
3379 {
3380 struct sci_port *sport = dev_get_drvdata(dev);
3381
3382 if (sport)
3383 uart_resume_port(&sci_uart_driver, &sport->port);
3384
3385 return 0;
3386 }
3387
3388 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3389
3390 static struct platform_driver sci_driver = {
3391 .probe = sci_probe,
3392 .remove = sci_remove,
3393 .driver = {
3394 .name = "sh-sci",
3395 .pm = &sci_dev_pm_ops,
3396 .of_match_table = of_match_ptr(of_sci_match),
3397 },
3398 };
3399
sci_init(void)3400 static int __init sci_init(void)
3401 {
3402 pr_info("%s\n", banner);
3403
3404 return platform_driver_register(&sci_driver);
3405 }
3406
sci_exit(void)3407 static void __exit sci_exit(void)
3408 {
3409 platform_driver_unregister(&sci_driver);
3410
3411 if (sci_uart_driver.state)
3412 uart_unregister_driver(&sci_uart_driver);
3413 }
3414
3415 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
3416 sh_early_platform_init_buffer("earlyprintk", &sci_driver,
3417 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3418 #endif
3419 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3420 static struct plat_sci_port port_cfg __initdata;
3421
early_console_setup(struct earlycon_device * device,int type)3422 static int __init early_console_setup(struct earlycon_device *device,
3423 int type)
3424 {
3425 if (!device->port.membase)
3426 return -ENODEV;
3427
3428 device->port.serial_in = sci_serial_in;
3429 device->port.serial_out = sci_serial_out;
3430 device->port.type = type;
3431 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3432 port_cfg.type = type;
3433 sci_ports[0].cfg = &port_cfg;
3434 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3435 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3436 sci_serial_out(&sci_ports[0].port, SCSCR,
3437 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3438
3439 device->con->write = serial_console_write;
3440 return 0;
3441 }
sci_early_console_setup(struct earlycon_device * device,const char * opt)3442 static int __init sci_early_console_setup(struct earlycon_device *device,
3443 const char *opt)
3444 {
3445 return early_console_setup(device, PORT_SCI);
3446 }
scif_early_console_setup(struct earlycon_device * device,const char * opt)3447 static int __init scif_early_console_setup(struct earlycon_device *device,
3448 const char *opt)
3449 {
3450 return early_console_setup(device, PORT_SCIF);
3451 }
rzscifa_early_console_setup(struct earlycon_device * device,const char * opt)3452 static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3453 const char *opt)
3454 {
3455 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3456 return early_console_setup(device, PORT_SCIF);
3457 }
3458
scifa_early_console_setup(struct earlycon_device * device,const char * opt)3459 static int __init scifa_early_console_setup(struct earlycon_device *device,
3460 const char *opt)
3461 {
3462 return early_console_setup(device, PORT_SCIFA);
3463 }
scifb_early_console_setup(struct earlycon_device * device,const char * opt)3464 static int __init scifb_early_console_setup(struct earlycon_device *device,
3465 const char *opt)
3466 {
3467 return early_console_setup(device, PORT_SCIFB);
3468 }
hscif_early_console_setup(struct earlycon_device * device,const char * opt)3469 static int __init hscif_early_console_setup(struct earlycon_device *device,
3470 const char *opt)
3471 {
3472 return early_console_setup(device, PORT_HSCIF);
3473 }
3474
3475 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3476 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3477 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3478 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
3479 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3480 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3481 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3482 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3483
3484 module_init(sci_init);
3485 module_exit(sci_exit);
3486
3487 MODULE_LICENSE("GPL");
3488 MODULE_ALIAS("platform:sh-sci");
3489 MODULE_AUTHOR("Paul Mundt");
3490 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
3491
