1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type PCI serial ports.
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 */
9 #undef DEBUG
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/tty.h>
17 #include <linux/serial_reg.h>
18 #include <linux/serial_core.h>
19 #include <linux/8250_pci.h>
20 #include <linux/bitops.h>
21
22 #include <asm/byteorder.h>
23 #include <asm/io.h>
24
25 #include "8250.h"
26
27 /*
28 * init function returns:
29 * > 0 - number of ports
30 * = 0 - use board->num_ports
31 * < 0 - error
32 */
33 struct pci_serial_quirk {
34 u32 vendor;
35 u32 device;
36 u32 subvendor;
37 u32 subdevice;
38 int (*probe)(struct pci_dev *dev);
39 int (*init)(struct pci_dev *dev);
40 int (*setup)(struct serial_private *,
41 const struct pciserial_board *,
42 struct uart_8250_port *, int);
43 void (*exit)(struct pci_dev *dev);
44 };
45
46 #define PCI_NUM_BAR_RESOURCES 6
47
48 struct serial_private {
49 struct pci_dev *dev;
50 unsigned int nr;
51 struct pci_serial_quirk *quirk;
52 const struct pciserial_board *board;
53 int line[0];
54 };
55
56 static int pci_default_setup(struct serial_private*,
57 const struct pciserial_board*, struct uart_8250_port *, int);
58
moan_device(const char * str,struct pci_dev * dev)59 static void moan_device(const char *str, struct pci_dev *dev)
60 {
61 dev_err(&dev->dev,
62 "%s: %s\n"
63 "Please send the output of lspci -vv, this\n"
64 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
65 "manufacturer and name of serial board or\n"
66 "modem board to <linux-serial@vger.kernel.org>.\n",
67 pci_name(dev), str, dev->vendor, dev->device,
68 dev->subsystem_vendor, dev->subsystem_device);
69 }
70
71 static int
setup_port(struct serial_private * priv,struct uart_8250_port * port,int bar,int offset,int regshift)72 setup_port(struct serial_private *priv, struct uart_8250_port *port,
73 int bar, int offset, int regshift)
74 {
75 struct pci_dev *dev = priv->dev;
76
77 if (bar >= PCI_NUM_BAR_RESOURCES)
78 return -EINVAL;
79
80 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
81 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
82 return -ENOMEM;
83
84 port->port.iotype = UPIO_MEM;
85 port->port.iobase = 0;
86 port->port.mapbase = pci_resource_start(dev, bar) + offset;
87 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
88 port->port.regshift = regshift;
89 } else {
90 port->port.iotype = UPIO_PORT;
91 port->port.iobase = pci_resource_start(dev, bar) + offset;
92 port->port.mapbase = 0;
93 port->port.membase = NULL;
94 port->port.regshift = 0;
95 }
96 return 0;
97 }
98
99 /*
100 * ADDI-DATA GmbH communication cards <info@addi-data.com>
101 */
addidata_apci7800_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)102 static int addidata_apci7800_setup(struct serial_private *priv,
103 const struct pciserial_board *board,
104 struct uart_8250_port *port, int idx)
105 {
106 unsigned int bar = 0, offset = board->first_offset;
107 bar = FL_GET_BASE(board->flags);
108
109 if (idx < 2) {
110 offset += idx * board->uart_offset;
111 } else if ((idx >= 2) && (idx < 4)) {
112 bar += 1;
113 offset += ((idx - 2) * board->uart_offset);
114 } else if ((idx >= 4) && (idx < 6)) {
115 bar += 2;
116 offset += ((idx - 4) * board->uart_offset);
117 } else if (idx >= 6) {
118 bar += 3;
119 offset += ((idx - 6) * board->uart_offset);
120 }
121
122 return setup_port(priv, port, bar, offset, board->reg_shift);
123 }
124
125 /*
126 * AFAVLAB uses a different mixture of BARs and offsets
127 * Not that ugly ;) -- HW
128 */
129 static int
afavlab_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)130 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
131 struct uart_8250_port *port, int idx)
132 {
133 unsigned int bar, offset = board->first_offset;
134
135 bar = FL_GET_BASE(board->flags);
136 if (idx < 4)
137 bar += idx;
138 else {
139 bar = 4;
140 offset += (idx - 4) * board->uart_offset;
141 }
142
143 return setup_port(priv, port, bar, offset, board->reg_shift);
144 }
145
146 /*
147 * HP's Remote Management Console. The Diva chip came in several
148 * different versions. N-class, L2000 and A500 have two Diva chips, each
149 * with 3 UARTs (the third UART on the second chip is unused). Superdome
150 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
151 * one Diva chip, but it has been expanded to 5 UARTs.
152 */
pci_hp_diva_init(struct pci_dev * dev)153 static int pci_hp_diva_init(struct pci_dev *dev)
154 {
155 int rc = 0;
156
157 switch (dev->subsystem_device) {
158 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
159 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
160 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
161 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
162 rc = 3;
163 break;
164 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
165 rc = 2;
166 break;
167 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
168 rc = 4;
169 break;
170 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
171 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
172 rc = 1;
173 break;
174 }
175
176 return rc;
177 }
178
179 /*
180 * HP's Diva chip puts the 4th/5th serial port further out, and
181 * some serial ports are supposed to be hidden on certain models.
182 */
183 static int
pci_hp_diva_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)184 pci_hp_diva_setup(struct serial_private *priv,
185 const struct pciserial_board *board,
186 struct uart_8250_port *port, int idx)
187 {
188 unsigned int offset = board->first_offset;
189 unsigned int bar = FL_GET_BASE(board->flags);
190
191 switch (priv->dev->subsystem_device) {
192 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
193 if (idx == 3)
194 idx++;
195 break;
196 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
197 if (idx > 0)
198 idx++;
199 if (idx > 2)
200 idx++;
201 break;
202 }
203 if (idx > 2)
204 offset = 0x18;
205
206 offset += idx * board->uart_offset;
207
208 return setup_port(priv, port, bar, offset, board->reg_shift);
209 }
210
211 /*
212 * Added for EKF Intel i960 serial boards
213 */
pci_inteli960ni_init(struct pci_dev * dev)214 static int pci_inteli960ni_init(struct pci_dev *dev)
215 {
216 u32 oldval;
217
218 if (!(dev->subsystem_device & 0x1000))
219 return -ENODEV;
220
221 /* is firmware started? */
222 pci_read_config_dword(dev, 0x44, &oldval);
223 if (oldval == 0x00001000L) { /* RESET value */
224 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
225 return -ENODEV;
226 }
227 return 0;
228 }
229
230 /*
231 * Some PCI serial cards using the PLX 9050 PCI interface chip require
232 * that the card interrupt be explicitly enabled or disabled. This
233 * seems to be mainly needed on card using the PLX which also use I/O
234 * mapped memory.
235 */
pci_plx9050_init(struct pci_dev * dev)236 static int pci_plx9050_init(struct pci_dev *dev)
237 {
238 u8 irq_config;
239 void __iomem *p;
240
241 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
242 moan_device("no memory in bar 0", dev);
243 return 0;
244 }
245
246 irq_config = 0x41;
247 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
248 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
249 irq_config = 0x43;
250
251 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
252 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
253 /*
254 * As the megawolf cards have the int pins active
255 * high, and have 2 UART chips, both ints must be
256 * enabled on the 9050. Also, the UARTS are set in
257 * 16450 mode by default, so we have to enable the
258 * 16C950 'enhanced' mode so that we can use the
259 * deep FIFOs
260 */
261 irq_config = 0x5b;
262 /*
263 * enable/disable interrupts
264 */
265 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
266 if (p == NULL)
267 return -ENOMEM;
268 writel(irq_config, p + 0x4c);
269
270 /*
271 * Read the register back to ensure that it took effect.
272 */
273 readl(p + 0x4c);
274 iounmap(p);
275
276 return 0;
277 }
278
pci_plx9050_exit(struct pci_dev * dev)279 static void pci_plx9050_exit(struct pci_dev *dev)
280 {
281 u8 __iomem *p;
282
283 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
284 return;
285
286 /*
287 * disable interrupts
288 */
289 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
290 if (p != NULL) {
291 writel(0, p + 0x4c);
292
293 /*
294 * Read the register back to ensure that it took effect.
295 */
296 readl(p + 0x4c);
297 iounmap(p);
298 }
299 }
300
301 #define NI8420_INT_ENABLE_REG 0x38
302 #define NI8420_INT_ENABLE_BIT 0x2000
303
pci_ni8420_exit(struct pci_dev * dev)304 static void pci_ni8420_exit(struct pci_dev *dev)
305 {
306 void __iomem *p;
307 unsigned int bar = 0;
308
309 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
310 moan_device("no memory in bar", dev);
311 return;
312 }
313
314 p = pci_ioremap_bar(dev, bar);
315 if (p == NULL)
316 return;
317
318 /* Disable the CPU Interrupt */
319 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
320 p + NI8420_INT_ENABLE_REG);
321 iounmap(p);
322 }
323
324
325 /* MITE registers */
326 #define MITE_IOWBSR1 0xc4
327 #define MITE_IOWCR1 0xf4
328 #define MITE_LCIMR1 0x08
329 #define MITE_LCIMR2 0x10
330
331 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
332
pci_ni8430_exit(struct pci_dev * dev)333 static void pci_ni8430_exit(struct pci_dev *dev)
334 {
335 void __iomem *p;
336 unsigned int bar = 0;
337
338 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
339 moan_device("no memory in bar", dev);
340 return;
341 }
342
343 p = pci_ioremap_bar(dev, bar);
344 if (p == NULL)
345 return;
346
347 /* Disable the CPU Interrupt */
348 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
349 iounmap(p);
350 }
351
352 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
353 static int
sbs_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)354 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
355 struct uart_8250_port *port, int idx)
356 {
357 unsigned int bar, offset = board->first_offset;
358
359 bar = 0;
360
361 if (idx < 4) {
362 /* first four channels map to 0, 0x100, 0x200, 0x300 */
363 offset += idx * board->uart_offset;
364 } else if (idx < 8) {
365 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
366 offset += idx * board->uart_offset + 0xC00;
367 } else /* we have only 8 ports on PMC-OCTALPRO */
368 return 1;
369
370 return setup_port(priv, port, bar, offset, board->reg_shift);
371 }
372
373 /*
374 * This does initialization for PMC OCTALPRO cards:
375 * maps the device memory, resets the UARTs (needed, bc
376 * if the module is removed and inserted again, the card
377 * is in the sleep mode) and enables global interrupt.
378 */
379
380 /* global control register offset for SBS PMC-OctalPro */
381 #define OCT_REG_CR_OFF 0x500
382
sbs_init(struct pci_dev * dev)383 static int sbs_init(struct pci_dev *dev)
384 {
385 u8 __iomem *p;
386
387 p = pci_ioremap_bar(dev, 0);
388
389 if (p == NULL)
390 return -ENOMEM;
391 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
392 writeb(0x10, p + OCT_REG_CR_OFF);
393 udelay(50);
394 writeb(0x0, p + OCT_REG_CR_OFF);
395
396 /* Set bit-2 (INTENABLE) of Control Register */
397 writeb(0x4, p + OCT_REG_CR_OFF);
398 iounmap(p);
399
400 return 0;
401 }
402
403 /*
404 * Disables the global interrupt of PMC-OctalPro
405 */
406
sbs_exit(struct pci_dev * dev)407 static void sbs_exit(struct pci_dev *dev)
408 {
409 u8 __iomem *p;
410
411 p = pci_ioremap_bar(dev, 0);
412 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
413 if (p != NULL)
414 writeb(0, p + OCT_REG_CR_OFF);
415 iounmap(p);
416 }
417
418 /*
419 * SIIG serial cards have an PCI interface chip which also controls
420 * the UART clocking frequency. Each UART can be clocked independently
421 * (except cards equipped with 4 UARTs) and initial clocking settings
422 * are stored in the EEPROM chip. It can cause problems because this
423 * version of serial driver doesn't support differently clocked UART's
424 * on single PCI card. To prevent this, initialization functions set
425 * high frequency clocking for all UART's on given card. It is safe (I
426 * hope) because it doesn't touch EEPROM settings to prevent conflicts
427 * with other OSes (like M$ DOS).
428 *
429 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
430 *
431 * There is two family of SIIG serial cards with different PCI
432 * interface chip and different configuration methods:
433 * - 10x cards have control registers in IO and/or memory space;
434 * - 20x cards have control registers in standard PCI configuration space.
435 *
436 * Note: all 10x cards have PCI device ids 0x10..
437 * all 20x cards have PCI device ids 0x20..
438 *
439 * There are also Quartet Serial cards which use Oxford Semiconductor
440 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
441 *
442 * Note: some SIIG cards are probed by the parport_serial object.
443 */
444
445 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
446 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
447
pci_siig10x_init(struct pci_dev * dev)448 static int pci_siig10x_init(struct pci_dev *dev)
449 {
450 u16 data;
451 void __iomem *p;
452
453 switch (dev->device & 0xfff8) {
454 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
455 data = 0xffdf;
456 break;
457 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
458 data = 0xf7ff;
459 break;
460 default: /* 1S1P, 4S */
461 data = 0xfffb;
462 break;
463 }
464
465 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
466 if (p == NULL)
467 return -ENOMEM;
468
469 writew(readw(p + 0x28) & data, p + 0x28);
470 readw(p + 0x28);
471 iounmap(p);
472 return 0;
473 }
474
475 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
476 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
477
pci_siig20x_init(struct pci_dev * dev)478 static int pci_siig20x_init(struct pci_dev *dev)
479 {
480 u8 data;
481
482 /* Change clock frequency for the first UART. */
483 pci_read_config_byte(dev, 0x6f, &data);
484 pci_write_config_byte(dev, 0x6f, data & 0xef);
485
486 /* If this card has 2 UART, we have to do the same with second UART. */
487 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
488 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
489 pci_read_config_byte(dev, 0x73, &data);
490 pci_write_config_byte(dev, 0x73, data & 0xef);
491 }
492 return 0;
493 }
494
pci_siig_init(struct pci_dev * dev)495 static int pci_siig_init(struct pci_dev *dev)
496 {
497 unsigned int type = dev->device & 0xff00;
498
499 if (type == 0x1000)
500 return pci_siig10x_init(dev);
501 else if (type == 0x2000)
502 return pci_siig20x_init(dev);
503
504 moan_device("Unknown SIIG card", dev);
505 return -ENODEV;
506 }
507
pci_siig_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)508 static int pci_siig_setup(struct serial_private *priv,
509 const struct pciserial_board *board,
510 struct uart_8250_port *port, int idx)
511 {
512 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
513
514 if (idx > 3) {
515 bar = 4;
516 offset = (idx - 4) * 8;
517 }
518
519 return setup_port(priv, port, bar, offset, 0);
520 }
521
522 /*
523 * Timedia has an explosion of boards, and to avoid the PCI table from
524 * growing *huge*, we use this function to collapse some 70 entries
525 * in the PCI table into one, for sanity's and compactness's sake.
526 */
527 static const unsigned short timedia_single_port[] = {
528 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
529 };
530
531 static const unsigned short timedia_dual_port[] = {
532 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
533 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
534 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
535 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
536 0xD079, 0
537 };
538
539 static const unsigned short timedia_quad_port[] = {
540 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
541 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
542 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
543 0xB157, 0
544 };
545
546 static const unsigned short timedia_eight_port[] = {
547 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
548 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
549 };
550
551 static const struct timedia_struct {
552 int num;
553 const unsigned short *ids;
554 } timedia_data[] = {
555 { 1, timedia_single_port },
556 { 2, timedia_dual_port },
557 { 4, timedia_quad_port },
558 { 8, timedia_eight_port }
559 };
560
561 /*
562 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
563 * listing them individually, this driver merely grabs them all with
564 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
565 * and should be left free to be claimed by parport_serial instead.
566 */
pci_timedia_probe(struct pci_dev * dev)567 static int pci_timedia_probe(struct pci_dev *dev)
568 {
569 /*
570 * Check the third digit of the subdevice ID
571 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
572 */
573 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
574 dev_info(&dev->dev,
575 "ignoring Timedia subdevice %04x for parport_serial\n",
576 dev->subsystem_device);
577 return -ENODEV;
578 }
579
580 return 0;
581 }
582
pci_timedia_init(struct pci_dev * dev)583 static int pci_timedia_init(struct pci_dev *dev)
584 {
585 const unsigned short *ids;
586 int i, j;
587
588 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
589 ids = timedia_data[i].ids;
590 for (j = 0; ids[j]; j++)
591 if (dev->subsystem_device == ids[j])
592 return timedia_data[i].num;
593 }
594 return 0;
595 }
596
597 /*
598 * Timedia/SUNIX uses a mixture of BARs and offsets
599 * Ugh, this is ugly as all hell --- TYT
600 */
601 static int
pci_timedia_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)602 pci_timedia_setup(struct serial_private *priv,
603 const struct pciserial_board *board,
604 struct uart_8250_port *port, int idx)
605 {
606 unsigned int bar = 0, offset = board->first_offset;
607
608 switch (idx) {
609 case 0:
610 bar = 0;
611 break;
612 case 1:
613 offset = board->uart_offset;
614 bar = 0;
615 break;
616 case 2:
617 bar = 1;
618 break;
619 case 3:
620 offset = board->uart_offset;
621 /* FALLTHROUGH */
622 case 4: /* BAR 2 */
623 case 5: /* BAR 3 */
624 case 6: /* BAR 4 */
625 case 7: /* BAR 5 */
626 bar = idx - 2;
627 }
628
629 return setup_port(priv, port, bar, offset, board->reg_shift);
630 }
631
632 /*
633 * Some Titan cards are also a little weird
634 */
635 static int
titan_400l_800l_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)636 titan_400l_800l_setup(struct serial_private *priv,
637 const struct pciserial_board *board,
638 struct uart_8250_port *port, int idx)
639 {
640 unsigned int bar, offset = board->first_offset;
641
642 switch (idx) {
643 case 0:
644 bar = 1;
645 break;
646 case 1:
647 bar = 2;
648 break;
649 default:
650 bar = 4;
651 offset = (idx - 2) * board->uart_offset;
652 }
653
654 return setup_port(priv, port, bar, offset, board->reg_shift);
655 }
656
pci_xircom_init(struct pci_dev * dev)657 static int pci_xircom_init(struct pci_dev *dev)
658 {
659 msleep(100);
660 return 0;
661 }
662
pci_ni8420_init(struct pci_dev * dev)663 static int pci_ni8420_init(struct pci_dev *dev)
664 {
665 void __iomem *p;
666 unsigned int bar = 0;
667
668 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
669 moan_device("no memory in bar", dev);
670 return 0;
671 }
672
673 p = pci_ioremap_bar(dev, bar);
674 if (p == NULL)
675 return -ENOMEM;
676
677 /* Enable CPU Interrupt */
678 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
679 p + NI8420_INT_ENABLE_REG);
680
681 iounmap(p);
682 return 0;
683 }
684
685 #define MITE_IOWBSR1_WSIZE 0xa
686 #define MITE_IOWBSR1_WIN_OFFSET 0x800
687 #define MITE_IOWBSR1_WENAB (1 << 7)
688 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
689 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
690 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
691
pci_ni8430_init(struct pci_dev * dev)692 static int pci_ni8430_init(struct pci_dev *dev)
693 {
694 void __iomem *p;
695 struct pci_bus_region region;
696 u32 device_window;
697 unsigned int bar = 0;
698
699 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
700 moan_device("no memory in bar", dev);
701 return 0;
702 }
703
704 p = pci_ioremap_bar(dev, bar);
705 if (p == NULL)
706 return -ENOMEM;
707
708 /*
709 * Set device window address and size in BAR0, while acknowledging that
710 * the resource structure may contain a translated address that differs
711 * from the address the device responds to.
712 */
713 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
714 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
715 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
716 writel(device_window, p + MITE_IOWBSR1);
717
718 /* Set window access to go to RAMSEL IO address space */
719 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
720 p + MITE_IOWCR1);
721
722 /* Enable IO Bus Interrupt 0 */
723 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
724
725 /* Enable CPU Interrupt */
726 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
727
728 iounmap(p);
729 return 0;
730 }
731
732 /* UART Port Control Register */
733 #define NI8430_PORTCON 0x0f
734 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
735
736 static int
pci_ni8430_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)737 pci_ni8430_setup(struct serial_private *priv,
738 const struct pciserial_board *board,
739 struct uart_8250_port *port, int idx)
740 {
741 struct pci_dev *dev = priv->dev;
742 void __iomem *p;
743 unsigned int bar, offset = board->first_offset;
744
745 if (idx >= board->num_ports)
746 return 1;
747
748 bar = FL_GET_BASE(board->flags);
749 offset += idx * board->uart_offset;
750
751 p = pci_ioremap_bar(dev, bar);
752 if (!p)
753 return -ENOMEM;
754
755 /* enable the transceiver */
756 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
757 p + offset + NI8430_PORTCON);
758
759 iounmap(p);
760
761 return setup_port(priv, port, bar, offset, board->reg_shift);
762 }
763
pci_netmos_9900_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)764 static int pci_netmos_9900_setup(struct serial_private *priv,
765 const struct pciserial_board *board,
766 struct uart_8250_port *port, int idx)
767 {
768 unsigned int bar;
769
770 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
771 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
772 /* netmos apparently orders BARs by datasheet layout, so serial
773 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
774 */
775 bar = 3 * idx;
776
777 return setup_port(priv, port, bar, 0, board->reg_shift);
778 } else {
779 return pci_default_setup(priv, board, port, idx);
780 }
781 }
782
783 /* the 99xx series comes with a range of device IDs and a variety
784 * of capabilities:
785 *
786 * 9900 has varying capabilities and can cascade to sub-controllers
787 * (cascading should be purely internal)
788 * 9904 is hardwired with 4 serial ports
789 * 9912 and 9922 are hardwired with 2 serial ports
790 */
pci_netmos_9900_numports(struct pci_dev * dev)791 static int pci_netmos_9900_numports(struct pci_dev *dev)
792 {
793 unsigned int c = dev->class;
794 unsigned int pi;
795 unsigned short sub_serports;
796
797 pi = c & 0xff;
798
799 if (pi == 2)
800 return 1;
801
802 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
803 /* two possibilities: 0x30ps encodes number of parallel and
804 * serial ports, or 0x1000 indicates *something*. This is not
805 * immediately obvious, since the 2s1p+4s configuration seems
806 * to offer all functionality on functions 0..2, while still
807 * advertising the same function 3 as the 4s+2s1p config.
808 */
809 sub_serports = dev->subsystem_device & 0xf;
810 if (sub_serports > 0)
811 return sub_serports;
812
813 dev_err(&dev->dev,
814 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
815 return 0;
816 }
817
818 moan_device("unknown NetMos/Mostech program interface", dev);
819 return 0;
820 }
821
pci_netmos_init(struct pci_dev * dev)822 static int pci_netmos_init(struct pci_dev *dev)
823 {
824 /* subdevice 0x00PS means <P> parallel, <S> serial */
825 unsigned int num_serial = dev->subsystem_device & 0xf;
826
827 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
828 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
829 return 0;
830
831 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
832 dev->subsystem_device == 0x0299)
833 return 0;
834
835 switch (dev->device) { /* FALLTHROUGH on all */
836 case PCI_DEVICE_ID_NETMOS_9904:
837 case PCI_DEVICE_ID_NETMOS_9912:
838 case PCI_DEVICE_ID_NETMOS_9922:
839 case PCI_DEVICE_ID_NETMOS_9900:
840 num_serial = pci_netmos_9900_numports(dev);
841 break;
842
843 default:
844 break;
845 }
846
847 if (num_serial == 0) {
848 moan_device("unknown NetMos/Mostech device", dev);
849 return -ENODEV;
850 }
851
852 return num_serial;
853 }
854
855 /*
856 * These chips are available with optionally one parallel port and up to
857 * two serial ports. Unfortunately they all have the same product id.
858 *
859 * Basic configuration is done over a region of 32 I/O ports. The base
860 * ioport is called INTA or INTC, depending on docs/other drivers.
861 *
862 * The region of the 32 I/O ports is configured in POSIO0R...
863 */
864
865 /* registers */
866 #define ITE_887x_MISCR 0x9c
867 #define ITE_887x_INTCBAR 0x78
868 #define ITE_887x_UARTBAR 0x7c
869 #define ITE_887x_PS0BAR 0x10
870 #define ITE_887x_POSIO0 0x60
871
872 /* I/O space size */
873 #define ITE_887x_IOSIZE 32
874 /* I/O space size (bits 26-24; 8 bytes = 011b) */
875 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
876 /* I/O space size (bits 26-24; 32 bytes = 101b) */
877 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
878 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
879 #define ITE_887x_POSIO_SPEED (3 << 29)
880 /* enable IO_Space bit */
881 #define ITE_887x_POSIO_ENABLE (1 << 31)
882
pci_ite887x_init(struct pci_dev * dev)883 static int pci_ite887x_init(struct pci_dev *dev)
884 {
885 /* inta_addr are the configuration addresses of the ITE */
886 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
887 0x200, 0x280, 0 };
888 int ret, i, type;
889 struct resource *iobase = NULL;
890 u32 miscr, uartbar, ioport;
891
892 /* search for the base-ioport */
893 i = 0;
894 while (inta_addr[i] && iobase == NULL) {
895 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
896 "ite887x");
897 if (iobase != NULL) {
898 /* write POSIO0R - speed | size | ioport */
899 pci_write_config_dword(dev, ITE_887x_POSIO0,
900 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
901 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
902 /* write INTCBAR - ioport */
903 pci_write_config_dword(dev, ITE_887x_INTCBAR,
904 inta_addr[i]);
905 ret = inb(inta_addr[i]);
906 if (ret != 0xff) {
907 /* ioport connected */
908 break;
909 }
910 release_region(iobase->start, ITE_887x_IOSIZE);
911 iobase = NULL;
912 }
913 i++;
914 }
915
916 if (!inta_addr[i]) {
917 dev_err(&dev->dev, "ite887x: could not find iobase\n");
918 return -ENODEV;
919 }
920
921 /* start of undocumented type checking (see parport_pc.c) */
922 type = inb(iobase->start + 0x18) & 0x0f;
923
924 switch (type) {
925 case 0x2: /* ITE8871 (1P) */
926 case 0xa: /* ITE8875 (1P) */
927 ret = 0;
928 break;
929 case 0xe: /* ITE8872 (2S1P) */
930 ret = 2;
931 break;
932 case 0x6: /* ITE8873 (1S) */
933 ret = 1;
934 break;
935 case 0x8: /* ITE8874 (2S) */
936 ret = 2;
937 break;
938 default:
939 moan_device("Unknown ITE887x", dev);
940 ret = -ENODEV;
941 }
942
943 /* configure all serial ports */
944 for (i = 0; i < ret; i++) {
945 /* read the I/O port from the device */
946 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
947 &ioport);
948 ioport &= 0x0000FF00; /* the actual base address */
949 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
950 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
951 ITE_887x_POSIO_IOSIZE_8 | ioport);
952
953 /* write the ioport to the UARTBAR */
954 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
955 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
956 uartbar |= (ioport << (16 * i)); /* set the ioport */
957 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
958
959 /* get current config */
960 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
961 /* disable interrupts (UARTx_Routing[3:0]) */
962 miscr &= ~(0xf << (12 - 4 * i));
963 /* activate the UART (UARTx_En) */
964 miscr |= 1 << (23 - i);
965 /* write new config with activated UART */
966 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
967 }
968
969 if (ret <= 0) {
970 /* the device has no UARTs if we get here */
971 release_region(iobase->start, ITE_887x_IOSIZE);
972 }
973
974 return ret;
975 }
976
pci_ite887x_exit(struct pci_dev * dev)977 static void pci_ite887x_exit(struct pci_dev *dev)
978 {
979 u32 ioport;
980 /* the ioport is bit 0-15 in POSIO0R */
981 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
982 ioport &= 0xffff;
983 release_region(ioport, ITE_887x_IOSIZE);
984 }
985
986 /*
987 * EndRun Technologies.
988 * Determine the number of ports available on the device.
989 */
990 #define PCI_VENDOR_ID_ENDRUN 0x7401
991 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
992
pci_endrun_init(struct pci_dev * dev)993 static int pci_endrun_init(struct pci_dev *dev)
994 {
995 u8 __iomem *p;
996 unsigned long deviceID;
997 unsigned int number_uarts = 0;
998
999 /* EndRun device is all 0xexxx */
1000 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1001 (dev->device & 0xf000) != 0xe000)
1002 return 0;
1003
1004 p = pci_iomap(dev, 0, 5);
1005 if (p == NULL)
1006 return -ENOMEM;
1007
1008 deviceID = ioread32(p);
1009 /* EndRun device */
1010 if (deviceID == 0x07000200) {
1011 number_uarts = ioread8(p + 4);
1012 dev_dbg(&dev->dev,
1013 "%d ports detected on EndRun PCI Express device\n",
1014 number_uarts);
1015 }
1016 pci_iounmap(dev, p);
1017 return number_uarts;
1018 }
1019
1020 /*
1021 * Oxford Semiconductor Inc.
1022 * Check that device is part of the Tornado range of devices, then determine
1023 * the number of ports available on the device.
1024 */
pci_oxsemi_tornado_init(struct pci_dev * dev)1025 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1026 {
1027 u8 __iomem *p;
1028 unsigned long deviceID;
1029 unsigned int number_uarts = 0;
1030
1031 /* OxSemi Tornado devices are all 0xCxxx */
1032 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1033 (dev->device & 0xF000) != 0xC000)
1034 return 0;
1035
1036 p = pci_iomap(dev, 0, 5);
1037 if (p == NULL)
1038 return -ENOMEM;
1039
1040 deviceID = ioread32(p);
1041 /* Tornado device */
1042 if (deviceID == 0x07000200) {
1043 number_uarts = ioread8(p + 4);
1044 dev_dbg(&dev->dev,
1045 "%d ports detected on Oxford PCI Express device\n",
1046 number_uarts);
1047 }
1048 pci_iounmap(dev, p);
1049 return number_uarts;
1050 }
1051
pci_asix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1052 static int pci_asix_setup(struct serial_private *priv,
1053 const struct pciserial_board *board,
1054 struct uart_8250_port *port, int idx)
1055 {
1056 port->bugs |= UART_BUG_PARITY;
1057 return pci_default_setup(priv, board, port, idx);
1058 }
1059
1060 /* Quatech devices have their own extra interface features */
1061
1062 struct quatech_feature {
1063 u16 devid;
1064 bool amcc;
1065 };
1066
1067 #define QPCR_TEST_FOR1 0x3F
1068 #define QPCR_TEST_GET1 0x00
1069 #define QPCR_TEST_FOR2 0x40
1070 #define QPCR_TEST_GET2 0x40
1071 #define QPCR_TEST_FOR3 0x80
1072 #define QPCR_TEST_GET3 0x40
1073 #define QPCR_TEST_FOR4 0xC0
1074 #define QPCR_TEST_GET4 0x80
1075
1076 #define QOPR_CLOCK_X1 0x0000
1077 #define QOPR_CLOCK_X2 0x0001
1078 #define QOPR_CLOCK_X4 0x0002
1079 #define QOPR_CLOCK_X8 0x0003
1080 #define QOPR_CLOCK_RATE_MASK 0x0003
1081
1082
1083 static struct quatech_feature quatech_cards[] = {
1084 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1085 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1086 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1087 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1088 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1089 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1090 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1091 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1092 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1093 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1094 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1095 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1096 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1097 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1098 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1099 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1100 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1101 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1102 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1103 { 0, }
1104 };
1105
pci_quatech_amcc(u16 devid)1106 static int pci_quatech_amcc(u16 devid)
1107 {
1108 struct quatech_feature *qf = &quatech_cards[0];
1109 while (qf->devid) {
1110 if (qf->devid == devid)
1111 return qf->amcc;
1112 qf++;
1113 }
1114 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1115 return 0;
1116 };
1117
pci_quatech_rqopr(struct uart_8250_port * port)1118 static int pci_quatech_rqopr(struct uart_8250_port *port)
1119 {
1120 unsigned long base = port->port.iobase;
1121 u8 LCR, val;
1122
1123 LCR = inb(base + UART_LCR);
1124 outb(0xBF, base + UART_LCR);
1125 val = inb(base + UART_SCR);
1126 outb(LCR, base + UART_LCR);
1127 return val;
1128 }
1129
pci_quatech_wqopr(struct uart_8250_port * port,u8 qopr)1130 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1131 {
1132 unsigned long base = port->port.iobase;
1133 u8 LCR;
1134
1135 LCR = inb(base + UART_LCR);
1136 outb(0xBF, base + UART_LCR);
1137 inb(base + UART_SCR);
1138 outb(qopr, base + UART_SCR);
1139 outb(LCR, base + UART_LCR);
1140 }
1141
pci_quatech_rqmcr(struct uart_8250_port * port)1142 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1143 {
1144 unsigned long base = port->port.iobase;
1145 u8 LCR, val, qmcr;
1146
1147 LCR = inb(base + UART_LCR);
1148 outb(0xBF, base + UART_LCR);
1149 val = inb(base + UART_SCR);
1150 outb(val | 0x10, base + UART_SCR);
1151 qmcr = inb(base + UART_MCR);
1152 outb(val, base + UART_SCR);
1153 outb(LCR, base + UART_LCR);
1154
1155 return qmcr;
1156 }
1157
pci_quatech_wqmcr(struct uart_8250_port * port,u8 qmcr)1158 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1159 {
1160 unsigned long base = port->port.iobase;
1161 u8 LCR, val;
1162
1163 LCR = inb(base + UART_LCR);
1164 outb(0xBF, base + UART_LCR);
1165 val = inb(base + UART_SCR);
1166 outb(val | 0x10, base + UART_SCR);
1167 outb(qmcr, base + UART_MCR);
1168 outb(val, base + UART_SCR);
1169 outb(LCR, base + UART_LCR);
1170 }
1171
pci_quatech_has_qmcr(struct uart_8250_port * port)1172 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1173 {
1174 unsigned long base = port->port.iobase;
1175 u8 LCR, val;
1176
1177 LCR = inb(base + UART_LCR);
1178 outb(0xBF, base + UART_LCR);
1179 val = inb(base + UART_SCR);
1180 if (val & 0x20) {
1181 outb(0x80, UART_LCR);
1182 if (!(inb(UART_SCR) & 0x20)) {
1183 outb(LCR, base + UART_LCR);
1184 return 1;
1185 }
1186 }
1187 return 0;
1188 }
1189
pci_quatech_test(struct uart_8250_port * port)1190 static int pci_quatech_test(struct uart_8250_port *port)
1191 {
1192 u8 reg, qopr;
1193
1194 qopr = pci_quatech_rqopr(port);
1195 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1196 reg = pci_quatech_rqopr(port) & 0xC0;
1197 if (reg != QPCR_TEST_GET1)
1198 return -EINVAL;
1199 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1200 reg = pci_quatech_rqopr(port) & 0xC0;
1201 if (reg != QPCR_TEST_GET2)
1202 return -EINVAL;
1203 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1204 reg = pci_quatech_rqopr(port) & 0xC0;
1205 if (reg != QPCR_TEST_GET3)
1206 return -EINVAL;
1207 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1208 reg = pci_quatech_rqopr(port) & 0xC0;
1209 if (reg != QPCR_TEST_GET4)
1210 return -EINVAL;
1211
1212 pci_quatech_wqopr(port, qopr);
1213 return 0;
1214 }
1215
pci_quatech_clock(struct uart_8250_port * port)1216 static int pci_quatech_clock(struct uart_8250_port *port)
1217 {
1218 u8 qopr, reg, set;
1219 unsigned long clock;
1220
1221 if (pci_quatech_test(port) < 0)
1222 return 1843200;
1223
1224 qopr = pci_quatech_rqopr(port);
1225
1226 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1227 reg = pci_quatech_rqopr(port);
1228 if (reg & QOPR_CLOCK_X8) {
1229 clock = 1843200;
1230 goto out;
1231 }
1232 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1233 reg = pci_quatech_rqopr(port);
1234 if (!(reg & QOPR_CLOCK_X8)) {
1235 clock = 1843200;
1236 goto out;
1237 }
1238 reg &= QOPR_CLOCK_X8;
1239 if (reg == QOPR_CLOCK_X2) {
1240 clock = 3685400;
1241 set = QOPR_CLOCK_X2;
1242 } else if (reg == QOPR_CLOCK_X4) {
1243 clock = 7372800;
1244 set = QOPR_CLOCK_X4;
1245 } else if (reg == QOPR_CLOCK_X8) {
1246 clock = 14745600;
1247 set = QOPR_CLOCK_X8;
1248 } else {
1249 clock = 1843200;
1250 set = QOPR_CLOCK_X1;
1251 }
1252 qopr &= ~QOPR_CLOCK_RATE_MASK;
1253 qopr |= set;
1254
1255 out:
1256 pci_quatech_wqopr(port, qopr);
1257 return clock;
1258 }
1259
pci_quatech_rs422(struct uart_8250_port * port)1260 static int pci_quatech_rs422(struct uart_8250_port *port)
1261 {
1262 u8 qmcr;
1263 int rs422 = 0;
1264
1265 if (!pci_quatech_has_qmcr(port))
1266 return 0;
1267 qmcr = pci_quatech_rqmcr(port);
1268 pci_quatech_wqmcr(port, 0xFF);
1269 if (pci_quatech_rqmcr(port))
1270 rs422 = 1;
1271 pci_quatech_wqmcr(port, qmcr);
1272 return rs422;
1273 }
1274
pci_quatech_init(struct pci_dev * dev)1275 static int pci_quatech_init(struct pci_dev *dev)
1276 {
1277 if (pci_quatech_amcc(dev->device)) {
1278 unsigned long base = pci_resource_start(dev, 0);
1279 if (base) {
1280 u32 tmp;
1281
1282 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1283 tmp = inl(base + 0x3c);
1284 outl(tmp | 0x01000000, base + 0x3c);
1285 outl(tmp &= ~0x01000000, base + 0x3c);
1286 }
1287 }
1288 return 0;
1289 }
1290
pci_quatech_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1291 static int pci_quatech_setup(struct serial_private *priv,
1292 const struct pciserial_board *board,
1293 struct uart_8250_port *port, int idx)
1294 {
1295 /* Needed by pci_quatech calls below */
1296 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1297 /* Set up the clocking */
1298 port->port.uartclk = pci_quatech_clock(port);
1299 /* For now just warn about RS422 */
1300 if (pci_quatech_rs422(port))
1301 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1302 return pci_default_setup(priv, board, port, idx);
1303 }
1304
pci_quatech_exit(struct pci_dev * dev)1305 static void pci_quatech_exit(struct pci_dev *dev)
1306 {
1307 }
1308
pci_default_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1309 static int pci_default_setup(struct serial_private *priv,
1310 const struct pciserial_board *board,
1311 struct uart_8250_port *port, int idx)
1312 {
1313 unsigned int bar, offset = board->first_offset, maxnr;
1314
1315 bar = FL_GET_BASE(board->flags);
1316 if (board->flags & FL_BASE_BARS)
1317 bar += idx;
1318 else
1319 offset += idx * board->uart_offset;
1320
1321 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1322 (board->reg_shift + 3);
1323
1324 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1325 return 1;
1326
1327 return setup_port(priv, port, bar, offset, board->reg_shift);
1328 }
1329
pci_pericom_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1330 static int pci_pericom_setup(struct serial_private *priv,
1331 const struct pciserial_board *board,
1332 struct uart_8250_port *port, int idx)
1333 {
1334 unsigned int bar, offset = board->first_offset, maxnr;
1335
1336 bar = FL_GET_BASE(board->flags);
1337 if (board->flags & FL_BASE_BARS)
1338 bar += idx;
1339 else
1340 offset += idx * board->uart_offset;
1341
1342 if (idx==3)
1343 offset = 0x38;
1344
1345 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1346 (board->reg_shift + 3);
1347
1348 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1349 return 1;
1350
1351 return setup_port(priv, port, bar, offset, board->reg_shift);
1352 }
1353
1354 static int
ce4100_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1355 ce4100_serial_setup(struct serial_private *priv,
1356 const struct pciserial_board *board,
1357 struct uart_8250_port *port, int idx)
1358 {
1359 int ret;
1360
1361 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1362 port->port.iotype = UPIO_MEM32;
1363 port->port.type = PORT_XSCALE;
1364 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1365 port->port.regshift = 2;
1366
1367 return ret;
1368 }
1369
1370 static int
pci_omegapci_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1371 pci_omegapci_setup(struct serial_private *priv,
1372 const struct pciserial_board *board,
1373 struct uart_8250_port *port, int idx)
1374 {
1375 return setup_port(priv, port, 2, idx * 8, 0);
1376 }
1377
1378 static int
pci_brcm_trumanage_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1379 pci_brcm_trumanage_setup(struct serial_private *priv,
1380 const struct pciserial_board *board,
1381 struct uart_8250_port *port, int idx)
1382 {
1383 int ret = pci_default_setup(priv, board, port, idx);
1384
1385 port->port.type = PORT_BRCM_TRUMANAGE;
1386 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1387 return ret;
1388 }
1389
1390 /* RTS will control by MCR if this bit is 0 */
1391 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1392 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1393 #define FINTEK_RTS_INVERT BIT(5)
1394
1395 /* We should do proper H/W transceiver setting before change to RS485 mode */
pci_fintek_rs485_config(struct uart_port * port,struct serial_rs485 * rs485)1396 static int pci_fintek_rs485_config(struct uart_port *port,
1397 struct serial_rs485 *rs485)
1398 {
1399 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1400 u8 setting;
1401 u8 *index = (u8 *) port->private_data;
1402
1403 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1404
1405 if (!rs485)
1406 rs485 = &port->rs485;
1407 else if (rs485->flags & SER_RS485_ENABLED)
1408 memset(rs485->padding, 0, sizeof(rs485->padding));
1409 else
1410 memset(rs485, 0, sizeof(*rs485));
1411
1412 /* F81504/508/512 not support RTS delay before or after send */
1413 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1414
1415 if (rs485->flags & SER_RS485_ENABLED) {
1416 /* Enable RTS H/W control mode */
1417 setting |= FINTEK_RTS_CONTROL_BY_HW;
1418
1419 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1420 /* RTS driving high on TX */
1421 setting &= ~FINTEK_RTS_INVERT;
1422 } else {
1423 /* RTS driving low on TX */
1424 setting |= FINTEK_RTS_INVERT;
1425 }
1426
1427 rs485->delay_rts_after_send = 0;
1428 rs485->delay_rts_before_send = 0;
1429 } else {
1430 /* Disable RTS H/W control mode */
1431 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1432 }
1433
1434 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1435
1436 if (rs485 != &port->rs485)
1437 port->rs485 = *rs485;
1438
1439 return 0;
1440 }
1441
pci_fintek_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1442 static int pci_fintek_setup(struct serial_private *priv,
1443 const struct pciserial_board *board,
1444 struct uart_8250_port *port, int idx)
1445 {
1446 struct pci_dev *pdev = priv->dev;
1447 u8 *data;
1448 u8 config_base;
1449 u16 iobase;
1450
1451 config_base = 0x40 + 0x08 * idx;
1452
1453 /* Get the io address from configuration space */
1454 pci_read_config_word(pdev, config_base + 4, &iobase);
1455
1456 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1457
1458 port->port.iotype = UPIO_PORT;
1459 port->port.iobase = iobase;
1460 port->port.rs485_config = pci_fintek_rs485_config;
1461
1462 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1463 if (!data)
1464 return -ENOMEM;
1465
1466 /* preserve index in PCI configuration space */
1467 *data = idx;
1468 port->port.private_data = data;
1469
1470 return 0;
1471 }
1472
pci_fintek_init(struct pci_dev * dev)1473 static int pci_fintek_init(struct pci_dev *dev)
1474 {
1475 unsigned long iobase;
1476 u32 max_port, i;
1477 resource_size_t bar_data[3];
1478 u8 config_base;
1479 struct serial_private *priv = pci_get_drvdata(dev);
1480 struct uart_8250_port *port;
1481
1482 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1483 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1484 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1485 return -ENODEV;
1486
1487 switch (dev->device) {
1488 case 0x1104: /* 4 ports */
1489 case 0x1108: /* 8 ports */
1490 max_port = dev->device & 0xff;
1491 break;
1492 case 0x1112: /* 12 ports */
1493 max_port = 12;
1494 break;
1495 default:
1496 return -EINVAL;
1497 }
1498
1499 /* Get the io address dispatch from the BIOS */
1500 bar_data[0] = pci_resource_start(dev, 5);
1501 bar_data[1] = pci_resource_start(dev, 4);
1502 bar_data[2] = pci_resource_start(dev, 3);
1503
1504 for (i = 0; i < max_port; ++i) {
1505 /* UART0 configuration offset start from 0x40 */
1506 config_base = 0x40 + 0x08 * i;
1507
1508 /* Calculate Real IO Port */
1509 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1510
1511 /* Enable UART I/O port */
1512 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1513
1514 /* Select 128-byte FIFO and 8x FIFO threshold */
1515 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1516
1517 /* LSB UART */
1518 pci_write_config_byte(dev, config_base + 0x04,
1519 (u8)(iobase & 0xff));
1520
1521 /* MSB UART */
1522 pci_write_config_byte(dev, config_base + 0x05,
1523 (u8)((iobase & 0xff00) >> 8));
1524
1525 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1526
1527 if (priv) {
1528 /* re-apply RS232/485 mode when
1529 * pciserial_resume_ports()
1530 */
1531 port = serial8250_get_port(priv->line[i]);
1532 pci_fintek_rs485_config(&port->port, NULL);
1533 } else {
1534 /* First init without port data
1535 * force init to RS232 Mode
1536 */
1537 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1538 }
1539 }
1540
1541 return max_port;
1542 }
1543
skip_tx_en_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1544 static int skip_tx_en_setup(struct serial_private *priv,
1545 const struct pciserial_board *board,
1546 struct uart_8250_port *port, int idx)
1547 {
1548 port->port.quirks |= UPQ_NO_TXEN_TEST;
1549 dev_dbg(&priv->dev->dev,
1550 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1551 priv->dev->vendor, priv->dev->device,
1552 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1553
1554 return pci_default_setup(priv, board, port, idx);
1555 }
1556
kt_handle_break(struct uart_port * p)1557 static void kt_handle_break(struct uart_port *p)
1558 {
1559 struct uart_8250_port *up = up_to_u8250p(p);
1560 /*
1561 * On receipt of a BI, serial device in Intel ME (Intel
1562 * management engine) needs to have its fifos cleared for sane
1563 * SOL (Serial Over Lan) output.
1564 */
1565 serial8250_clear_and_reinit_fifos(up);
1566 }
1567
kt_serial_in(struct uart_port * p,int offset)1568 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1569 {
1570 struct uart_8250_port *up = up_to_u8250p(p);
1571 unsigned int val;
1572
1573 /*
1574 * When the Intel ME (management engine) gets reset its serial
1575 * port registers could return 0 momentarily. Functions like
1576 * serial8250_console_write, read and save the IER, perform
1577 * some operation and then restore it. In order to avoid
1578 * setting IER register inadvertently to 0, if the value read
1579 * is 0, double check with ier value in uart_8250_port and use
1580 * that instead. up->ier should be the same value as what is
1581 * currently configured.
1582 */
1583 val = inb(p->iobase + offset);
1584 if (offset == UART_IER) {
1585 if (val == 0)
1586 val = up->ier;
1587 }
1588 return val;
1589 }
1590
kt_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1591 static int kt_serial_setup(struct serial_private *priv,
1592 const struct pciserial_board *board,
1593 struct uart_8250_port *port, int idx)
1594 {
1595 port->port.flags |= UPF_BUG_THRE;
1596 port->port.serial_in = kt_serial_in;
1597 port->port.handle_break = kt_handle_break;
1598 return skip_tx_en_setup(priv, board, port, idx);
1599 }
1600
pci_eg20t_init(struct pci_dev * dev)1601 static int pci_eg20t_init(struct pci_dev *dev)
1602 {
1603 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1604 return -ENODEV;
1605 #else
1606 return 0;
1607 #endif
1608 }
1609
1610 static int
pci_wch_ch353_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1611 pci_wch_ch353_setup(struct serial_private *priv,
1612 const struct pciserial_board *board,
1613 struct uart_8250_port *port, int idx)
1614 {
1615 port->port.flags |= UPF_FIXED_TYPE;
1616 port->port.type = PORT_16550A;
1617 return pci_default_setup(priv, board, port, idx);
1618 }
1619
1620 static int
pci_wch_ch355_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1621 pci_wch_ch355_setup(struct serial_private *priv,
1622 const struct pciserial_board *board,
1623 struct uart_8250_port *port, int idx)
1624 {
1625 port->port.flags |= UPF_FIXED_TYPE;
1626 port->port.type = PORT_16550A;
1627 return pci_default_setup(priv, board, port, idx);
1628 }
1629
1630 static int
pci_wch_ch38x_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1631 pci_wch_ch38x_setup(struct serial_private *priv,
1632 const struct pciserial_board *board,
1633 struct uart_8250_port *port, int idx)
1634 {
1635 port->port.flags |= UPF_FIXED_TYPE;
1636 port->port.type = PORT_16850;
1637 return pci_default_setup(priv, board, port, idx);
1638 }
1639
1640 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1641 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1642 #define PCI_DEVICE_ID_OCTPRO 0x0001
1643 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1644 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1645 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1646 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1647 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1648 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1649 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1650 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1651 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1652 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1653 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1654 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1655 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1656 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1657 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1658 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1659 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1660 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1661 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1662 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1663 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1664 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1665 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1666 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1667 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1668 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1669 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1670 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1671 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1672 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1673 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1674 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1675 #define PCI_VENDOR_ID_WCH 0x4348
1676 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1677 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1678 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1679 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1680 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1681 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1682 #define PCI_VENDOR_ID_AGESTAR 0x5372
1683 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1684 #define PCI_VENDOR_ID_ASIX 0x9710
1685 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1686 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1687
1688 #define PCIE_VENDOR_ID_WCH 0x1c00
1689 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1690 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1691 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1692
1693 #define PCI_VENDOR_ID_PERICOM 0x12D8
1694 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
1695 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
1696 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
1697 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
1698
1699 #define PCI_VENDOR_ID_ACCESIO 0x494f
1700 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
1701 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
1702 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
1703 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
1704 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
1705 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
1706 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
1707 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
1708 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
1709 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
1710 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
1711 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
1712 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
1713 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
1714 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
1715 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
1716 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
1717 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
1718 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
1719 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
1720 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
1721 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
1722 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
1723 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
1724 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
1725 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
1726 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
1727 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
1728 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
1729 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
1730 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
1731 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
1732 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
1733
1734
1735
1736 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1737 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1738 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1739
1740 /*
1741 * Master list of serial port init/setup/exit quirks.
1742 * This does not describe the general nature of the port.
1743 * (ie, baud base, number and location of ports, etc)
1744 *
1745 * This list is ordered alphabetically by vendor then device.
1746 * Specific entries must come before more generic entries.
1747 */
1748 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1749 /*
1750 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1751 */
1752 {
1753 .vendor = PCI_VENDOR_ID_AMCC,
1754 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1755 .subvendor = PCI_ANY_ID,
1756 .subdevice = PCI_ANY_ID,
1757 .setup = addidata_apci7800_setup,
1758 },
1759 /*
1760 * AFAVLAB cards - these may be called via parport_serial
1761 * It is not clear whether this applies to all products.
1762 */
1763 {
1764 .vendor = PCI_VENDOR_ID_AFAVLAB,
1765 .device = PCI_ANY_ID,
1766 .subvendor = PCI_ANY_ID,
1767 .subdevice = PCI_ANY_ID,
1768 .setup = afavlab_setup,
1769 },
1770 /*
1771 * HP Diva
1772 */
1773 {
1774 .vendor = PCI_VENDOR_ID_HP,
1775 .device = PCI_DEVICE_ID_HP_DIVA,
1776 .subvendor = PCI_ANY_ID,
1777 .subdevice = PCI_ANY_ID,
1778 .init = pci_hp_diva_init,
1779 .setup = pci_hp_diva_setup,
1780 },
1781 /*
1782 * Intel
1783 */
1784 {
1785 .vendor = PCI_VENDOR_ID_INTEL,
1786 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1787 .subvendor = 0xe4bf,
1788 .subdevice = PCI_ANY_ID,
1789 .init = pci_inteli960ni_init,
1790 .setup = pci_default_setup,
1791 },
1792 {
1793 .vendor = PCI_VENDOR_ID_INTEL,
1794 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1795 .subvendor = PCI_ANY_ID,
1796 .subdevice = PCI_ANY_ID,
1797 .setup = skip_tx_en_setup,
1798 },
1799 {
1800 .vendor = PCI_VENDOR_ID_INTEL,
1801 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1802 .subvendor = PCI_ANY_ID,
1803 .subdevice = PCI_ANY_ID,
1804 .setup = skip_tx_en_setup,
1805 },
1806 {
1807 .vendor = PCI_VENDOR_ID_INTEL,
1808 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1809 .subvendor = PCI_ANY_ID,
1810 .subdevice = PCI_ANY_ID,
1811 .setup = skip_tx_en_setup,
1812 },
1813 {
1814 .vendor = PCI_VENDOR_ID_INTEL,
1815 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1816 .subvendor = PCI_ANY_ID,
1817 .subdevice = PCI_ANY_ID,
1818 .setup = ce4100_serial_setup,
1819 },
1820 {
1821 .vendor = PCI_VENDOR_ID_INTEL,
1822 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1823 .subvendor = PCI_ANY_ID,
1824 .subdevice = PCI_ANY_ID,
1825 .setup = kt_serial_setup,
1826 },
1827 /*
1828 * ITE
1829 */
1830 {
1831 .vendor = PCI_VENDOR_ID_ITE,
1832 .device = PCI_DEVICE_ID_ITE_8872,
1833 .subvendor = PCI_ANY_ID,
1834 .subdevice = PCI_ANY_ID,
1835 .init = pci_ite887x_init,
1836 .setup = pci_default_setup,
1837 .exit = pci_ite887x_exit,
1838 },
1839 /*
1840 * National Instruments
1841 */
1842 {
1843 .vendor = PCI_VENDOR_ID_NI,
1844 .device = PCI_DEVICE_ID_NI_PCI23216,
1845 .subvendor = PCI_ANY_ID,
1846 .subdevice = PCI_ANY_ID,
1847 .init = pci_ni8420_init,
1848 .setup = pci_default_setup,
1849 .exit = pci_ni8420_exit,
1850 },
1851 {
1852 .vendor = PCI_VENDOR_ID_NI,
1853 .device = PCI_DEVICE_ID_NI_PCI2328,
1854 .subvendor = PCI_ANY_ID,
1855 .subdevice = PCI_ANY_ID,
1856 .init = pci_ni8420_init,
1857 .setup = pci_default_setup,
1858 .exit = pci_ni8420_exit,
1859 },
1860 {
1861 .vendor = PCI_VENDOR_ID_NI,
1862 .device = PCI_DEVICE_ID_NI_PCI2324,
1863 .subvendor = PCI_ANY_ID,
1864 .subdevice = PCI_ANY_ID,
1865 .init = pci_ni8420_init,
1866 .setup = pci_default_setup,
1867 .exit = pci_ni8420_exit,
1868 },
1869 {
1870 .vendor = PCI_VENDOR_ID_NI,
1871 .device = PCI_DEVICE_ID_NI_PCI2322,
1872 .subvendor = PCI_ANY_ID,
1873 .subdevice = PCI_ANY_ID,
1874 .init = pci_ni8420_init,
1875 .setup = pci_default_setup,
1876 .exit = pci_ni8420_exit,
1877 },
1878 {
1879 .vendor = PCI_VENDOR_ID_NI,
1880 .device = PCI_DEVICE_ID_NI_PCI2324I,
1881 .subvendor = PCI_ANY_ID,
1882 .subdevice = PCI_ANY_ID,
1883 .init = pci_ni8420_init,
1884 .setup = pci_default_setup,
1885 .exit = pci_ni8420_exit,
1886 },
1887 {
1888 .vendor = PCI_VENDOR_ID_NI,
1889 .device = PCI_DEVICE_ID_NI_PCI2322I,
1890 .subvendor = PCI_ANY_ID,
1891 .subdevice = PCI_ANY_ID,
1892 .init = pci_ni8420_init,
1893 .setup = pci_default_setup,
1894 .exit = pci_ni8420_exit,
1895 },
1896 {
1897 .vendor = PCI_VENDOR_ID_NI,
1898 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1899 .subvendor = PCI_ANY_ID,
1900 .subdevice = PCI_ANY_ID,
1901 .init = pci_ni8420_init,
1902 .setup = pci_default_setup,
1903 .exit = pci_ni8420_exit,
1904 },
1905 {
1906 .vendor = PCI_VENDOR_ID_NI,
1907 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1908 .subvendor = PCI_ANY_ID,
1909 .subdevice = PCI_ANY_ID,
1910 .init = pci_ni8420_init,
1911 .setup = pci_default_setup,
1912 .exit = pci_ni8420_exit,
1913 },
1914 {
1915 .vendor = PCI_VENDOR_ID_NI,
1916 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1917 .subvendor = PCI_ANY_ID,
1918 .subdevice = PCI_ANY_ID,
1919 .init = pci_ni8420_init,
1920 .setup = pci_default_setup,
1921 .exit = pci_ni8420_exit,
1922 },
1923 {
1924 .vendor = PCI_VENDOR_ID_NI,
1925 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1926 .subvendor = PCI_ANY_ID,
1927 .subdevice = PCI_ANY_ID,
1928 .init = pci_ni8420_init,
1929 .setup = pci_default_setup,
1930 .exit = pci_ni8420_exit,
1931 },
1932 {
1933 .vendor = PCI_VENDOR_ID_NI,
1934 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1935 .subvendor = PCI_ANY_ID,
1936 .subdevice = PCI_ANY_ID,
1937 .init = pci_ni8420_init,
1938 .setup = pci_default_setup,
1939 .exit = pci_ni8420_exit,
1940 },
1941 {
1942 .vendor = PCI_VENDOR_ID_NI,
1943 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1944 .subvendor = PCI_ANY_ID,
1945 .subdevice = PCI_ANY_ID,
1946 .init = pci_ni8420_init,
1947 .setup = pci_default_setup,
1948 .exit = pci_ni8420_exit,
1949 },
1950 {
1951 .vendor = PCI_VENDOR_ID_NI,
1952 .device = PCI_ANY_ID,
1953 .subvendor = PCI_ANY_ID,
1954 .subdevice = PCI_ANY_ID,
1955 .init = pci_ni8430_init,
1956 .setup = pci_ni8430_setup,
1957 .exit = pci_ni8430_exit,
1958 },
1959 /* Quatech */
1960 {
1961 .vendor = PCI_VENDOR_ID_QUATECH,
1962 .device = PCI_ANY_ID,
1963 .subvendor = PCI_ANY_ID,
1964 .subdevice = PCI_ANY_ID,
1965 .init = pci_quatech_init,
1966 .setup = pci_quatech_setup,
1967 .exit = pci_quatech_exit,
1968 },
1969 /*
1970 * Panacom
1971 */
1972 {
1973 .vendor = PCI_VENDOR_ID_PANACOM,
1974 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1975 .subvendor = PCI_ANY_ID,
1976 .subdevice = PCI_ANY_ID,
1977 .init = pci_plx9050_init,
1978 .setup = pci_default_setup,
1979 .exit = pci_plx9050_exit,
1980 },
1981 {
1982 .vendor = PCI_VENDOR_ID_PANACOM,
1983 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1984 .subvendor = PCI_ANY_ID,
1985 .subdevice = PCI_ANY_ID,
1986 .init = pci_plx9050_init,
1987 .setup = pci_default_setup,
1988 .exit = pci_plx9050_exit,
1989 },
1990 /*
1991 * Pericom (Only 7954 - It have a offset jump for port 4)
1992 */
1993 {
1994 .vendor = PCI_VENDOR_ID_PERICOM,
1995 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
1996 .subvendor = PCI_ANY_ID,
1997 .subdevice = PCI_ANY_ID,
1998 .setup = pci_pericom_setup,
1999 },
2000 /*
2001 * PLX
2002 */
2003 {
2004 .vendor = PCI_VENDOR_ID_PLX,
2005 .device = PCI_DEVICE_ID_PLX_9050,
2006 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2007 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2008 .init = pci_plx9050_init,
2009 .setup = pci_default_setup,
2010 .exit = pci_plx9050_exit,
2011 },
2012 {
2013 .vendor = PCI_VENDOR_ID_PLX,
2014 .device = PCI_DEVICE_ID_PLX_9050,
2015 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2016 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2017 .init = pci_plx9050_init,
2018 .setup = pci_default_setup,
2019 .exit = pci_plx9050_exit,
2020 },
2021 {
2022 .vendor = PCI_VENDOR_ID_PLX,
2023 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2024 .subvendor = PCI_VENDOR_ID_PLX,
2025 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2026 .init = pci_plx9050_init,
2027 .setup = pci_default_setup,
2028 .exit = pci_plx9050_exit,
2029 },
2030 /*
2031 * SBS Technologies, Inc., PMC-OCTALPRO 232
2032 */
2033 {
2034 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2035 .device = PCI_DEVICE_ID_OCTPRO,
2036 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2037 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2038 .init = sbs_init,
2039 .setup = sbs_setup,
2040 .exit = sbs_exit,
2041 },
2042 /*
2043 * SBS Technologies, Inc., PMC-OCTALPRO 422
2044 */
2045 {
2046 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2047 .device = PCI_DEVICE_ID_OCTPRO,
2048 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2049 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2050 .init = sbs_init,
2051 .setup = sbs_setup,
2052 .exit = sbs_exit,
2053 },
2054 /*
2055 * SBS Technologies, Inc., P-Octal 232
2056 */
2057 {
2058 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2059 .device = PCI_DEVICE_ID_OCTPRO,
2060 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2061 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2062 .init = sbs_init,
2063 .setup = sbs_setup,
2064 .exit = sbs_exit,
2065 },
2066 /*
2067 * SBS Technologies, Inc., P-Octal 422
2068 */
2069 {
2070 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2071 .device = PCI_DEVICE_ID_OCTPRO,
2072 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2073 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2074 .init = sbs_init,
2075 .setup = sbs_setup,
2076 .exit = sbs_exit,
2077 },
2078 /*
2079 * SIIG cards - these may be called via parport_serial
2080 */
2081 {
2082 .vendor = PCI_VENDOR_ID_SIIG,
2083 .device = PCI_ANY_ID,
2084 .subvendor = PCI_ANY_ID,
2085 .subdevice = PCI_ANY_ID,
2086 .init = pci_siig_init,
2087 .setup = pci_siig_setup,
2088 },
2089 /*
2090 * Titan cards
2091 */
2092 {
2093 .vendor = PCI_VENDOR_ID_TITAN,
2094 .device = PCI_DEVICE_ID_TITAN_400L,
2095 .subvendor = PCI_ANY_ID,
2096 .subdevice = PCI_ANY_ID,
2097 .setup = titan_400l_800l_setup,
2098 },
2099 {
2100 .vendor = PCI_VENDOR_ID_TITAN,
2101 .device = PCI_DEVICE_ID_TITAN_800L,
2102 .subvendor = PCI_ANY_ID,
2103 .subdevice = PCI_ANY_ID,
2104 .setup = titan_400l_800l_setup,
2105 },
2106 /*
2107 * Timedia cards
2108 */
2109 {
2110 .vendor = PCI_VENDOR_ID_TIMEDIA,
2111 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2112 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2113 .subdevice = PCI_ANY_ID,
2114 .probe = pci_timedia_probe,
2115 .init = pci_timedia_init,
2116 .setup = pci_timedia_setup,
2117 },
2118 {
2119 .vendor = PCI_VENDOR_ID_TIMEDIA,
2120 .device = PCI_ANY_ID,
2121 .subvendor = PCI_ANY_ID,
2122 .subdevice = PCI_ANY_ID,
2123 .setup = pci_timedia_setup,
2124 },
2125 /*
2126 * SUNIX (Timedia) cards
2127 * Do not "probe" for these cards as there is at least one combination
2128 * card that should be handled by parport_pc that doesn't match the
2129 * rule in pci_timedia_probe.
2130 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2131 * There are some boards with part number SER5037AL that report
2132 * subdevice ID 0x0002.
2133 */
2134 {
2135 .vendor = PCI_VENDOR_ID_SUNIX,
2136 .device = PCI_DEVICE_ID_SUNIX_1999,
2137 .subvendor = PCI_VENDOR_ID_SUNIX,
2138 .subdevice = PCI_ANY_ID,
2139 .init = pci_timedia_init,
2140 .setup = pci_timedia_setup,
2141 },
2142 /*
2143 * Xircom cards
2144 */
2145 {
2146 .vendor = PCI_VENDOR_ID_XIRCOM,
2147 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2148 .subvendor = PCI_ANY_ID,
2149 .subdevice = PCI_ANY_ID,
2150 .init = pci_xircom_init,
2151 .setup = pci_default_setup,
2152 },
2153 /*
2154 * Netmos cards - these may be called via parport_serial
2155 */
2156 {
2157 .vendor = PCI_VENDOR_ID_NETMOS,
2158 .device = PCI_ANY_ID,
2159 .subvendor = PCI_ANY_ID,
2160 .subdevice = PCI_ANY_ID,
2161 .init = pci_netmos_init,
2162 .setup = pci_netmos_9900_setup,
2163 },
2164 /*
2165 * EndRun Technologies
2166 */
2167 {
2168 .vendor = PCI_VENDOR_ID_ENDRUN,
2169 .device = PCI_ANY_ID,
2170 .subvendor = PCI_ANY_ID,
2171 .subdevice = PCI_ANY_ID,
2172 .init = pci_endrun_init,
2173 .setup = pci_default_setup,
2174 },
2175 /*
2176 * For Oxford Semiconductor Tornado based devices
2177 */
2178 {
2179 .vendor = PCI_VENDOR_ID_OXSEMI,
2180 .device = PCI_ANY_ID,
2181 .subvendor = PCI_ANY_ID,
2182 .subdevice = PCI_ANY_ID,
2183 .init = pci_oxsemi_tornado_init,
2184 .setup = pci_default_setup,
2185 },
2186 {
2187 .vendor = PCI_VENDOR_ID_MAINPINE,
2188 .device = PCI_ANY_ID,
2189 .subvendor = PCI_ANY_ID,
2190 .subdevice = PCI_ANY_ID,
2191 .init = pci_oxsemi_tornado_init,
2192 .setup = pci_default_setup,
2193 },
2194 {
2195 .vendor = PCI_VENDOR_ID_DIGI,
2196 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2197 .subvendor = PCI_SUBVENDOR_ID_IBM,
2198 .subdevice = PCI_ANY_ID,
2199 .init = pci_oxsemi_tornado_init,
2200 .setup = pci_default_setup,
2201 },
2202 {
2203 .vendor = PCI_VENDOR_ID_INTEL,
2204 .device = 0x8811,
2205 .subvendor = PCI_ANY_ID,
2206 .subdevice = PCI_ANY_ID,
2207 .init = pci_eg20t_init,
2208 .setup = pci_default_setup,
2209 },
2210 {
2211 .vendor = PCI_VENDOR_ID_INTEL,
2212 .device = 0x8812,
2213 .subvendor = PCI_ANY_ID,
2214 .subdevice = PCI_ANY_ID,
2215 .init = pci_eg20t_init,
2216 .setup = pci_default_setup,
2217 },
2218 {
2219 .vendor = PCI_VENDOR_ID_INTEL,
2220 .device = 0x8813,
2221 .subvendor = PCI_ANY_ID,
2222 .subdevice = PCI_ANY_ID,
2223 .init = pci_eg20t_init,
2224 .setup = pci_default_setup,
2225 },
2226 {
2227 .vendor = PCI_VENDOR_ID_INTEL,
2228 .device = 0x8814,
2229 .subvendor = PCI_ANY_ID,
2230 .subdevice = PCI_ANY_ID,
2231 .init = pci_eg20t_init,
2232 .setup = pci_default_setup,
2233 },
2234 {
2235 .vendor = 0x10DB,
2236 .device = 0x8027,
2237 .subvendor = PCI_ANY_ID,
2238 .subdevice = PCI_ANY_ID,
2239 .init = pci_eg20t_init,
2240 .setup = pci_default_setup,
2241 },
2242 {
2243 .vendor = 0x10DB,
2244 .device = 0x8028,
2245 .subvendor = PCI_ANY_ID,
2246 .subdevice = PCI_ANY_ID,
2247 .init = pci_eg20t_init,
2248 .setup = pci_default_setup,
2249 },
2250 {
2251 .vendor = 0x10DB,
2252 .device = 0x8029,
2253 .subvendor = PCI_ANY_ID,
2254 .subdevice = PCI_ANY_ID,
2255 .init = pci_eg20t_init,
2256 .setup = pci_default_setup,
2257 },
2258 {
2259 .vendor = 0x10DB,
2260 .device = 0x800C,
2261 .subvendor = PCI_ANY_ID,
2262 .subdevice = PCI_ANY_ID,
2263 .init = pci_eg20t_init,
2264 .setup = pci_default_setup,
2265 },
2266 {
2267 .vendor = 0x10DB,
2268 .device = 0x800D,
2269 .subvendor = PCI_ANY_ID,
2270 .subdevice = PCI_ANY_ID,
2271 .init = pci_eg20t_init,
2272 .setup = pci_default_setup,
2273 },
2274 /*
2275 * Cronyx Omega PCI (PLX-chip based)
2276 */
2277 {
2278 .vendor = PCI_VENDOR_ID_PLX,
2279 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2280 .subvendor = PCI_ANY_ID,
2281 .subdevice = PCI_ANY_ID,
2282 .setup = pci_omegapci_setup,
2283 },
2284 /* WCH CH353 1S1P card (16550 clone) */
2285 {
2286 .vendor = PCI_VENDOR_ID_WCH,
2287 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2288 .subvendor = PCI_ANY_ID,
2289 .subdevice = PCI_ANY_ID,
2290 .setup = pci_wch_ch353_setup,
2291 },
2292 /* WCH CH353 2S1P card (16550 clone) */
2293 {
2294 .vendor = PCI_VENDOR_ID_WCH,
2295 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2296 .subvendor = PCI_ANY_ID,
2297 .subdevice = PCI_ANY_ID,
2298 .setup = pci_wch_ch353_setup,
2299 },
2300 /* WCH CH353 4S card (16550 clone) */
2301 {
2302 .vendor = PCI_VENDOR_ID_WCH,
2303 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2304 .subvendor = PCI_ANY_ID,
2305 .subdevice = PCI_ANY_ID,
2306 .setup = pci_wch_ch353_setup,
2307 },
2308 /* WCH CH353 2S1PF card (16550 clone) */
2309 {
2310 .vendor = PCI_VENDOR_ID_WCH,
2311 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2312 .subvendor = PCI_ANY_ID,
2313 .subdevice = PCI_ANY_ID,
2314 .setup = pci_wch_ch353_setup,
2315 },
2316 /* WCH CH352 2S card (16550 clone) */
2317 {
2318 .vendor = PCI_VENDOR_ID_WCH,
2319 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2320 .subvendor = PCI_ANY_ID,
2321 .subdevice = PCI_ANY_ID,
2322 .setup = pci_wch_ch353_setup,
2323 },
2324 /* WCH CH355 4S card (16550 clone) */
2325 {
2326 .vendor = PCI_VENDOR_ID_WCH,
2327 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2328 .subvendor = PCI_ANY_ID,
2329 .subdevice = PCI_ANY_ID,
2330 .setup = pci_wch_ch355_setup,
2331 },
2332 /* WCH CH382 2S card (16850 clone) */
2333 {
2334 .vendor = PCIE_VENDOR_ID_WCH,
2335 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2336 .subvendor = PCI_ANY_ID,
2337 .subdevice = PCI_ANY_ID,
2338 .setup = pci_wch_ch38x_setup,
2339 },
2340 /* WCH CH382 2S1P card (16850 clone) */
2341 {
2342 .vendor = PCIE_VENDOR_ID_WCH,
2343 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2344 .subvendor = PCI_ANY_ID,
2345 .subdevice = PCI_ANY_ID,
2346 .setup = pci_wch_ch38x_setup,
2347 },
2348 /* WCH CH384 4S card (16850 clone) */
2349 {
2350 .vendor = PCIE_VENDOR_ID_WCH,
2351 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2352 .subvendor = PCI_ANY_ID,
2353 .subdevice = PCI_ANY_ID,
2354 .setup = pci_wch_ch38x_setup,
2355 },
2356 /*
2357 * ASIX devices with FIFO bug
2358 */
2359 {
2360 .vendor = PCI_VENDOR_ID_ASIX,
2361 .device = PCI_ANY_ID,
2362 .subvendor = PCI_ANY_ID,
2363 .subdevice = PCI_ANY_ID,
2364 .setup = pci_asix_setup,
2365 },
2366 /*
2367 * Broadcom TruManage (NetXtreme)
2368 */
2369 {
2370 .vendor = PCI_VENDOR_ID_BROADCOM,
2371 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2372 .subvendor = PCI_ANY_ID,
2373 .subdevice = PCI_ANY_ID,
2374 .setup = pci_brcm_trumanage_setup,
2375 },
2376 {
2377 .vendor = 0x1c29,
2378 .device = 0x1104,
2379 .subvendor = PCI_ANY_ID,
2380 .subdevice = PCI_ANY_ID,
2381 .setup = pci_fintek_setup,
2382 .init = pci_fintek_init,
2383 },
2384 {
2385 .vendor = 0x1c29,
2386 .device = 0x1108,
2387 .subvendor = PCI_ANY_ID,
2388 .subdevice = PCI_ANY_ID,
2389 .setup = pci_fintek_setup,
2390 .init = pci_fintek_init,
2391 },
2392 {
2393 .vendor = 0x1c29,
2394 .device = 0x1112,
2395 .subvendor = PCI_ANY_ID,
2396 .subdevice = PCI_ANY_ID,
2397 .setup = pci_fintek_setup,
2398 .init = pci_fintek_init,
2399 },
2400
2401 /*
2402 * Default "match everything" terminator entry
2403 */
2404 {
2405 .vendor = PCI_ANY_ID,
2406 .device = PCI_ANY_ID,
2407 .subvendor = PCI_ANY_ID,
2408 .subdevice = PCI_ANY_ID,
2409 .setup = pci_default_setup,
2410 }
2411 };
2412
quirk_id_matches(u32 quirk_id,u32 dev_id)2413 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2414 {
2415 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2416 }
2417
find_quirk(struct pci_dev * dev)2418 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2419 {
2420 struct pci_serial_quirk *quirk;
2421
2422 for (quirk = pci_serial_quirks; ; quirk++)
2423 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2424 quirk_id_matches(quirk->device, dev->device) &&
2425 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2426 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2427 break;
2428 return quirk;
2429 }
2430
get_pci_irq(struct pci_dev * dev,const struct pciserial_board * board)2431 static inline int get_pci_irq(struct pci_dev *dev,
2432 const struct pciserial_board *board)
2433 {
2434 if (board->flags & FL_NOIRQ)
2435 return 0;
2436 else
2437 return dev->irq;
2438 }
2439
2440 /*
2441 * This is the configuration table for all of the PCI serial boards
2442 * which we support. It is directly indexed by the pci_board_num_t enum
2443 * value, which is encoded in the pci_device_id PCI probe table's
2444 * driver_data member.
2445 *
2446 * The makeup of these names are:
2447 * pbn_bn{_bt}_n_baud{_offsetinhex}
2448 *
2449 * bn = PCI BAR number
2450 * bt = Index using PCI BARs
2451 * n = number of serial ports
2452 * baud = baud rate
2453 * offsetinhex = offset for each sequential port (in hex)
2454 *
2455 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2456 *
2457 * Please note: in theory if n = 1, _bt infix should make no difference.
2458 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2459 */
2460 enum pci_board_num_t {
2461 pbn_default = 0,
2462
2463 pbn_b0_1_115200,
2464 pbn_b0_2_115200,
2465 pbn_b0_4_115200,
2466 pbn_b0_5_115200,
2467 pbn_b0_8_115200,
2468
2469 pbn_b0_1_921600,
2470 pbn_b0_2_921600,
2471 pbn_b0_4_921600,
2472
2473 pbn_b0_2_1130000,
2474
2475 pbn_b0_4_1152000,
2476
2477 pbn_b0_4_1250000,
2478
2479 pbn_b0_2_1843200,
2480 pbn_b0_4_1843200,
2481
2482 pbn_b0_1_4000000,
2483
2484 pbn_b0_bt_1_115200,
2485 pbn_b0_bt_2_115200,
2486 pbn_b0_bt_4_115200,
2487 pbn_b0_bt_8_115200,
2488
2489 pbn_b0_bt_1_460800,
2490 pbn_b0_bt_2_460800,
2491 pbn_b0_bt_4_460800,
2492
2493 pbn_b0_bt_1_921600,
2494 pbn_b0_bt_2_921600,
2495 pbn_b0_bt_4_921600,
2496 pbn_b0_bt_8_921600,
2497
2498 pbn_b1_1_115200,
2499 pbn_b1_2_115200,
2500 pbn_b1_4_115200,
2501 pbn_b1_8_115200,
2502 pbn_b1_16_115200,
2503
2504 pbn_b1_1_921600,
2505 pbn_b1_2_921600,
2506 pbn_b1_4_921600,
2507 pbn_b1_8_921600,
2508
2509 pbn_b1_2_1250000,
2510
2511 pbn_b1_bt_1_115200,
2512 pbn_b1_bt_2_115200,
2513 pbn_b1_bt_4_115200,
2514
2515 pbn_b1_bt_2_921600,
2516
2517 pbn_b1_1_1382400,
2518 pbn_b1_2_1382400,
2519 pbn_b1_4_1382400,
2520 pbn_b1_8_1382400,
2521
2522 pbn_b2_1_115200,
2523 pbn_b2_2_115200,
2524 pbn_b2_4_115200,
2525 pbn_b2_8_115200,
2526
2527 pbn_b2_1_460800,
2528 pbn_b2_4_460800,
2529 pbn_b2_8_460800,
2530 pbn_b2_16_460800,
2531
2532 pbn_b2_1_921600,
2533 pbn_b2_4_921600,
2534 pbn_b2_8_921600,
2535
2536 pbn_b2_8_1152000,
2537
2538 pbn_b2_bt_1_115200,
2539 pbn_b2_bt_2_115200,
2540 pbn_b2_bt_4_115200,
2541
2542 pbn_b2_bt_2_921600,
2543 pbn_b2_bt_4_921600,
2544
2545 pbn_b3_2_115200,
2546 pbn_b3_4_115200,
2547 pbn_b3_8_115200,
2548
2549 pbn_b4_bt_2_921600,
2550 pbn_b4_bt_4_921600,
2551 pbn_b4_bt_8_921600,
2552
2553 /*
2554 * Board-specific versions.
2555 */
2556 pbn_panacom,
2557 pbn_panacom2,
2558 pbn_panacom4,
2559 pbn_plx_romulus,
2560 pbn_endrun_2_4000000,
2561 pbn_oxsemi,
2562 pbn_oxsemi_1_4000000,
2563 pbn_oxsemi_2_4000000,
2564 pbn_oxsemi_4_4000000,
2565 pbn_oxsemi_8_4000000,
2566 pbn_intel_i960,
2567 pbn_sgi_ioc3,
2568 pbn_computone_4,
2569 pbn_computone_6,
2570 pbn_computone_8,
2571 pbn_sbsxrsio,
2572 pbn_pasemi_1682M,
2573 pbn_ni8430_2,
2574 pbn_ni8430_4,
2575 pbn_ni8430_8,
2576 pbn_ni8430_16,
2577 pbn_ADDIDATA_PCIe_1_3906250,
2578 pbn_ADDIDATA_PCIe_2_3906250,
2579 pbn_ADDIDATA_PCIe_4_3906250,
2580 pbn_ADDIDATA_PCIe_8_3906250,
2581 pbn_ce4100_1_115200,
2582 pbn_omegapci,
2583 pbn_NETMOS9900_2s_115200,
2584 pbn_brcm_trumanage,
2585 pbn_fintek_4,
2586 pbn_fintek_8,
2587 pbn_fintek_12,
2588 pbn_wch382_2,
2589 pbn_wch384_4,
2590 pbn_pericom_PI7C9X7951,
2591 pbn_pericom_PI7C9X7952,
2592 pbn_pericom_PI7C9X7954,
2593 pbn_pericom_PI7C9X7958,
2594 };
2595
2596 /*
2597 * uart_offset - the space between channels
2598 * reg_shift - describes how the UART registers are mapped
2599 * to PCI memory by the card.
2600 * For example IER register on SBS, Inc. PMC-OctPro is located at
2601 * offset 0x10 from the UART base, while UART_IER is defined as 1
2602 * in include/linux/serial_reg.h,
2603 * see first lines of serial_in() and serial_out() in 8250.c
2604 */
2605
2606 static struct pciserial_board pci_boards[] = {
2607 [pbn_default] = {
2608 .flags = FL_BASE0,
2609 .num_ports = 1,
2610 .base_baud = 115200,
2611 .uart_offset = 8,
2612 },
2613 [pbn_b0_1_115200] = {
2614 .flags = FL_BASE0,
2615 .num_ports = 1,
2616 .base_baud = 115200,
2617 .uart_offset = 8,
2618 },
2619 [pbn_b0_2_115200] = {
2620 .flags = FL_BASE0,
2621 .num_ports = 2,
2622 .base_baud = 115200,
2623 .uart_offset = 8,
2624 },
2625 [pbn_b0_4_115200] = {
2626 .flags = FL_BASE0,
2627 .num_ports = 4,
2628 .base_baud = 115200,
2629 .uart_offset = 8,
2630 },
2631 [pbn_b0_5_115200] = {
2632 .flags = FL_BASE0,
2633 .num_ports = 5,
2634 .base_baud = 115200,
2635 .uart_offset = 8,
2636 },
2637 [pbn_b0_8_115200] = {
2638 .flags = FL_BASE0,
2639 .num_ports = 8,
2640 .base_baud = 115200,
2641 .uart_offset = 8,
2642 },
2643 [pbn_b0_1_921600] = {
2644 .flags = FL_BASE0,
2645 .num_ports = 1,
2646 .base_baud = 921600,
2647 .uart_offset = 8,
2648 },
2649 [pbn_b0_2_921600] = {
2650 .flags = FL_BASE0,
2651 .num_ports = 2,
2652 .base_baud = 921600,
2653 .uart_offset = 8,
2654 },
2655 [pbn_b0_4_921600] = {
2656 .flags = FL_BASE0,
2657 .num_ports = 4,
2658 .base_baud = 921600,
2659 .uart_offset = 8,
2660 },
2661
2662 [pbn_b0_2_1130000] = {
2663 .flags = FL_BASE0,
2664 .num_ports = 2,
2665 .base_baud = 1130000,
2666 .uart_offset = 8,
2667 },
2668
2669 [pbn_b0_4_1152000] = {
2670 .flags = FL_BASE0,
2671 .num_ports = 4,
2672 .base_baud = 1152000,
2673 .uart_offset = 8,
2674 },
2675
2676 [pbn_b0_4_1250000] = {
2677 .flags = FL_BASE0,
2678 .num_ports = 4,
2679 .base_baud = 1250000,
2680 .uart_offset = 8,
2681 },
2682
2683 [pbn_b0_2_1843200] = {
2684 .flags = FL_BASE0,
2685 .num_ports = 2,
2686 .base_baud = 1843200,
2687 .uart_offset = 8,
2688 },
2689 [pbn_b0_4_1843200] = {
2690 .flags = FL_BASE0,
2691 .num_ports = 4,
2692 .base_baud = 1843200,
2693 .uart_offset = 8,
2694 },
2695
2696 [pbn_b0_1_4000000] = {
2697 .flags = FL_BASE0,
2698 .num_ports = 1,
2699 .base_baud = 4000000,
2700 .uart_offset = 8,
2701 },
2702
2703 [pbn_b0_bt_1_115200] = {
2704 .flags = FL_BASE0|FL_BASE_BARS,
2705 .num_ports = 1,
2706 .base_baud = 115200,
2707 .uart_offset = 8,
2708 },
2709 [pbn_b0_bt_2_115200] = {
2710 .flags = FL_BASE0|FL_BASE_BARS,
2711 .num_ports = 2,
2712 .base_baud = 115200,
2713 .uart_offset = 8,
2714 },
2715 [pbn_b0_bt_4_115200] = {
2716 .flags = FL_BASE0|FL_BASE_BARS,
2717 .num_ports = 4,
2718 .base_baud = 115200,
2719 .uart_offset = 8,
2720 },
2721 [pbn_b0_bt_8_115200] = {
2722 .flags = FL_BASE0|FL_BASE_BARS,
2723 .num_ports = 8,
2724 .base_baud = 115200,
2725 .uart_offset = 8,
2726 },
2727
2728 [pbn_b0_bt_1_460800] = {
2729 .flags = FL_BASE0|FL_BASE_BARS,
2730 .num_ports = 1,
2731 .base_baud = 460800,
2732 .uart_offset = 8,
2733 },
2734 [pbn_b0_bt_2_460800] = {
2735 .flags = FL_BASE0|FL_BASE_BARS,
2736 .num_ports = 2,
2737 .base_baud = 460800,
2738 .uart_offset = 8,
2739 },
2740 [pbn_b0_bt_4_460800] = {
2741 .flags = FL_BASE0|FL_BASE_BARS,
2742 .num_ports = 4,
2743 .base_baud = 460800,
2744 .uart_offset = 8,
2745 },
2746
2747 [pbn_b0_bt_1_921600] = {
2748 .flags = FL_BASE0|FL_BASE_BARS,
2749 .num_ports = 1,
2750 .base_baud = 921600,
2751 .uart_offset = 8,
2752 },
2753 [pbn_b0_bt_2_921600] = {
2754 .flags = FL_BASE0|FL_BASE_BARS,
2755 .num_ports = 2,
2756 .base_baud = 921600,
2757 .uart_offset = 8,
2758 },
2759 [pbn_b0_bt_4_921600] = {
2760 .flags = FL_BASE0|FL_BASE_BARS,
2761 .num_ports = 4,
2762 .base_baud = 921600,
2763 .uart_offset = 8,
2764 },
2765 [pbn_b0_bt_8_921600] = {
2766 .flags = FL_BASE0|FL_BASE_BARS,
2767 .num_ports = 8,
2768 .base_baud = 921600,
2769 .uart_offset = 8,
2770 },
2771
2772 [pbn_b1_1_115200] = {
2773 .flags = FL_BASE1,
2774 .num_ports = 1,
2775 .base_baud = 115200,
2776 .uart_offset = 8,
2777 },
2778 [pbn_b1_2_115200] = {
2779 .flags = FL_BASE1,
2780 .num_ports = 2,
2781 .base_baud = 115200,
2782 .uart_offset = 8,
2783 },
2784 [pbn_b1_4_115200] = {
2785 .flags = FL_BASE1,
2786 .num_ports = 4,
2787 .base_baud = 115200,
2788 .uart_offset = 8,
2789 },
2790 [pbn_b1_8_115200] = {
2791 .flags = FL_BASE1,
2792 .num_ports = 8,
2793 .base_baud = 115200,
2794 .uart_offset = 8,
2795 },
2796 [pbn_b1_16_115200] = {
2797 .flags = FL_BASE1,
2798 .num_ports = 16,
2799 .base_baud = 115200,
2800 .uart_offset = 8,
2801 },
2802
2803 [pbn_b1_1_921600] = {
2804 .flags = FL_BASE1,
2805 .num_ports = 1,
2806 .base_baud = 921600,
2807 .uart_offset = 8,
2808 },
2809 [pbn_b1_2_921600] = {
2810 .flags = FL_BASE1,
2811 .num_ports = 2,
2812 .base_baud = 921600,
2813 .uart_offset = 8,
2814 },
2815 [pbn_b1_4_921600] = {
2816 .flags = FL_BASE1,
2817 .num_ports = 4,
2818 .base_baud = 921600,
2819 .uart_offset = 8,
2820 },
2821 [pbn_b1_8_921600] = {
2822 .flags = FL_BASE1,
2823 .num_ports = 8,
2824 .base_baud = 921600,
2825 .uart_offset = 8,
2826 },
2827 [pbn_b1_2_1250000] = {
2828 .flags = FL_BASE1,
2829 .num_ports = 2,
2830 .base_baud = 1250000,
2831 .uart_offset = 8,
2832 },
2833
2834 [pbn_b1_bt_1_115200] = {
2835 .flags = FL_BASE1|FL_BASE_BARS,
2836 .num_ports = 1,
2837 .base_baud = 115200,
2838 .uart_offset = 8,
2839 },
2840 [pbn_b1_bt_2_115200] = {
2841 .flags = FL_BASE1|FL_BASE_BARS,
2842 .num_ports = 2,
2843 .base_baud = 115200,
2844 .uart_offset = 8,
2845 },
2846 [pbn_b1_bt_4_115200] = {
2847 .flags = FL_BASE1|FL_BASE_BARS,
2848 .num_ports = 4,
2849 .base_baud = 115200,
2850 .uart_offset = 8,
2851 },
2852
2853 [pbn_b1_bt_2_921600] = {
2854 .flags = FL_BASE1|FL_BASE_BARS,
2855 .num_ports = 2,
2856 .base_baud = 921600,
2857 .uart_offset = 8,
2858 },
2859
2860 [pbn_b1_1_1382400] = {
2861 .flags = FL_BASE1,
2862 .num_ports = 1,
2863 .base_baud = 1382400,
2864 .uart_offset = 8,
2865 },
2866 [pbn_b1_2_1382400] = {
2867 .flags = FL_BASE1,
2868 .num_ports = 2,
2869 .base_baud = 1382400,
2870 .uart_offset = 8,
2871 },
2872 [pbn_b1_4_1382400] = {
2873 .flags = FL_BASE1,
2874 .num_ports = 4,
2875 .base_baud = 1382400,
2876 .uart_offset = 8,
2877 },
2878 [pbn_b1_8_1382400] = {
2879 .flags = FL_BASE1,
2880 .num_ports = 8,
2881 .base_baud = 1382400,
2882 .uart_offset = 8,
2883 },
2884
2885 [pbn_b2_1_115200] = {
2886 .flags = FL_BASE2,
2887 .num_ports = 1,
2888 .base_baud = 115200,
2889 .uart_offset = 8,
2890 },
2891 [pbn_b2_2_115200] = {
2892 .flags = FL_BASE2,
2893 .num_ports = 2,
2894 .base_baud = 115200,
2895 .uart_offset = 8,
2896 },
2897 [pbn_b2_4_115200] = {
2898 .flags = FL_BASE2,
2899 .num_ports = 4,
2900 .base_baud = 115200,
2901 .uart_offset = 8,
2902 },
2903 [pbn_b2_8_115200] = {
2904 .flags = FL_BASE2,
2905 .num_ports = 8,
2906 .base_baud = 115200,
2907 .uart_offset = 8,
2908 },
2909
2910 [pbn_b2_1_460800] = {
2911 .flags = FL_BASE2,
2912 .num_ports = 1,
2913 .base_baud = 460800,
2914 .uart_offset = 8,
2915 },
2916 [pbn_b2_4_460800] = {
2917 .flags = FL_BASE2,
2918 .num_ports = 4,
2919 .base_baud = 460800,
2920 .uart_offset = 8,
2921 },
2922 [pbn_b2_8_460800] = {
2923 .flags = FL_BASE2,
2924 .num_ports = 8,
2925 .base_baud = 460800,
2926 .uart_offset = 8,
2927 },
2928 [pbn_b2_16_460800] = {
2929 .flags = FL_BASE2,
2930 .num_ports = 16,
2931 .base_baud = 460800,
2932 .uart_offset = 8,
2933 },
2934
2935 [pbn_b2_1_921600] = {
2936 .flags = FL_BASE2,
2937 .num_ports = 1,
2938 .base_baud = 921600,
2939 .uart_offset = 8,
2940 },
2941 [pbn_b2_4_921600] = {
2942 .flags = FL_BASE2,
2943 .num_ports = 4,
2944 .base_baud = 921600,
2945 .uart_offset = 8,
2946 },
2947 [pbn_b2_8_921600] = {
2948 .flags = FL_BASE2,
2949 .num_ports = 8,
2950 .base_baud = 921600,
2951 .uart_offset = 8,
2952 },
2953
2954 [pbn_b2_8_1152000] = {
2955 .flags = FL_BASE2,
2956 .num_ports = 8,
2957 .base_baud = 1152000,
2958 .uart_offset = 8,
2959 },
2960
2961 [pbn_b2_bt_1_115200] = {
2962 .flags = FL_BASE2|FL_BASE_BARS,
2963 .num_ports = 1,
2964 .base_baud = 115200,
2965 .uart_offset = 8,
2966 },
2967 [pbn_b2_bt_2_115200] = {
2968 .flags = FL_BASE2|FL_BASE_BARS,
2969 .num_ports = 2,
2970 .base_baud = 115200,
2971 .uart_offset = 8,
2972 },
2973 [pbn_b2_bt_4_115200] = {
2974 .flags = FL_BASE2|FL_BASE_BARS,
2975 .num_ports = 4,
2976 .base_baud = 115200,
2977 .uart_offset = 8,
2978 },
2979
2980 [pbn_b2_bt_2_921600] = {
2981 .flags = FL_BASE2|FL_BASE_BARS,
2982 .num_ports = 2,
2983 .base_baud = 921600,
2984 .uart_offset = 8,
2985 },
2986 [pbn_b2_bt_4_921600] = {
2987 .flags = FL_BASE2|FL_BASE_BARS,
2988 .num_ports = 4,
2989 .base_baud = 921600,
2990 .uart_offset = 8,
2991 },
2992
2993 [pbn_b3_2_115200] = {
2994 .flags = FL_BASE3,
2995 .num_ports = 2,
2996 .base_baud = 115200,
2997 .uart_offset = 8,
2998 },
2999 [pbn_b3_4_115200] = {
3000 .flags = FL_BASE3,
3001 .num_ports = 4,
3002 .base_baud = 115200,
3003 .uart_offset = 8,
3004 },
3005 [pbn_b3_8_115200] = {
3006 .flags = FL_BASE3,
3007 .num_ports = 8,
3008 .base_baud = 115200,
3009 .uart_offset = 8,
3010 },
3011
3012 [pbn_b4_bt_2_921600] = {
3013 .flags = FL_BASE4,
3014 .num_ports = 2,
3015 .base_baud = 921600,
3016 .uart_offset = 8,
3017 },
3018 [pbn_b4_bt_4_921600] = {
3019 .flags = FL_BASE4,
3020 .num_ports = 4,
3021 .base_baud = 921600,
3022 .uart_offset = 8,
3023 },
3024 [pbn_b4_bt_8_921600] = {
3025 .flags = FL_BASE4,
3026 .num_ports = 8,
3027 .base_baud = 921600,
3028 .uart_offset = 8,
3029 },
3030
3031 /*
3032 * Entries following this are board-specific.
3033 */
3034
3035 /*
3036 * Panacom - IOMEM
3037 */
3038 [pbn_panacom] = {
3039 .flags = FL_BASE2,
3040 .num_ports = 2,
3041 .base_baud = 921600,
3042 .uart_offset = 0x400,
3043 .reg_shift = 7,
3044 },
3045 [pbn_panacom2] = {
3046 .flags = FL_BASE2|FL_BASE_BARS,
3047 .num_ports = 2,
3048 .base_baud = 921600,
3049 .uart_offset = 0x400,
3050 .reg_shift = 7,
3051 },
3052 [pbn_panacom4] = {
3053 .flags = FL_BASE2|FL_BASE_BARS,
3054 .num_ports = 4,
3055 .base_baud = 921600,
3056 .uart_offset = 0x400,
3057 .reg_shift = 7,
3058 },
3059
3060 /* I think this entry is broken - the first_offset looks wrong --rmk */
3061 [pbn_plx_romulus] = {
3062 .flags = FL_BASE2,
3063 .num_ports = 4,
3064 .base_baud = 921600,
3065 .uart_offset = 8 << 2,
3066 .reg_shift = 2,
3067 .first_offset = 0x03,
3068 },
3069
3070 /*
3071 * EndRun Technologies
3072 * Uses the size of PCI Base region 0 to
3073 * signal now many ports are available
3074 * 2 port 952 Uart support
3075 */
3076 [pbn_endrun_2_4000000] = {
3077 .flags = FL_BASE0,
3078 .num_ports = 2,
3079 .base_baud = 4000000,
3080 .uart_offset = 0x200,
3081 .first_offset = 0x1000,
3082 },
3083
3084 /*
3085 * This board uses the size of PCI Base region 0 to
3086 * signal now many ports are available
3087 */
3088 [pbn_oxsemi] = {
3089 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3090 .num_ports = 32,
3091 .base_baud = 115200,
3092 .uart_offset = 8,
3093 },
3094 [pbn_oxsemi_1_4000000] = {
3095 .flags = FL_BASE0,
3096 .num_ports = 1,
3097 .base_baud = 4000000,
3098 .uart_offset = 0x200,
3099 .first_offset = 0x1000,
3100 },
3101 [pbn_oxsemi_2_4000000] = {
3102 .flags = FL_BASE0,
3103 .num_ports = 2,
3104 .base_baud = 4000000,
3105 .uart_offset = 0x200,
3106 .first_offset = 0x1000,
3107 },
3108 [pbn_oxsemi_4_4000000] = {
3109 .flags = FL_BASE0,
3110 .num_ports = 4,
3111 .base_baud = 4000000,
3112 .uart_offset = 0x200,
3113 .first_offset = 0x1000,
3114 },
3115 [pbn_oxsemi_8_4000000] = {
3116 .flags = FL_BASE0,
3117 .num_ports = 8,
3118 .base_baud = 4000000,
3119 .uart_offset = 0x200,
3120 .first_offset = 0x1000,
3121 },
3122
3123
3124 /*
3125 * EKF addition for i960 Boards form EKF with serial port.
3126 * Max 256 ports.
3127 */
3128 [pbn_intel_i960] = {
3129 .flags = FL_BASE0,
3130 .num_ports = 32,
3131 .base_baud = 921600,
3132 .uart_offset = 8 << 2,
3133 .reg_shift = 2,
3134 .first_offset = 0x10000,
3135 },
3136 [pbn_sgi_ioc3] = {
3137 .flags = FL_BASE0|FL_NOIRQ,
3138 .num_ports = 1,
3139 .base_baud = 458333,
3140 .uart_offset = 8,
3141 .reg_shift = 0,
3142 .first_offset = 0x20178,
3143 },
3144
3145 /*
3146 * Computone - uses IOMEM.
3147 */
3148 [pbn_computone_4] = {
3149 .flags = FL_BASE0,
3150 .num_ports = 4,
3151 .base_baud = 921600,
3152 .uart_offset = 0x40,
3153 .reg_shift = 2,
3154 .first_offset = 0x200,
3155 },
3156 [pbn_computone_6] = {
3157 .flags = FL_BASE0,
3158 .num_ports = 6,
3159 .base_baud = 921600,
3160 .uart_offset = 0x40,
3161 .reg_shift = 2,
3162 .first_offset = 0x200,
3163 },
3164 [pbn_computone_8] = {
3165 .flags = FL_BASE0,
3166 .num_ports = 8,
3167 .base_baud = 921600,
3168 .uart_offset = 0x40,
3169 .reg_shift = 2,
3170 .first_offset = 0x200,
3171 },
3172 [pbn_sbsxrsio] = {
3173 .flags = FL_BASE0,
3174 .num_ports = 8,
3175 .base_baud = 460800,
3176 .uart_offset = 256,
3177 .reg_shift = 4,
3178 },
3179 /*
3180 * PA Semi PWRficient PA6T-1682M on-chip UART
3181 */
3182 [pbn_pasemi_1682M] = {
3183 .flags = FL_BASE0,
3184 .num_ports = 1,
3185 .base_baud = 8333333,
3186 },
3187 /*
3188 * National Instruments 843x
3189 */
3190 [pbn_ni8430_16] = {
3191 .flags = FL_BASE0,
3192 .num_ports = 16,
3193 .base_baud = 3686400,
3194 .uart_offset = 0x10,
3195 .first_offset = 0x800,
3196 },
3197 [pbn_ni8430_8] = {
3198 .flags = FL_BASE0,
3199 .num_ports = 8,
3200 .base_baud = 3686400,
3201 .uart_offset = 0x10,
3202 .first_offset = 0x800,
3203 },
3204 [pbn_ni8430_4] = {
3205 .flags = FL_BASE0,
3206 .num_ports = 4,
3207 .base_baud = 3686400,
3208 .uart_offset = 0x10,
3209 .first_offset = 0x800,
3210 },
3211 [pbn_ni8430_2] = {
3212 .flags = FL_BASE0,
3213 .num_ports = 2,
3214 .base_baud = 3686400,
3215 .uart_offset = 0x10,
3216 .first_offset = 0x800,
3217 },
3218 /*
3219 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3220 */
3221 [pbn_ADDIDATA_PCIe_1_3906250] = {
3222 .flags = FL_BASE0,
3223 .num_ports = 1,
3224 .base_baud = 3906250,
3225 .uart_offset = 0x200,
3226 .first_offset = 0x1000,
3227 },
3228 [pbn_ADDIDATA_PCIe_2_3906250] = {
3229 .flags = FL_BASE0,
3230 .num_ports = 2,
3231 .base_baud = 3906250,
3232 .uart_offset = 0x200,
3233 .first_offset = 0x1000,
3234 },
3235 [pbn_ADDIDATA_PCIe_4_3906250] = {
3236 .flags = FL_BASE0,
3237 .num_ports = 4,
3238 .base_baud = 3906250,
3239 .uart_offset = 0x200,
3240 .first_offset = 0x1000,
3241 },
3242 [pbn_ADDIDATA_PCIe_8_3906250] = {
3243 .flags = FL_BASE0,
3244 .num_ports = 8,
3245 .base_baud = 3906250,
3246 .uart_offset = 0x200,
3247 .first_offset = 0x1000,
3248 },
3249 [pbn_ce4100_1_115200] = {
3250 .flags = FL_BASE_BARS,
3251 .num_ports = 2,
3252 .base_baud = 921600,
3253 .reg_shift = 2,
3254 },
3255 [pbn_omegapci] = {
3256 .flags = FL_BASE0,
3257 .num_ports = 8,
3258 .base_baud = 115200,
3259 .uart_offset = 0x200,
3260 },
3261 [pbn_NETMOS9900_2s_115200] = {
3262 .flags = FL_BASE0,
3263 .num_ports = 2,
3264 .base_baud = 115200,
3265 },
3266 [pbn_brcm_trumanage] = {
3267 .flags = FL_BASE0,
3268 .num_ports = 1,
3269 .reg_shift = 2,
3270 .base_baud = 115200,
3271 },
3272 [pbn_fintek_4] = {
3273 .num_ports = 4,
3274 .uart_offset = 8,
3275 .base_baud = 115200,
3276 .first_offset = 0x40,
3277 },
3278 [pbn_fintek_8] = {
3279 .num_ports = 8,
3280 .uart_offset = 8,
3281 .base_baud = 115200,
3282 .first_offset = 0x40,
3283 },
3284 [pbn_fintek_12] = {
3285 .num_ports = 12,
3286 .uart_offset = 8,
3287 .base_baud = 115200,
3288 .first_offset = 0x40,
3289 },
3290 [pbn_wch382_2] = {
3291 .flags = FL_BASE0,
3292 .num_ports = 2,
3293 .base_baud = 115200,
3294 .uart_offset = 8,
3295 .first_offset = 0xC0,
3296 },
3297 [pbn_wch384_4] = {
3298 .flags = FL_BASE0,
3299 .num_ports = 4,
3300 .base_baud = 115200,
3301 .uart_offset = 8,
3302 .first_offset = 0xC0,
3303 },
3304 /*
3305 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3306 */
3307 [pbn_pericom_PI7C9X7951] = {
3308 .flags = FL_BASE0,
3309 .num_ports = 1,
3310 .base_baud = 921600,
3311 .uart_offset = 0x8,
3312 },
3313 [pbn_pericom_PI7C9X7952] = {
3314 .flags = FL_BASE0,
3315 .num_ports = 2,
3316 .base_baud = 921600,
3317 .uart_offset = 0x8,
3318 },
3319 [pbn_pericom_PI7C9X7954] = {
3320 .flags = FL_BASE0,
3321 .num_ports = 4,
3322 .base_baud = 921600,
3323 .uart_offset = 0x8,
3324 },
3325 [pbn_pericom_PI7C9X7958] = {
3326 .flags = FL_BASE0,
3327 .num_ports = 8,
3328 .base_baud = 921600,
3329 .uart_offset = 0x8,
3330 },
3331 };
3332
3333 static const struct pci_device_id blacklist[] = {
3334 /* softmodems */
3335 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3336 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3337 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3338
3339 /* multi-io cards handled by parport_serial */
3340 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3341 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3342 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3343
3344 /* Moxa Smartio MUE boards handled by 8250_moxa */
3345 { PCI_VDEVICE(MOXA, 0x1024), },
3346 { PCI_VDEVICE(MOXA, 0x1025), },
3347 { PCI_VDEVICE(MOXA, 0x1045), },
3348 { PCI_VDEVICE(MOXA, 0x1144), },
3349 { PCI_VDEVICE(MOXA, 0x1160), },
3350 { PCI_VDEVICE(MOXA, 0x1161), },
3351 { PCI_VDEVICE(MOXA, 0x1182), },
3352 { PCI_VDEVICE(MOXA, 0x1183), },
3353 { PCI_VDEVICE(MOXA, 0x1322), },
3354 { PCI_VDEVICE(MOXA, 0x1342), },
3355 { PCI_VDEVICE(MOXA, 0x1381), },
3356 { PCI_VDEVICE(MOXA, 0x1683), },
3357
3358 /* Intel platforms with MID UART */
3359 { PCI_VDEVICE(INTEL, 0x081b), },
3360 { PCI_VDEVICE(INTEL, 0x081c), },
3361 { PCI_VDEVICE(INTEL, 0x081d), },
3362 { PCI_VDEVICE(INTEL, 0x1191), },
3363 { PCI_VDEVICE(INTEL, 0x18d8), },
3364 { PCI_VDEVICE(INTEL, 0x19d8), },
3365
3366 /* Intel platforms with DesignWare UART */
3367 { PCI_VDEVICE(INTEL, 0x0936), },
3368 { PCI_VDEVICE(INTEL, 0x0f0a), },
3369 { PCI_VDEVICE(INTEL, 0x0f0c), },
3370 { PCI_VDEVICE(INTEL, 0x228a), },
3371 { PCI_VDEVICE(INTEL, 0x228c), },
3372 { PCI_VDEVICE(INTEL, 0x9ce3), },
3373 { PCI_VDEVICE(INTEL, 0x9ce4), },
3374
3375 /* Exar devices */
3376 { PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3377 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
3378 };
3379
serial_pci_is_class_communication(struct pci_dev * dev)3380 static int serial_pci_is_class_communication(struct pci_dev *dev)
3381 {
3382 /*
3383 * If it is not a communications device or the programming
3384 * interface is greater than 6, give up.
3385 */
3386 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3387 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3388 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3389 (dev->class & 0xff) > 6)
3390 return -ENODEV;
3391
3392 return 0;
3393 }
3394
serial_pci_is_blacklisted(struct pci_dev * dev)3395 static int serial_pci_is_blacklisted(struct pci_dev *dev)
3396 {
3397 const struct pci_device_id *bldev;
3398
3399 /*
3400 * Do not access blacklisted devices that are known not to
3401 * feature serial ports or are handled by other modules.
3402 */
3403 for (bldev = blacklist;
3404 bldev < blacklist + ARRAY_SIZE(blacklist);
3405 bldev++) {
3406 if (dev->vendor == bldev->vendor &&
3407 dev->device == bldev->device)
3408 return -ENODEV;
3409 }
3410
3411 return 0;
3412 }
3413
3414 /*
3415 * Given a complete unknown PCI device, try to use some heuristics to
3416 * guess what the configuration might be, based on the pitiful PCI
3417 * serial specs. Returns 0 on success, -ENODEV on failure.
3418 */
3419 static int
serial_pci_guess_board(struct pci_dev * dev,struct pciserial_board * board)3420 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3421 {
3422 int num_iomem, num_port, first_port = -1, i;
3423
3424 /*
3425 * Should we try to make guesses for multiport serial devices later?
3426 */
3427 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
3428 return -ENODEV;
3429
3430 num_iomem = num_port = 0;
3431 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3432 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3433 num_port++;
3434 if (first_port == -1)
3435 first_port = i;
3436 }
3437 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3438 num_iomem++;
3439 }
3440
3441 /*
3442 * If there is 1 or 0 iomem regions, and exactly one port,
3443 * use it. We guess the number of ports based on the IO
3444 * region size.
3445 */
3446 if (num_iomem <= 1 && num_port == 1) {
3447 board->flags = first_port;
3448 board->num_ports = pci_resource_len(dev, first_port) / 8;
3449 return 0;
3450 }
3451
3452 /*
3453 * Now guess if we've got a board which indexes by BARs.
3454 * Each IO BAR should be 8 bytes, and they should follow
3455 * consecutively.
3456 */
3457 first_port = -1;
3458 num_port = 0;
3459 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3460 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3461 pci_resource_len(dev, i) == 8 &&
3462 (first_port == -1 || (first_port + num_port) == i)) {
3463 num_port++;
3464 if (first_port == -1)
3465 first_port = i;
3466 }
3467 }
3468
3469 if (num_port > 1) {
3470 board->flags = first_port | FL_BASE_BARS;
3471 board->num_ports = num_port;
3472 return 0;
3473 }
3474
3475 return -ENODEV;
3476 }
3477
3478 static inline int
serial_pci_matches(const struct pciserial_board * board,const struct pciserial_board * guessed)3479 serial_pci_matches(const struct pciserial_board *board,
3480 const struct pciserial_board *guessed)
3481 {
3482 return
3483 board->num_ports == guessed->num_ports &&
3484 board->base_baud == guessed->base_baud &&
3485 board->uart_offset == guessed->uart_offset &&
3486 board->reg_shift == guessed->reg_shift &&
3487 board->first_offset == guessed->first_offset;
3488 }
3489
3490 struct serial_private *
pciserial_init_ports(struct pci_dev * dev,const struct pciserial_board * board)3491 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3492 {
3493 struct uart_8250_port uart;
3494 struct serial_private *priv;
3495 struct pci_serial_quirk *quirk;
3496 int rc, nr_ports, i;
3497
3498 nr_ports = board->num_ports;
3499
3500 /*
3501 * Find an init and setup quirks.
3502 */
3503 quirk = find_quirk(dev);
3504
3505 /*
3506 * Run the new-style initialization function.
3507 * The initialization function returns:
3508 * <0 - error
3509 * 0 - use board->num_ports
3510 * >0 - number of ports
3511 */
3512 if (quirk->init) {
3513 rc = quirk->init(dev);
3514 if (rc < 0) {
3515 priv = ERR_PTR(rc);
3516 goto err_out;
3517 }
3518 if (rc)
3519 nr_ports = rc;
3520 }
3521
3522 priv = kzalloc(sizeof(struct serial_private) +
3523 sizeof(unsigned int) * nr_ports,
3524 GFP_KERNEL);
3525 if (!priv) {
3526 priv = ERR_PTR(-ENOMEM);
3527 goto err_deinit;
3528 }
3529
3530 priv->dev = dev;
3531 priv->quirk = quirk;
3532
3533 memset(&uart, 0, sizeof(uart));
3534 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3535 uart.port.uartclk = board->base_baud * 16;
3536 uart.port.irq = get_pci_irq(dev, board);
3537 uart.port.dev = &dev->dev;
3538
3539 for (i = 0; i < nr_ports; i++) {
3540 if (quirk->setup(priv, board, &uart, i))
3541 break;
3542
3543 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3544 uart.port.iobase, uart.port.irq, uart.port.iotype);
3545
3546 priv->line[i] = serial8250_register_8250_port(&uart);
3547 if (priv->line[i] < 0) {
3548 dev_err(&dev->dev,
3549 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3550 uart.port.iobase, uart.port.irq,
3551 uart.port.iotype, priv->line[i]);
3552 break;
3553 }
3554 }
3555 priv->nr = i;
3556 priv->board = board;
3557 return priv;
3558
3559 err_deinit:
3560 if (quirk->exit)
3561 quirk->exit(dev);
3562 err_out:
3563 return priv;
3564 }
3565 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3566
pciserial_detach_ports(struct serial_private * priv)3567 static void pciserial_detach_ports(struct serial_private *priv)
3568 {
3569 struct pci_serial_quirk *quirk;
3570 int i;
3571
3572 for (i = 0; i < priv->nr; i++)
3573 serial8250_unregister_port(priv->line[i]);
3574
3575 /*
3576 * Find the exit quirks.
3577 */
3578 quirk = find_quirk(priv->dev);
3579 if (quirk->exit)
3580 quirk->exit(priv->dev);
3581 }
3582
pciserial_remove_ports(struct serial_private * priv)3583 void pciserial_remove_ports(struct serial_private *priv)
3584 {
3585 pciserial_detach_ports(priv);
3586 kfree(priv);
3587 }
3588 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3589
pciserial_suspend_ports(struct serial_private * priv)3590 void pciserial_suspend_ports(struct serial_private *priv)
3591 {
3592 int i;
3593
3594 for (i = 0; i < priv->nr; i++)
3595 if (priv->line[i] >= 0)
3596 serial8250_suspend_port(priv->line[i]);
3597
3598 /*
3599 * Ensure that every init quirk is properly torn down
3600 */
3601 if (priv->quirk->exit)
3602 priv->quirk->exit(priv->dev);
3603 }
3604 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3605
pciserial_resume_ports(struct serial_private * priv)3606 void pciserial_resume_ports(struct serial_private *priv)
3607 {
3608 int i;
3609
3610 /*
3611 * Ensure that the board is correctly configured.
3612 */
3613 if (priv->quirk->init)
3614 priv->quirk->init(priv->dev);
3615
3616 for (i = 0; i < priv->nr; i++)
3617 if (priv->line[i] >= 0)
3618 serial8250_resume_port(priv->line[i]);
3619 }
3620 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3621
3622 /*
3623 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3624 * to the arrangement of serial ports on a PCI card.
3625 */
3626 static int
pciserial_init_one(struct pci_dev * dev,const struct pci_device_id * ent)3627 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3628 {
3629 struct pci_serial_quirk *quirk;
3630 struct serial_private *priv;
3631 const struct pciserial_board *board;
3632 struct pciserial_board tmp;
3633 int rc;
3634
3635 quirk = find_quirk(dev);
3636 if (quirk->probe) {
3637 rc = quirk->probe(dev);
3638 if (rc)
3639 return rc;
3640 }
3641
3642 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3643 dev_err(&dev->dev, "invalid driver_data: %ld\n",
3644 ent->driver_data);
3645 return -EINVAL;
3646 }
3647
3648 board = &pci_boards[ent->driver_data];
3649
3650 rc = serial_pci_is_class_communication(dev);
3651 if (rc)
3652 return rc;
3653
3654 rc = serial_pci_is_blacklisted(dev);
3655 if (rc)
3656 return rc;
3657
3658 rc = pcim_enable_device(dev);
3659 pci_save_state(dev);
3660 if (rc)
3661 return rc;
3662
3663 if (ent->driver_data == pbn_default) {
3664 /*
3665 * Use a copy of the pci_board entry for this;
3666 * avoid changing entries in the table.
3667 */
3668 memcpy(&tmp, board, sizeof(struct pciserial_board));
3669 board = &tmp;
3670
3671 /*
3672 * We matched one of our class entries. Try to
3673 * determine the parameters of this board.
3674 */
3675 rc = serial_pci_guess_board(dev, &tmp);
3676 if (rc)
3677 return rc;
3678 } else {
3679 /*
3680 * We matched an explicit entry. If we are able to
3681 * detect this boards settings with our heuristic,
3682 * then we no longer need this entry.
3683 */
3684 memcpy(&tmp, &pci_boards[pbn_default],
3685 sizeof(struct pciserial_board));
3686 rc = serial_pci_guess_board(dev, &tmp);
3687 if (rc == 0 && serial_pci_matches(board, &tmp))
3688 moan_device("Redundant entry in serial pci_table.",
3689 dev);
3690 }
3691
3692 priv = pciserial_init_ports(dev, board);
3693 if (IS_ERR(priv))
3694 return PTR_ERR(priv);
3695
3696 pci_set_drvdata(dev, priv);
3697 return 0;
3698 }
3699
pciserial_remove_one(struct pci_dev * dev)3700 static void pciserial_remove_one(struct pci_dev *dev)
3701 {
3702 struct serial_private *priv = pci_get_drvdata(dev);
3703
3704 pciserial_remove_ports(priv);
3705 }
3706
3707 #ifdef CONFIG_PM_SLEEP
pciserial_suspend_one(struct device * dev)3708 static int pciserial_suspend_one(struct device *dev)
3709 {
3710 struct pci_dev *pdev = to_pci_dev(dev);
3711 struct serial_private *priv = pci_get_drvdata(pdev);
3712
3713 if (priv)
3714 pciserial_suspend_ports(priv);
3715
3716 return 0;
3717 }
3718
pciserial_resume_one(struct device * dev)3719 static int pciserial_resume_one(struct device *dev)
3720 {
3721 struct pci_dev *pdev = to_pci_dev(dev);
3722 struct serial_private *priv = pci_get_drvdata(pdev);
3723 int err;
3724
3725 if (priv) {
3726 /*
3727 * The device may have been disabled. Re-enable it.
3728 */
3729 err = pci_enable_device(pdev);
3730 /* FIXME: We cannot simply error out here */
3731 if (err)
3732 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
3733 pciserial_resume_ports(priv);
3734 }
3735 return 0;
3736 }
3737 #endif
3738
3739 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
3740 pciserial_resume_one);
3741
3742 static const struct pci_device_id serial_pci_tbl[] = {
3743 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3744 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3745 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3746 pbn_b2_8_921600 },
3747 /* Advantech also use 0x3618 and 0xf618 */
3748 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
3749 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3750 pbn_b0_4_921600 },
3751 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
3752 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3753 pbn_b0_4_921600 },
3754 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3755 PCI_SUBVENDOR_ID_CONNECT_TECH,
3756 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3757 pbn_b1_8_1382400 },
3758 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3759 PCI_SUBVENDOR_ID_CONNECT_TECH,
3760 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3761 pbn_b1_4_1382400 },
3762 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3763 PCI_SUBVENDOR_ID_CONNECT_TECH,
3764 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3765 pbn_b1_2_1382400 },
3766 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3767 PCI_SUBVENDOR_ID_CONNECT_TECH,
3768 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3769 pbn_b1_8_1382400 },
3770 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3771 PCI_SUBVENDOR_ID_CONNECT_TECH,
3772 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3773 pbn_b1_4_1382400 },
3774 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3775 PCI_SUBVENDOR_ID_CONNECT_TECH,
3776 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3777 pbn_b1_2_1382400 },
3778 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3779 PCI_SUBVENDOR_ID_CONNECT_TECH,
3780 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3781 pbn_b1_8_921600 },
3782 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3783 PCI_SUBVENDOR_ID_CONNECT_TECH,
3784 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3785 pbn_b1_8_921600 },
3786 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3787 PCI_SUBVENDOR_ID_CONNECT_TECH,
3788 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3789 pbn_b1_4_921600 },
3790 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3791 PCI_SUBVENDOR_ID_CONNECT_TECH,
3792 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3793 pbn_b1_4_921600 },
3794 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3795 PCI_SUBVENDOR_ID_CONNECT_TECH,
3796 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3797 pbn_b1_2_921600 },
3798 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3799 PCI_SUBVENDOR_ID_CONNECT_TECH,
3800 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3801 pbn_b1_8_921600 },
3802 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3803 PCI_SUBVENDOR_ID_CONNECT_TECH,
3804 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3805 pbn_b1_8_921600 },
3806 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3807 PCI_SUBVENDOR_ID_CONNECT_TECH,
3808 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3809 pbn_b1_4_921600 },
3810 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3811 PCI_SUBVENDOR_ID_CONNECT_TECH,
3812 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3813 pbn_b1_2_1250000 },
3814 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3815 PCI_SUBVENDOR_ID_CONNECT_TECH,
3816 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3817 pbn_b0_2_1843200 },
3818 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3819 PCI_SUBVENDOR_ID_CONNECT_TECH,
3820 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3821 pbn_b0_4_1843200 },
3822 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3823 PCI_VENDOR_ID_AFAVLAB,
3824 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3825 pbn_b0_4_1152000 },
3826 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3828 pbn_b2_bt_1_115200 },
3829 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3830 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3831 pbn_b2_bt_2_115200 },
3832 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3833 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3834 pbn_b2_bt_4_115200 },
3835 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3836 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3837 pbn_b2_bt_2_115200 },
3838 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3840 pbn_b2_bt_4_115200 },
3841 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3842 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3843 pbn_b2_8_115200 },
3844 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3846 pbn_b2_8_460800 },
3847 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3849 pbn_b2_8_115200 },
3850
3851 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3853 pbn_b2_bt_2_115200 },
3854 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3855 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3856 pbn_b2_bt_2_921600 },
3857 /*
3858 * VScom SPCOM800, from sl@s.pl
3859 */
3860 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3861 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3862 pbn_b2_8_921600 },
3863 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3864 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3865 pbn_b2_4_921600 },
3866 /* Unknown card - subdevice 0x1584 */
3867 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3868 PCI_VENDOR_ID_PLX,
3869 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3870 pbn_b2_4_115200 },
3871 /* Unknown card - subdevice 0x1588 */
3872 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3873 PCI_VENDOR_ID_PLX,
3874 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
3875 pbn_b2_8_115200 },
3876 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3877 PCI_SUBVENDOR_ID_KEYSPAN,
3878 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3879 pbn_panacom },
3880 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3882 pbn_panacom4 },
3883 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3884 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3885 pbn_panacom2 },
3886 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3887 PCI_VENDOR_ID_ESDGMBH,
3888 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3889 pbn_b2_4_115200 },
3890 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3891 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3892 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3893 pbn_b2_4_460800 },
3894 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3895 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3896 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3897 pbn_b2_8_460800 },
3898 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3899 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3900 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3901 pbn_b2_16_460800 },
3902 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3903 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3904 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3905 pbn_b2_16_460800 },
3906 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3907 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3908 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3909 pbn_b2_4_460800 },
3910 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3911 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3912 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3913 pbn_b2_8_460800 },
3914 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3915 PCI_SUBVENDOR_ID_EXSYS,
3916 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3917 pbn_b2_4_115200 },
3918 /*
3919 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3920 * (Exoray@isys.ca)
3921 */
3922 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3923 0x10b5, 0x106a, 0, 0,
3924 pbn_plx_romulus },
3925 /*
3926 * EndRun Technologies. PCI express device range.
3927 * EndRun PTP/1588 has 2 Native UARTs.
3928 */
3929 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
3930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3931 pbn_endrun_2_4000000 },
3932 /*
3933 * Quatech cards. These actually have configurable clocks but for
3934 * now we just use the default.
3935 *
3936 * 100 series are RS232, 200 series RS422,
3937 */
3938 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3940 pbn_b1_4_115200 },
3941 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3943 pbn_b1_2_115200 },
3944 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
3945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3946 pbn_b2_2_115200 },
3947 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
3948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3949 pbn_b1_2_115200 },
3950 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
3951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3952 pbn_b2_2_115200 },
3953 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
3954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3955 pbn_b1_4_115200 },
3956 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3958 pbn_b1_8_115200 },
3959 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3961 pbn_b1_8_115200 },
3962 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
3963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3964 pbn_b1_4_115200 },
3965 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
3966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3967 pbn_b1_2_115200 },
3968 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
3969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3970 pbn_b1_4_115200 },
3971 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
3972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3973 pbn_b1_2_115200 },
3974 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
3975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3976 pbn_b2_4_115200 },
3977 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
3978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3979 pbn_b2_2_115200 },
3980 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
3981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3982 pbn_b2_1_115200 },
3983 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
3984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3985 pbn_b2_4_115200 },
3986 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
3987 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3988 pbn_b2_2_115200 },
3989 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
3990 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3991 pbn_b2_1_115200 },
3992 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
3993 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3994 pbn_b0_8_115200 },
3995
3996 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3997 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3998 0, 0,
3999 pbn_b0_4_921600 },
4000 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4001 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4002 0, 0,
4003 pbn_b0_4_1152000 },
4004 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4006 pbn_b0_bt_2_921600 },
4007
4008 /*
4009 * The below card is a little controversial since it is the
4010 * subject of a PCI vendor/device ID clash. (See
4011 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4012 * For now just used the hex ID 0x950a.
4013 */
4014 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4015 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4016 0, 0, pbn_b0_2_115200 },
4017 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4018 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4019 0, 0, pbn_b0_2_115200 },
4020 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4021 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4022 pbn_b0_2_1130000 },
4023 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4024 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4025 pbn_b0_1_921600 },
4026 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4028 pbn_b0_4_115200 },
4029 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4030 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4031 pbn_b0_bt_2_921600 },
4032 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4034 pbn_b2_8_1152000 },
4035
4036 /*
4037 * Oxford Semiconductor Inc. Tornado PCI express device range.
4038 */
4039 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4040 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4041 pbn_b0_1_4000000 },
4042 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4044 pbn_b0_1_4000000 },
4045 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4046 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4047 pbn_oxsemi_1_4000000 },
4048 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4049 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4050 pbn_oxsemi_1_4000000 },
4051 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4052 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4053 pbn_b0_1_4000000 },
4054 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4055 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4056 pbn_b0_1_4000000 },
4057 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4059 pbn_oxsemi_1_4000000 },
4060 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4062 pbn_oxsemi_1_4000000 },
4063 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4065 pbn_b0_1_4000000 },
4066 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4067 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4068 pbn_b0_1_4000000 },
4069 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4070 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4071 pbn_b0_1_4000000 },
4072 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4073 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4074 pbn_b0_1_4000000 },
4075 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4076 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4077 pbn_oxsemi_2_4000000 },
4078 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4079 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4080 pbn_oxsemi_2_4000000 },
4081 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4083 pbn_oxsemi_4_4000000 },
4084 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4086 pbn_oxsemi_4_4000000 },
4087 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4088 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4089 pbn_oxsemi_8_4000000 },
4090 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4092 pbn_oxsemi_8_4000000 },
4093 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4094 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4095 pbn_oxsemi_1_4000000 },
4096 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4097 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4098 pbn_oxsemi_1_4000000 },
4099 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4100 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4101 pbn_oxsemi_1_4000000 },
4102 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4103 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4104 pbn_oxsemi_1_4000000 },
4105 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4106 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4107 pbn_oxsemi_1_4000000 },
4108 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4109 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4110 pbn_oxsemi_1_4000000 },
4111 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4112 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4113 pbn_oxsemi_1_4000000 },
4114 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4115 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4116 pbn_oxsemi_1_4000000 },
4117 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4118 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4119 pbn_oxsemi_1_4000000 },
4120 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4121 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4122 pbn_oxsemi_1_4000000 },
4123 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4124 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4125 pbn_oxsemi_1_4000000 },
4126 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4128 pbn_oxsemi_1_4000000 },
4129 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4131 pbn_oxsemi_1_4000000 },
4132 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4134 pbn_oxsemi_1_4000000 },
4135 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4137 pbn_oxsemi_1_4000000 },
4138 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4140 pbn_oxsemi_1_4000000 },
4141 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4142 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4143 pbn_oxsemi_1_4000000 },
4144 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4145 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4146 pbn_oxsemi_1_4000000 },
4147 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4148 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4149 pbn_oxsemi_1_4000000 },
4150 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4151 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4152 pbn_oxsemi_1_4000000 },
4153 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4154 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4155 pbn_oxsemi_1_4000000 },
4156 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4158 pbn_oxsemi_1_4000000 },
4159 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4161 pbn_oxsemi_1_4000000 },
4162 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4164 pbn_oxsemi_1_4000000 },
4165 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4167 pbn_oxsemi_1_4000000 },
4168 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4170 pbn_oxsemi_1_4000000 },
4171 /*
4172 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4173 */
4174 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4175 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4176 pbn_oxsemi_1_4000000 },
4177 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4178 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4179 pbn_oxsemi_2_4000000 },
4180 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4181 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4182 pbn_oxsemi_4_4000000 },
4183 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4184 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4185 pbn_oxsemi_8_4000000 },
4186
4187 /*
4188 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4189 */
4190 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4191 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4192 pbn_oxsemi_2_4000000 },
4193
4194 /*
4195 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4196 * from skokodyn@yahoo.com
4197 */
4198 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4199 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4200 pbn_sbsxrsio },
4201 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4202 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4203 pbn_sbsxrsio },
4204 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4205 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4206 pbn_sbsxrsio },
4207 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4208 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4209 pbn_sbsxrsio },
4210
4211 /*
4212 * Digitan DS560-558, from jimd@esoft.com
4213 */
4214 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4215 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4216 pbn_b1_1_115200 },
4217
4218 /*
4219 * Titan Electronic cards
4220 * The 400L and 800L have a custom setup quirk.
4221 */
4222 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4223 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4224 pbn_b0_1_921600 },
4225 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4226 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4227 pbn_b0_2_921600 },
4228 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4230 pbn_b0_4_921600 },
4231 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4232 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4233 pbn_b0_4_921600 },
4234 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4235 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4236 pbn_b1_1_921600 },
4237 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4238 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4239 pbn_b1_bt_2_921600 },
4240 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4241 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4242 pbn_b0_bt_4_921600 },
4243 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4245 pbn_b0_bt_8_921600 },
4246 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4247 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4248 pbn_b4_bt_2_921600 },
4249 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4250 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4251 pbn_b4_bt_4_921600 },
4252 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4253 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4254 pbn_b4_bt_8_921600 },
4255 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4256 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4257 pbn_b0_4_921600 },
4258 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4259 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4260 pbn_b0_4_921600 },
4261 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4262 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4263 pbn_b0_4_921600 },
4264 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4265 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4266 pbn_oxsemi_1_4000000 },
4267 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4268 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4269 pbn_oxsemi_2_4000000 },
4270 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4271 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4272 pbn_oxsemi_4_4000000 },
4273 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4274 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4275 pbn_oxsemi_8_4000000 },
4276 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4278 pbn_oxsemi_2_4000000 },
4279 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4281 pbn_oxsemi_2_4000000 },
4282 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4284 pbn_b0_bt_2_921600 },
4285 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4287 pbn_b0_4_921600 },
4288 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4290 pbn_b0_4_921600 },
4291 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4292 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4293 pbn_b0_4_921600 },
4294 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4295 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4296 pbn_b0_4_921600 },
4297
4298 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4299 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4300 pbn_b2_1_460800 },
4301 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4303 pbn_b2_1_460800 },
4304 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4305 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4306 pbn_b2_1_460800 },
4307 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4308 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4309 pbn_b2_bt_2_921600 },
4310 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4311 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312 pbn_b2_bt_2_921600 },
4313 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4314 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4315 pbn_b2_bt_2_921600 },
4316 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4317 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4318 pbn_b2_bt_4_921600 },
4319 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4320 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4321 pbn_b2_bt_4_921600 },
4322 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4323 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4324 pbn_b2_bt_4_921600 },
4325 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4326 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4327 pbn_b0_1_921600 },
4328 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4329 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4330 pbn_b0_1_921600 },
4331 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4333 pbn_b0_1_921600 },
4334 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336 pbn_b0_bt_2_921600 },
4337 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339 pbn_b0_bt_2_921600 },
4340 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 pbn_b0_bt_2_921600 },
4343 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4344 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345 pbn_b0_bt_4_921600 },
4346 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348 pbn_b0_bt_4_921600 },
4349 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4350 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351 pbn_b0_bt_4_921600 },
4352 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4353 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4354 pbn_b0_bt_8_921600 },
4355 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4357 pbn_b0_bt_8_921600 },
4358 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4360 pbn_b0_bt_8_921600 },
4361
4362 /*
4363 * Computone devices submitted by Doug McNash dmcnash@computone.com
4364 */
4365 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4366 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4367 0, 0, pbn_computone_4 },
4368 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4369 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4370 0, 0, pbn_computone_8 },
4371 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4372 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4373 0, 0, pbn_computone_6 },
4374
4375 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4376 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4377 pbn_oxsemi },
4378 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4379 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4380 pbn_b0_bt_1_921600 },
4381
4382 /*
4383 * SUNIX (TIMEDIA)
4384 */
4385 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4386 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4387 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4388 pbn_b0_bt_1_921600 },
4389
4390 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4391 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4392 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4393 pbn_b0_bt_1_921600 },
4394
4395 /*
4396 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4397 */
4398 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4400 pbn_b0_bt_8_115200 },
4401 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4403 pbn_b0_bt_8_115200 },
4404
4405 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4407 pbn_b0_bt_2_115200 },
4408 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4410 pbn_b0_bt_2_115200 },
4411 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4413 pbn_b0_bt_2_115200 },
4414 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4416 pbn_b0_bt_2_115200 },
4417 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4419 pbn_b0_bt_2_115200 },
4420 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4422 pbn_b0_bt_4_460800 },
4423 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4425 pbn_b0_bt_4_460800 },
4426 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4428 pbn_b0_bt_2_460800 },
4429 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4431 pbn_b0_bt_2_460800 },
4432 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4434 pbn_b0_bt_2_460800 },
4435 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4437 pbn_b0_bt_1_115200 },
4438 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4440 pbn_b0_bt_1_460800 },
4441
4442 /*
4443 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4444 * Cards are identified by their subsystem vendor IDs, which
4445 * (in hex) match the model number.
4446 *
4447 * Note that JC140x are RS422/485 cards which require ox950
4448 * ACR = 0x10, and as such are not currently fully supported.
4449 */
4450 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4451 0x1204, 0x0004, 0, 0,
4452 pbn_b0_4_921600 },
4453 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4454 0x1208, 0x0004, 0, 0,
4455 pbn_b0_4_921600 },
4456 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4457 0x1402, 0x0002, 0, 0,
4458 pbn_b0_2_921600 }, */
4459 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4460 0x1404, 0x0004, 0, 0,
4461 pbn_b0_4_921600 }, */
4462 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4463 0x1208, 0x0004, 0, 0,
4464 pbn_b0_4_921600 },
4465
4466 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4467 0x1204, 0x0004, 0, 0,
4468 pbn_b0_4_921600 },
4469 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4470 0x1208, 0x0004, 0, 0,
4471 pbn_b0_4_921600 },
4472 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4473 0x1208, 0x0004, 0, 0,
4474 pbn_b0_4_921600 },
4475 /*
4476 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4477 */
4478 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4480 pbn_b1_1_1382400 },
4481
4482 /*
4483 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4484 */
4485 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4487 pbn_b1_1_1382400 },
4488
4489 /*
4490 * RAStel 2 port modem, gerg@moreton.com.au
4491 */
4492 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4494 pbn_b2_bt_2_115200 },
4495
4496 /*
4497 * EKF addition for i960 Boards form EKF with serial port
4498 */
4499 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4500 0xE4BF, PCI_ANY_ID, 0, 0,
4501 pbn_intel_i960 },
4502
4503 /*
4504 * Xircom Cardbus/Ethernet combos
4505 */
4506 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4508 pbn_b0_1_115200 },
4509 /*
4510 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4511 */
4512 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514 pbn_b0_1_115200 },
4515
4516 /*
4517 * Untested PCI modems, sent in from various folks...
4518 */
4519
4520 /*
4521 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4522 */
4523 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4524 0x1048, 0x1500, 0, 0,
4525 pbn_b1_1_115200 },
4526
4527 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4528 0xFF00, 0, 0, 0,
4529 pbn_sgi_ioc3 },
4530
4531 /*
4532 * HP Diva card
4533 */
4534 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4535 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4536 pbn_b1_1_115200 },
4537 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4538 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4539 pbn_b0_5_115200 },
4540 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4541 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4542 pbn_b2_1_115200 },
4543
4544 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4545 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4546 pbn_b3_2_115200 },
4547 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4548 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4549 pbn_b3_4_115200 },
4550 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4551 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4552 pbn_b3_8_115200 },
4553 /*
4554 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
4555 */
4556 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
4557 PCI_ANY_ID, PCI_ANY_ID,
4558 0,
4559 0, pbn_pericom_PI7C9X7951 },
4560 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
4561 PCI_ANY_ID, PCI_ANY_ID,
4562 0,
4563 0, pbn_pericom_PI7C9X7952 },
4564 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
4565 PCI_ANY_ID, PCI_ANY_ID,
4566 0,
4567 0, pbn_pericom_PI7C9X7954 },
4568 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
4569 PCI_ANY_ID, PCI_ANY_ID,
4570 0,
4571 0, pbn_pericom_PI7C9X7958 },
4572 /*
4573 * ACCES I/O Products quad
4574 */
4575 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577 pbn_pericom_PI7C9X7954 },
4578 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580 pbn_pericom_PI7C9X7954 },
4581 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583 pbn_pericom_PI7C9X7954 },
4584 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 pbn_pericom_PI7C9X7954 },
4587 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 pbn_pericom_PI7C9X7954 },
4590 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592 pbn_pericom_PI7C9X7954 },
4593 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 pbn_pericom_PI7C9X7954 },
4596 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598 pbn_pericom_PI7C9X7954 },
4599 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601 pbn_pericom_PI7C9X7954 },
4602 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4604 pbn_pericom_PI7C9X7954 },
4605 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 pbn_pericom_PI7C9X7954 },
4608 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 pbn_pericom_PI7C9X7954 },
4611 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613 pbn_pericom_PI7C9X7954 },
4614 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616 pbn_pericom_PI7C9X7954 },
4617 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619 pbn_pericom_PI7C9X7954 },
4620 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622 pbn_pericom_PI7C9X7954 },
4623 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625 pbn_pericom_PI7C9X7954 },
4626 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628 pbn_pericom_PI7C9X7954 },
4629 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4631 pbn_pericom_PI7C9X7954 },
4632 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
4633 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4634 pbn_pericom_PI7C9X7954 },
4635 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637 pbn_pericom_PI7C9X7954 },
4638 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
4639 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4640 pbn_pericom_PI7C9X7954 },
4641 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
4642 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4643 pbn_pericom_PI7C9X7954 },
4644 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4646 pbn_pericom_PI7C9X7954 },
4647 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4649 pbn_pericom_PI7C9X7958 },
4650 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
4651 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4652 pbn_pericom_PI7C9X7958 },
4653 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4655 pbn_pericom_PI7C9X7958 },
4656 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
4657 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4658 pbn_pericom_PI7C9X7958 },
4659 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4661 pbn_pericom_PI7C9X7958 },
4662 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
4663 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4664 pbn_pericom_PI7C9X7958 },
4665 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
4666 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4667 pbn_pericom_PI7C9X7958 },
4668 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
4669 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4670 pbn_pericom_PI7C9X7958 },
4671 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
4672 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4673 pbn_pericom_PI7C9X7958 },
4674 /*
4675 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4676 */
4677 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4678 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4679 pbn_b0_1_115200 },
4680 /*
4681 * ITE
4682 */
4683 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4684 PCI_ANY_ID, PCI_ANY_ID,
4685 0, 0,
4686 pbn_b1_bt_1_115200 },
4687
4688 /*
4689 * IntaShield IS-200
4690 */
4691 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4693 pbn_b2_2_115200 },
4694 /*
4695 * IntaShield IS-400
4696 */
4697 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4699 pbn_b2_4_115200 },
4700 /*
4701 * BrainBoxes UC-260
4702 */
4703 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
4704 PCI_ANY_ID, PCI_ANY_ID,
4705 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4706 pbn_b2_4_115200 },
4707 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
4708 PCI_ANY_ID, PCI_ANY_ID,
4709 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4710 pbn_b2_4_115200 },
4711 /*
4712 * Perle PCI-RAS cards
4713 */
4714 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4715 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4716 0, 0, pbn_b2_4_921600 },
4717 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4718 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4719 0, 0, pbn_b2_8_921600 },
4720
4721 /*
4722 * Mainpine series cards: Fairly standard layout but fools
4723 * parts of the autodetect in some cases and uses otherwise
4724 * unmatched communications subclasses in the PCI Express case
4725 */
4726
4727 { /* RockForceDUO */
4728 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4729 PCI_VENDOR_ID_MAINPINE, 0x0200,
4730 0, 0, pbn_b0_2_115200 },
4731 { /* RockForceQUATRO */
4732 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4733 PCI_VENDOR_ID_MAINPINE, 0x0300,
4734 0, 0, pbn_b0_4_115200 },
4735 { /* RockForceDUO+ */
4736 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4737 PCI_VENDOR_ID_MAINPINE, 0x0400,
4738 0, 0, pbn_b0_2_115200 },
4739 { /* RockForceQUATRO+ */
4740 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4741 PCI_VENDOR_ID_MAINPINE, 0x0500,
4742 0, 0, pbn_b0_4_115200 },
4743 { /* RockForce+ */
4744 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4745 PCI_VENDOR_ID_MAINPINE, 0x0600,
4746 0, 0, pbn_b0_2_115200 },
4747 { /* RockForce+ */
4748 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4749 PCI_VENDOR_ID_MAINPINE, 0x0700,
4750 0, 0, pbn_b0_4_115200 },
4751 { /* RockForceOCTO+ */
4752 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4753 PCI_VENDOR_ID_MAINPINE, 0x0800,
4754 0, 0, pbn_b0_8_115200 },
4755 { /* RockForceDUO+ */
4756 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4757 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4758 0, 0, pbn_b0_2_115200 },
4759 { /* RockForceQUARTRO+ */
4760 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4761 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4762 0, 0, pbn_b0_4_115200 },
4763 { /* RockForceOCTO+ */
4764 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4765 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4766 0, 0, pbn_b0_8_115200 },
4767 { /* RockForceD1 */
4768 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4769 PCI_VENDOR_ID_MAINPINE, 0x2000,
4770 0, 0, pbn_b0_1_115200 },
4771 { /* RockForceF1 */
4772 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4773 PCI_VENDOR_ID_MAINPINE, 0x2100,
4774 0, 0, pbn_b0_1_115200 },
4775 { /* RockForceD2 */
4776 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4777 PCI_VENDOR_ID_MAINPINE, 0x2200,
4778 0, 0, pbn_b0_2_115200 },
4779 { /* RockForceF2 */
4780 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4781 PCI_VENDOR_ID_MAINPINE, 0x2300,
4782 0, 0, pbn_b0_2_115200 },
4783 { /* RockForceD4 */
4784 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4785 PCI_VENDOR_ID_MAINPINE, 0x2400,
4786 0, 0, pbn_b0_4_115200 },
4787 { /* RockForceF4 */
4788 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4789 PCI_VENDOR_ID_MAINPINE, 0x2500,
4790 0, 0, pbn_b0_4_115200 },
4791 { /* RockForceD8 */
4792 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4793 PCI_VENDOR_ID_MAINPINE, 0x2600,
4794 0, 0, pbn_b0_8_115200 },
4795 { /* RockForceF8 */
4796 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4797 PCI_VENDOR_ID_MAINPINE, 0x2700,
4798 0, 0, pbn_b0_8_115200 },
4799 { /* IQ Express D1 */
4800 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4801 PCI_VENDOR_ID_MAINPINE, 0x3000,
4802 0, 0, pbn_b0_1_115200 },
4803 { /* IQ Express F1 */
4804 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4805 PCI_VENDOR_ID_MAINPINE, 0x3100,
4806 0, 0, pbn_b0_1_115200 },
4807 { /* IQ Express D2 */
4808 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4809 PCI_VENDOR_ID_MAINPINE, 0x3200,
4810 0, 0, pbn_b0_2_115200 },
4811 { /* IQ Express F2 */
4812 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4813 PCI_VENDOR_ID_MAINPINE, 0x3300,
4814 0, 0, pbn_b0_2_115200 },
4815 { /* IQ Express D4 */
4816 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4817 PCI_VENDOR_ID_MAINPINE, 0x3400,
4818 0, 0, pbn_b0_4_115200 },
4819 { /* IQ Express F4 */
4820 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4821 PCI_VENDOR_ID_MAINPINE, 0x3500,
4822 0, 0, pbn_b0_4_115200 },
4823 { /* IQ Express D8 */
4824 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4825 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4826 0, 0, pbn_b0_8_115200 },
4827 { /* IQ Express F8 */
4828 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4829 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4830 0, 0, pbn_b0_8_115200 },
4831
4832
4833 /*
4834 * PA Semi PA6T-1682M on-chip UART
4835 */
4836 { PCI_VENDOR_ID_PASEMI, 0xa004,
4837 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4838 pbn_pasemi_1682M },
4839
4840 /*
4841 * National Instruments
4842 */
4843 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4844 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4845 pbn_b1_16_115200 },
4846 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4847 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4848 pbn_b1_8_115200 },
4849 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4850 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4851 pbn_b1_bt_4_115200 },
4852 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4853 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4854 pbn_b1_bt_2_115200 },
4855 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4856 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4857 pbn_b1_bt_4_115200 },
4858 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4859 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4860 pbn_b1_bt_2_115200 },
4861 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4862 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4863 pbn_b1_16_115200 },
4864 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4865 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4866 pbn_b1_8_115200 },
4867 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4868 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4869 pbn_b1_bt_4_115200 },
4870 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4871 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4872 pbn_b1_bt_2_115200 },
4873 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4874 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4875 pbn_b1_bt_4_115200 },
4876 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4877 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4878 pbn_b1_bt_2_115200 },
4879 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4880 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4881 pbn_ni8430_2 },
4882 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4883 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4884 pbn_ni8430_2 },
4885 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4887 pbn_ni8430_4 },
4888 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4889 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4890 pbn_ni8430_4 },
4891 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4892 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4893 pbn_ni8430_8 },
4894 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4895 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4896 pbn_ni8430_8 },
4897 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4898 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4899 pbn_ni8430_16 },
4900 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4902 pbn_ni8430_16 },
4903 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4905 pbn_ni8430_2 },
4906 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4908 pbn_ni8430_2 },
4909 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4911 pbn_ni8430_4 },
4912 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4914 pbn_ni8430_4 },
4915
4916 /*
4917 * ADDI-DATA GmbH communication cards <info@addi-data.com>
4918 */
4919 { PCI_VENDOR_ID_ADDIDATA,
4920 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4921 PCI_ANY_ID,
4922 PCI_ANY_ID,
4923 0,
4924 0,
4925 pbn_b0_4_115200 },
4926
4927 { PCI_VENDOR_ID_ADDIDATA,
4928 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4929 PCI_ANY_ID,
4930 PCI_ANY_ID,
4931 0,
4932 0,
4933 pbn_b0_2_115200 },
4934
4935 { PCI_VENDOR_ID_ADDIDATA,
4936 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4937 PCI_ANY_ID,
4938 PCI_ANY_ID,
4939 0,
4940 0,
4941 pbn_b0_1_115200 },
4942
4943 { PCI_VENDOR_ID_AMCC,
4944 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
4945 PCI_ANY_ID,
4946 PCI_ANY_ID,
4947 0,
4948 0,
4949 pbn_b1_8_115200 },
4950
4951 { PCI_VENDOR_ID_ADDIDATA,
4952 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4953 PCI_ANY_ID,
4954 PCI_ANY_ID,
4955 0,
4956 0,
4957 pbn_b0_4_115200 },
4958
4959 { PCI_VENDOR_ID_ADDIDATA,
4960 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4961 PCI_ANY_ID,
4962 PCI_ANY_ID,
4963 0,
4964 0,
4965 pbn_b0_2_115200 },
4966
4967 { PCI_VENDOR_ID_ADDIDATA,
4968 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4969 PCI_ANY_ID,
4970 PCI_ANY_ID,
4971 0,
4972 0,
4973 pbn_b0_1_115200 },
4974
4975 { PCI_VENDOR_ID_ADDIDATA,
4976 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4977 PCI_ANY_ID,
4978 PCI_ANY_ID,
4979 0,
4980 0,
4981 pbn_b0_4_115200 },
4982
4983 { PCI_VENDOR_ID_ADDIDATA,
4984 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4985 PCI_ANY_ID,
4986 PCI_ANY_ID,
4987 0,
4988 0,
4989 pbn_b0_2_115200 },
4990
4991 { PCI_VENDOR_ID_ADDIDATA,
4992 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4993 PCI_ANY_ID,
4994 PCI_ANY_ID,
4995 0,
4996 0,
4997 pbn_b0_1_115200 },
4998
4999 { PCI_VENDOR_ID_ADDIDATA,
5000 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5001 PCI_ANY_ID,
5002 PCI_ANY_ID,
5003 0,
5004 0,
5005 pbn_b0_8_115200 },
5006
5007 { PCI_VENDOR_ID_ADDIDATA,
5008 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5009 PCI_ANY_ID,
5010 PCI_ANY_ID,
5011 0,
5012 0,
5013 pbn_ADDIDATA_PCIe_4_3906250 },
5014
5015 { PCI_VENDOR_ID_ADDIDATA,
5016 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5017 PCI_ANY_ID,
5018 PCI_ANY_ID,
5019 0,
5020 0,
5021 pbn_ADDIDATA_PCIe_2_3906250 },
5022
5023 { PCI_VENDOR_ID_ADDIDATA,
5024 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5025 PCI_ANY_ID,
5026 PCI_ANY_ID,
5027 0,
5028 0,
5029 pbn_ADDIDATA_PCIe_1_3906250 },
5030
5031 { PCI_VENDOR_ID_ADDIDATA,
5032 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5033 PCI_ANY_ID,
5034 PCI_ANY_ID,
5035 0,
5036 0,
5037 pbn_ADDIDATA_PCIe_8_3906250 },
5038
5039 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5040 PCI_VENDOR_ID_IBM, 0x0299,
5041 0, 0, pbn_b0_bt_2_115200 },
5042
5043 /*
5044 * other NetMos 9835 devices are most likely handled by the
5045 * parport_serial driver, check drivers/parport/parport_serial.c
5046 * before adding them here.
5047 */
5048
5049 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5050 0xA000, 0x1000,
5051 0, 0, pbn_b0_1_115200 },
5052
5053 /* the 9901 is a rebranded 9912 */
5054 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5055 0xA000, 0x1000,
5056 0, 0, pbn_b0_1_115200 },
5057
5058 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5059 0xA000, 0x1000,
5060 0, 0, pbn_b0_1_115200 },
5061
5062 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5063 0xA000, 0x1000,
5064 0, 0, pbn_b0_1_115200 },
5065
5066 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5067 0xA000, 0x1000,
5068 0, 0, pbn_b0_1_115200 },
5069
5070 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5071 0xA000, 0x3002,
5072 0, 0, pbn_NETMOS9900_2s_115200 },
5073
5074 /*
5075 * Best Connectivity and Rosewill PCI Multi I/O cards
5076 */
5077
5078 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5079 0xA000, 0x1000,
5080 0, 0, pbn_b0_1_115200 },
5081
5082 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5083 0xA000, 0x3002,
5084 0, 0, pbn_b0_bt_2_115200 },
5085
5086 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5087 0xA000, 0x3004,
5088 0, 0, pbn_b0_bt_4_115200 },
5089 /* Intel CE4100 */
5090 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5092 pbn_ce4100_1_115200 },
5093
5094 /*
5095 * Cronyx Omega PCI
5096 */
5097 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5098 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5099 pbn_omegapci },
5100
5101 /*
5102 * Broadcom TruManage
5103 */
5104 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5106 pbn_brcm_trumanage },
5107
5108 /*
5109 * AgeStar as-prs2-009
5110 */
5111 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5112 PCI_ANY_ID, PCI_ANY_ID,
5113 0, 0, pbn_b0_bt_2_115200 },
5114
5115 /*
5116 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5117 * so not listed here.
5118 */
5119 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5120 PCI_ANY_ID, PCI_ANY_ID,
5121 0, 0, pbn_b0_bt_4_115200 },
5122
5123 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5124 PCI_ANY_ID, PCI_ANY_ID,
5125 0, 0, pbn_b0_bt_2_115200 },
5126
5127 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5128 PCI_ANY_ID, PCI_ANY_ID,
5129 0, 0, pbn_b0_bt_4_115200 },
5130
5131 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5132 PCI_ANY_ID, PCI_ANY_ID,
5133 0, 0, pbn_wch382_2 },
5134
5135 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5136 PCI_ANY_ID, PCI_ANY_ID,
5137 0, 0, pbn_wch384_4 },
5138
5139 /* Fintek PCI serial cards */
5140 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5141 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5142 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5143
5144 /* MKS Tenta SCOM-080x serial cards */
5145 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5146 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5147
5148 /* Amazon PCI serial device */
5149 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5150
5151 /*
5152 * These entries match devices with class COMMUNICATION_SERIAL,
5153 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5154 */
5155 { PCI_ANY_ID, PCI_ANY_ID,
5156 PCI_ANY_ID, PCI_ANY_ID,
5157 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5158 0xffff00, pbn_default },
5159 { PCI_ANY_ID, PCI_ANY_ID,
5160 PCI_ANY_ID, PCI_ANY_ID,
5161 PCI_CLASS_COMMUNICATION_MODEM << 8,
5162 0xffff00, pbn_default },
5163 { PCI_ANY_ID, PCI_ANY_ID,
5164 PCI_ANY_ID, PCI_ANY_ID,
5165 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5166 0xffff00, pbn_default },
5167 { 0, }
5168 };
5169
serial8250_io_error_detected(struct pci_dev * dev,pci_channel_state_t state)5170 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5171 pci_channel_state_t state)
5172 {
5173 struct serial_private *priv = pci_get_drvdata(dev);
5174
5175 if (state == pci_channel_io_perm_failure)
5176 return PCI_ERS_RESULT_DISCONNECT;
5177
5178 if (priv)
5179 pciserial_detach_ports(priv);
5180
5181 pci_disable_device(dev);
5182
5183 return PCI_ERS_RESULT_NEED_RESET;
5184 }
5185
serial8250_io_slot_reset(struct pci_dev * dev)5186 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5187 {
5188 int rc;
5189
5190 rc = pci_enable_device(dev);
5191
5192 if (rc)
5193 return PCI_ERS_RESULT_DISCONNECT;
5194
5195 pci_restore_state(dev);
5196 pci_save_state(dev);
5197
5198 return PCI_ERS_RESULT_RECOVERED;
5199 }
5200
serial8250_io_resume(struct pci_dev * dev)5201 static void serial8250_io_resume(struct pci_dev *dev)
5202 {
5203 struct serial_private *priv = pci_get_drvdata(dev);
5204 struct serial_private *new;
5205
5206 if (!priv)
5207 return;
5208
5209 new = pciserial_init_ports(dev, priv->board);
5210 if (!IS_ERR(new)) {
5211 pci_set_drvdata(dev, new);
5212 kfree(priv);
5213 }
5214 }
5215
5216 static const struct pci_error_handlers serial8250_err_handler = {
5217 .error_detected = serial8250_io_error_detected,
5218 .slot_reset = serial8250_io_slot_reset,
5219 .resume = serial8250_io_resume,
5220 };
5221
5222 static struct pci_driver serial_pci_driver = {
5223 .name = "serial",
5224 .probe = pciserial_init_one,
5225 .remove = pciserial_remove_one,
5226 .driver = {
5227 .pm = &pciserial_pm_ops,
5228 },
5229 .id_table = serial_pci_tbl,
5230 .err_handler = &serial8250_err_handler,
5231 };
5232
5233 module_pci_driver(serial_pci_driver);
5234
5235 MODULE_LICENSE("GPL");
5236 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5237 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
5238
