1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type PCI serial ports.
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 */
9 #undef DEBUG
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/math.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/tty.h>
18 #include <linux/serial_reg.h>
19 #include <linux/serial_core.h>
20 #include <linux/8250_pci.h>
21 #include <linux/bitops.h>
22
23 #include <asm/byteorder.h>
24 #include <asm/io.h>
25
26 #include "8250.h"
27 #include "8250_pcilib.h"
28
29 /*
30 * init function returns:
31 * > 0 - number of ports
32 * = 0 - use board->num_ports
33 * < 0 - error
34 */
35 struct pci_serial_quirk {
36 u32 vendor;
37 u32 device;
38 u32 subvendor;
39 u32 subdevice;
40 int (*probe)(struct pci_dev *dev);
41 int (*init)(struct pci_dev *dev);
42 int (*setup)(struct serial_private *,
43 const struct pciserial_board *,
44 struct uart_8250_port *, int);
45 void (*exit)(struct pci_dev *dev);
46 };
47
48 struct f815xxa_data {
49 spinlock_t lock;
50 int idx;
51 };
52
53 struct serial_private {
54 struct pci_dev *dev;
55 unsigned int nr;
56 struct pci_serial_quirk *quirk;
57 const struct pciserial_board *board;
58 int line[];
59 };
60
61 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
62
63 static const struct pci_device_id pci_use_msi[] = {
64 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
65 0xA000, 0x1000) },
66 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
67 0xA000, 0x1000) },
68 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
69 0xA000, 0x1000) },
70 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
71 0xA000, 0x1000) },
72 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
73 PCI_ANY_ID, PCI_ANY_ID) },
74 { }
75 };
76
77 static int pci_default_setup(struct serial_private*,
78 const struct pciserial_board*, struct uart_8250_port *, int);
79
moan_device(const char * str,struct pci_dev * dev)80 static void moan_device(const char *str, struct pci_dev *dev)
81 {
82 pci_err(dev, "%s\n"
83 "Please send the output of lspci -vv, this\n"
84 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
85 "manufacturer and name of serial board or\n"
86 "modem board to <linux-serial@vger.kernel.org>.\n",
87 str, dev->vendor, dev->device,
88 dev->subsystem_vendor, dev->subsystem_device);
89 }
90
91 static int
setup_port(struct serial_private * priv,struct uart_8250_port * port,u8 bar,unsigned int offset,int regshift)92 setup_port(struct serial_private *priv, struct uart_8250_port *port,
93 u8 bar, unsigned int offset, int regshift)
94 {
95 return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift);
96 }
97
98 /*
99 * ADDI-DATA GmbH communication cards <info@addi-data.com>
100 */
addidata_apci7800_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)101 static int addidata_apci7800_setup(struct serial_private *priv,
102 const struct pciserial_board *board,
103 struct uart_8250_port *port, int idx)
104 {
105 unsigned int bar = 0, offset = board->first_offset;
106 bar = FL_GET_BASE(board->flags);
107
108 if (idx < 2) {
109 offset += idx * board->uart_offset;
110 } else if ((idx >= 2) && (idx < 4)) {
111 bar += 1;
112 offset += ((idx - 2) * board->uart_offset);
113 } else if ((idx >= 4) && (idx < 6)) {
114 bar += 2;
115 offset += ((idx - 4) * board->uart_offset);
116 } else if (idx >= 6) {
117 bar += 3;
118 offset += ((idx - 6) * board->uart_offset);
119 }
120
121 return setup_port(priv, port, bar, offset, board->reg_shift);
122 }
123
124 /*
125 * AFAVLAB uses a different mixture of BARs and offsets
126 * Not that ugly ;) -- HW
127 */
128 static int
afavlab_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)129 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
130 struct uart_8250_port *port, int idx)
131 {
132 unsigned int bar, offset = board->first_offset;
133
134 bar = FL_GET_BASE(board->flags);
135 if (idx < 4)
136 bar += idx;
137 else {
138 bar = 4;
139 offset += (idx - 4) * board->uart_offset;
140 }
141
142 return setup_port(priv, port, bar, offset, board->reg_shift);
143 }
144
145 /*
146 * HP's Remote Management Console. The Diva chip came in several
147 * different versions. N-class, L2000 and A500 have two Diva chips, each
148 * with 3 UARTs (the third UART on the second chip is unused). Superdome
149 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
150 * one Diva chip, but it has been expanded to 5 UARTs.
151 */
pci_hp_diva_init(struct pci_dev * dev)152 static int pci_hp_diva_init(struct pci_dev *dev)
153 {
154 int rc = 0;
155
156 switch (dev->subsystem_device) {
157 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
158 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
159 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
160 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
161 rc = 3;
162 break;
163 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
164 rc = 2;
165 break;
166 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
167 rc = 4;
168 break;
169 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
170 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
171 rc = 1;
172 break;
173 }
174
175 return rc;
176 }
177
178 /*
179 * HP's Diva chip puts the 4th/5th serial port further out, and
180 * some serial ports are supposed to be hidden on certain models.
181 */
182 static int
pci_hp_diva_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)183 pci_hp_diva_setup(struct serial_private *priv,
184 const struct pciserial_board *board,
185 struct uart_8250_port *port, int idx)
186 {
187 unsigned int offset = board->first_offset;
188 unsigned int bar = FL_GET_BASE(board->flags);
189
190 switch (priv->dev->subsystem_device) {
191 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
192 if (idx == 3)
193 idx++;
194 break;
195 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
196 if (idx > 0)
197 idx++;
198 if (idx > 2)
199 idx++;
200 break;
201 }
202 if (idx > 2)
203 offset = 0x18;
204
205 offset += idx * board->uart_offset;
206
207 return setup_port(priv, port, bar, offset, board->reg_shift);
208 }
209
210 /*
211 * Added for EKF Intel i960 serial boards
212 */
pci_inteli960ni_init(struct pci_dev * dev)213 static int pci_inteli960ni_init(struct pci_dev *dev)
214 {
215 u32 oldval;
216
217 if (!(dev->subsystem_device & 0x1000))
218 return -ENODEV;
219
220 /* is firmware started? */
221 pci_read_config_dword(dev, 0x44, &oldval);
222 if (oldval == 0x00001000L) { /* RESET value */
223 pci_dbg(dev, "Local i960 firmware missing\n");
224 return -ENODEV;
225 }
226 return 0;
227 }
228
229 /*
230 * Some PCI serial cards using the PLX 9050 PCI interface chip require
231 * that the card interrupt be explicitly enabled or disabled. This
232 * seems to be mainly needed on card using the PLX which also use I/O
233 * mapped memory.
234 */
pci_plx9050_init(struct pci_dev * dev)235 static int pci_plx9050_init(struct pci_dev *dev)
236 {
237 u8 irq_config;
238 void __iomem *p;
239
240 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
241 moan_device("no memory in bar 0", dev);
242 return 0;
243 }
244
245 irq_config = 0x41;
246 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
247 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
248 irq_config = 0x43;
249
250 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
251 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
252 /*
253 * As the megawolf cards have the int pins active
254 * high, and have 2 UART chips, both ints must be
255 * enabled on the 9050. Also, the UARTS are set in
256 * 16450 mode by default, so we have to enable the
257 * 16C950 'enhanced' mode so that we can use the
258 * deep FIFOs
259 */
260 irq_config = 0x5b;
261 /*
262 * enable/disable interrupts
263 */
264 p = ioremap(pci_resource_start(dev, 0), 0x80);
265 if (p == NULL)
266 return -ENOMEM;
267 writel(irq_config, p + 0x4c);
268
269 /*
270 * Read the register back to ensure that it took effect.
271 */
272 readl(p + 0x4c);
273 iounmap(p);
274
275 return 0;
276 }
277
pci_plx9050_exit(struct pci_dev * dev)278 static void pci_plx9050_exit(struct pci_dev *dev)
279 {
280 u8 __iomem *p;
281
282 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
283 return;
284
285 /*
286 * disable interrupts
287 */
288 p = ioremap(pci_resource_start(dev, 0), 0x80);
289 if (p != NULL) {
290 writel(0, p + 0x4c);
291
292 /*
293 * Read the register back to ensure that it took effect.
294 */
295 readl(p + 0x4c);
296 iounmap(p);
297 }
298 }
299
300 #define NI8420_INT_ENABLE_REG 0x38
301 #define NI8420_INT_ENABLE_BIT 0x2000
302
pci_ni8420_exit(struct pci_dev * dev)303 static void pci_ni8420_exit(struct pci_dev *dev)
304 {
305 void __iomem *p;
306 unsigned int bar = 0;
307
308 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
309 moan_device("no memory in bar", dev);
310 return;
311 }
312
313 p = pci_ioremap_bar(dev, bar);
314 if (p == NULL)
315 return;
316
317 /* Disable the CPU Interrupt */
318 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
319 p + NI8420_INT_ENABLE_REG);
320 iounmap(p);
321 }
322
323
324 /* MITE registers */
325 #define MITE_IOWBSR1 0xc4
326 #define MITE_IOWCR1 0xf4
327 #define MITE_LCIMR1 0x08
328 #define MITE_LCIMR2 0x10
329
330 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
331
pci_ni8430_exit(struct pci_dev * dev)332 static void pci_ni8430_exit(struct pci_dev *dev)
333 {
334 void __iomem *p;
335 unsigned int bar = 0;
336
337 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
338 moan_device("no memory in bar", dev);
339 return;
340 }
341
342 p = pci_ioremap_bar(dev, bar);
343 if (p == NULL)
344 return;
345
346 /* Disable the CPU Interrupt */
347 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
348 iounmap(p);
349 }
350
351 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
352 static int
sbs_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)353 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
354 struct uart_8250_port *port, int idx)
355 {
356 unsigned int bar, offset = board->first_offset;
357
358 bar = 0;
359
360 if (idx < 4) {
361 /* first four channels map to 0, 0x100, 0x200, 0x300 */
362 offset += idx * board->uart_offset;
363 } else if (idx < 8) {
364 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
365 offset += idx * board->uart_offset + 0xC00;
366 } else /* we have only 8 ports on PMC-OCTALPRO */
367 return 1;
368
369 return setup_port(priv, port, bar, offset, board->reg_shift);
370 }
371
372 /*
373 * This does initialization for PMC OCTALPRO cards:
374 * maps the device memory, resets the UARTs (needed, bc
375 * if the module is removed and inserted again, the card
376 * is in the sleep mode) and enables global interrupt.
377 */
378
379 /* global control register offset for SBS PMC-OctalPro */
380 #define OCT_REG_CR_OFF 0x500
381
sbs_init(struct pci_dev * dev)382 static int sbs_init(struct pci_dev *dev)
383 {
384 u8 __iomem *p;
385
386 p = pci_ioremap_bar(dev, 0);
387
388 if (p == NULL)
389 return -ENOMEM;
390 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
391 writeb(0x10, p + OCT_REG_CR_OFF);
392 udelay(50);
393 writeb(0x0, p + OCT_REG_CR_OFF);
394
395 /* Set bit-2 (INTENABLE) of Control Register */
396 writeb(0x4, p + OCT_REG_CR_OFF);
397 iounmap(p);
398
399 return 0;
400 }
401
402 /*
403 * Disables the global interrupt of PMC-OctalPro
404 */
405
sbs_exit(struct pci_dev * dev)406 static void sbs_exit(struct pci_dev *dev)
407 {
408 u8 __iomem *p;
409
410 p = pci_ioremap_bar(dev, 0);
411 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
412 if (p != NULL)
413 writeb(0, p + OCT_REG_CR_OFF);
414 iounmap(p);
415 }
416
417 /*
418 * SIIG serial cards have an PCI interface chip which also controls
419 * the UART clocking frequency. Each UART can be clocked independently
420 * (except cards equipped with 4 UARTs) and initial clocking settings
421 * are stored in the EEPROM chip. It can cause problems because this
422 * version of serial driver doesn't support differently clocked UART's
423 * on single PCI card. To prevent this, initialization functions set
424 * high frequency clocking for all UART's on given card. It is safe (I
425 * hope) because it doesn't touch EEPROM settings to prevent conflicts
426 * with other OSes (like M$ DOS).
427 *
428 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
429 *
430 * There is two family of SIIG serial cards with different PCI
431 * interface chip and different configuration methods:
432 * - 10x cards have control registers in IO and/or memory space;
433 * - 20x cards have control registers in standard PCI configuration space.
434 *
435 * Note: all 10x cards have PCI device ids 0x10..
436 * all 20x cards have PCI device ids 0x20..
437 *
438 * There are also Quartet Serial cards which use Oxford Semiconductor
439 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
440 *
441 * Note: some SIIG cards are probed by the parport_serial object.
442 */
443
444 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
445 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
446
pci_siig10x_init(struct pci_dev * dev)447 static int pci_siig10x_init(struct pci_dev *dev)
448 {
449 u16 data;
450 void __iomem *p;
451
452 switch (dev->device & 0xfff8) {
453 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
454 data = 0xffdf;
455 break;
456 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
457 data = 0xf7ff;
458 break;
459 default: /* 1S1P, 4S */
460 data = 0xfffb;
461 break;
462 }
463
464 p = ioremap(pci_resource_start(dev, 0), 0x80);
465 if (p == NULL)
466 return -ENOMEM;
467
468 writew(readw(p + 0x28) & data, p + 0x28);
469 readw(p + 0x28);
470 iounmap(p);
471 return 0;
472 }
473
474 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
475 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
476
pci_siig20x_init(struct pci_dev * dev)477 static int pci_siig20x_init(struct pci_dev *dev)
478 {
479 u8 data;
480
481 /* Change clock frequency for the first UART. */
482 pci_read_config_byte(dev, 0x6f, &data);
483 pci_write_config_byte(dev, 0x6f, data & 0xef);
484
485 /* If this card has 2 UART, we have to do the same with second UART. */
486 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
487 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
488 pci_read_config_byte(dev, 0x73, &data);
489 pci_write_config_byte(dev, 0x73, data & 0xef);
490 }
491 return 0;
492 }
493
pci_siig_init(struct pci_dev * dev)494 static int pci_siig_init(struct pci_dev *dev)
495 {
496 unsigned int type = dev->device & 0xff00;
497
498 if (type == 0x1000)
499 return pci_siig10x_init(dev);
500 if (type == 0x2000)
501 return pci_siig20x_init(dev);
502
503 moan_device("Unknown SIIG card", dev);
504 return -ENODEV;
505 }
506
pci_siig_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)507 static int pci_siig_setup(struct serial_private *priv,
508 const struct pciserial_board *board,
509 struct uart_8250_port *port, int idx)
510 {
511 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
512
513 if (idx > 3) {
514 bar = 4;
515 offset = (idx - 4) * 8;
516 }
517
518 return setup_port(priv, port, bar, offset, 0);
519 }
520
521 /*
522 * Timedia has an explosion of boards, and to avoid the PCI table from
523 * growing *huge*, we use this function to collapse some 70 entries
524 * in the PCI table into one, for sanity's and compactness's sake.
525 */
526 static const unsigned short timedia_single_port[] = {
527 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
528 };
529
530 static const unsigned short timedia_dual_port[] = {
531 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
532 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
533 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
534 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
535 0xD079, 0
536 };
537
538 static const unsigned short timedia_quad_port[] = {
539 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
540 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
541 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
542 0xB157, 0
543 };
544
545 static const unsigned short timedia_eight_port[] = {
546 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
547 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
548 };
549
550 static const struct timedia_struct {
551 int num;
552 const unsigned short *ids;
553 } timedia_data[] = {
554 { 1, timedia_single_port },
555 { 2, timedia_dual_port },
556 { 4, timedia_quad_port },
557 { 8, timedia_eight_port }
558 };
559
560 /*
561 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
562 * listing them individually, this driver merely grabs them all with
563 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
564 * and should be left free to be claimed by parport_serial instead.
565 */
pci_timedia_probe(struct pci_dev * dev)566 static int pci_timedia_probe(struct pci_dev *dev)
567 {
568 /*
569 * Check the third digit of the subdevice ID
570 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
571 */
572 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
573 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n",
574 dev->subsystem_device);
575 return -ENODEV;
576 }
577
578 return 0;
579 }
580
pci_timedia_init(struct pci_dev * dev)581 static int pci_timedia_init(struct pci_dev *dev)
582 {
583 const unsigned short *ids;
584 int i, j;
585
586 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
587 ids = timedia_data[i].ids;
588 for (j = 0; ids[j]; j++)
589 if (dev->subsystem_device == ids[j])
590 return timedia_data[i].num;
591 }
592 return 0;
593 }
594
595 /*
596 * Timedia/SUNIX uses a mixture of BARs and offsets
597 * Ugh, this is ugly as all hell --- TYT
598 */
599 static int
pci_timedia_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)600 pci_timedia_setup(struct serial_private *priv,
601 const struct pciserial_board *board,
602 struct uart_8250_port *port, int idx)
603 {
604 unsigned int bar = 0, offset = board->first_offset;
605
606 switch (idx) {
607 case 0:
608 bar = 0;
609 break;
610 case 1:
611 offset = board->uart_offset;
612 bar = 0;
613 break;
614 case 2:
615 bar = 1;
616 break;
617 case 3:
618 offset = board->uart_offset;
619 fallthrough;
620 case 4: /* BAR 2 */
621 case 5: /* BAR 3 */
622 case 6: /* BAR 4 */
623 case 7: /* BAR 5 */
624 bar = idx - 2;
625 }
626
627 return setup_port(priv, port, bar, offset, board->reg_shift);
628 }
629
630 /*
631 * Some Titan cards are also a little weird
632 */
633 static int
titan_400l_800l_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)634 titan_400l_800l_setup(struct serial_private *priv,
635 const struct pciserial_board *board,
636 struct uart_8250_port *port, int idx)
637 {
638 unsigned int bar, offset = board->first_offset;
639
640 switch (idx) {
641 case 0:
642 bar = 1;
643 break;
644 case 1:
645 bar = 2;
646 break;
647 default:
648 bar = 4;
649 offset = (idx - 2) * board->uart_offset;
650 }
651
652 return setup_port(priv, port, bar, offset, board->reg_shift);
653 }
654
pci_xircom_init(struct pci_dev * dev)655 static int pci_xircom_init(struct pci_dev *dev)
656 {
657 msleep(100);
658 return 0;
659 }
660
pci_ni8420_init(struct pci_dev * dev)661 static int pci_ni8420_init(struct pci_dev *dev)
662 {
663 void __iomem *p;
664 unsigned int bar = 0;
665
666 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
667 moan_device("no memory in bar", dev);
668 return 0;
669 }
670
671 p = pci_ioremap_bar(dev, bar);
672 if (p == NULL)
673 return -ENOMEM;
674
675 /* Enable CPU Interrupt */
676 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
677 p + NI8420_INT_ENABLE_REG);
678
679 iounmap(p);
680 return 0;
681 }
682
683 #define MITE_IOWBSR1_WSIZE 0xa
684 #define MITE_IOWBSR1_WIN_OFFSET 0x800
685 #define MITE_IOWBSR1_WENAB (1 << 7)
686 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
687 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
688 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
689
pci_ni8430_init(struct pci_dev * dev)690 static int pci_ni8430_init(struct pci_dev *dev)
691 {
692 void __iomem *p;
693 struct pci_bus_region region;
694 u32 device_window;
695 unsigned int bar = 0;
696
697 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
698 moan_device("no memory in bar", dev);
699 return 0;
700 }
701
702 p = pci_ioremap_bar(dev, bar);
703 if (p == NULL)
704 return -ENOMEM;
705
706 /*
707 * Set device window address and size in BAR0, while acknowledging that
708 * the resource structure may contain a translated address that differs
709 * from the address the device responds to.
710 */
711 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
712 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
713 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
714 writel(device_window, p + MITE_IOWBSR1);
715
716 /* Set window access to go to RAMSEL IO address space */
717 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
718 p + MITE_IOWCR1);
719
720 /* Enable IO Bus Interrupt 0 */
721 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
722
723 /* Enable CPU Interrupt */
724 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
725
726 iounmap(p);
727 return 0;
728 }
729
730 /* UART Port Control Register */
731 #define NI8430_PORTCON 0x0f
732 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
733
734 static int
pci_ni8430_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)735 pci_ni8430_setup(struct serial_private *priv,
736 const struct pciserial_board *board,
737 struct uart_8250_port *port, int idx)
738 {
739 struct pci_dev *dev = priv->dev;
740 void __iomem *p;
741 unsigned int bar, offset = board->first_offset;
742
743 if (idx >= board->num_ports)
744 return 1;
745
746 bar = FL_GET_BASE(board->flags);
747 offset += idx * board->uart_offset;
748
749 p = pci_ioremap_bar(dev, bar);
750 if (!p)
751 return -ENOMEM;
752
753 /* enable the transceiver */
754 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
755 p + offset + NI8430_PORTCON);
756
757 iounmap(p);
758
759 return setup_port(priv, port, bar, offset, board->reg_shift);
760 }
761
pci_netmos_9900_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)762 static int pci_netmos_9900_setup(struct serial_private *priv,
763 const struct pciserial_board *board,
764 struct uart_8250_port *port, int idx)
765 {
766 unsigned int bar;
767
768 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
769 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
770 /* netmos apparently orders BARs by datasheet layout, so serial
771 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
772 */
773 bar = 3 * idx;
774
775 return setup_port(priv, port, bar, 0, board->reg_shift);
776 }
777
778 return pci_default_setup(priv, board, port, idx);
779 }
780
781 /* the 99xx series comes with a range of device IDs and a variety
782 * of capabilities:
783 *
784 * 9900 has varying capabilities and can cascade to sub-controllers
785 * (cascading should be purely internal)
786 * 9904 is hardwired with 4 serial ports
787 * 9912 and 9922 are hardwired with 2 serial ports
788 */
pci_netmos_9900_numports(struct pci_dev * dev)789 static int pci_netmos_9900_numports(struct pci_dev *dev)
790 {
791 unsigned int c = dev->class;
792 unsigned int pi;
793 unsigned short sub_serports;
794
795 pi = c & 0xff;
796
797 if (pi == 2)
798 return 1;
799
800 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
801 /* two possibilities: 0x30ps encodes number of parallel and
802 * serial ports, or 0x1000 indicates *something*. This is not
803 * immediately obvious, since the 2s1p+4s configuration seems
804 * to offer all functionality on functions 0..2, while still
805 * advertising the same function 3 as the 4s+2s1p config.
806 */
807 sub_serports = dev->subsystem_device & 0xf;
808 if (sub_serports > 0)
809 return sub_serports;
810
811 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
812 return 0;
813 }
814
815 moan_device("unknown NetMos/Mostech program interface", dev);
816 return 0;
817 }
818
pci_netmos_init(struct pci_dev * dev)819 static int pci_netmos_init(struct pci_dev *dev)
820 {
821 /* subdevice 0x00PS means <P> parallel, <S> serial */
822 unsigned int num_serial = dev->subsystem_device & 0xf;
823
824 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
825 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
826 return 0;
827
828 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
829 dev->subsystem_device == 0x0299)
830 return 0;
831
832 switch (dev->device) { /* FALLTHROUGH on all */
833 case PCI_DEVICE_ID_NETMOS_9904:
834 case PCI_DEVICE_ID_NETMOS_9912:
835 case PCI_DEVICE_ID_NETMOS_9922:
836 case PCI_DEVICE_ID_NETMOS_9900:
837 num_serial = pci_netmos_9900_numports(dev);
838 break;
839
840 default:
841 break;
842 }
843
844 if (num_serial == 0) {
845 moan_device("unknown NetMos/Mostech device", dev);
846 return -ENODEV;
847 }
848
849 return num_serial;
850 }
851
852 /*
853 * These chips are available with optionally one parallel port and up to
854 * two serial ports. Unfortunately they all have the same product id.
855 *
856 * Basic configuration is done over a region of 32 I/O ports. The base
857 * ioport is called INTA or INTC, depending on docs/other drivers.
858 *
859 * The region of the 32 I/O ports is configured in POSIO0R...
860 */
861
862 /* registers */
863 #define ITE_887x_MISCR 0x9c
864 #define ITE_887x_INTCBAR 0x78
865 #define ITE_887x_UARTBAR 0x7c
866 #define ITE_887x_PS0BAR 0x10
867 #define ITE_887x_POSIO0 0x60
868
869 /* I/O space size */
870 #define ITE_887x_IOSIZE 32
871 /* I/O space size (bits 26-24; 8 bytes = 011b) */
872 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
873 /* I/O space size (bits 26-24; 32 bytes = 101b) */
874 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
875 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
876 #define ITE_887x_POSIO_SPEED (3 << 29)
877 /* enable IO_Space bit */
878 #define ITE_887x_POSIO_ENABLE (1 << 31)
879
880 /* inta_addr are the configuration addresses of the ITE */
881 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 };
pci_ite887x_init(struct pci_dev * dev)882 static int pci_ite887x_init(struct pci_dev *dev)
883 {
884 int ret, i, type;
885 struct resource *iobase = NULL;
886 u32 miscr, uartbar, ioport;
887
888 /* search for the base-ioport */
889 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) {
890 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
891 "ite887x");
892 if (iobase != NULL) {
893 /* write POSIO0R - speed | size | ioport */
894 pci_write_config_dword(dev, ITE_887x_POSIO0,
895 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
896 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
897 /* write INTCBAR - ioport */
898 pci_write_config_dword(dev, ITE_887x_INTCBAR,
899 inta_addr[i]);
900 ret = inb(inta_addr[i]);
901 if (ret != 0xff) {
902 /* ioport connected */
903 break;
904 }
905 release_region(iobase->start, ITE_887x_IOSIZE);
906 }
907 }
908
909 if (i == ARRAY_SIZE(inta_addr)) {
910 pci_err(dev, "could not find iobase\n");
911 return -ENODEV;
912 }
913
914 /* start of undocumented type checking (see parport_pc.c) */
915 type = inb(iobase->start + 0x18) & 0x0f;
916
917 switch (type) {
918 case 0x2: /* ITE8871 (1P) */
919 case 0xa: /* ITE8875 (1P) */
920 ret = 0;
921 break;
922 case 0xe: /* ITE8872 (2S1P) */
923 ret = 2;
924 break;
925 case 0x6: /* ITE8873 (1S) */
926 ret = 1;
927 break;
928 case 0x8: /* ITE8874 (2S) */
929 ret = 2;
930 break;
931 default:
932 moan_device("Unknown ITE887x", dev);
933 ret = -ENODEV;
934 }
935
936 /* configure all serial ports */
937 for (i = 0; i < ret; i++) {
938 /* read the I/O port from the device */
939 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
940 &ioport);
941 ioport &= 0x0000FF00; /* the actual base address */
942 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
943 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
944 ITE_887x_POSIO_IOSIZE_8 | ioport);
945
946 /* write the ioport to the UARTBAR */
947 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
948 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
949 uartbar |= (ioport << (16 * i)); /* set the ioport */
950 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
951
952 /* get current config */
953 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
954 /* disable interrupts (UARTx_Routing[3:0]) */
955 miscr &= ~(0xf << (12 - 4 * i));
956 /* activate the UART (UARTx_En) */
957 miscr |= 1 << (23 - i);
958 /* write new config with activated UART */
959 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
960 }
961
962 if (ret <= 0) {
963 /* the device has no UARTs if we get here */
964 release_region(iobase->start, ITE_887x_IOSIZE);
965 }
966
967 return ret;
968 }
969
pci_ite887x_exit(struct pci_dev * dev)970 static void pci_ite887x_exit(struct pci_dev *dev)
971 {
972 u32 ioport;
973 /* the ioport is bit 0-15 in POSIO0R */
974 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
975 ioport &= 0xffff;
976 release_region(ioport, ITE_887x_IOSIZE);
977 }
978
979 /*
980 * Oxford Semiconductor Inc.
981 * Check if an OxSemi device is part of the Tornado range of devices.
982 */
983 #define PCI_VENDOR_ID_ENDRUN 0x7401
984 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
985
pci_oxsemi_tornado_p(struct pci_dev * dev)986 static bool pci_oxsemi_tornado_p(struct pci_dev *dev)
987 {
988 /* OxSemi Tornado devices are all 0xCxxx */
989 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
990 (dev->device & 0xf000) != 0xc000)
991 return false;
992
993 /* EndRun devices are all 0xExxx */
994 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
995 (dev->device & 0xf000) != 0xe000)
996 return false;
997
998 return true;
999 }
1000
1001 /*
1002 * Determine the number of ports available on a Tornado device.
1003 */
pci_oxsemi_tornado_init(struct pci_dev * dev)1004 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1005 {
1006 u8 __iomem *p;
1007 unsigned long deviceID;
1008 unsigned int number_uarts = 0;
1009
1010 if (!pci_oxsemi_tornado_p(dev))
1011 return 0;
1012
1013 p = pci_iomap(dev, 0, 5);
1014 if (p == NULL)
1015 return -ENOMEM;
1016
1017 deviceID = ioread32(p);
1018 /* Tornado device */
1019 if (deviceID == 0x07000200) {
1020 number_uarts = ioread8(p + 4);
1021 pci_dbg(dev, "%d ports detected on %s PCI Express device\n",
1022 number_uarts,
1023 dev->vendor == PCI_VENDOR_ID_ENDRUN ?
1024 "EndRun" : "Oxford");
1025 }
1026 pci_iounmap(dev, p);
1027 return number_uarts;
1028 }
1029
1030 /* Tornado-specific constants for the TCR and CPR registers; see below. */
1031 #define OXSEMI_TORNADO_TCR_MASK 0xf
1032 #define OXSEMI_TORNADO_CPR_MASK 0x1ff
1033 #define OXSEMI_TORNADO_CPR_MIN 0x008
1034 #define OXSEMI_TORNADO_CPR_DEF 0x10f
1035
1036 /*
1037 * Determine the oversampling rate, the clock prescaler, and the clock
1038 * divisor for the requested baud rate. The clock rate is 62.5 MHz,
1039 * which is four times the baud base, and the prescaler increments in
1040 * steps of 1/8. Therefore to make calculations on integers we need
1041 * to use a scaled clock rate, which is the baud base multiplied by 32
1042 * (or our assumed UART clock rate multiplied by 2).
1043 *
1044 * The allowed oversampling rates are from 4 up to 16 inclusive (values
1045 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows
1046 * values between 1.000 and 63.875 inclusive (operation for values from
1047 * 0.000 to 0.875 has not been specified). The clock divisor is the usual
1048 * unsigned 16-bit integer.
1049 *
1050 * For the most accurate baud rate we use a table of predetermined
1051 * oversampling rates and clock prescalers that records all possible
1052 * products of the two parameters in the range from 4 up to 255 inclusive,
1053 * and additionally 335 for the 1500000bps rate, with the prescaler scaled
1054 * by 8. The table is sorted by the decreasing value of the oversampling
1055 * rate and ties are resolved by sorting by the decreasing value of the
1056 * product. This way preference is given to higher oversampling rates.
1057 *
1058 * We iterate over the table and choose the product of an oversampling
1059 * rate and a clock prescaler that gives the lowest integer division
1060 * result deviation, or if an exact integer divider is found we stop
1061 * looking for it right away. We do some fixup if the resulting clock
1062 * divisor required would be out of its unsigned 16-bit integer range.
1063 *
1064 * Finally we abuse the supposed fractional part returned to encode the
1065 * 4-bit value of the oversampling rate and the 9-bit value of the clock
1066 * prescaler which will end up in the TCR and CPR/CPR2 registers.
1067 */
pci_oxsemi_tornado_get_divisor(struct uart_port * port,unsigned int baud,unsigned int * frac)1068 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port,
1069 unsigned int baud,
1070 unsigned int *frac)
1071 {
1072 static u8 p[][2] = {
1073 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, },
1074 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, },
1075 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, },
1076 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, },
1077 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, },
1078 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, },
1079 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, },
1080 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, },
1081 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, },
1082 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, },
1083 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, },
1084 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, },
1085 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, },
1086 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, },
1087 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, },
1088 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, },
1089 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, },
1090 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, },
1091 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, },
1092 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, },
1093 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, },
1094 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, },
1095 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, },
1096 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, },
1097 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, },
1098 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, },
1099 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, },
1100 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, },
1101 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, },
1102 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, },
1103 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, },
1104 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, },
1105 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, },
1106 { 4, 9, }, { 4, 8, },
1107 };
1108 /* Scale the quotient for comparison to get the fractional part. */
1109 const unsigned int quot_scale = 65536;
1110 unsigned int sclk = port->uartclk * 2;
1111 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud);
1112 unsigned int best_squot;
1113 unsigned int squot;
1114 unsigned int quot;
1115 u16 cpr;
1116 u8 tcr;
1117 int i;
1118
1119 /* Old custom speed handling. */
1120 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
1121 unsigned int cust_div = port->custom_divisor;
1122
1123 quot = cust_div & UART_DIV_MAX;
1124 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK;
1125 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK;
1126 if (cpr < OXSEMI_TORNADO_CPR_MIN)
1127 cpr = OXSEMI_TORNADO_CPR_DEF;
1128 } else {
1129 best_squot = quot_scale;
1130 for (i = 0; i < ARRAY_SIZE(p); i++) {
1131 unsigned int spre;
1132 unsigned int srem;
1133 u8 cp;
1134 u8 tc;
1135
1136 tc = p[i][0];
1137 cp = p[i][1];
1138 spre = tc * cp;
1139
1140 srem = sdiv % spre;
1141 if (srem > spre / 2)
1142 srem = spre - srem;
1143 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre);
1144
1145 if (srem == 0) {
1146 tcr = tc;
1147 cpr = cp;
1148 quot = sdiv / spre;
1149 break;
1150 } else if (squot < best_squot) {
1151 best_squot = squot;
1152 tcr = tc;
1153 cpr = cp;
1154 quot = DIV_ROUND_CLOSEST(sdiv, spre);
1155 }
1156 }
1157 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 &&
1158 quot % 2 == 0) {
1159 quot >>= 1;
1160 tcr <<= 1;
1161 }
1162 while (quot > UART_DIV_MAX) {
1163 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) {
1164 quot >>= 1;
1165 tcr <<= 1;
1166 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) {
1167 quot >>= 1;
1168 cpr <<= 1;
1169 } else {
1170 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK;
1171 cpr = OXSEMI_TORNADO_CPR_MASK;
1172 }
1173 }
1174 }
1175
1176 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK);
1177 return quot;
1178 }
1179
1180 /*
1181 * Set the oversampling rate in the transmitter clock cycle register (TCR),
1182 * the clock prescaler in the clock prescaler register (CPR and CPR2), and
1183 * the clock divisor in the divisor latch (DLL and DLM). Note that for
1184 * backwards compatibility any write to CPR clears CPR2 and therefore CPR
1185 * has to be written first, followed by CPR2, which occupies the location
1186 * of CKS used with earlier UART designs.
1187 */
pci_oxsemi_tornado_set_divisor(struct uart_port * port,unsigned int baud,unsigned int quot,unsigned int quot_frac)1188 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port,
1189 unsigned int baud,
1190 unsigned int quot,
1191 unsigned int quot_frac)
1192 {
1193 struct uart_8250_port *up = up_to_u8250p(port);
1194 u8 cpr2 = quot_frac >> 16;
1195 u8 cpr = quot_frac >> 8;
1196 u8 tcr = quot_frac;
1197
1198 serial_icr_write(up, UART_TCR, tcr);
1199 serial_icr_write(up, UART_CPR, cpr);
1200 serial_icr_write(up, UART_CKS, cpr2);
1201 serial8250_do_set_divisor(port, baud, quot, 0);
1202 }
1203
1204 /*
1205 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate
1206 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used.
1207 */
pci_oxsemi_tornado_set_mctrl(struct uart_port * port,unsigned int mctrl)1208 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port,
1209 unsigned int mctrl)
1210 {
1211 struct uart_8250_port *up = up_to_u8250p(port);
1212
1213 up->mcr |= UART_MCR_CLKSEL;
1214 serial8250_do_set_mctrl(port, mctrl);
1215 }
1216
1217 /*
1218 * We require EFR features for clock programming, so set UPF_FULL_PROBE
1219 * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting.
1220 */
pci_oxsemi_tornado_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * up,int idx)1221 static int pci_oxsemi_tornado_setup(struct serial_private *priv,
1222 const struct pciserial_board *board,
1223 struct uart_8250_port *up, int idx)
1224 {
1225 struct pci_dev *dev = priv->dev;
1226
1227 if (pci_oxsemi_tornado_p(dev)) {
1228 up->port.flags |= UPF_FULL_PROBE;
1229 up->port.get_divisor = pci_oxsemi_tornado_get_divisor;
1230 up->port.set_divisor = pci_oxsemi_tornado_set_divisor;
1231 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl;
1232 }
1233
1234 return pci_default_setup(priv, board, up, idx);
1235 }
1236
1237 #define QPCR_TEST_FOR1 0x3F
1238 #define QPCR_TEST_GET1 0x00
1239 #define QPCR_TEST_FOR2 0x40
1240 #define QPCR_TEST_GET2 0x40
1241 #define QPCR_TEST_FOR3 0x80
1242 #define QPCR_TEST_GET3 0x40
1243 #define QPCR_TEST_FOR4 0xC0
1244 #define QPCR_TEST_GET4 0x80
1245
1246 #define QOPR_CLOCK_X1 0x0000
1247 #define QOPR_CLOCK_X2 0x0001
1248 #define QOPR_CLOCK_X4 0x0002
1249 #define QOPR_CLOCK_X8 0x0003
1250 #define QOPR_CLOCK_RATE_MASK 0x0003
1251
1252 /* Quatech devices have their own extra interface features */
1253 static struct pci_device_id quatech_cards[] = {
1254 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) },
1255 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) },
1256 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) },
1257 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) },
1258 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) },
1259 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) },
1260 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) },
1261 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) },
1262 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) },
1263 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) },
1264 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) },
1265 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) },
1266 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) },
1267 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) },
1268 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) },
1269 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) },
1270 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) },
1271 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) },
1272 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) },
1273 { 0, }
1274 };
1275
pci_quatech_rqopr(struct uart_8250_port * port)1276 static int pci_quatech_rqopr(struct uart_8250_port *port)
1277 {
1278 unsigned long base = port->port.iobase;
1279 u8 LCR, val;
1280
1281 LCR = inb(base + UART_LCR);
1282 outb(0xBF, base + UART_LCR);
1283 val = inb(base + UART_SCR);
1284 outb(LCR, base + UART_LCR);
1285 return val;
1286 }
1287
pci_quatech_wqopr(struct uart_8250_port * port,u8 qopr)1288 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1289 {
1290 unsigned long base = port->port.iobase;
1291 u8 LCR;
1292
1293 LCR = inb(base + UART_LCR);
1294 outb(0xBF, base + UART_LCR);
1295 inb(base + UART_SCR);
1296 outb(qopr, base + UART_SCR);
1297 outb(LCR, base + UART_LCR);
1298 }
1299
pci_quatech_rqmcr(struct uart_8250_port * port)1300 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1301 {
1302 unsigned long base = port->port.iobase;
1303 u8 LCR, val, qmcr;
1304
1305 LCR = inb(base + UART_LCR);
1306 outb(0xBF, base + UART_LCR);
1307 val = inb(base + UART_SCR);
1308 outb(val | 0x10, base + UART_SCR);
1309 qmcr = inb(base + UART_MCR);
1310 outb(val, base + UART_SCR);
1311 outb(LCR, base + UART_LCR);
1312
1313 return qmcr;
1314 }
1315
pci_quatech_wqmcr(struct uart_8250_port * port,u8 qmcr)1316 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1317 {
1318 unsigned long base = port->port.iobase;
1319 u8 LCR, val;
1320
1321 LCR = inb(base + UART_LCR);
1322 outb(0xBF, base + UART_LCR);
1323 val = inb(base + UART_SCR);
1324 outb(val | 0x10, base + UART_SCR);
1325 outb(qmcr, base + UART_MCR);
1326 outb(val, base + UART_SCR);
1327 outb(LCR, base + UART_LCR);
1328 }
1329
pci_quatech_has_qmcr(struct uart_8250_port * port)1330 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1331 {
1332 unsigned long base = port->port.iobase;
1333 u8 LCR, val;
1334
1335 LCR = inb(base + UART_LCR);
1336 outb(0xBF, base + UART_LCR);
1337 val = inb(base + UART_SCR);
1338 if (val & 0x20) {
1339 outb(0x80, UART_LCR);
1340 if (!(inb(UART_SCR) & 0x20)) {
1341 outb(LCR, base + UART_LCR);
1342 return 1;
1343 }
1344 }
1345 return 0;
1346 }
1347
pci_quatech_test(struct uart_8250_port * port)1348 static int pci_quatech_test(struct uart_8250_port *port)
1349 {
1350 u8 reg, qopr;
1351
1352 qopr = pci_quatech_rqopr(port);
1353 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1354 reg = pci_quatech_rqopr(port) & 0xC0;
1355 if (reg != QPCR_TEST_GET1)
1356 return -EINVAL;
1357 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1358 reg = pci_quatech_rqopr(port) & 0xC0;
1359 if (reg != QPCR_TEST_GET2)
1360 return -EINVAL;
1361 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1362 reg = pci_quatech_rqopr(port) & 0xC0;
1363 if (reg != QPCR_TEST_GET3)
1364 return -EINVAL;
1365 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1366 reg = pci_quatech_rqopr(port) & 0xC0;
1367 if (reg != QPCR_TEST_GET4)
1368 return -EINVAL;
1369
1370 pci_quatech_wqopr(port, qopr);
1371 return 0;
1372 }
1373
pci_quatech_clock(struct uart_8250_port * port)1374 static int pci_quatech_clock(struct uart_8250_port *port)
1375 {
1376 u8 qopr, reg, set;
1377 unsigned long clock;
1378
1379 if (pci_quatech_test(port) < 0)
1380 return 1843200;
1381
1382 qopr = pci_quatech_rqopr(port);
1383
1384 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1385 reg = pci_quatech_rqopr(port);
1386 if (reg & QOPR_CLOCK_X8) {
1387 clock = 1843200;
1388 goto out;
1389 }
1390 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1391 reg = pci_quatech_rqopr(port);
1392 if (!(reg & QOPR_CLOCK_X8)) {
1393 clock = 1843200;
1394 goto out;
1395 }
1396 reg &= QOPR_CLOCK_X8;
1397 if (reg == QOPR_CLOCK_X2) {
1398 clock = 3685400;
1399 set = QOPR_CLOCK_X2;
1400 } else if (reg == QOPR_CLOCK_X4) {
1401 clock = 7372800;
1402 set = QOPR_CLOCK_X4;
1403 } else if (reg == QOPR_CLOCK_X8) {
1404 clock = 14745600;
1405 set = QOPR_CLOCK_X8;
1406 } else {
1407 clock = 1843200;
1408 set = QOPR_CLOCK_X1;
1409 }
1410 qopr &= ~QOPR_CLOCK_RATE_MASK;
1411 qopr |= set;
1412
1413 out:
1414 pci_quatech_wqopr(port, qopr);
1415 return clock;
1416 }
1417
pci_quatech_rs422(struct uart_8250_port * port)1418 static int pci_quatech_rs422(struct uart_8250_port *port)
1419 {
1420 u8 qmcr;
1421 int rs422 = 0;
1422
1423 if (!pci_quatech_has_qmcr(port))
1424 return 0;
1425 qmcr = pci_quatech_rqmcr(port);
1426 pci_quatech_wqmcr(port, 0xFF);
1427 if (pci_quatech_rqmcr(port))
1428 rs422 = 1;
1429 pci_quatech_wqmcr(port, qmcr);
1430 return rs422;
1431 }
1432
pci_quatech_init(struct pci_dev * dev)1433 static int pci_quatech_init(struct pci_dev *dev)
1434 {
1435 const struct pci_device_id *match;
1436 bool amcc = false;
1437
1438 match = pci_match_id(quatech_cards, dev);
1439 if (match)
1440 amcc = match->driver_data;
1441 else
1442 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device);
1443
1444 if (amcc) {
1445 unsigned long base = pci_resource_start(dev, 0);
1446 if (base) {
1447 u32 tmp;
1448
1449 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1450 tmp = inl(base + 0x3c);
1451 outl(tmp | 0x01000000, base + 0x3c);
1452 outl(tmp & ~0x01000000, base + 0x3c);
1453 }
1454 }
1455 return 0;
1456 }
1457
pci_quatech_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1458 static int pci_quatech_setup(struct serial_private *priv,
1459 const struct pciserial_board *board,
1460 struct uart_8250_port *port, int idx)
1461 {
1462 /* Needed by pci_quatech calls below */
1463 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1464 /* Set up the clocking */
1465 port->port.uartclk = pci_quatech_clock(port);
1466 /* For now just warn about RS422 */
1467 if (pci_quatech_rs422(port))
1468 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n");
1469 return pci_default_setup(priv, board, port, idx);
1470 }
1471
pci_default_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1472 static int pci_default_setup(struct serial_private *priv,
1473 const struct pciserial_board *board,
1474 struct uart_8250_port *port, int idx)
1475 {
1476 unsigned int bar, offset = board->first_offset, maxnr;
1477
1478 bar = FL_GET_BASE(board->flags);
1479 if (board->flags & FL_BASE_BARS)
1480 bar += idx;
1481 else
1482 offset += idx * board->uart_offset;
1483
1484 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1485 (board->reg_shift + 3);
1486
1487 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1488 return 1;
1489
1490 return setup_port(priv, port, bar, offset, board->reg_shift);
1491 }
1492
1493 static int
ce4100_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1494 ce4100_serial_setup(struct serial_private *priv,
1495 const struct pciserial_board *board,
1496 struct uart_8250_port *port, int idx)
1497 {
1498 int ret;
1499
1500 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1501 port->port.iotype = UPIO_MEM32;
1502 port->port.type = PORT_XSCALE;
1503 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1504 port->port.regshift = 2;
1505
1506 return ret;
1507 }
1508
1509 static int
pci_omegapci_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1510 pci_omegapci_setup(struct serial_private *priv,
1511 const struct pciserial_board *board,
1512 struct uart_8250_port *port, int idx)
1513 {
1514 return setup_port(priv, port, 2, idx * 8, 0);
1515 }
1516
1517 static int
pci_brcm_trumanage_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1518 pci_brcm_trumanage_setup(struct serial_private *priv,
1519 const struct pciserial_board *board,
1520 struct uart_8250_port *port, int idx)
1521 {
1522 int ret = pci_default_setup(priv, board, port, idx);
1523
1524 port->port.type = PORT_BRCM_TRUMANAGE;
1525 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1526 return ret;
1527 }
1528
1529 /* RTS will control by MCR if this bit is 0 */
1530 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1531 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1532 #define FINTEK_RTS_INVERT BIT(5)
1533
1534 /* We should do proper H/W transceiver setting before change to RS485 mode */
pci_fintek_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1535 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios,
1536 struct serial_rs485 *rs485)
1537 {
1538 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1539 u8 setting;
1540 u8 *index = (u8 *) port->private_data;
1541
1542 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1543
1544 if (rs485->flags & SER_RS485_ENABLED) {
1545 /* Enable RTS H/W control mode */
1546 setting |= FINTEK_RTS_CONTROL_BY_HW;
1547
1548 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1549 /* RTS driving high on TX */
1550 setting &= ~FINTEK_RTS_INVERT;
1551 } else {
1552 /* RTS driving low on TX */
1553 setting |= FINTEK_RTS_INVERT;
1554 }
1555 } else {
1556 /* Disable RTS H/W control mode */
1557 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1558 }
1559
1560 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1561
1562 return 0;
1563 }
1564
1565 static const struct serial_rs485 pci_fintek_rs485_supported = {
1566 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND,
1567 /* F81504/508/512 does not support RTS delay before or after send */
1568 };
1569
pci_fintek_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1570 static int pci_fintek_setup(struct serial_private *priv,
1571 const struct pciserial_board *board,
1572 struct uart_8250_port *port, int idx)
1573 {
1574 struct pci_dev *pdev = priv->dev;
1575 u8 *data;
1576 u8 config_base;
1577 u16 iobase;
1578
1579 config_base = 0x40 + 0x08 * idx;
1580
1581 /* Get the io address from configuration space */
1582 pci_read_config_word(pdev, config_base + 4, &iobase);
1583
1584 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase);
1585
1586 port->port.iotype = UPIO_PORT;
1587 port->port.iobase = iobase;
1588 port->port.rs485_config = pci_fintek_rs485_config;
1589 port->port.rs485_supported = pci_fintek_rs485_supported;
1590
1591 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1592 if (!data)
1593 return -ENOMEM;
1594
1595 /* preserve index in PCI configuration space */
1596 *data = idx;
1597 port->port.private_data = data;
1598
1599 return 0;
1600 }
1601
pci_fintek_init(struct pci_dev * dev)1602 static int pci_fintek_init(struct pci_dev *dev)
1603 {
1604 unsigned long iobase;
1605 u32 max_port, i;
1606 resource_size_t bar_data[3];
1607 u8 config_base;
1608 struct serial_private *priv = pci_get_drvdata(dev);
1609
1610 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1611 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1612 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1613 return -ENODEV;
1614
1615 switch (dev->device) {
1616 case 0x1104: /* 4 ports */
1617 case 0x1108: /* 8 ports */
1618 max_port = dev->device & 0xff;
1619 break;
1620 case 0x1112: /* 12 ports */
1621 max_port = 12;
1622 break;
1623 default:
1624 return -EINVAL;
1625 }
1626
1627 /* Get the io address dispatch from the BIOS */
1628 bar_data[0] = pci_resource_start(dev, 5);
1629 bar_data[1] = pci_resource_start(dev, 4);
1630 bar_data[2] = pci_resource_start(dev, 3);
1631
1632 for (i = 0; i < max_port; ++i) {
1633 /* UART0 configuration offset start from 0x40 */
1634 config_base = 0x40 + 0x08 * i;
1635
1636 /* Calculate Real IO Port */
1637 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1638
1639 /* Enable UART I/O port */
1640 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1641
1642 /* Select 128-byte FIFO and 8x FIFO threshold */
1643 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1644
1645 /* LSB UART */
1646 pci_write_config_byte(dev, config_base + 0x04,
1647 (u8)(iobase & 0xff));
1648
1649 /* MSB UART */
1650 pci_write_config_byte(dev, config_base + 0x05,
1651 (u8)((iobase & 0xff00) >> 8));
1652
1653 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1654
1655 if (!priv) {
1656 /* First init without port data
1657 * force init to RS232 Mode
1658 */
1659 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1660 }
1661 }
1662
1663 return max_port;
1664 }
1665
f815xxa_mem_serial_out(struct uart_port * p,int offset,int value)1666 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value)
1667 {
1668 struct f815xxa_data *data = p->private_data;
1669 unsigned long flags;
1670
1671 spin_lock_irqsave(&data->lock, flags);
1672 writeb(value, p->membase + offset);
1673 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1674 spin_unlock_irqrestore(&data->lock, flags);
1675 }
1676
pci_fintek_f815xxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1677 static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1678 const struct pciserial_board *board,
1679 struct uart_8250_port *port, int idx)
1680 {
1681 struct pci_dev *pdev = priv->dev;
1682 struct f815xxa_data *data;
1683
1684 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1685 if (!data)
1686 return -ENOMEM;
1687
1688 data->idx = idx;
1689 spin_lock_init(&data->lock);
1690
1691 port->port.private_data = data;
1692 port->port.iotype = UPIO_MEM;
1693 port->port.flags |= UPF_IOREMAP;
1694 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1695 port->port.serial_out = f815xxa_mem_serial_out;
1696
1697 return 0;
1698 }
1699
pci_fintek_f815xxa_init(struct pci_dev * dev)1700 static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1701 {
1702 u32 max_port, i;
1703 int config_base;
1704
1705 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1706 return -ENODEV;
1707
1708 switch (dev->device) {
1709 case 0x1204: /* 4 ports */
1710 case 0x1208: /* 8 ports */
1711 max_port = dev->device & 0xff;
1712 break;
1713 case 0x1212: /* 12 ports */
1714 max_port = 12;
1715 break;
1716 default:
1717 return -EINVAL;
1718 }
1719
1720 /* Set to mmio decode */
1721 pci_write_config_byte(dev, 0x209, 0x40);
1722
1723 for (i = 0; i < max_port; ++i) {
1724 /* UART0 configuration offset start from 0x2A0 */
1725 config_base = 0x2A0 + 0x08 * i;
1726
1727 /* Select 128-byte FIFO and 8x FIFO threshold */
1728 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1729
1730 /* Enable UART I/O port */
1731 pci_write_config_byte(dev, config_base + 0, 0x01);
1732 }
1733
1734 return max_port;
1735 }
1736
skip_tx_en_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1737 static int skip_tx_en_setup(struct serial_private *priv,
1738 const struct pciserial_board *board,
1739 struct uart_8250_port *port, int idx)
1740 {
1741 port->port.quirks |= UPQ_NO_TXEN_TEST;
1742 pci_dbg(priv->dev,
1743 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1744 priv->dev->vendor, priv->dev->device,
1745 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1746
1747 return pci_default_setup(priv, board, port, idx);
1748 }
1749
kt_handle_break(struct uart_port * p)1750 static void kt_handle_break(struct uart_port *p)
1751 {
1752 struct uart_8250_port *up = up_to_u8250p(p);
1753 /*
1754 * On receipt of a BI, serial device in Intel ME (Intel
1755 * management engine) needs to have its fifos cleared for sane
1756 * SOL (Serial Over Lan) output.
1757 */
1758 serial8250_clear_and_reinit_fifos(up);
1759 }
1760
kt_serial_in(struct uart_port * p,int offset)1761 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1762 {
1763 struct uart_8250_port *up = up_to_u8250p(p);
1764 unsigned int val;
1765
1766 /*
1767 * When the Intel ME (management engine) gets reset its serial
1768 * port registers could return 0 momentarily. Functions like
1769 * serial8250_console_write, read and save the IER, perform
1770 * some operation and then restore it. In order to avoid
1771 * setting IER register inadvertently to 0, if the value read
1772 * is 0, double check with ier value in uart_8250_port and use
1773 * that instead. up->ier should be the same value as what is
1774 * currently configured.
1775 */
1776 val = inb(p->iobase + offset);
1777 if (offset == UART_IER) {
1778 if (val == 0)
1779 val = up->ier;
1780 }
1781 return val;
1782 }
1783
kt_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1784 static int kt_serial_setup(struct serial_private *priv,
1785 const struct pciserial_board *board,
1786 struct uart_8250_port *port, int idx)
1787 {
1788 port->port.flags |= UPF_BUG_THRE;
1789 port->port.serial_in = kt_serial_in;
1790 port->port.handle_break = kt_handle_break;
1791 return skip_tx_en_setup(priv, board, port, idx);
1792 }
1793
pci_eg20t_init(struct pci_dev * dev)1794 static int pci_eg20t_init(struct pci_dev *dev)
1795 {
1796 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1797 return -ENODEV;
1798 #else
1799 return 0;
1800 #endif
1801 }
1802
1803 static int
pci_wch_ch353_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1804 pci_wch_ch353_setup(struct serial_private *priv,
1805 const struct pciserial_board *board,
1806 struct uart_8250_port *port, int idx)
1807 {
1808 port->port.flags |= UPF_FIXED_TYPE;
1809 port->port.type = PORT_16550A;
1810 return pci_default_setup(priv, board, port, idx);
1811 }
1812
1813 static int
pci_wch_ch355_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1814 pci_wch_ch355_setup(struct serial_private *priv,
1815 const struct pciserial_board *board,
1816 struct uart_8250_port *port, int idx)
1817 {
1818 port->port.flags |= UPF_FIXED_TYPE;
1819 port->port.type = PORT_16550A;
1820 return pci_default_setup(priv, board, port, idx);
1821 }
1822
1823 static int
pci_wch_ch38x_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1824 pci_wch_ch38x_setup(struct serial_private *priv,
1825 const struct pciserial_board *board,
1826 struct uart_8250_port *port, int idx)
1827 {
1828 port->port.flags |= UPF_FIXED_TYPE;
1829 port->port.type = PORT_16850;
1830 return pci_default_setup(priv, board, port, idx);
1831 }
1832
1833
1834 #define CH384_XINT_ENABLE_REG 0xEB
1835 #define CH384_XINT_ENABLE_BIT 0x02
1836
pci_wch_ch38x_init(struct pci_dev * dev)1837 static int pci_wch_ch38x_init(struct pci_dev *dev)
1838 {
1839 int max_port;
1840 unsigned long iobase;
1841
1842
1843 switch (dev->device) {
1844 case 0x3853: /* 8 ports */
1845 max_port = 8;
1846 break;
1847 default:
1848 return -EINVAL;
1849 }
1850
1851 iobase = pci_resource_start(dev, 0);
1852 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG);
1853
1854 return max_port;
1855 }
1856
pci_wch_ch38x_exit(struct pci_dev * dev)1857 static void pci_wch_ch38x_exit(struct pci_dev *dev)
1858 {
1859 unsigned long iobase;
1860
1861 iobase = pci_resource_start(dev, 0);
1862 outb(0x0, iobase + CH384_XINT_ENABLE_REG);
1863 }
1864
1865
1866 static int
pci_sunix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1867 pci_sunix_setup(struct serial_private *priv,
1868 const struct pciserial_board *board,
1869 struct uart_8250_port *port, int idx)
1870 {
1871 int bar;
1872 int offset;
1873
1874 port->port.flags |= UPF_FIXED_TYPE;
1875 port->port.type = PORT_SUNIX;
1876
1877 if (idx < 4) {
1878 bar = 0;
1879 offset = idx * board->uart_offset;
1880 } else {
1881 bar = 1;
1882 idx -= 4;
1883 idx = div_s64_rem(idx, 4, &offset);
1884 offset = idx * 64 + offset * board->uart_offset;
1885 }
1886
1887 return setup_port(priv, port, bar, offset, 0);
1888 }
1889
1890 static int
pci_moxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1891 pci_moxa_setup(struct serial_private *priv,
1892 const struct pciserial_board *board,
1893 struct uart_8250_port *port, int idx)
1894 {
1895 unsigned int bar = FL_GET_BASE(board->flags);
1896 int offset;
1897
1898 if (board->num_ports == 4 && idx == 3)
1899 offset = 7 * board->uart_offset;
1900 else
1901 offset = idx * board->uart_offset;
1902
1903 return setup_port(priv, port, bar, offset, 0);
1904 }
1905
1906 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1907 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1908 #define PCI_DEVICE_ID_OCTPRO 0x0001
1909 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1910 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1911 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1912 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1913 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1914 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1915 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1916 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1917 #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600
1918 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611
1919 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1920 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1921 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1922 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1923 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1924 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1925 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1926 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1927 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1928 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1929 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1930 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1931 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1932 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1933 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1934 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1935 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1936 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1937 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1938 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1939 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1940 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1941 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1942 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1943 #define PCI_VENDOR_ID_WCH 0x4348
1944 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1945 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1946 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1947 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1948 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1949 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1950 #define PCI_VENDOR_ID_AGESTAR 0x5372
1951 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1952 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1953 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1954
1955 #define PCIE_VENDOR_ID_WCH 0x1c00
1956 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1957 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1958 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853
1959 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1960
1961 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024
1962 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
1963 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
1964 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
1965 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
1966 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
1967 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
1968 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
1969 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
1970 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
1971 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
1972 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
1973
1974 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1975 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1976 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1977
1978 /*
1979 * Master list of serial port init/setup/exit quirks.
1980 * This does not describe the general nature of the port.
1981 * (ie, baud base, number and location of ports, etc)
1982 *
1983 * This list is ordered alphabetically by vendor then device.
1984 * Specific entries must come before more generic entries.
1985 */
1986 static struct pci_serial_quirk pci_serial_quirks[] = {
1987 /*
1988 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1989 */
1990 {
1991 .vendor = PCI_VENDOR_ID_AMCC,
1992 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1993 .subvendor = PCI_ANY_ID,
1994 .subdevice = PCI_ANY_ID,
1995 .setup = addidata_apci7800_setup,
1996 },
1997 /*
1998 * AFAVLAB cards - these may be called via parport_serial
1999 * It is not clear whether this applies to all products.
2000 */
2001 {
2002 .vendor = PCI_VENDOR_ID_AFAVLAB,
2003 .device = PCI_ANY_ID,
2004 .subvendor = PCI_ANY_ID,
2005 .subdevice = PCI_ANY_ID,
2006 .setup = afavlab_setup,
2007 },
2008 /*
2009 * HP Diva
2010 */
2011 {
2012 .vendor = PCI_VENDOR_ID_HP,
2013 .device = PCI_DEVICE_ID_HP_DIVA,
2014 .subvendor = PCI_ANY_ID,
2015 .subdevice = PCI_ANY_ID,
2016 .init = pci_hp_diva_init,
2017 .setup = pci_hp_diva_setup,
2018 },
2019 /*
2020 * HPE PCI serial device
2021 */
2022 {
2023 .vendor = PCI_VENDOR_ID_HP_3PAR,
2024 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL,
2025 .subvendor = PCI_ANY_ID,
2026 .subdevice = PCI_ANY_ID,
2027 .setup = pci_hp_diva_setup,
2028 },
2029 /*
2030 * Intel
2031 */
2032 {
2033 .vendor = PCI_VENDOR_ID_INTEL,
2034 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2035 .subvendor = 0xe4bf,
2036 .subdevice = PCI_ANY_ID,
2037 .init = pci_inteli960ni_init,
2038 .setup = pci_default_setup,
2039 },
2040 {
2041 .vendor = PCI_VENDOR_ID_INTEL,
2042 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2043 .subvendor = PCI_ANY_ID,
2044 .subdevice = PCI_ANY_ID,
2045 .setup = skip_tx_en_setup,
2046 },
2047 {
2048 .vendor = PCI_VENDOR_ID_INTEL,
2049 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2050 .subvendor = PCI_ANY_ID,
2051 .subdevice = PCI_ANY_ID,
2052 .setup = skip_tx_en_setup,
2053 },
2054 {
2055 .vendor = PCI_VENDOR_ID_INTEL,
2056 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2057 .subvendor = PCI_ANY_ID,
2058 .subdevice = PCI_ANY_ID,
2059 .setup = skip_tx_en_setup,
2060 },
2061 {
2062 .vendor = PCI_VENDOR_ID_INTEL,
2063 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2064 .subvendor = PCI_ANY_ID,
2065 .subdevice = PCI_ANY_ID,
2066 .setup = ce4100_serial_setup,
2067 },
2068 {
2069 .vendor = PCI_VENDOR_ID_INTEL,
2070 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2071 .subvendor = PCI_ANY_ID,
2072 .subdevice = PCI_ANY_ID,
2073 .setup = kt_serial_setup,
2074 },
2075 /*
2076 * ITE
2077 */
2078 {
2079 .vendor = PCI_VENDOR_ID_ITE,
2080 .device = PCI_DEVICE_ID_ITE_8872,
2081 .subvendor = PCI_ANY_ID,
2082 .subdevice = PCI_ANY_ID,
2083 .init = pci_ite887x_init,
2084 .setup = pci_default_setup,
2085 .exit = pci_ite887x_exit,
2086 },
2087 /*
2088 * National Instruments
2089 */
2090 {
2091 .vendor = PCI_VENDOR_ID_NI,
2092 .device = PCI_DEVICE_ID_NI_PCI23216,
2093 .subvendor = PCI_ANY_ID,
2094 .subdevice = PCI_ANY_ID,
2095 .init = pci_ni8420_init,
2096 .setup = pci_default_setup,
2097 .exit = pci_ni8420_exit,
2098 },
2099 {
2100 .vendor = PCI_VENDOR_ID_NI,
2101 .device = PCI_DEVICE_ID_NI_PCI2328,
2102 .subvendor = PCI_ANY_ID,
2103 .subdevice = PCI_ANY_ID,
2104 .init = pci_ni8420_init,
2105 .setup = pci_default_setup,
2106 .exit = pci_ni8420_exit,
2107 },
2108 {
2109 .vendor = PCI_VENDOR_ID_NI,
2110 .device = PCI_DEVICE_ID_NI_PCI2324,
2111 .subvendor = PCI_ANY_ID,
2112 .subdevice = PCI_ANY_ID,
2113 .init = pci_ni8420_init,
2114 .setup = pci_default_setup,
2115 .exit = pci_ni8420_exit,
2116 },
2117 {
2118 .vendor = PCI_VENDOR_ID_NI,
2119 .device = PCI_DEVICE_ID_NI_PCI2322,
2120 .subvendor = PCI_ANY_ID,
2121 .subdevice = PCI_ANY_ID,
2122 .init = pci_ni8420_init,
2123 .setup = pci_default_setup,
2124 .exit = pci_ni8420_exit,
2125 },
2126 {
2127 .vendor = PCI_VENDOR_ID_NI,
2128 .device = PCI_DEVICE_ID_NI_PCI2324I,
2129 .subvendor = PCI_ANY_ID,
2130 .subdevice = PCI_ANY_ID,
2131 .init = pci_ni8420_init,
2132 .setup = pci_default_setup,
2133 .exit = pci_ni8420_exit,
2134 },
2135 {
2136 .vendor = PCI_VENDOR_ID_NI,
2137 .device = PCI_DEVICE_ID_NI_PCI2322I,
2138 .subvendor = PCI_ANY_ID,
2139 .subdevice = PCI_ANY_ID,
2140 .init = pci_ni8420_init,
2141 .setup = pci_default_setup,
2142 .exit = pci_ni8420_exit,
2143 },
2144 {
2145 .vendor = PCI_VENDOR_ID_NI,
2146 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2147 .subvendor = PCI_ANY_ID,
2148 .subdevice = PCI_ANY_ID,
2149 .init = pci_ni8420_init,
2150 .setup = pci_default_setup,
2151 .exit = pci_ni8420_exit,
2152 },
2153 {
2154 .vendor = PCI_VENDOR_ID_NI,
2155 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2156 .subvendor = PCI_ANY_ID,
2157 .subdevice = PCI_ANY_ID,
2158 .init = pci_ni8420_init,
2159 .setup = pci_default_setup,
2160 .exit = pci_ni8420_exit,
2161 },
2162 {
2163 .vendor = PCI_VENDOR_ID_NI,
2164 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2165 .subvendor = PCI_ANY_ID,
2166 .subdevice = PCI_ANY_ID,
2167 .init = pci_ni8420_init,
2168 .setup = pci_default_setup,
2169 .exit = pci_ni8420_exit,
2170 },
2171 {
2172 .vendor = PCI_VENDOR_ID_NI,
2173 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2174 .subvendor = PCI_ANY_ID,
2175 .subdevice = PCI_ANY_ID,
2176 .init = pci_ni8420_init,
2177 .setup = pci_default_setup,
2178 .exit = pci_ni8420_exit,
2179 },
2180 {
2181 .vendor = PCI_VENDOR_ID_NI,
2182 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2183 .subvendor = PCI_ANY_ID,
2184 .subdevice = PCI_ANY_ID,
2185 .init = pci_ni8420_init,
2186 .setup = pci_default_setup,
2187 .exit = pci_ni8420_exit,
2188 },
2189 {
2190 .vendor = PCI_VENDOR_ID_NI,
2191 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2192 .subvendor = PCI_ANY_ID,
2193 .subdevice = PCI_ANY_ID,
2194 .init = pci_ni8420_init,
2195 .setup = pci_default_setup,
2196 .exit = pci_ni8420_exit,
2197 },
2198 {
2199 .vendor = PCI_VENDOR_ID_NI,
2200 .device = PCI_ANY_ID,
2201 .subvendor = PCI_ANY_ID,
2202 .subdevice = PCI_ANY_ID,
2203 .init = pci_ni8430_init,
2204 .setup = pci_ni8430_setup,
2205 .exit = pci_ni8430_exit,
2206 },
2207 /* Quatech */
2208 {
2209 .vendor = PCI_VENDOR_ID_QUATECH,
2210 .device = PCI_ANY_ID,
2211 .subvendor = PCI_ANY_ID,
2212 .subdevice = PCI_ANY_ID,
2213 .init = pci_quatech_init,
2214 .setup = pci_quatech_setup,
2215 },
2216 /*
2217 * Panacom
2218 */
2219 {
2220 .vendor = PCI_VENDOR_ID_PANACOM,
2221 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2222 .subvendor = PCI_ANY_ID,
2223 .subdevice = PCI_ANY_ID,
2224 .init = pci_plx9050_init,
2225 .setup = pci_default_setup,
2226 .exit = pci_plx9050_exit,
2227 },
2228 {
2229 .vendor = PCI_VENDOR_ID_PANACOM,
2230 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2231 .subvendor = PCI_ANY_ID,
2232 .subdevice = PCI_ANY_ID,
2233 .init = pci_plx9050_init,
2234 .setup = pci_default_setup,
2235 .exit = pci_plx9050_exit,
2236 },
2237 /*
2238 * PLX
2239 */
2240 {
2241 .vendor = PCI_VENDOR_ID_PLX,
2242 .device = PCI_DEVICE_ID_PLX_9050,
2243 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2244 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2245 .init = pci_plx9050_init,
2246 .setup = pci_default_setup,
2247 .exit = pci_plx9050_exit,
2248 },
2249 {
2250 .vendor = PCI_VENDOR_ID_PLX,
2251 .device = PCI_DEVICE_ID_PLX_9050,
2252 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2253 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2254 .init = pci_plx9050_init,
2255 .setup = pci_default_setup,
2256 .exit = pci_plx9050_exit,
2257 },
2258 {
2259 .vendor = PCI_VENDOR_ID_PLX,
2260 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2261 .subvendor = PCI_VENDOR_ID_PLX,
2262 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2263 .init = pci_plx9050_init,
2264 .setup = pci_default_setup,
2265 .exit = pci_plx9050_exit,
2266 },
2267 /*
2268 * SBS Technologies, Inc., PMC-OCTALPRO 232
2269 */
2270 {
2271 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2272 .device = PCI_DEVICE_ID_OCTPRO,
2273 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2274 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2275 .init = sbs_init,
2276 .setup = sbs_setup,
2277 .exit = sbs_exit,
2278 },
2279 /*
2280 * SBS Technologies, Inc., PMC-OCTALPRO 422
2281 */
2282 {
2283 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2284 .device = PCI_DEVICE_ID_OCTPRO,
2285 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2286 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2287 .init = sbs_init,
2288 .setup = sbs_setup,
2289 .exit = sbs_exit,
2290 },
2291 /*
2292 * SBS Technologies, Inc., P-Octal 232
2293 */
2294 {
2295 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2296 .device = PCI_DEVICE_ID_OCTPRO,
2297 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2298 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2299 .init = sbs_init,
2300 .setup = sbs_setup,
2301 .exit = sbs_exit,
2302 },
2303 /*
2304 * SBS Technologies, Inc., P-Octal 422
2305 */
2306 {
2307 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2308 .device = PCI_DEVICE_ID_OCTPRO,
2309 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2310 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2311 .init = sbs_init,
2312 .setup = sbs_setup,
2313 .exit = sbs_exit,
2314 },
2315 /*
2316 * SIIG cards - these may be called via parport_serial
2317 */
2318 {
2319 .vendor = PCI_VENDOR_ID_SIIG,
2320 .device = PCI_ANY_ID,
2321 .subvendor = PCI_ANY_ID,
2322 .subdevice = PCI_ANY_ID,
2323 .init = pci_siig_init,
2324 .setup = pci_siig_setup,
2325 },
2326 /*
2327 * Titan cards
2328 */
2329 {
2330 .vendor = PCI_VENDOR_ID_TITAN,
2331 .device = PCI_DEVICE_ID_TITAN_400L,
2332 .subvendor = PCI_ANY_ID,
2333 .subdevice = PCI_ANY_ID,
2334 .setup = titan_400l_800l_setup,
2335 },
2336 {
2337 .vendor = PCI_VENDOR_ID_TITAN,
2338 .device = PCI_DEVICE_ID_TITAN_800L,
2339 .subvendor = PCI_ANY_ID,
2340 .subdevice = PCI_ANY_ID,
2341 .setup = titan_400l_800l_setup,
2342 },
2343 /*
2344 * Timedia cards
2345 */
2346 {
2347 .vendor = PCI_VENDOR_ID_TIMEDIA,
2348 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2349 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2350 .subdevice = PCI_ANY_ID,
2351 .probe = pci_timedia_probe,
2352 .init = pci_timedia_init,
2353 .setup = pci_timedia_setup,
2354 },
2355 {
2356 .vendor = PCI_VENDOR_ID_TIMEDIA,
2357 .device = PCI_ANY_ID,
2358 .subvendor = PCI_ANY_ID,
2359 .subdevice = PCI_ANY_ID,
2360 .setup = pci_timedia_setup,
2361 },
2362 /*
2363 * Sunix PCI serial boards
2364 */
2365 {
2366 .vendor = PCI_VENDOR_ID_SUNIX,
2367 .device = PCI_DEVICE_ID_SUNIX_1999,
2368 .subvendor = PCI_VENDOR_ID_SUNIX,
2369 .subdevice = PCI_ANY_ID,
2370 .setup = pci_sunix_setup,
2371 },
2372 /*
2373 * Xircom cards
2374 */
2375 {
2376 .vendor = PCI_VENDOR_ID_XIRCOM,
2377 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2378 .subvendor = PCI_ANY_ID,
2379 .subdevice = PCI_ANY_ID,
2380 .init = pci_xircom_init,
2381 .setup = pci_default_setup,
2382 },
2383 /*
2384 * Netmos cards - these may be called via parport_serial
2385 */
2386 {
2387 .vendor = PCI_VENDOR_ID_NETMOS,
2388 .device = PCI_ANY_ID,
2389 .subvendor = PCI_ANY_ID,
2390 .subdevice = PCI_ANY_ID,
2391 .init = pci_netmos_init,
2392 .setup = pci_netmos_9900_setup,
2393 },
2394 /*
2395 * EndRun Technologies
2396 */
2397 {
2398 .vendor = PCI_VENDOR_ID_ENDRUN,
2399 .device = PCI_ANY_ID,
2400 .subvendor = PCI_ANY_ID,
2401 .subdevice = PCI_ANY_ID,
2402 .init = pci_oxsemi_tornado_init,
2403 .setup = pci_default_setup,
2404 },
2405 /*
2406 * For Oxford Semiconductor Tornado based devices
2407 */
2408 {
2409 .vendor = PCI_VENDOR_ID_OXSEMI,
2410 .device = PCI_ANY_ID,
2411 .subvendor = PCI_ANY_ID,
2412 .subdevice = PCI_ANY_ID,
2413 .init = pci_oxsemi_tornado_init,
2414 .setup = pci_oxsemi_tornado_setup,
2415 },
2416 {
2417 .vendor = PCI_VENDOR_ID_MAINPINE,
2418 .device = PCI_ANY_ID,
2419 .subvendor = PCI_ANY_ID,
2420 .subdevice = PCI_ANY_ID,
2421 .init = pci_oxsemi_tornado_init,
2422 .setup = pci_oxsemi_tornado_setup,
2423 },
2424 {
2425 .vendor = PCI_VENDOR_ID_DIGI,
2426 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2427 .subvendor = PCI_SUBVENDOR_ID_IBM,
2428 .subdevice = PCI_ANY_ID,
2429 .init = pci_oxsemi_tornado_init,
2430 .setup = pci_oxsemi_tornado_setup,
2431 },
2432 {
2433 .vendor = PCI_VENDOR_ID_INTEL,
2434 .device = 0x8811,
2435 .subvendor = PCI_ANY_ID,
2436 .subdevice = PCI_ANY_ID,
2437 .init = pci_eg20t_init,
2438 .setup = pci_default_setup,
2439 },
2440 {
2441 .vendor = PCI_VENDOR_ID_INTEL,
2442 .device = 0x8812,
2443 .subvendor = PCI_ANY_ID,
2444 .subdevice = PCI_ANY_ID,
2445 .init = pci_eg20t_init,
2446 .setup = pci_default_setup,
2447 },
2448 {
2449 .vendor = PCI_VENDOR_ID_INTEL,
2450 .device = 0x8813,
2451 .subvendor = PCI_ANY_ID,
2452 .subdevice = PCI_ANY_ID,
2453 .init = pci_eg20t_init,
2454 .setup = pci_default_setup,
2455 },
2456 {
2457 .vendor = PCI_VENDOR_ID_INTEL,
2458 .device = 0x8814,
2459 .subvendor = PCI_ANY_ID,
2460 .subdevice = PCI_ANY_ID,
2461 .init = pci_eg20t_init,
2462 .setup = pci_default_setup,
2463 },
2464 {
2465 .vendor = 0x10DB,
2466 .device = 0x8027,
2467 .subvendor = PCI_ANY_ID,
2468 .subdevice = PCI_ANY_ID,
2469 .init = pci_eg20t_init,
2470 .setup = pci_default_setup,
2471 },
2472 {
2473 .vendor = 0x10DB,
2474 .device = 0x8028,
2475 .subvendor = PCI_ANY_ID,
2476 .subdevice = PCI_ANY_ID,
2477 .init = pci_eg20t_init,
2478 .setup = pci_default_setup,
2479 },
2480 {
2481 .vendor = 0x10DB,
2482 .device = 0x8029,
2483 .subvendor = PCI_ANY_ID,
2484 .subdevice = PCI_ANY_ID,
2485 .init = pci_eg20t_init,
2486 .setup = pci_default_setup,
2487 },
2488 {
2489 .vendor = 0x10DB,
2490 .device = 0x800C,
2491 .subvendor = PCI_ANY_ID,
2492 .subdevice = PCI_ANY_ID,
2493 .init = pci_eg20t_init,
2494 .setup = pci_default_setup,
2495 },
2496 {
2497 .vendor = 0x10DB,
2498 .device = 0x800D,
2499 .subvendor = PCI_ANY_ID,
2500 .subdevice = PCI_ANY_ID,
2501 .init = pci_eg20t_init,
2502 .setup = pci_default_setup,
2503 },
2504 /*
2505 * Cronyx Omega PCI (PLX-chip based)
2506 */
2507 {
2508 .vendor = PCI_VENDOR_ID_PLX,
2509 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2510 .subvendor = PCI_ANY_ID,
2511 .subdevice = PCI_ANY_ID,
2512 .setup = pci_omegapci_setup,
2513 },
2514 /* WCH CH353 1S1P card (16550 clone) */
2515 {
2516 .vendor = PCI_VENDOR_ID_WCH,
2517 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2518 .subvendor = PCI_ANY_ID,
2519 .subdevice = PCI_ANY_ID,
2520 .setup = pci_wch_ch353_setup,
2521 },
2522 /* WCH CH353 2S1P card (16550 clone) */
2523 {
2524 .vendor = PCI_VENDOR_ID_WCH,
2525 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2526 .subvendor = PCI_ANY_ID,
2527 .subdevice = PCI_ANY_ID,
2528 .setup = pci_wch_ch353_setup,
2529 },
2530 /* WCH CH353 4S card (16550 clone) */
2531 {
2532 .vendor = PCI_VENDOR_ID_WCH,
2533 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2534 .subvendor = PCI_ANY_ID,
2535 .subdevice = PCI_ANY_ID,
2536 .setup = pci_wch_ch353_setup,
2537 },
2538 /* WCH CH353 2S1PF card (16550 clone) */
2539 {
2540 .vendor = PCI_VENDOR_ID_WCH,
2541 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2542 .subvendor = PCI_ANY_ID,
2543 .subdevice = PCI_ANY_ID,
2544 .setup = pci_wch_ch353_setup,
2545 },
2546 /* WCH CH352 2S card (16550 clone) */
2547 {
2548 .vendor = PCI_VENDOR_ID_WCH,
2549 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2550 .subvendor = PCI_ANY_ID,
2551 .subdevice = PCI_ANY_ID,
2552 .setup = pci_wch_ch353_setup,
2553 },
2554 /* WCH CH355 4S card (16550 clone) */
2555 {
2556 .vendor = PCI_VENDOR_ID_WCH,
2557 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2558 .subvendor = PCI_ANY_ID,
2559 .subdevice = PCI_ANY_ID,
2560 .setup = pci_wch_ch355_setup,
2561 },
2562 /* WCH CH382 2S card (16850 clone) */
2563 {
2564 .vendor = PCIE_VENDOR_ID_WCH,
2565 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2566 .subvendor = PCI_ANY_ID,
2567 .subdevice = PCI_ANY_ID,
2568 .setup = pci_wch_ch38x_setup,
2569 },
2570 /* WCH CH382 2S1P card (16850 clone) */
2571 {
2572 .vendor = PCIE_VENDOR_ID_WCH,
2573 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2574 .subvendor = PCI_ANY_ID,
2575 .subdevice = PCI_ANY_ID,
2576 .setup = pci_wch_ch38x_setup,
2577 },
2578 /* WCH CH384 4S card (16850 clone) */
2579 {
2580 .vendor = PCIE_VENDOR_ID_WCH,
2581 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2582 .subvendor = PCI_ANY_ID,
2583 .subdevice = PCI_ANY_ID,
2584 .setup = pci_wch_ch38x_setup,
2585 },
2586 /* WCH CH384 8S card (16850 clone) */
2587 {
2588 .vendor = PCIE_VENDOR_ID_WCH,
2589 .device = PCIE_DEVICE_ID_WCH_CH384_8S,
2590 .subvendor = PCI_ANY_ID,
2591 .subdevice = PCI_ANY_ID,
2592 .init = pci_wch_ch38x_init,
2593 .exit = pci_wch_ch38x_exit,
2594 .setup = pci_wch_ch38x_setup,
2595 },
2596 /*
2597 * Broadcom TruManage (NetXtreme)
2598 */
2599 {
2600 .vendor = PCI_VENDOR_ID_BROADCOM,
2601 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2602 .subvendor = PCI_ANY_ID,
2603 .subdevice = PCI_ANY_ID,
2604 .setup = pci_brcm_trumanage_setup,
2605 },
2606 {
2607 .vendor = 0x1c29,
2608 .device = 0x1104,
2609 .subvendor = PCI_ANY_ID,
2610 .subdevice = PCI_ANY_ID,
2611 .setup = pci_fintek_setup,
2612 .init = pci_fintek_init,
2613 },
2614 {
2615 .vendor = 0x1c29,
2616 .device = 0x1108,
2617 .subvendor = PCI_ANY_ID,
2618 .subdevice = PCI_ANY_ID,
2619 .setup = pci_fintek_setup,
2620 .init = pci_fintek_init,
2621 },
2622 {
2623 .vendor = 0x1c29,
2624 .device = 0x1112,
2625 .subvendor = PCI_ANY_ID,
2626 .subdevice = PCI_ANY_ID,
2627 .setup = pci_fintek_setup,
2628 .init = pci_fintek_init,
2629 },
2630 /*
2631 * MOXA
2632 */
2633 {
2634 .vendor = PCI_VENDOR_ID_MOXA,
2635 .device = PCI_ANY_ID,
2636 .subvendor = PCI_ANY_ID,
2637 .subdevice = PCI_ANY_ID,
2638 .setup = pci_moxa_setup,
2639 },
2640 {
2641 .vendor = 0x1c29,
2642 .device = 0x1204,
2643 .subvendor = PCI_ANY_ID,
2644 .subdevice = PCI_ANY_ID,
2645 .setup = pci_fintek_f815xxa_setup,
2646 .init = pci_fintek_f815xxa_init,
2647 },
2648 {
2649 .vendor = 0x1c29,
2650 .device = 0x1208,
2651 .subvendor = PCI_ANY_ID,
2652 .subdevice = PCI_ANY_ID,
2653 .setup = pci_fintek_f815xxa_setup,
2654 .init = pci_fintek_f815xxa_init,
2655 },
2656 {
2657 .vendor = 0x1c29,
2658 .device = 0x1212,
2659 .subvendor = PCI_ANY_ID,
2660 .subdevice = PCI_ANY_ID,
2661 .setup = pci_fintek_f815xxa_setup,
2662 .init = pci_fintek_f815xxa_init,
2663 },
2664
2665 /*
2666 * Default "match everything" terminator entry
2667 */
2668 {
2669 .vendor = PCI_ANY_ID,
2670 .device = PCI_ANY_ID,
2671 .subvendor = PCI_ANY_ID,
2672 .subdevice = PCI_ANY_ID,
2673 .setup = pci_default_setup,
2674 }
2675 };
2676
quirk_id_matches(u32 quirk_id,u32 dev_id)2677 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2678 {
2679 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2680 }
2681
find_quirk(struct pci_dev * dev)2682 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2683 {
2684 struct pci_serial_quirk *quirk;
2685
2686 for (quirk = pci_serial_quirks; ; quirk++)
2687 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2688 quirk_id_matches(quirk->device, dev->device) &&
2689 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2690 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2691 break;
2692 return quirk;
2693 }
2694
2695 /*
2696 * This is the configuration table for all of the PCI serial boards
2697 * which we support. It is directly indexed by the pci_board_num_t enum
2698 * value, which is encoded in the pci_device_id PCI probe table's
2699 * driver_data member.
2700 *
2701 * The makeup of these names are:
2702 * pbn_bn{_bt}_n_baud{_offsetinhex}
2703 *
2704 * bn = PCI BAR number
2705 * bt = Index using PCI BARs
2706 * n = number of serial ports
2707 * baud = baud rate
2708 * offsetinhex = offset for each sequential port (in hex)
2709 *
2710 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2711 *
2712 * Please note: in theory if n = 1, _bt infix should make no difference.
2713 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2714 */
2715 enum pci_board_num_t {
2716 pbn_default = 0,
2717
2718 pbn_b0_1_115200,
2719 pbn_b0_2_115200,
2720 pbn_b0_4_115200,
2721 pbn_b0_5_115200,
2722 pbn_b0_8_115200,
2723
2724 pbn_b0_1_921600,
2725 pbn_b0_2_921600,
2726 pbn_b0_4_921600,
2727
2728 pbn_b0_2_1130000,
2729
2730 pbn_b0_4_1152000,
2731
2732 pbn_b0_4_1250000,
2733
2734 pbn_b0_2_1843200,
2735 pbn_b0_4_1843200,
2736
2737 pbn_b0_1_15625000,
2738
2739 pbn_b0_bt_1_115200,
2740 pbn_b0_bt_2_115200,
2741 pbn_b0_bt_4_115200,
2742 pbn_b0_bt_8_115200,
2743
2744 pbn_b0_bt_1_460800,
2745 pbn_b0_bt_2_460800,
2746 pbn_b0_bt_4_460800,
2747
2748 pbn_b0_bt_1_921600,
2749 pbn_b0_bt_2_921600,
2750 pbn_b0_bt_4_921600,
2751 pbn_b0_bt_8_921600,
2752
2753 pbn_b1_1_115200,
2754 pbn_b1_2_115200,
2755 pbn_b1_4_115200,
2756 pbn_b1_8_115200,
2757 pbn_b1_16_115200,
2758
2759 pbn_b1_1_921600,
2760 pbn_b1_2_921600,
2761 pbn_b1_4_921600,
2762 pbn_b1_8_921600,
2763
2764 pbn_b1_2_1250000,
2765
2766 pbn_b1_bt_1_115200,
2767 pbn_b1_bt_2_115200,
2768 pbn_b1_bt_4_115200,
2769
2770 pbn_b1_bt_2_921600,
2771
2772 pbn_b1_1_1382400,
2773 pbn_b1_2_1382400,
2774 pbn_b1_4_1382400,
2775 pbn_b1_8_1382400,
2776
2777 pbn_b2_1_115200,
2778 pbn_b2_2_115200,
2779 pbn_b2_4_115200,
2780 pbn_b2_8_115200,
2781
2782 pbn_b2_1_460800,
2783 pbn_b2_4_460800,
2784 pbn_b2_8_460800,
2785 pbn_b2_16_460800,
2786
2787 pbn_b2_1_921600,
2788 pbn_b2_4_921600,
2789 pbn_b2_8_921600,
2790
2791 pbn_b2_8_1152000,
2792
2793 pbn_b2_bt_1_115200,
2794 pbn_b2_bt_2_115200,
2795 pbn_b2_bt_4_115200,
2796
2797 pbn_b2_bt_2_921600,
2798 pbn_b2_bt_4_921600,
2799
2800 pbn_b3_2_115200,
2801 pbn_b3_4_115200,
2802 pbn_b3_8_115200,
2803
2804 pbn_b4_bt_2_921600,
2805 pbn_b4_bt_4_921600,
2806 pbn_b4_bt_8_921600,
2807
2808 /*
2809 * Board-specific versions.
2810 */
2811 pbn_panacom,
2812 pbn_panacom2,
2813 pbn_panacom4,
2814 pbn_plx_romulus,
2815 pbn_oxsemi,
2816 pbn_oxsemi_1_15625000,
2817 pbn_oxsemi_2_15625000,
2818 pbn_oxsemi_4_15625000,
2819 pbn_oxsemi_8_15625000,
2820 pbn_intel_i960,
2821 pbn_sgi_ioc3,
2822 pbn_computone_4,
2823 pbn_computone_6,
2824 pbn_computone_8,
2825 pbn_sbsxrsio,
2826 pbn_pasemi_1682M,
2827 pbn_ni8430_2,
2828 pbn_ni8430_4,
2829 pbn_ni8430_8,
2830 pbn_ni8430_16,
2831 pbn_ADDIDATA_PCIe_1_3906250,
2832 pbn_ADDIDATA_PCIe_2_3906250,
2833 pbn_ADDIDATA_PCIe_4_3906250,
2834 pbn_ADDIDATA_PCIe_8_3906250,
2835 pbn_ce4100_1_115200,
2836 pbn_omegapci,
2837 pbn_NETMOS9900_2s_115200,
2838 pbn_brcm_trumanage,
2839 pbn_fintek_4,
2840 pbn_fintek_8,
2841 pbn_fintek_12,
2842 pbn_fintek_F81504A,
2843 pbn_fintek_F81508A,
2844 pbn_fintek_F81512A,
2845 pbn_wch382_2,
2846 pbn_wch384_4,
2847 pbn_wch384_8,
2848 pbn_sunix_pci_1s,
2849 pbn_sunix_pci_2s,
2850 pbn_sunix_pci_4s,
2851 pbn_sunix_pci_8s,
2852 pbn_sunix_pci_16s,
2853 pbn_titan_1_4000000,
2854 pbn_titan_2_4000000,
2855 pbn_titan_4_4000000,
2856 pbn_titan_8_4000000,
2857 pbn_moxa8250_2p,
2858 pbn_moxa8250_4p,
2859 pbn_moxa8250_8p,
2860 };
2861
2862 /*
2863 * uart_offset - the space between channels
2864 * reg_shift - describes how the UART registers are mapped
2865 * to PCI memory by the card.
2866 * For example IER register on SBS, Inc. PMC-OctPro is located at
2867 * offset 0x10 from the UART base, while UART_IER is defined as 1
2868 * in include/linux/serial_reg.h,
2869 * see first lines of serial_in() and serial_out() in 8250.c
2870 */
2871
2872 static struct pciserial_board pci_boards[] = {
2873 [pbn_default] = {
2874 .flags = FL_BASE0,
2875 .num_ports = 1,
2876 .base_baud = 115200,
2877 .uart_offset = 8,
2878 },
2879 [pbn_b0_1_115200] = {
2880 .flags = FL_BASE0,
2881 .num_ports = 1,
2882 .base_baud = 115200,
2883 .uart_offset = 8,
2884 },
2885 [pbn_b0_2_115200] = {
2886 .flags = FL_BASE0,
2887 .num_ports = 2,
2888 .base_baud = 115200,
2889 .uart_offset = 8,
2890 },
2891 [pbn_b0_4_115200] = {
2892 .flags = FL_BASE0,
2893 .num_ports = 4,
2894 .base_baud = 115200,
2895 .uart_offset = 8,
2896 },
2897 [pbn_b0_5_115200] = {
2898 .flags = FL_BASE0,
2899 .num_ports = 5,
2900 .base_baud = 115200,
2901 .uart_offset = 8,
2902 },
2903 [pbn_b0_8_115200] = {
2904 .flags = FL_BASE0,
2905 .num_ports = 8,
2906 .base_baud = 115200,
2907 .uart_offset = 8,
2908 },
2909 [pbn_b0_1_921600] = {
2910 .flags = FL_BASE0,
2911 .num_ports = 1,
2912 .base_baud = 921600,
2913 .uart_offset = 8,
2914 },
2915 [pbn_b0_2_921600] = {
2916 .flags = FL_BASE0,
2917 .num_ports = 2,
2918 .base_baud = 921600,
2919 .uart_offset = 8,
2920 },
2921 [pbn_b0_4_921600] = {
2922 .flags = FL_BASE0,
2923 .num_ports = 4,
2924 .base_baud = 921600,
2925 .uart_offset = 8,
2926 },
2927
2928 [pbn_b0_2_1130000] = {
2929 .flags = FL_BASE0,
2930 .num_ports = 2,
2931 .base_baud = 1130000,
2932 .uart_offset = 8,
2933 },
2934
2935 [pbn_b0_4_1152000] = {
2936 .flags = FL_BASE0,
2937 .num_ports = 4,
2938 .base_baud = 1152000,
2939 .uart_offset = 8,
2940 },
2941
2942 [pbn_b0_4_1250000] = {
2943 .flags = FL_BASE0,
2944 .num_ports = 4,
2945 .base_baud = 1250000,
2946 .uart_offset = 8,
2947 },
2948
2949 [pbn_b0_2_1843200] = {
2950 .flags = FL_BASE0,
2951 .num_ports = 2,
2952 .base_baud = 1843200,
2953 .uart_offset = 8,
2954 },
2955 [pbn_b0_4_1843200] = {
2956 .flags = FL_BASE0,
2957 .num_ports = 4,
2958 .base_baud = 1843200,
2959 .uart_offset = 8,
2960 },
2961
2962 [pbn_b0_1_15625000] = {
2963 .flags = FL_BASE0,
2964 .num_ports = 1,
2965 .base_baud = 15625000,
2966 .uart_offset = 8,
2967 },
2968
2969 [pbn_b0_bt_1_115200] = {
2970 .flags = FL_BASE0|FL_BASE_BARS,
2971 .num_ports = 1,
2972 .base_baud = 115200,
2973 .uart_offset = 8,
2974 },
2975 [pbn_b0_bt_2_115200] = {
2976 .flags = FL_BASE0|FL_BASE_BARS,
2977 .num_ports = 2,
2978 .base_baud = 115200,
2979 .uart_offset = 8,
2980 },
2981 [pbn_b0_bt_4_115200] = {
2982 .flags = FL_BASE0|FL_BASE_BARS,
2983 .num_ports = 4,
2984 .base_baud = 115200,
2985 .uart_offset = 8,
2986 },
2987 [pbn_b0_bt_8_115200] = {
2988 .flags = FL_BASE0|FL_BASE_BARS,
2989 .num_ports = 8,
2990 .base_baud = 115200,
2991 .uart_offset = 8,
2992 },
2993
2994 [pbn_b0_bt_1_460800] = {
2995 .flags = FL_BASE0|FL_BASE_BARS,
2996 .num_ports = 1,
2997 .base_baud = 460800,
2998 .uart_offset = 8,
2999 },
3000 [pbn_b0_bt_2_460800] = {
3001 .flags = FL_BASE0|FL_BASE_BARS,
3002 .num_ports = 2,
3003 .base_baud = 460800,
3004 .uart_offset = 8,
3005 },
3006 [pbn_b0_bt_4_460800] = {
3007 .flags = FL_BASE0|FL_BASE_BARS,
3008 .num_ports = 4,
3009 .base_baud = 460800,
3010 .uart_offset = 8,
3011 },
3012
3013 [pbn_b0_bt_1_921600] = {
3014 .flags = FL_BASE0|FL_BASE_BARS,
3015 .num_ports = 1,
3016 .base_baud = 921600,
3017 .uart_offset = 8,
3018 },
3019 [pbn_b0_bt_2_921600] = {
3020 .flags = FL_BASE0|FL_BASE_BARS,
3021 .num_ports = 2,
3022 .base_baud = 921600,
3023 .uart_offset = 8,
3024 },
3025 [pbn_b0_bt_4_921600] = {
3026 .flags = FL_BASE0|FL_BASE_BARS,
3027 .num_ports = 4,
3028 .base_baud = 921600,
3029 .uart_offset = 8,
3030 },
3031 [pbn_b0_bt_8_921600] = {
3032 .flags = FL_BASE0|FL_BASE_BARS,
3033 .num_ports = 8,
3034 .base_baud = 921600,
3035 .uart_offset = 8,
3036 },
3037
3038 [pbn_b1_1_115200] = {
3039 .flags = FL_BASE1,
3040 .num_ports = 1,
3041 .base_baud = 115200,
3042 .uart_offset = 8,
3043 },
3044 [pbn_b1_2_115200] = {
3045 .flags = FL_BASE1,
3046 .num_ports = 2,
3047 .base_baud = 115200,
3048 .uart_offset = 8,
3049 },
3050 [pbn_b1_4_115200] = {
3051 .flags = FL_BASE1,
3052 .num_ports = 4,
3053 .base_baud = 115200,
3054 .uart_offset = 8,
3055 },
3056 [pbn_b1_8_115200] = {
3057 .flags = FL_BASE1,
3058 .num_ports = 8,
3059 .base_baud = 115200,
3060 .uart_offset = 8,
3061 },
3062 [pbn_b1_16_115200] = {
3063 .flags = FL_BASE1,
3064 .num_ports = 16,
3065 .base_baud = 115200,
3066 .uart_offset = 8,
3067 },
3068
3069 [pbn_b1_1_921600] = {
3070 .flags = FL_BASE1,
3071 .num_ports = 1,
3072 .base_baud = 921600,
3073 .uart_offset = 8,
3074 },
3075 [pbn_b1_2_921600] = {
3076 .flags = FL_BASE1,
3077 .num_ports = 2,
3078 .base_baud = 921600,
3079 .uart_offset = 8,
3080 },
3081 [pbn_b1_4_921600] = {
3082 .flags = FL_BASE1,
3083 .num_ports = 4,
3084 .base_baud = 921600,
3085 .uart_offset = 8,
3086 },
3087 [pbn_b1_8_921600] = {
3088 .flags = FL_BASE1,
3089 .num_ports = 8,
3090 .base_baud = 921600,
3091 .uart_offset = 8,
3092 },
3093 [pbn_b1_2_1250000] = {
3094 .flags = FL_BASE1,
3095 .num_ports = 2,
3096 .base_baud = 1250000,
3097 .uart_offset = 8,
3098 },
3099
3100 [pbn_b1_bt_1_115200] = {
3101 .flags = FL_BASE1|FL_BASE_BARS,
3102 .num_ports = 1,
3103 .base_baud = 115200,
3104 .uart_offset = 8,
3105 },
3106 [pbn_b1_bt_2_115200] = {
3107 .flags = FL_BASE1|FL_BASE_BARS,
3108 .num_ports = 2,
3109 .base_baud = 115200,
3110 .uart_offset = 8,
3111 },
3112 [pbn_b1_bt_4_115200] = {
3113 .flags = FL_BASE1|FL_BASE_BARS,
3114 .num_ports = 4,
3115 .base_baud = 115200,
3116 .uart_offset = 8,
3117 },
3118
3119 [pbn_b1_bt_2_921600] = {
3120 .flags = FL_BASE1|FL_BASE_BARS,
3121 .num_ports = 2,
3122 .base_baud = 921600,
3123 .uart_offset = 8,
3124 },
3125
3126 [pbn_b1_1_1382400] = {
3127 .flags = FL_BASE1,
3128 .num_ports = 1,
3129 .base_baud = 1382400,
3130 .uart_offset = 8,
3131 },
3132 [pbn_b1_2_1382400] = {
3133 .flags = FL_BASE1,
3134 .num_ports = 2,
3135 .base_baud = 1382400,
3136 .uart_offset = 8,
3137 },
3138 [pbn_b1_4_1382400] = {
3139 .flags = FL_BASE1,
3140 .num_ports = 4,
3141 .base_baud = 1382400,
3142 .uart_offset = 8,
3143 },
3144 [pbn_b1_8_1382400] = {
3145 .flags = FL_BASE1,
3146 .num_ports = 8,
3147 .base_baud = 1382400,
3148 .uart_offset = 8,
3149 },
3150
3151 [pbn_b2_1_115200] = {
3152 .flags = FL_BASE2,
3153 .num_ports = 1,
3154 .base_baud = 115200,
3155 .uart_offset = 8,
3156 },
3157 [pbn_b2_2_115200] = {
3158 .flags = FL_BASE2,
3159 .num_ports = 2,
3160 .base_baud = 115200,
3161 .uart_offset = 8,
3162 },
3163 [pbn_b2_4_115200] = {
3164 .flags = FL_BASE2,
3165 .num_ports = 4,
3166 .base_baud = 115200,
3167 .uart_offset = 8,
3168 },
3169 [pbn_b2_8_115200] = {
3170 .flags = FL_BASE2,
3171 .num_ports = 8,
3172 .base_baud = 115200,
3173 .uart_offset = 8,
3174 },
3175
3176 [pbn_b2_1_460800] = {
3177 .flags = FL_BASE2,
3178 .num_ports = 1,
3179 .base_baud = 460800,
3180 .uart_offset = 8,
3181 },
3182 [pbn_b2_4_460800] = {
3183 .flags = FL_BASE2,
3184 .num_ports = 4,
3185 .base_baud = 460800,
3186 .uart_offset = 8,
3187 },
3188 [pbn_b2_8_460800] = {
3189 .flags = FL_BASE2,
3190 .num_ports = 8,
3191 .base_baud = 460800,
3192 .uart_offset = 8,
3193 },
3194 [pbn_b2_16_460800] = {
3195 .flags = FL_BASE2,
3196 .num_ports = 16,
3197 .base_baud = 460800,
3198 .uart_offset = 8,
3199 },
3200
3201 [pbn_b2_1_921600] = {
3202 .flags = FL_BASE2,
3203 .num_ports = 1,
3204 .base_baud = 921600,
3205 .uart_offset = 8,
3206 },
3207 [pbn_b2_4_921600] = {
3208 .flags = FL_BASE2,
3209 .num_ports = 4,
3210 .base_baud = 921600,
3211 .uart_offset = 8,
3212 },
3213 [pbn_b2_8_921600] = {
3214 .flags = FL_BASE2,
3215 .num_ports = 8,
3216 .base_baud = 921600,
3217 .uart_offset = 8,
3218 },
3219
3220 [pbn_b2_8_1152000] = {
3221 .flags = FL_BASE2,
3222 .num_ports = 8,
3223 .base_baud = 1152000,
3224 .uart_offset = 8,
3225 },
3226
3227 [pbn_b2_bt_1_115200] = {
3228 .flags = FL_BASE2|FL_BASE_BARS,
3229 .num_ports = 1,
3230 .base_baud = 115200,
3231 .uart_offset = 8,
3232 },
3233 [pbn_b2_bt_2_115200] = {
3234 .flags = FL_BASE2|FL_BASE_BARS,
3235 .num_ports = 2,
3236 .base_baud = 115200,
3237 .uart_offset = 8,
3238 },
3239 [pbn_b2_bt_4_115200] = {
3240 .flags = FL_BASE2|FL_BASE_BARS,
3241 .num_ports = 4,
3242 .base_baud = 115200,
3243 .uart_offset = 8,
3244 },
3245
3246 [pbn_b2_bt_2_921600] = {
3247 .flags = FL_BASE2|FL_BASE_BARS,
3248 .num_ports = 2,
3249 .base_baud = 921600,
3250 .uart_offset = 8,
3251 },
3252 [pbn_b2_bt_4_921600] = {
3253 .flags = FL_BASE2|FL_BASE_BARS,
3254 .num_ports = 4,
3255 .base_baud = 921600,
3256 .uart_offset = 8,
3257 },
3258
3259 [pbn_b3_2_115200] = {
3260 .flags = FL_BASE3,
3261 .num_ports = 2,
3262 .base_baud = 115200,
3263 .uart_offset = 8,
3264 },
3265 [pbn_b3_4_115200] = {
3266 .flags = FL_BASE3,
3267 .num_ports = 4,
3268 .base_baud = 115200,
3269 .uart_offset = 8,
3270 },
3271 [pbn_b3_8_115200] = {
3272 .flags = FL_BASE3,
3273 .num_ports = 8,
3274 .base_baud = 115200,
3275 .uart_offset = 8,
3276 },
3277
3278 [pbn_b4_bt_2_921600] = {
3279 .flags = FL_BASE4,
3280 .num_ports = 2,
3281 .base_baud = 921600,
3282 .uart_offset = 8,
3283 },
3284 [pbn_b4_bt_4_921600] = {
3285 .flags = FL_BASE4,
3286 .num_ports = 4,
3287 .base_baud = 921600,
3288 .uart_offset = 8,
3289 },
3290 [pbn_b4_bt_8_921600] = {
3291 .flags = FL_BASE4,
3292 .num_ports = 8,
3293 .base_baud = 921600,
3294 .uart_offset = 8,
3295 },
3296
3297 /*
3298 * Entries following this are board-specific.
3299 */
3300
3301 /*
3302 * Panacom - IOMEM
3303 */
3304 [pbn_panacom] = {
3305 .flags = FL_BASE2,
3306 .num_ports = 2,
3307 .base_baud = 921600,
3308 .uart_offset = 0x400,
3309 .reg_shift = 7,
3310 },
3311 [pbn_panacom2] = {
3312 .flags = FL_BASE2|FL_BASE_BARS,
3313 .num_ports = 2,
3314 .base_baud = 921600,
3315 .uart_offset = 0x400,
3316 .reg_shift = 7,
3317 },
3318 [pbn_panacom4] = {
3319 .flags = FL_BASE2|FL_BASE_BARS,
3320 .num_ports = 4,
3321 .base_baud = 921600,
3322 .uart_offset = 0x400,
3323 .reg_shift = 7,
3324 },
3325
3326 /* I think this entry is broken - the first_offset looks wrong --rmk */
3327 [pbn_plx_romulus] = {
3328 .flags = FL_BASE2,
3329 .num_ports = 4,
3330 .base_baud = 921600,
3331 .uart_offset = 8 << 2,
3332 .reg_shift = 2,
3333 .first_offset = 0x03,
3334 },
3335
3336 /*
3337 * This board uses the size of PCI Base region 0 to
3338 * signal now many ports are available
3339 */
3340 [pbn_oxsemi] = {
3341 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3342 .num_ports = 32,
3343 .base_baud = 115200,
3344 .uart_offset = 8,
3345 },
3346 [pbn_oxsemi_1_15625000] = {
3347 .flags = FL_BASE0,
3348 .num_ports = 1,
3349 .base_baud = 15625000,
3350 .uart_offset = 0x200,
3351 .first_offset = 0x1000,
3352 },
3353 [pbn_oxsemi_2_15625000] = {
3354 .flags = FL_BASE0,
3355 .num_ports = 2,
3356 .base_baud = 15625000,
3357 .uart_offset = 0x200,
3358 .first_offset = 0x1000,
3359 },
3360 [pbn_oxsemi_4_15625000] = {
3361 .flags = FL_BASE0,
3362 .num_ports = 4,
3363 .base_baud = 15625000,
3364 .uart_offset = 0x200,
3365 .first_offset = 0x1000,
3366 },
3367 [pbn_oxsemi_8_15625000] = {
3368 .flags = FL_BASE0,
3369 .num_ports = 8,
3370 .base_baud = 15625000,
3371 .uart_offset = 0x200,
3372 .first_offset = 0x1000,
3373 },
3374
3375
3376 /*
3377 * EKF addition for i960 Boards form EKF with serial port.
3378 * Max 256 ports.
3379 */
3380 [pbn_intel_i960] = {
3381 .flags = FL_BASE0,
3382 .num_ports = 32,
3383 .base_baud = 921600,
3384 .uart_offset = 8 << 2,
3385 .reg_shift = 2,
3386 .first_offset = 0x10000,
3387 },
3388 [pbn_sgi_ioc3] = {
3389 .flags = FL_BASE0|FL_NOIRQ,
3390 .num_ports = 1,
3391 .base_baud = 458333,
3392 .uart_offset = 8,
3393 .reg_shift = 0,
3394 .first_offset = 0x20178,
3395 },
3396
3397 /*
3398 * Computone - uses IOMEM.
3399 */
3400 [pbn_computone_4] = {
3401 .flags = FL_BASE0,
3402 .num_ports = 4,
3403 .base_baud = 921600,
3404 .uart_offset = 0x40,
3405 .reg_shift = 2,
3406 .first_offset = 0x200,
3407 },
3408 [pbn_computone_6] = {
3409 .flags = FL_BASE0,
3410 .num_ports = 6,
3411 .base_baud = 921600,
3412 .uart_offset = 0x40,
3413 .reg_shift = 2,
3414 .first_offset = 0x200,
3415 },
3416 [pbn_computone_8] = {
3417 .flags = FL_BASE0,
3418 .num_ports = 8,
3419 .base_baud = 921600,
3420 .uart_offset = 0x40,
3421 .reg_shift = 2,
3422 .first_offset = 0x200,
3423 },
3424 [pbn_sbsxrsio] = {
3425 .flags = FL_BASE0,
3426 .num_ports = 8,
3427 .base_baud = 460800,
3428 .uart_offset = 256,
3429 .reg_shift = 4,
3430 },
3431 /*
3432 * PA Semi PWRficient PA6T-1682M on-chip UART
3433 */
3434 [pbn_pasemi_1682M] = {
3435 .flags = FL_BASE0,
3436 .num_ports = 1,
3437 .base_baud = 8333333,
3438 },
3439 /*
3440 * National Instruments 843x
3441 */
3442 [pbn_ni8430_16] = {
3443 .flags = FL_BASE0,
3444 .num_ports = 16,
3445 .base_baud = 3686400,
3446 .uart_offset = 0x10,
3447 .first_offset = 0x800,
3448 },
3449 [pbn_ni8430_8] = {
3450 .flags = FL_BASE0,
3451 .num_ports = 8,
3452 .base_baud = 3686400,
3453 .uart_offset = 0x10,
3454 .first_offset = 0x800,
3455 },
3456 [pbn_ni8430_4] = {
3457 .flags = FL_BASE0,
3458 .num_ports = 4,
3459 .base_baud = 3686400,
3460 .uart_offset = 0x10,
3461 .first_offset = 0x800,
3462 },
3463 [pbn_ni8430_2] = {
3464 .flags = FL_BASE0,
3465 .num_ports = 2,
3466 .base_baud = 3686400,
3467 .uart_offset = 0x10,
3468 .first_offset = 0x800,
3469 },
3470 /*
3471 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3472 */
3473 [pbn_ADDIDATA_PCIe_1_3906250] = {
3474 .flags = FL_BASE0,
3475 .num_ports = 1,
3476 .base_baud = 3906250,
3477 .uart_offset = 0x200,
3478 .first_offset = 0x1000,
3479 },
3480 [pbn_ADDIDATA_PCIe_2_3906250] = {
3481 .flags = FL_BASE0,
3482 .num_ports = 2,
3483 .base_baud = 3906250,
3484 .uart_offset = 0x200,
3485 .first_offset = 0x1000,
3486 },
3487 [pbn_ADDIDATA_PCIe_4_3906250] = {
3488 .flags = FL_BASE0,
3489 .num_ports = 4,
3490 .base_baud = 3906250,
3491 .uart_offset = 0x200,
3492 .first_offset = 0x1000,
3493 },
3494 [pbn_ADDIDATA_PCIe_8_3906250] = {
3495 .flags = FL_BASE0,
3496 .num_ports = 8,
3497 .base_baud = 3906250,
3498 .uart_offset = 0x200,
3499 .first_offset = 0x1000,
3500 },
3501 [pbn_ce4100_1_115200] = {
3502 .flags = FL_BASE_BARS,
3503 .num_ports = 2,
3504 .base_baud = 921600,
3505 .reg_shift = 2,
3506 },
3507 [pbn_omegapci] = {
3508 .flags = FL_BASE0,
3509 .num_ports = 8,
3510 .base_baud = 115200,
3511 .uart_offset = 0x200,
3512 },
3513 [pbn_NETMOS9900_2s_115200] = {
3514 .flags = FL_BASE0,
3515 .num_ports = 2,
3516 .base_baud = 115200,
3517 },
3518 [pbn_brcm_trumanage] = {
3519 .flags = FL_BASE0,
3520 .num_ports = 1,
3521 .reg_shift = 2,
3522 .base_baud = 115200,
3523 },
3524 [pbn_fintek_4] = {
3525 .num_ports = 4,
3526 .uart_offset = 8,
3527 .base_baud = 115200,
3528 .first_offset = 0x40,
3529 },
3530 [pbn_fintek_8] = {
3531 .num_ports = 8,
3532 .uart_offset = 8,
3533 .base_baud = 115200,
3534 .first_offset = 0x40,
3535 },
3536 [pbn_fintek_12] = {
3537 .num_ports = 12,
3538 .uart_offset = 8,
3539 .base_baud = 115200,
3540 .first_offset = 0x40,
3541 },
3542 [pbn_fintek_F81504A] = {
3543 .num_ports = 4,
3544 .uart_offset = 8,
3545 .base_baud = 115200,
3546 },
3547 [pbn_fintek_F81508A] = {
3548 .num_ports = 8,
3549 .uart_offset = 8,
3550 .base_baud = 115200,
3551 },
3552 [pbn_fintek_F81512A] = {
3553 .num_ports = 12,
3554 .uart_offset = 8,
3555 .base_baud = 115200,
3556 },
3557 [pbn_wch382_2] = {
3558 .flags = FL_BASE0,
3559 .num_ports = 2,
3560 .base_baud = 115200,
3561 .uart_offset = 8,
3562 .first_offset = 0xC0,
3563 },
3564 [pbn_wch384_4] = {
3565 .flags = FL_BASE0,
3566 .num_ports = 4,
3567 .base_baud = 115200,
3568 .uart_offset = 8,
3569 .first_offset = 0xC0,
3570 },
3571 [pbn_wch384_8] = {
3572 .flags = FL_BASE0,
3573 .num_ports = 8,
3574 .base_baud = 115200,
3575 .uart_offset = 8,
3576 .first_offset = 0x00,
3577 },
3578 [pbn_sunix_pci_1s] = {
3579 .num_ports = 1,
3580 .base_baud = 921600,
3581 .uart_offset = 0x8,
3582 },
3583 [pbn_sunix_pci_2s] = {
3584 .num_ports = 2,
3585 .base_baud = 921600,
3586 .uart_offset = 0x8,
3587 },
3588 [pbn_sunix_pci_4s] = {
3589 .num_ports = 4,
3590 .base_baud = 921600,
3591 .uart_offset = 0x8,
3592 },
3593 [pbn_sunix_pci_8s] = {
3594 .num_ports = 8,
3595 .base_baud = 921600,
3596 .uart_offset = 0x8,
3597 },
3598 [pbn_sunix_pci_16s] = {
3599 .num_ports = 16,
3600 .base_baud = 921600,
3601 .uart_offset = 0x8,
3602 },
3603 [pbn_titan_1_4000000] = {
3604 .flags = FL_BASE0,
3605 .num_ports = 1,
3606 .base_baud = 4000000,
3607 .uart_offset = 0x200,
3608 .first_offset = 0x1000,
3609 },
3610 [pbn_titan_2_4000000] = {
3611 .flags = FL_BASE0,
3612 .num_ports = 2,
3613 .base_baud = 4000000,
3614 .uart_offset = 0x200,
3615 .first_offset = 0x1000,
3616 },
3617 [pbn_titan_4_4000000] = {
3618 .flags = FL_BASE0,
3619 .num_ports = 4,
3620 .base_baud = 4000000,
3621 .uart_offset = 0x200,
3622 .first_offset = 0x1000,
3623 },
3624 [pbn_titan_8_4000000] = {
3625 .flags = FL_BASE0,
3626 .num_ports = 8,
3627 .base_baud = 4000000,
3628 .uart_offset = 0x200,
3629 .first_offset = 0x1000,
3630 },
3631 [pbn_moxa8250_2p] = {
3632 .flags = FL_BASE1,
3633 .num_ports = 2,
3634 .base_baud = 921600,
3635 .uart_offset = 0x200,
3636 },
3637 [pbn_moxa8250_4p] = {
3638 .flags = FL_BASE1,
3639 .num_ports = 4,
3640 .base_baud = 921600,
3641 .uart_offset = 0x200,
3642 },
3643 [pbn_moxa8250_8p] = {
3644 .flags = FL_BASE1,
3645 .num_ports = 8,
3646 .base_baud = 921600,
3647 .uart_offset = 0x200,
3648 },
3649 };
3650
3651 #define REPORT_CONFIG(option) \
3652 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option)
3653 #define REPORT_8250_CONFIG(option) \
3654 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \
3655 0 : (kernel_ulong_t)&"SERIAL_8250_"#option)
3656
3657 static const struct pci_device_id blacklist[] = {
3658 /* softmodems */
3659 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3660 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3661 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3662
3663 /* multi-io cards handled by parport_serial */
3664 /* WCH CH353 2S1P */
3665 { PCI_DEVICE(0x4348, 0x7053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
3666 /* WCH CH353 1S1P */
3667 { PCI_DEVICE(0x4348, 0x5053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
3668 /* WCH CH382 2S1P */
3669 { PCI_DEVICE(0x1c00, 0x3250), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
3670
3671 /* Intel platforms with MID UART */
3672 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), },
3673 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), },
3674 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), },
3675 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), },
3676 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), },
3677 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), },
3678
3679 /* Intel platforms with DesignWare UART */
3680 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), },
3681 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), },
3682 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), },
3683 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), },
3684 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), },
3685 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), },
3686 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), },
3687 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), },
3688 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), },
3689 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), },
3690 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), },
3691 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), },
3692 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), },
3693
3694 /* Exar devices */
3695 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
3696 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
3697
3698 /* Pericom devices */
3699 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
3700 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
3701
3702 /* End of the black list */
3703 { }
3704 };
3705
serial_pci_is_class_communication(struct pci_dev * dev)3706 static int serial_pci_is_class_communication(struct pci_dev *dev)
3707 {
3708 /*
3709 * If it is not a communications device or the programming
3710 * interface is greater than 6, give up.
3711 */
3712 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3713 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3714 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3715 (dev->class & 0xff) > 6)
3716 return -ENODEV;
3717
3718 return 0;
3719 }
3720
3721 /*
3722 * Given a complete unknown PCI device, try to use some heuristics to
3723 * guess what the configuration might be, based on the pitiful PCI
3724 * serial specs. Returns 0 on success, -ENODEV on failure.
3725 */
3726 static int
serial_pci_guess_board(struct pci_dev * dev,struct pciserial_board * board)3727 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3728 {
3729 int num_iomem, num_port, first_port = -1, i;
3730 int rc;
3731
3732 rc = serial_pci_is_class_communication(dev);
3733 if (rc)
3734 return rc;
3735
3736 /*
3737 * Should we try to make guesses for multiport serial devices later?
3738 */
3739 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
3740 return -ENODEV;
3741
3742 num_iomem = num_port = 0;
3743 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3744 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3745 num_port++;
3746 if (first_port == -1)
3747 first_port = i;
3748 }
3749 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3750 num_iomem++;
3751 }
3752
3753 /*
3754 * If there is 1 or 0 iomem regions, and exactly one port,
3755 * use it. We guess the number of ports based on the IO
3756 * region size.
3757 */
3758 if (num_iomem <= 1 && num_port == 1) {
3759 board->flags = first_port;
3760 board->num_ports = pci_resource_len(dev, first_port) / 8;
3761 return 0;
3762 }
3763
3764 /*
3765 * Now guess if we've got a board which indexes by BARs.
3766 * Each IO BAR should be 8 bytes, and they should follow
3767 * consecutively.
3768 */
3769 first_port = -1;
3770 num_port = 0;
3771 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3772 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3773 pci_resource_len(dev, i) == 8 &&
3774 (first_port == -1 || (first_port + num_port) == i)) {
3775 num_port++;
3776 if (first_port == -1)
3777 first_port = i;
3778 }
3779 }
3780
3781 if (num_port > 1) {
3782 board->flags = first_port | FL_BASE_BARS;
3783 board->num_ports = num_port;
3784 return 0;
3785 }
3786
3787 return -ENODEV;
3788 }
3789
3790 static inline int
serial_pci_matches(const struct pciserial_board * board,const struct pciserial_board * guessed)3791 serial_pci_matches(const struct pciserial_board *board,
3792 const struct pciserial_board *guessed)
3793 {
3794 return
3795 board->num_ports == guessed->num_ports &&
3796 board->base_baud == guessed->base_baud &&
3797 board->uart_offset == guessed->uart_offset &&
3798 board->reg_shift == guessed->reg_shift &&
3799 board->first_offset == guessed->first_offset;
3800 }
3801
3802 struct serial_private *
pciserial_init_ports(struct pci_dev * dev,const struct pciserial_board * board)3803 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3804 {
3805 struct uart_8250_port uart;
3806 struct serial_private *priv;
3807 struct pci_serial_quirk *quirk;
3808 int rc, nr_ports, i;
3809
3810 nr_ports = board->num_ports;
3811
3812 /*
3813 * Find an init and setup quirks.
3814 */
3815 quirk = find_quirk(dev);
3816
3817 /*
3818 * Run the new-style initialization function.
3819 * The initialization function returns:
3820 * <0 - error
3821 * 0 - use board->num_ports
3822 * >0 - number of ports
3823 */
3824 if (quirk->init) {
3825 rc = quirk->init(dev);
3826 if (rc < 0) {
3827 priv = ERR_PTR(rc);
3828 goto err_out;
3829 }
3830 if (rc)
3831 nr_ports = rc;
3832 }
3833
3834 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL);
3835 if (!priv) {
3836 priv = ERR_PTR(-ENOMEM);
3837 goto err_deinit;
3838 }
3839
3840 priv->dev = dev;
3841 priv->quirk = quirk;
3842
3843 memset(&uart, 0, sizeof(uart));
3844 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3845 uart.port.uartclk = board->base_baud * 16;
3846
3847 if (board->flags & FL_NOIRQ) {
3848 uart.port.irq = 0;
3849 } else {
3850 if (pci_match_id(pci_use_msi, dev)) {
3851 pci_dbg(dev, "Using MSI(-X) interrupts\n");
3852 pci_set_master(dev);
3853 uart.port.flags &= ~UPF_SHARE_IRQ;
3854 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
3855 } else {
3856 pci_dbg(dev, "Using legacy interrupts\n");
3857 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY);
3858 }
3859 if (rc < 0) {
3860 kfree(priv);
3861 priv = ERR_PTR(rc);
3862 goto err_deinit;
3863 }
3864
3865 uart.port.irq = pci_irq_vector(dev, 0);
3866 }
3867
3868 uart.port.dev = &dev->dev;
3869
3870 for (i = 0; i < nr_ports; i++) {
3871 if (quirk->setup(priv, board, &uart, i))
3872 break;
3873
3874 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3875 uart.port.iobase, uart.port.irq, uart.port.iotype);
3876
3877 priv->line[i] = serial8250_register_8250_port(&uart);
3878 if (priv->line[i] < 0) {
3879 pci_err(dev,
3880 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3881 uart.port.iobase, uart.port.irq,
3882 uart.port.iotype, priv->line[i]);
3883 break;
3884 }
3885 }
3886 priv->nr = i;
3887 priv->board = board;
3888 return priv;
3889
3890 err_deinit:
3891 if (quirk->exit)
3892 quirk->exit(dev);
3893 err_out:
3894 return priv;
3895 }
3896 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3897
pciserial_detach_ports(struct serial_private * priv)3898 static void pciserial_detach_ports(struct serial_private *priv)
3899 {
3900 struct pci_serial_quirk *quirk;
3901 int i;
3902
3903 for (i = 0; i < priv->nr; i++)
3904 serial8250_unregister_port(priv->line[i]);
3905
3906 /*
3907 * Find the exit quirks.
3908 */
3909 quirk = find_quirk(priv->dev);
3910 if (quirk->exit)
3911 quirk->exit(priv->dev);
3912 }
3913
pciserial_remove_ports(struct serial_private * priv)3914 void pciserial_remove_ports(struct serial_private *priv)
3915 {
3916 pciserial_detach_ports(priv);
3917 kfree(priv);
3918 }
3919 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3920
pciserial_suspend_ports(struct serial_private * priv)3921 void pciserial_suspend_ports(struct serial_private *priv)
3922 {
3923 int i;
3924
3925 for (i = 0; i < priv->nr; i++)
3926 if (priv->line[i] >= 0)
3927 serial8250_suspend_port(priv->line[i]);
3928
3929 /*
3930 * Ensure that every init quirk is properly torn down
3931 */
3932 if (priv->quirk->exit)
3933 priv->quirk->exit(priv->dev);
3934 }
3935 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3936
pciserial_resume_ports(struct serial_private * priv)3937 void pciserial_resume_ports(struct serial_private *priv)
3938 {
3939 int i;
3940
3941 /*
3942 * Ensure that the board is correctly configured.
3943 */
3944 if (priv->quirk->init)
3945 priv->quirk->init(priv->dev);
3946
3947 for (i = 0; i < priv->nr; i++)
3948 if (priv->line[i] >= 0)
3949 serial8250_resume_port(priv->line[i]);
3950 }
3951 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3952
3953 /*
3954 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3955 * to the arrangement of serial ports on a PCI card.
3956 */
3957 static int
pciserial_init_one(struct pci_dev * dev,const struct pci_device_id * ent)3958 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3959 {
3960 struct pci_serial_quirk *quirk;
3961 struct serial_private *priv;
3962 const struct pciserial_board *board;
3963 const struct pci_device_id *exclude;
3964 struct pciserial_board tmp;
3965 int rc;
3966
3967 quirk = find_quirk(dev);
3968 if (quirk->probe) {
3969 rc = quirk->probe(dev);
3970 if (rc)
3971 return rc;
3972 }
3973
3974 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3975 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data);
3976 return -EINVAL;
3977 }
3978
3979 board = &pci_boards[ent->driver_data];
3980
3981 exclude = pci_match_id(blacklist, dev);
3982 if (exclude) {
3983 if (exclude->driver_data)
3984 pci_warn(dev, "ignoring port, enable %s to handle\n",
3985 (const char *)exclude->driver_data);
3986 return -ENODEV;
3987 }
3988
3989 rc = pcim_enable_device(dev);
3990 pci_save_state(dev);
3991 if (rc)
3992 return rc;
3993
3994 if (ent->driver_data == pbn_default) {
3995 /*
3996 * Use a copy of the pci_board entry for this;
3997 * avoid changing entries in the table.
3998 */
3999 memcpy(&tmp, board, sizeof(struct pciserial_board));
4000 board = &tmp;
4001
4002 /*
4003 * We matched one of our class entries. Try to
4004 * determine the parameters of this board.
4005 */
4006 rc = serial_pci_guess_board(dev, &tmp);
4007 if (rc)
4008 return rc;
4009 } else {
4010 /*
4011 * We matched an explicit entry. If we are able to
4012 * detect this boards settings with our heuristic,
4013 * then we no longer need this entry.
4014 */
4015 memcpy(&tmp, &pci_boards[pbn_default],
4016 sizeof(struct pciserial_board));
4017 rc = serial_pci_guess_board(dev, &tmp);
4018 if (rc == 0 && serial_pci_matches(board, &tmp))
4019 moan_device("Redundant entry in serial pci_table.",
4020 dev);
4021 }
4022
4023 priv = pciserial_init_ports(dev, board);
4024 if (IS_ERR(priv))
4025 return PTR_ERR(priv);
4026
4027 pci_set_drvdata(dev, priv);
4028 return 0;
4029 }
4030
pciserial_remove_one(struct pci_dev * dev)4031 static void pciserial_remove_one(struct pci_dev *dev)
4032 {
4033 struct serial_private *priv = pci_get_drvdata(dev);
4034
4035 pciserial_remove_ports(priv);
4036 }
4037
4038 #ifdef CONFIG_PM_SLEEP
pciserial_suspend_one(struct device * dev)4039 static int pciserial_suspend_one(struct device *dev)
4040 {
4041 struct serial_private *priv = dev_get_drvdata(dev);
4042
4043 if (priv)
4044 pciserial_suspend_ports(priv);
4045
4046 return 0;
4047 }
4048
pciserial_resume_one(struct device * dev)4049 static int pciserial_resume_one(struct device *dev)
4050 {
4051 struct pci_dev *pdev = to_pci_dev(dev);
4052 struct serial_private *priv = pci_get_drvdata(pdev);
4053 int err;
4054
4055 if (priv) {
4056 /*
4057 * The device may have been disabled. Re-enable it.
4058 */
4059 err = pci_enable_device(pdev);
4060 /* FIXME: We cannot simply error out here */
4061 if (err)
4062 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n");
4063 pciserial_resume_ports(priv);
4064 }
4065 return 0;
4066 }
4067 #endif
4068
4069 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4070 pciserial_resume_one);
4071
4072 static const struct pci_device_id serial_pci_tbl[] = {
4073 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600,
4074 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0,
4075 pbn_b0_4_921600 },
4076 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4077 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4078 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4079 pbn_b2_8_921600 },
4080 /* Advantech also use 0x3618 and 0xf618 */
4081 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4082 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4083 pbn_b0_4_921600 },
4084 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4085 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4086 pbn_b0_4_921600 },
4087 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4088 PCI_SUBVENDOR_ID_CONNECT_TECH,
4089 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4090 pbn_b1_8_1382400 },
4091 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4092 PCI_SUBVENDOR_ID_CONNECT_TECH,
4093 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4094 pbn_b1_4_1382400 },
4095 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4096 PCI_SUBVENDOR_ID_CONNECT_TECH,
4097 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4098 pbn_b1_2_1382400 },
4099 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4100 PCI_SUBVENDOR_ID_CONNECT_TECH,
4101 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4102 pbn_b1_8_1382400 },
4103 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4104 PCI_SUBVENDOR_ID_CONNECT_TECH,
4105 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4106 pbn_b1_4_1382400 },
4107 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4108 PCI_SUBVENDOR_ID_CONNECT_TECH,
4109 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4110 pbn_b1_2_1382400 },
4111 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4112 PCI_SUBVENDOR_ID_CONNECT_TECH,
4113 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4114 pbn_b1_8_921600 },
4115 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4116 PCI_SUBVENDOR_ID_CONNECT_TECH,
4117 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4118 pbn_b1_8_921600 },
4119 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4120 PCI_SUBVENDOR_ID_CONNECT_TECH,
4121 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4122 pbn_b1_4_921600 },
4123 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4124 PCI_SUBVENDOR_ID_CONNECT_TECH,
4125 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4126 pbn_b1_4_921600 },
4127 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4128 PCI_SUBVENDOR_ID_CONNECT_TECH,
4129 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4130 pbn_b1_2_921600 },
4131 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4132 PCI_SUBVENDOR_ID_CONNECT_TECH,
4133 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4134 pbn_b1_8_921600 },
4135 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4136 PCI_SUBVENDOR_ID_CONNECT_TECH,
4137 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4138 pbn_b1_8_921600 },
4139 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4140 PCI_SUBVENDOR_ID_CONNECT_TECH,
4141 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4142 pbn_b1_4_921600 },
4143 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4144 PCI_SUBVENDOR_ID_CONNECT_TECH,
4145 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4146 pbn_b1_2_1250000 },
4147 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4148 PCI_SUBVENDOR_ID_CONNECT_TECH,
4149 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4150 pbn_b0_2_1843200 },
4151 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4152 PCI_SUBVENDOR_ID_CONNECT_TECH,
4153 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4154 pbn_b0_4_1843200 },
4155 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4156 PCI_VENDOR_ID_AFAVLAB,
4157 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4158 pbn_b0_4_1152000 },
4159 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4161 pbn_b2_bt_1_115200 },
4162 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4164 pbn_b2_bt_2_115200 },
4165 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4167 pbn_b2_bt_4_115200 },
4168 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4170 pbn_b2_bt_2_115200 },
4171 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4173 pbn_b2_bt_4_115200 },
4174 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4176 pbn_b2_8_115200 },
4177 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4178 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4179 pbn_b2_8_460800 },
4180 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4181 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4182 pbn_b2_8_115200 },
4183
4184 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4185 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4186 pbn_b2_bt_2_115200 },
4187 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4188 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4189 pbn_b2_bt_2_921600 },
4190 /*
4191 * VScom SPCOM800, from sl@s.pl
4192 */
4193 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4194 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4195 pbn_b2_8_921600 },
4196 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4197 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4198 pbn_b2_4_921600 },
4199 /* Unknown card - subdevice 0x1584 */
4200 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4201 PCI_VENDOR_ID_PLX,
4202 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4203 pbn_b2_4_115200 },
4204 /* Unknown card - subdevice 0x1588 */
4205 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4206 PCI_VENDOR_ID_PLX,
4207 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4208 pbn_b2_8_115200 },
4209 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4210 PCI_SUBVENDOR_ID_KEYSPAN,
4211 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4212 pbn_panacom },
4213 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4215 pbn_panacom4 },
4216 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4218 pbn_panacom2 },
4219 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4220 PCI_VENDOR_ID_ESDGMBH,
4221 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4222 pbn_b2_4_115200 },
4223 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4224 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4225 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4226 pbn_b2_4_460800 },
4227 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4228 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4229 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4230 pbn_b2_8_460800 },
4231 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4232 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4233 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4234 pbn_b2_16_460800 },
4235 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4236 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4237 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4238 pbn_b2_16_460800 },
4239 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4240 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4241 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4242 pbn_b2_4_460800 },
4243 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4244 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4245 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4246 pbn_b2_8_460800 },
4247 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4248 PCI_SUBVENDOR_ID_EXSYS,
4249 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4250 pbn_b2_4_115200 },
4251 /*
4252 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4253 * (Exoray@isys.ca)
4254 */
4255 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4256 0x10b5, 0x106a, 0, 0,
4257 pbn_plx_romulus },
4258 /*
4259 * Quatech cards. These actually have configurable clocks but for
4260 * now we just use the default.
4261 *
4262 * 100 series are RS232, 200 series RS422,
4263 */
4264 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4265 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4266 pbn_b1_4_115200 },
4267 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4268 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4269 pbn_b1_2_115200 },
4270 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4271 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4272 pbn_b2_2_115200 },
4273 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4274 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4275 pbn_b1_2_115200 },
4276 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4278 pbn_b2_2_115200 },
4279 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4281 pbn_b1_4_115200 },
4282 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4284 pbn_b1_8_115200 },
4285 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4287 pbn_b1_8_115200 },
4288 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4290 pbn_b1_4_115200 },
4291 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4292 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4293 pbn_b1_2_115200 },
4294 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4295 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4296 pbn_b1_4_115200 },
4297 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4298 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4299 pbn_b1_2_115200 },
4300 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4301 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4302 pbn_b2_4_115200 },
4303 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4304 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4305 pbn_b2_2_115200 },
4306 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4307 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4308 pbn_b2_1_115200 },
4309 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4310 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4311 pbn_b2_4_115200 },
4312 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4313 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4314 pbn_b2_2_115200 },
4315 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4316 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4317 pbn_b2_1_115200 },
4318 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4319 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4320 pbn_b0_8_115200 },
4321
4322 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4323 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4324 0, 0,
4325 pbn_b0_4_921600 },
4326 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4327 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4328 0, 0,
4329 pbn_b0_4_1152000 },
4330 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4332 pbn_b0_bt_2_921600 },
4333
4334 /*
4335 * The below card is a little controversial since it is the
4336 * subject of a PCI vendor/device ID clash. (See
4337 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4338 * For now just used the hex ID 0x950a.
4339 */
4340 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4341 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4342 0, 0, pbn_b0_2_115200 },
4343 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4344 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4345 0, 0, pbn_b0_2_115200 },
4346 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348 pbn_b0_2_1130000 },
4349 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4350 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4351 pbn_b0_1_921600 },
4352 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4353 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4354 pbn_b0_4_115200 },
4355 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4357 pbn_b0_bt_2_921600 },
4358 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4360 pbn_b2_8_1152000 },
4361
4362 /*
4363 * Oxford Semiconductor Inc. Tornado PCI express device range.
4364 */
4365 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4366 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4367 pbn_b0_1_15625000 },
4368 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4369 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4370 pbn_b0_1_15625000 },
4371 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4372 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4373 pbn_oxsemi_1_15625000 },
4374 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4375 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4376 pbn_oxsemi_1_15625000 },
4377 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4378 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4379 pbn_b0_1_15625000 },
4380 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4381 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4382 pbn_b0_1_15625000 },
4383 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4384 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4385 pbn_oxsemi_1_15625000 },
4386 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4387 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4388 pbn_oxsemi_1_15625000 },
4389 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4390 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4391 pbn_b0_1_15625000 },
4392 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4393 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4394 pbn_b0_1_15625000 },
4395 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4396 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4397 pbn_b0_1_15625000 },
4398 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4400 pbn_b0_1_15625000 },
4401 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4403 pbn_oxsemi_2_15625000 },
4404 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4405 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4406 pbn_oxsemi_2_15625000 },
4407 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409 pbn_oxsemi_4_15625000 },
4410 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4412 pbn_oxsemi_4_15625000 },
4413 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4415 pbn_oxsemi_8_15625000 },
4416 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4418 pbn_oxsemi_8_15625000 },
4419 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4421 pbn_oxsemi_1_15625000 },
4422 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4424 pbn_oxsemi_1_15625000 },
4425 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4427 pbn_oxsemi_1_15625000 },
4428 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4430 pbn_oxsemi_1_15625000 },
4431 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4433 pbn_oxsemi_1_15625000 },
4434 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4436 pbn_oxsemi_1_15625000 },
4437 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4439 pbn_oxsemi_1_15625000 },
4440 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4442 pbn_oxsemi_1_15625000 },
4443 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4445 pbn_oxsemi_1_15625000 },
4446 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4448 pbn_oxsemi_1_15625000 },
4449 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451 pbn_oxsemi_1_15625000 },
4452 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4454 pbn_oxsemi_1_15625000 },
4455 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457 pbn_oxsemi_1_15625000 },
4458 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4460 pbn_oxsemi_1_15625000 },
4461 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4463 pbn_oxsemi_1_15625000 },
4464 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4466 pbn_oxsemi_1_15625000 },
4467 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4469 pbn_oxsemi_1_15625000 },
4470 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4472 pbn_oxsemi_1_15625000 },
4473 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4475 pbn_oxsemi_1_15625000 },
4476 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4478 pbn_oxsemi_1_15625000 },
4479 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4481 pbn_oxsemi_1_15625000 },
4482 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4484 pbn_oxsemi_1_15625000 },
4485 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4487 pbn_oxsemi_1_15625000 },
4488 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4490 pbn_oxsemi_1_15625000 },
4491 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4493 pbn_oxsemi_1_15625000 },
4494 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4496 pbn_oxsemi_1_15625000 },
4497 /*
4498 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4499 */
4500 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4501 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4502 pbn_oxsemi_1_15625000 },
4503 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4504 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4505 pbn_oxsemi_2_15625000 },
4506 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4507 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4508 pbn_oxsemi_4_15625000 },
4509 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4510 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4511 pbn_oxsemi_8_15625000 },
4512
4513 /*
4514 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4515 */
4516 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4517 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4518 pbn_oxsemi_2_15625000 },
4519 /*
4520 * EndRun Technologies. PCI express device range.
4521 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952.
4522 */
4523 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4525 pbn_oxsemi_2_15625000 },
4526
4527 /*
4528 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4529 * from skokodyn@yahoo.com
4530 */
4531 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4532 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4533 pbn_sbsxrsio },
4534 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4535 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4536 pbn_sbsxrsio },
4537 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4538 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4539 pbn_sbsxrsio },
4540 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4541 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4542 pbn_sbsxrsio },
4543
4544 /*
4545 * Digitan DS560-558, from jimd@esoft.com
4546 */
4547 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4548 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4549 pbn_b1_1_115200 },
4550
4551 /*
4552 * Titan Electronic cards
4553 * The 400L and 800L have a custom setup quirk.
4554 */
4555 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4556 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4557 pbn_b0_1_921600 },
4558 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4559 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4560 pbn_b0_2_921600 },
4561 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4562 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4563 pbn_b0_4_921600 },
4564 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4565 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4566 pbn_b0_4_921600 },
4567 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4568 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4569 pbn_b1_1_921600 },
4570 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4571 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4572 pbn_b1_bt_2_921600 },
4573 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4574 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4575 pbn_b0_bt_4_921600 },
4576 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4577 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4578 pbn_b0_bt_8_921600 },
4579 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4581 pbn_b4_bt_2_921600 },
4582 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4584 pbn_b4_bt_4_921600 },
4585 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587 pbn_b4_bt_8_921600 },
4588 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590 pbn_b0_4_921600 },
4591 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 pbn_b0_4_921600 },
4594 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 pbn_b0_4_921600 },
4597 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 pbn_titan_1_4000000 },
4600 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602 pbn_titan_2_4000000 },
4603 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_titan_4_4000000 },
4606 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 pbn_titan_8_4000000 },
4609 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611 pbn_titan_2_4000000 },
4612 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 pbn_titan_2_4000000 },
4615 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 pbn_b0_bt_2_921600 },
4618 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620 pbn_b0_4_921600 },
4621 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 pbn_b0_4_921600 },
4624 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626 pbn_b0_4_921600 },
4627 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629 pbn_b0_4_921600 },
4630
4631 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4633 pbn_b2_1_460800 },
4634 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4636 pbn_b2_1_460800 },
4637 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639 pbn_b2_1_460800 },
4640 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642 pbn_b2_bt_2_921600 },
4643 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4645 pbn_b2_bt_2_921600 },
4646 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4648 pbn_b2_bt_2_921600 },
4649 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4650 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4651 pbn_b2_bt_4_921600 },
4652 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4653 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4654 pbn_b2_bt_4_921600 },
4655 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4657 pbn_b2_bt_4_921600 },
4658 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4660 pbn_b0_1_921600 },
4661 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4662 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4663 pbn_b0_1_921600 },
4664 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4666 pbn_b0_1_921600 },
4667 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4669 pbn_b0_bt_2_921600 },
4670 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672 pbn_b0_bt_2_921600 },
4673 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4675 pbn_b0_bt_2_921600 },
4676 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4678 pbn_b0_bt_4_921600 },
4679 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4680 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4681 pbn_b0_bt_4_921600 },
4682 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4684 pbn_b0_bt_4_921600 },
4685 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687 pbn_b0_bt_8_921600 },
4688 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4690 pbn_b0_bt_8_921600 },
4691 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4693 pbn_b0_bt_8_921600 },
4694
4695 /*
4696 * Computone devices submitted by Doug McNash dmcnash@computone.com
4697 */
4698 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4699 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4700 0, 0, pbn_computone_4 },
4701 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4702 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4703 0, 0, pbn_computone_8 },
4704 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4705 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4706 0, 0, pbn_computone_6 },
4707
4708 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710 pbn_oxsemi },
4711 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4712 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4713 pbn_b0_bt_1_921600 },
4714
4715 /*
4716 * Sunix PCI serial boards
4717 */
4718 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4719 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
4720 pbn_sunix_pci_1s },
4721 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4722 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
4723 pbn_sunix_pci_2s },
4724 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4725 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
4726 pbn_sunix_pci_4s },
4727 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4728 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
4729 pbn_sunix_pci_4s },
4730 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4731 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
4732 pbn_sunix_pci_8s },
4733 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4734 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
4735 pbn_sunix_pci_8s },
4736 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4737 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
4738 pbn_sunix_pci_16s },
4739
4740 /*
4741 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4742 */
4743 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4745 pbn_b0_bt_8_115200 },
4746 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4747 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4748 pbn_b0_bt_8_115200 },
4749
4750 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4752 pbn_b0_bt_2_115200 },
4753 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4754 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4755 pbn_b0_bt_2_115200 },
4756 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4757 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4758 pbn_b0_bt_2_115200 },
4759 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4760 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4761 pbn_b0_bt_2_115200 },
4762 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4763 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4764 pbn_b0_bt_2_115200 },
4765 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4766 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4767 pbn_b0_bt_4_460800 },
4768 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4769 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4770 pbn_b0_bt_4_460800 },
4771 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4772 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4773 pbn_b0_bt_2_460800 },
4774 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4775 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4776 pbn_b0_bt_2_460800 },
4777 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779 pbn_b0_bt_2_460800 },
4780 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4781 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4782 pbn_b0_bt_1_115200 },
4783 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4784 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4785 pbn_b0_bt_1_460800 },
4786
4787 /*
4788 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4789 * Cards are identified by their subsystem vendor IDs, which
4790 * (in hex) match the model number.
4791 *
4792 * Note that JC140x are RS422/485 cards which require ox950
4793 * ACR = 0x10, and as such are not currently fully supported.
4794 */
4795 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4796 0x1204, 0x0004, 0, 0,
4797 pbn_b0_4_921600 },
4798 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4799 0x1208, 0x0004, 0, 0,
4800 pbn_b0_4_921600 },
4801 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4802 0x1402, 0x0002, 0, 0,
4803 pbn_b0_2_921600 }, */
4804 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4805 0x1404, 0x0004, 0, 0,
4806 pbn_b0_4_921600 }, */
4807 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4808 0x1208, 0x0004, 0, 0,
4809 pbn_b0_4_921600 },
4810
4811 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4812 0x1204, 0x0004, 0, 0,
4813 pbn_b0_4_921600 },
4814 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4815 0x1208, 0x0004, 0, 0,
4816 pbn_b0_4_921600 },
4817 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4818 0x1208, 0x0004, 0, 0,
4819 pbn_b0_4_921600 },
4820 /*
4821 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4822 */
4823 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4824 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4825 pbn_b1_1_1382400 },
4826
4827 /*
4828 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4829 */
4830 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4831 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4832 pbn_b1_1_1382400 },
4833
4834 /*
4835 * RAStel 2 port modem, gerg@moreton.com.au
4836 */
4837 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4838 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4839 pbn_b2_bt_2_115200 },
4840
4841 /*
4842 * EKF addition for i960 Boards form EKF with serial port
4843 */
4844 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4845 0xE4BF, PCI_ANY_ID, 0, 0,
4846 pbn_intel_i960 },
4847
4848 /*
4849 * Xircom Cardbus/Ethernet combos
4850 */
4851 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4853 pbn_b0_1_115200 },
4854 /*
4855 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4856 */
4857 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4858 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4859 pbn_b0_1_115200 },
4860
4861 /*
4862 * Untested PCI modems, sent in from various folks...
4863 */
4864
4865 /*
4866 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4867 */
4868 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4869 0x1048, 0x1500, 0, 0,
4870 pbn_b1_1_115200 },
4871
4872 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4873 0xFF00, 0, 0, 0,
4874 pbn_sgi_ioc3 },
4875
4876 /*
4877 * HP Diva card
4878 */
4879 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4880 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4881 pbn_b1_1_115200 },
4882 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4883 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4884 pbn_b0_5_115200 },
4885 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4887 pbn_b2_1_115200 },
4888 /* HPE PCI serial device */
4889 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
4890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4891 pbn_b1_1_115200 },
4892
4893 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4894 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4895 pbn_b3_2_115200 },
4896 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4898 pbn_b3_4_115200 },
4899 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4901 pbn_b3_8_115200 },
4902 /*
4903 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4904 */
4905 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4907 pbn_b0_1_115200 },
4908 /*
4909 * ITE
4910 */
4911 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4912 PCI_ANY_ID, PCI_ANY_ID,
4913 0, 0,
4914 pbn_b1_bt_1_115200 },
4915
4916 /*
4917 * IntaShield IS-200
4918 */
4919 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4920 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4921 pbn_b2_2_115200 },
4922 /*
4923 * IntaShield IS-400
4924 */
4925 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4926 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4927 pbn_b2_4_115200 },
4928 /* Brainboxes Devices */
4929 /*
4930 * Brainboxes UC-101
4931 */
4932 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
4933 PCI_ANY_ID, PCI_ANY_ID,
4934 0, 0,
4935 pbn_b2_2_115200 },
4936 /*
4937 * Brainboxes UC-235/246
4938 */
4939 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
4940 PCI_ANY_ID, PCI_ANY_ID,
4941 0, 0,
4942 pbn_b2_1_115200 },
4943 /*
4944 * Brainboxes UC-257
4945 */
4946 { PCI_VENDOR_ID_INTASHIELD, 0x0861,
4947 PCI_ANY_ID, PCI_ANY_ID,
4948 0, 0,
4949 pbn_b2_2_115200 },
4950 /*
4951 * Brainboxes UC-260/271/701/756
4952 */
4953 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
4954 PCI_ANY_ID, PCI_ANY_ID,
4955 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4956 pbn_b2_4_115200 },
4957 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
4958 PCI_ANY_ID, PCI_ANY_ID,
4959 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4960 pbn_b2_4_115200 },
4961 /*
4962 * Brainboxes UC-268
4963 */
4964 { PCI_VENDOR_ID_INTASHIELD, 0x0841,
4965 PCI_ANY_ID, PCI_ANY_ID,
4966 0, 0,
4967 pbn_b2_4_115200 },
4968 /*
4969 * Brainboxes UC-275/279
4970 */
4971 { PCI_VENDOR_ID_INTASHIELD, 0x0881,
4972 PCI_ANY_ID, PCI_ANY_ID,
4973 0, 0,
4974 pbn_b2_8_115200 },
4975 /*
4976 * Brainboxes UC-302
4977 */
4978 { PCI_VENDOR_ID_INTASHIELD, 0x08E1,
4979 PCI_ANY_ID, PCI_ANY_ID,
4980 0, 0,
4981 pbn_b2_2_115200 },
4982 /*
4983 * Brainboxes UC-310
4984 */
4985 { PCI_VENDOR_ID_INTASHIELD, 0x08C1,
4986 PCI_ANY_ID, PCI_ANY_ID,
4987 0, 0,
4988 pbn_b2_2_115200 },
4989 /*
4990 * Brainboxes UC-313
4991 */
4992 { PCI_VENDOR_ID_INTASHIELD, 0x08A3,
4993 PCI_ANY_ID, PCI_ANY_ID,
4994 0, 0,
4995 pbn_b2_2_115200 },
4996 /*
4997 * Brainboxes UC-320/324
4998 */
4999 { PCI_VENDOR_ID_INTASHIELD, 0x0A61,
5000 PCI_ANY_ID, PCI_ANY_ID,
5001 0, 0,
5002 pbn_b2_1_115200 },
5003 /*
5004 * Brainboxes UC-346
5005 */
5006 { PCI_VENDOR_ID_INTASHIELD, 0x0B02,
5007 PCI_ANY_ID, PCI_ANY_ID,
5008 0, 0,
5009 pbn_b2_4_115200 },
5010 /*
5011 * Brainboxes UC-357
5012 */
5013 { PCI_VENDOR_ID_INTASHIELD, 0x0A81,
5014 PCI_ANY_ID, PCI_ANY_ID,
5015 0, 0,
5016 pbn_b2_2_115200 },
5017 { PCI_VENDOR_ID_INTASHIELD, 0x0A83,
5018 PCI_ANY_ID, PCI_ANY_ID,
5019 0, 0,
5020 pbn_b2_2_115200 },
5021 /*
5022 * Brainboxes UC-368
5023 */
5024 { PCI_VENDOR_ID_INTASHIELD, 0x0C41,
5025 PCI_ANY_ID, PCI_ANY_ID,
5026 0, 0,
5027 pbn_b2_4_115200 },
5028 /*
5029 * Brainboxes UC-420/431
5030 */
5031 { PCI_VENDOR_ID_INTASHIELD, 0x0921,
5032 PCI_ANY_ID, PCI_ANY_ID,
5033 0, 0,
5034 pbn_b2_4_115200 },
5035 /*
5036 * Brainboxes PX-101
5037 */
5038 { PCI_VENDOR_ID_INTASHIELD, 0x4005,
5039 PCI_ANY_ID, PCI_ANY_ID,
5040 0, 0,
5041 pbn_b0_2_115200 },
5042 { PCI_VENDOR_ID_INTASHIELD, 0x4019,
5043 PCI_ANY_ID, PCI_ANY_ID,
5044 0, 0,
5045 pbn_oxsemi_2_15625000 },
5046 /*
5047 * Brainboxes PX-235/246
5048 */
5049 { PCI_VENDOR_ID_INTASHIELD, 0x4004,
5050 PCI_ANY_ID, PCI_ANY_ID,
5051 0, 0,
5052 pbn_b0_1_115200 },
5053 { PCI_VENDOR_ID_INTASHIELD, 0x4016,
5054 PCI_ANY_ID, PCI_ANY_ID,
5055 0, 0,
5056 pbn_oxsemi_1_15625000 },
5057 /*
5058 * Brainboxes PX-203/PX-257
5059 */
5060 { PCI_VENDOR_ID_INTASHIELD, 0x4006,
5061 PCI_ANY_ID, PCI_ANY_ID,
5062 0, 0,
5063 pbn_b0_2_115200 },
5064 { PCI_VENDOR_ID_INTASHIELD, 0x4015,
5065 PCI_ANY_ID, PCI_ANY_ID,
5066 0, 0,
5067 pbn_oxsemi_4_15625000 },
5068 /*
5069 * Brainboxes PX-260/PX-701
5070 */
5071 { PCI_VENDOR_ID_INTASHIELD, 0x400A,
5072 PCI_ANY_ID, PCI_ANY_ID,
5073 0, 0,
5074 pbn_oxsemi_4_15625000 },
5075 /*
5076 * Brainboxes PX-310
5077 */
5078 { PCI_VENDOR_ID_INTASHIELD, 0x400E,
5079 PCI_ANY_ID, PCI_ANY_ID,
5080 0, 0,
5081 pbn_oxsemi_2_15625000 },
5082 /*
5083 * Brainboxes PX-313
5084 */
5085 { PCI_VENDOR_ID_INTASHIELD, 0x400C,
5086 PCI_ANY_ID, PCI_ANY_ID,
5087 0, 0,
5088 pbn_oxsemi_2_15625000 },
5089 /*
5090 * Brainboxes PX-320/324/PX-376/PX-387
5091 */
5092 { PCI_VENDOR_ID_INTASHIELD, 0x400B,
5093 PCI_ANY_ID, PCI_ANY_ID,
5094 0, 0,
5095 pbn_oxsemi_1_15625000 },
5096 /*
5097 * Brainboxes PX-335/346
5098 */
5099 { PCI_VENDOR_ID_INTASHIELD, 0x400F,
5100 PCI_ANY_ID, PCI_ANY_ID,
5101 0, 0,
5102 pbn_oxsemi_4_15625000 },
5103 /*
5104 * Brainboxes PX-368
5105 */
5106 { PCI_VENDOR_ID_INTASHIELD, 0x4010,
5107 PCI_ANY_ID, PCI_ANY_ID,
5108 0, 0,
5109 pbn_oxsemi_4_15625000 },
5110 /*
5111 * Brainboxes PX-420
5112 */
5113 { PCI_VENDOR_ID_INTASHIELD, 0x4000,
5114 PCI_ANY_ID, PCI_ANY_ID,
5115 0, 0,
5116 pbn_b0_4_115200 },
5117 { PCI_VENDOR_ID_INTASHIELD, 0x4011,
5118 PCI_ANY_ID, PCI_ANY_ID,
5119 0, 0,
5120 pbn_oxsemi_4_15625000 },
5121 /*
5122 * Brainboxes PX-803
5123 */
5124 { PCI_VENDOR_ID_INTASHIELD, 0x4009,
5125 PCI_ANY_ID, PCI_ANY_ID,
5126 0, 0,
5127 pbn_b0_1_115200 },
5128 { PCI_VENDOR_ID_INTASHIELD, 0x401E,
5129 PCI_ANY_ID, PCI_ANY_ID,
5130 0, 0,
5131 pbn_oxsemi_1_15625000 },
5132 /*
5133 * Brainboxes PX-846
5134 */
5135 { PCI_VENDOR_ID_INTASHIELD, 0x4008,
5136 PCI_ANY_ID, PCI_ANY_ID,
5137 0, 0,
5138 pbn_b0_1_115200 },
5139 { PCI_VENDOR_ID_INTASHIELD, 0x4017,
5140 PCI_ANY_ID, PCI_ANY_ID,
5141 0, 0,
5142 pbn_oxsemi_1_15625000 },
5143
5144 /*
5145 * Perle PCI-RAS cards
5146 */
5147 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5148 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5149 0, 0, pbn_b2_4_921600 },
5150 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5151 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5152 0, 0, pbn_b2_8_921600 },
5153
5154 /*
5155 * Mainpine series cards: Fairly standard layout but fools
5156 * parts of the autodetect in some cases and uses otherwise
5157 * unmatched communications subclasses in the PCI Express case
5158 */
5159
5160 { /* RockForceDUO */
5161 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5162 PCI_VENDOR_ID_MAINPINE, 0x0200,
5163 0, 0, pbn_b0_2_115200 },
5164 { /* RockForceQUATRO */
5165 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5166 PCI_VENDOR_ID_MAINPINE, 0x0300,
5167 0, 0, pbn_b0_4_115200 },
5168 { /* RockForceDUO+ */
5169 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5170 PCI_VENDOR_ID_MAINPINE, 0x0400,
5171 0, 0, pbn_b0_2_115200 },
5172 { /* RockForceQUATRO+ */
5173 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5174 PCI_VENDOR_ID_MAINPINE, 0x0500,
5175 0, 0, pbn_b0_4_115200 },
5176 { /* RockForce+ */
5177 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5178 PCI_VENDOR_ID_MAINPINE, 0x0600,
5179 0, 0, pbn_b0_2_115200 },
5180 { /* RockForce+ */
5181 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5182 PCI_VENDOR_ID_MAINPINE, 0x0700,
5183 0, 0, pbn_b0_4_115200 },
5184 { /* RockForceOCTO+ */
5185 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5186 PCI_VENDOR_ID_MAINPINE, 0x0800,
5187 0, 0, pbn_b0_8_115200 },
5188 { /* RockForceDUO+ */
5189 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5190 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5191 0, 0, pbn_b0_2_115200 },
5192 { /* RockForceQUARTRO+ */
5193 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5194 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5195 0, 0, pbn_b0_4_115200 },
5196 { /* RockForceOCTO+ */
5197 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5198 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5199 0, 0, pbn_b0_8_115200 },
5200 { /* RockForceD1 */
5201 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5202 PCI_VENDOR_ID_MAINPINE, 0x2000,
5203 0, 0, pbn_b0_1_115200 },
5204 { /* RockForceF1 */
5205 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5206 PCI_VENDOR_ID_MAINPINE, 0x2100,
5207 0, 0, pbn_b0_1_115200 },
5208 { /* RockForceD2 */
5209 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5210 PCI_VENDOR_ID_MAINPINE, 0x2200,
5211 0, 0, pbn_b0_2_115200 },
5212 { /* RockForceF2 */
5213 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5214 PCI_VENDOR_ID_MAINPINE, 0x2300,
5215 0, 0, pbn_b0_2_115200 },
5216 { /* RockForceD4 */
5217 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5218 PCI_VENDOR_ID_MAINPINE, 0x2400,
5219 0, 0, pbn_b0_4_115200 },
5220 { /* RockForceF4 */
5221 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5222 PCI_VENDOR_ID_MAINPINE, 0x2500,
5223 0, 0, pbn_b0_4_115200 },
5224 { /* RockForceD8 */
5225 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5226 PCI_VENDOR_ID_MAINPINE, 0x2600,
5227 0, 0, pbn_b0_8_115200 },
5228 { /* RockForceF8 */
5229 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5230 PCI_VENDOR_ID_MAINPINE, 0x2700,
5231 0, 0, pbn_b0_8_115200 },
5232 { /* IQ Express D1 */
5233 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5234 PCI_VENDOR_ID_MAINPINE, 0x3000,
5235 0, 0, pbn_b0_1_115200 },
5236 { /* IQ Express F1 */
5237 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5238 PCI_VENDOR_ID_MAINPINE, 0x3100,
5239 0, 0, pbn_b0_1_115200 },
5240 { /* IQ Express D2 */
5241 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5242 PCI_VENDOR_ID_MAINPINE, 0x3200,
5243 0, 0, pbn_b0_2_115200 },
5244 { /* IQ Express F2 */
5245 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5246 PCI_VENDOR_ID_MAINPINE, 0x3300,
5247 0, 0, pbn_b0_2_115200 },
5248 { /* IQ Express D4 */
5249 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5250 PCI_VENDOR_ID_MAINPINE, 0x3400,
5251 0, 0, pbn_b0_4_115200 },
5252 { /* IQ Express F4 */
5253 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5254 PCI_VENDOR_ID_MAINPINE, 0x3500,
5255 0, 0, pbn_b0_4_115200 },
5256 { /* IQ Express D8 */
5257 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5258 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5259 0, 0, pbn_b0_8_115200 },
5260 { /* IQ Express F8 */
5261 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5262 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5263 0, 0, pbn_b0_8_115200 },
5264
5265
5266 /*
5267 * PA Semi PA6T-1682M on-chip UART
5268 */
5269 { PCI_VENDOR_ID_PASEMI, 0xa004,
5270 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5271 pbn_pasemi_1682M },
5272
5273 /*
5274 * National Instruments
5275 */
5276 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5278 pbn_b1_16_115200 },
5279 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5281 pbn_b1_8_115200 },
5282 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5284 pbn_b1_bt_4_115200 },
5285 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5287 pbn_b1_bt_2_115200 },
5288 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5290 pbn_b1_bt_4_115200 },
5291 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5292 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5293 pbn_b1_bt_2_115200 },
5294 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5295 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5296 pbn_b1_16_115200 },
5297 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5298 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5299 pbn_b1_8_115200 },
5300 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5301 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5302 pbn_b1_bt_4_115200 },
5303 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5304 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5305 pbn_b1_bt_2_115200 },
5306 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5307 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5308 pbn_b1_bt_4_115200 },
5309 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5310 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5311 pbn_b1_bt_2_115200 },
5312 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5313 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5314 pbn_ni8430_2 },
5315 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5316 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5317 pbn_ni8430_2 },
5318 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5319 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5320 pbn_ni8430_4 },
5321 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5322 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5323 pbn_ni8430_4 },
5324 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5325 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5326 pbn_ni8430_8 },
5327 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5328 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5329 pbn_ni8430_8 },
5330 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5332 pbn_ni8430_16 },
5333 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5334 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5335 pbn_ni8430_16 },
5336 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5337 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5338 pbn_ni8430_2 },
5339 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5340 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5341 pbn_ni8430_2 },
5342 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5343 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5344 pbn_ni8430_4 },
5345 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5346 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5347 pbn_ni8430_4 },
5348
5349 /*
5350 * MOXA
5351 */
5352 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E,
5353 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5354 pbn_moxa8250_2p },
5355 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL,
5356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5357 pbn_moxa8250_2p },
5358 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A,
5359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5360 pbn_moxa8250_4p },
5361 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL,
5362 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5363 pbn_moxa8250_4p },
5364 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A,
5365 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5366 pbn_moxa8250_8p },
5367 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B,
5368 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5369 pbn_moxa8250_8p },
5370 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A,
5371 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5372 pbn_moxa8250_8p },
5373 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I,
5374 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5375 pbn_moxa8250_8p },
5376 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL,
5377 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5378 pbn_moxa8250_2p },
5379 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A,
5380 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5381 pbn_moxa8250_4p },
5382 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A,
5383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5384 pbn_moxa8250_8p },
5385 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A,
5386 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5387 pbn_moxa8250_8p },
5388
5389 /*
5390 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5391 */
5392 { PCI_VENDOR_ID_ADDIDATA,
5393 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5394 PCI_ANY_ID,
5395 PCI_ANY_ID,
5396 0,
5397 0,
5398 pbn_b0_4_115200 },
5399
5400 { PCI_VENDOR_ID_ADDIDATA,
5401 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5402 PCI_ANY_ID,
5403 PCI_ANY_ID,
5404 0,
5405 0,
5406 pbn_b0_2_115200 },
5407
5408 { PCI_VENDOR_ID_ADDIDATA,
5409 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5410 PCI_ANY_ID,
5411 PCI_ANY_ID,
5412 0,
5413 0,
5414 pbn_b0_1_115200 },
5415
5416 { PCI_VENDOR_ID_AMCC,
5417 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5418 PCI_ANY_ID,
5419 PCI_ANY_ID,
5420 0,
5421 0,
5422 pbn_b1_8_115200 },
5423
5424 { PCI_VENDOR_ID_ADDIDATA,
5425 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5426 PCI_ANY_ID,
5427 PCI_ANY_ID,
5428 0,
5429 0,
5430 pbn_b0_4_115200 },
5431
5432 { PCI_VENDOR_ID_ADDIDATA,
5433 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5434 PCI_ANY_ID,
5435 PCI_ANY_ID,
5436 0,
5437 0,
5438 pbn_b0_2_115200 },
5439
5440 { PCI_VENDOR_ID_ADDIDATA,
5441 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5442 PCI_ANY_ID,
5443 PCI_ANY_ID,
5444 0,
5445 0,
5446 pbn_b0_1_115200 },
5447
5448 { PCI_VENDOR_ID_ADDIDATA,
5449 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5450 PCI_ANY_ID,
5451 PCI_ANY_ID,
5452 0,
5453 0,
5454 pbn_b0_4_115200 },
5455
5456 { PCI_VENDOR_ID_ADDIDATA,
5457 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5458 PCI_ANY_ID,
5459 PCI_ANY_ID,
5460 0,
5461 0,
5462 pbn_b0_2_115200 },
5463
5464 { PCI_VENDOR_ID_ADDIDATA,
5465 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5466 PCI_ANY_ID,
5467 PCI_ANY_ID,
5468 0,
5469 0,
5470 pbn_b0_1_115200 },
5471
5472 { PCI_VENDOR_ID_ADDIDATA,
5473 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5474 PCI_ANY_ID,
5475 PCI_ANY_ID,
5476 0,
5477 0,
5478 pbn_b0_8_115200 },
5479
5480 { PCI_VENDOR_ID_ADDIDATA,
5481 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5482 PCI_ANY_ID,
5483 PCI_ANY_ID,
5484 0,
5485 0,
5486 pbn_ADDIDATA_PCIe_4_3906250 },
5487
5488 { PCI_VENDOR_ID_ADDIDATA,
5489 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5490 PCI_ANY_ID,
5491 PCI_ANY_ID,
5492 0,
5493 0,
5494 pbn_ADDIDATA_PCIe_2_3906250 },
5495
5496 { PCI_VENDOR_ID_ADDIDATA,
5497 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5498 PCI_ANY_ID,
5499 PCI_ANY_ID,
5500 0,
5501 0,
5502 pbn_ADDIDATA_PCIe_1_3906250 },
5503
5504 { PCI_VENDOR_ID_ADDIDATA,
5505 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5506 PCI_ANY_ID,
5507 PCI_ANY_ID,
5508 0,
5509 0,
5510 pbn_ADDIDATA_PCIe_8_3906250 },
5511
5512 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5513 PCI_VENDOR_ID_IBM, 0x0299,
5514 0, 0, pbn_b0_bt_2_115200 },
5515
5516 /*
5517 * other NetMos 9835 devices are most likely handled by the
5518 * parport_serial driver, check drivers/parport/parport_serial.c
5519 * before adding them here.
5520 */
5521
5522 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5523 0xA000, 0x1000,
5524 0, 0, pbn_b0_1_115200 },
5525
5526 /* the 9901 is a rebranded 9912 */
5527 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5528 0xA000, 0x1000,
5529 0, 0, pbn_b0_1_115200 },
5530
5531 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5532 0xA000, 0x1000,
5533 0, 0, pbn_b0_1_115200 },
5534
5535 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5536 0xA000, 0x1000,
5537 0, 0, pbn_b0_1_115200 },
5538
5539 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5540 0xA000, 0x1000,
5541 0, 0, pbn_b0_1_115200 },
5542
5543 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5544 0xA000, 0x3002,
5545 0, 0, pbn_NETMOS9900_2s_115200 },
5546
5547 /*
5548 * Best Connectivity and Rosewill PCI Multi I/O cards
5549 */
5550
5551 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5552 0xA000, 0x1000,
5553 0, 0, pbn_b0_1_115200 },
5554
5555 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5556 0xA000, 0x3002,
5557 0, 0, pbn_b0_bt_2_115200 },
5558
5559 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5560 0xA000, 0x3004,
5561 0, 0, pbn_b0_bt_4_115200 },
5562
5563 /*
5564 * ASIX AX99100 PCIe to Multi I/O Controller
5565 */
5566 { PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
5567 0xA000, 0x1000,
5568 0, 0, pbn_b0_1_115200 },
5569
5570 /* Intel CE4100 */
5571 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5572 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5573 pbn_ce4100_1_115200 },
5574
5575 /*
5576 * Cronyx Omega PCI
5577 */
5578 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5580 pbn_omegapci },
5581
5582 /*
5583 * Broadcom TruManage
5584 */
5585 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5587 pbn_brcm_trumanage },
5588
5589 /*
5590 * AgeStar as-prs2-009
5591 */
5592 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5593 PCI_ANY_ID, PCI_ANY_ID,
5594 0, 0, pbn_b0_bt_2_115200 },
5595
5596 /*
5597 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5598 * so not listed here.
5599 */
5600 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5601 PCI_ANY_ID, PCI_ANY_ID,
5602 0, 0, pbn_b0_bt_4_115200 },
5603
5604 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5605 PCI_ANY_ID, PCI_ANY_ID,
5606 0, 0, pbn_b0_bt_2_115200 },
5607
5608 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5609 PCI_ANY_ID, PCI_ANY_ID,
5610 0, 0, pbn_b0_bt_4_115200 },
5611
5612 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5613 PCI_ANY_ID, PCI_ANY_ID,
5614 0, 0, pbn_wch382_2 },
5615
5616 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5617 PCI_ANY_ID, PCI_ANY_ID,
5618 0, 0, pbn_wch384_4 },
5619
5620 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S,
5621 PCI_ANY_ID, PCI_ANY_ID,
5622 0, 0, pbn_wch384_8 },
5623 /*
5624 * Realtek RealManage
5625 */
5626 { PCI_VENDOR_ID_REALTEK, 0x816a,
5627 PCI_ANY_ID, PCI_ANY_ID,
5628 0, 0, pbn_b0_1_115200 },
5629
5630 { PCI_VENDOR_ID_REALTEK, 0x816b,
5631 PCI_ANY_ID, PCI_ANY_ID,
5632 0, 0, pbn_b0_1_115200 },
5633
5634 /* Fintek PCI serial cards */
5635 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5636 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5637 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5638 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
5639 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
5640 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
5641
5642 /* MKS Tenta SCOM-080x serial cards */
5643 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5644 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5645
5646 /* Amazon PCI serial device */
5647 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5648
5649 /*
5650 * These entries match devices with class COMMUNICATION_SERIAL,
5651 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5652 */
5653 { PCI_ANY_ID, PCI_ANY_ID,
5654 PCI_ANY_ID, PCI_ANY_ID,
5655 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5656 0xffff00, pbn_default },
5657 { PCI_ANY_ID, PCI_ANY_ID,
5658 PCI_ANY_ID, PCI_ANY_ID,
5659 PCI_CLASS_COMMUNICATION_MODEM << 8,
5660 0xffff00, pbn_default },
5661 { PCI_ANY_ID, PCI_ANY_ID,
5662 PCI_ANY_ID, PCI_ANY_ID,
5663 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5664 0xffff00, pbn_default },
5665 { 0, }
5666 };
5667
serial8250_io_error_detected(struct pci_dev * dev,pci_channel_state_t state)5668 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5669 pci_channel_state_t state)
5670 {
5671 struct serial_private *priv = pci_get_drvdata(dev);
5672
5673 if (state == pci_channel_io_perm_failure)
5674 return PCI_ERS_RESULT_DISCONNECT;
5675
5676 if (priv)
5677 pciserial_detach_ports(priv);
5678
5679 pci_disable_device(dev);
5680
5681 return PCI_ERS_RESULT_NEED_RESET;
5682 }
5683
serial8250_io_slot_reset(struct pci_dev * dev)5684 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5685 {
5686 int rc;
5687
5688 rc = pci_enable_device(dev);
5689
5690 if (rc)
5691 return PCI_ERS_RESULT_DISCONNECT;
5692
5693 pci_restore_state(dev);
5694 pci_save_state(dev);
5695
5696 return PCI_ERS_RESULT_RECOVERED;
5697 }
5698
serial8250_io_resume(struct pci_dev * dev)5699 static void serial8250_io_resume(struct pci_dev *dev)
5700 {
5701 struct serial_private *priv = pci_get_drvdata(dev);
5702 struct serial_private *new;
5703
5704 if (!priv)
5705 return;
5706
5707 new = pciserial_init_ports(dev, priv->board);
5708 if (!IS_ERR(new)) {
5709 pci_set_drvdata(dev, new);
5710 kfree(priv);
5711 }
5712 }
5713
5714 static const struct pci_error_handlers serial8250_err_handler = {
5715 .error_detected = serial8250_io_error_detected,
5716 .slot_reset = serial8250_io_slot_reset,
5717 .resume = serial8250_io_resume,
5718 };
5719
5720 static struct pci_driver serial_pci_driver = {
5721 .name = "serial",
5722 .probe = pciserial_init_one,
5723 .remove = pciserial_remove_one,
5724 .driver = {
5725 .pm = &pciserial_pm_ops,
5726 },
5727 .id_table = serial_pci_tbl,
5728 .err_handler = &serial8250_err_handler,
5729 };
5730
5731 module_pci_driver(serial_pci_driver);
5732
5733 MODULE_LICENSE("GPL");
5734 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5735 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
5736 MODULE_IMPORT_NS(SERIAL_8250_PCI);
5737
