1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * STM32 ALSA SoC Digital Audio Interface (SAI) driver.
4 *
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of_irq.h>
14 #include <linux/of_platform.h>
15 #include <linux/regmap.h>
16
17 #include <sound/asoundef.h>
18 #include <sound/core.h>
19 #include <sound/dmaengine_pcm.h>
20 #include <sound/pcm_params.h>
21
22 #include "stm32_sai.h"
23
24 #define SAI_FREE_PROTOCOL 0x0
25 #define SAI_SPDIF_PROTOCOL 0x1
26
27 #define SAI_SLOT_SIZE_AUTO 0x0
28 #define SAI_SLOT_SIZE_16 0x1
29 #define SAI_SLOT_SIZE_32 0x2
30
31 #define SAI_DATASIZE_8 0x2
32 #define SAI_DATASIZE_10 0x3
33 #define SAI_DATASIZE_16 0x4
34 #define SAI_DATASIZE_20 0x5
35 #define SAI_DATASIZE_24 0x6
36 #define SAI_DATASIZE_32 0x7
37
38 #define STM_SAI_DAI_NAME_SIZE 15
39
40 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
41 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
42
43 #define STM_SAI_A_ID 0x0
44 #define STM_SAI_B_ID 0x1
45
46 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
47 #define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID)
48 #define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B")
49
50 #define SAI_SYNC_NONE 0x0
51 #define SAI_SYNC_INTERNAL 0x1
52 #define SAI_SYNC_EXTERNAL 0x2
53
54 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif)
55 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm)
56 #define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm)
57 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata))
58
59 #define SAI_IEC60958_BLOCK_FRAMES 192
60 #define SAI_IEC60958_STATUS_BYTES 24
61
62 #define SAI_MCLK_NAME_LEN 32
63 #define SAI_RATE_11K 11025
64
65 /**
66 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
67 * @pdev: device data pointer
68 * @regmap: SAI register map pointer
69 * @regmap_config: SAI sub block register map configuration pointer
70 * @dma_params: dma configuration data for rx or tx channel
71 * @cpu_dai_drv: DAI driver data pointer
72 * @cpu_dai: DAI runtime data pointer
73 * @substream: PCM substream data pointer
74 * @pdata: SAI block parent data pointer
75 * @np_sync_provider: synchronization provider node
76 * @sai_ck: kernel clock feeding the SAI clock generator
77 * @sai_mclk: master clock from SAI mclk provider
78 * @phys_addr: SAI registers physical base address
79 * @mclk_rate: SAI block master clock frequency (Hz). set at init
80 * @id: SAI sub block id corresponding to sub-block A or B
81 * @dir: SAI block direction (playback or capture). set at init
82 * @master: SAI block mode flag. (true=master, false=slave) set at init
83 * @spdif: SAI S/PDIF iec60958 mode flag. set at init
84 * @fmt: SAI block format. relevant only for custom protocols. set at init
85 * @sync: SAI block synchronization mode. (none, internal or external)
86 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B)
87 * @synci: SAI block ext sync source (client setting). (SAI sync provider index)
88 * @fs_length: frame synchronization length. depends on protocol settings
89 * @slots: rx or tx slot number
90 * @slot_width: rx or tx slot width in bits
91 * @slot_mask: rx or tx active slots mask. set at init or at runtime
92 * @data_size: PCM data width. corresponds to PCM substream width.
93 * @spdif_frm_cnt: S/PDIF playback frame counter
94 * @iec958: iec958 data
95 * @ctrl_lock: control lock
96 * @irq_lock: prevent race condition with IRQ
97 */
98 struct stm32_sai_sub_data {
99 struct platform_device *pdev;
100 struct regmap *regmap;
101 const struct regmap_config *regmap_config;
102 struct snd_dmaengine_dai_dma_data dma_params;
103 struct snd_soc_dai_driver cpu_dai_drv;
104 struct snd_soc_dai *cpu_dai;
105 struct snd_pcm_substream *substream;
106 struct stm32_sai_data *pdata;
107 struct device_node *np_sync_provider;
108 struct clk *sai_ck;
109 struct clk *sai_mclk;
110 dma_addr_t phys_addr;
111 unsigned int mclk_rate;
112 unsigned int id;
113 int dir;
114 bool master;
115 bool spdif;
116 int fmt;
117 int sync;
118 int synco;
119 int synci;
120 int fs_length;
121 int slots;
122 int slot_width;
123 int slot_mask;
124 int data_size;
125 unsigned int spdif_frm_cnt;
126 struct snd_aes_iec958 iec958;
127 struct mutex ctrl_lock; /* protect resources accessed by controls */
128 spinlock_t irq_lock; /* used to prevent race condition with IRQ */
129 };
130
131 enum stm32_sai_fifo_th {
132 STM_SAI_FIFO_TH_EMPTY,
133 STM_SAI_FIFO_TH_QUARTER,
134 STM_SAI_FIFO_TH_HALF,
135 STM_SAI_FIFO_TH_3_QUARTER,
136 STM_SAI_FIFO_TH_FULL,
137 };
138
stm32_sai_sub_readable_reg(struct device * dev,unsigned int reg)139 static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg)
140 {
141 switch (reg) {
142 case STM_SAI_CR1_REGX:
143 case STM_SAI_CR2_REGX:
144 case STM_SAI_FRCR_REGX:
145 case STM_SAI_SLOTR_REGX:
146 case STM_SAI_IMR_REGX:
147 case STM_SAI_SR_REGX:
148 case STM_SAI_CLRFR_REGX:
149 case STM_SAI_DR_REGX:
150 case STM_SAI_PDMCR_REGX:
151 case STM_SAI_PDMLY_REGX:
152 return true;
153 default:
154 return false;
155 }
156 }
157
stm32_sai_sub_volatile_reg(struct device * dev,unsigned int reg)158 static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg)
159 {
160 switch (reg) {
161 case STM_SAI_DR_REGX:
162 case STM_SAI_SR_REGX:
163 return true;
164 default:
165 return false;
166 }
167 }
168
stm32_sai_sub_writeable_reg(struct device * dev,unsigned int reg)169 static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg)
170 {
171 switch (reg) {
172 case STM_SAI_CR1_REGX:
173 case STM_SAI_CR2_REGX:
174 case STM_SAI_FRCR_REGX:
175 case STM_SAI_SLOTR_REGX:
176 case STM_SAI_IMR_REGX:
177 case STM_SAI_CLRFR_REGX:
178 case STM_SAI_DR_REGX:
179 case STM_SAI_PDMCR_REGX:
180 case STM_SAI_PDMLY_REGX:
181 return true;
182 default:
183 return false;
184 }
185 }
186
187 static const struct regmap_config stm32_sai_sub_regmap_config_f4 = {
188 .reg_bits = 32,
189 .reg_stride = 4,
190 .val_bits = 32,
191 .max_register = STM_SAI_DR_REGX,
192 .readable_reg = stm32_sai_sub_readable_reg,
193 .volatile_reg = stm32_sai_sub_volatile_reg,
194 .writeable_reg = stm32_sai_sub_writeable_reg,
195 .fast_io = true,
196 .cache_type = REGCACHE_FLAT,
197 };
198
199 static const struct regmap_config stm32_sai_sub_regmap_config_h7 = {
200 .reg_bits = 32,
201 .reg_stride = 4,
202 .val_bits = 32,
203 .max_register = STM_SAI_PDMLY_REGX,
204 .readable_reg = stm32_sai_sub_readable_reg,
205 .volatile_reg = stm32_sai_sub_volatile_reg,
206 .writeable_reg = stm32_sai_sub_writeable_reg,
207 .fast_io = true,
208 .cache_type = REGCACHE_FLAT,
209 };
210
snd_pcm_iec958_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)211 static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol,
212 struct snd_ctl_elem_info *uinfo)
213 {
214 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
215 uinfo->count = 1;
216
217 return 0;
218 }
219
snd_pcm_iec958_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uctl)220 static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol,
221 struct snd_ctl_elem_value *uctl)
222 {
223 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
224
225 mutex_lock(&sai->ctrl_lock);
226 memcpy(uctl->value.iec958.status, sai->iec958.status, 4);
227 mutex_unlock(&sai->ctrl_lock);
228
229 return 0;
230 }
231
snd_pcm_iec958_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uctl)232 static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol,
233 struct snd_ctl_elem_value *uctl)
234 {
235 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
236
237 mutex_lock(&sai->ctrl_lock);
238 memcpy(sai->iec958.status, uctl->value.iec958.status, 4);
239 mutex_unlock(&sai->ctrl_lock);
240
241 return 0;
242 }
243
244 static const struct snd_kcontrol_new iec958_ctls = {
245 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
246 SNDRV_CTL_ELEM_ACCESS_VOLATILE),
247 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
248 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
249 .info = snd_pcm_iec958_info,
250 .get = snd_pcm_iec958_get,
251 .put = snd_pcm_iec958_put,
252 };
253
254 struct stm32_sai_mclk_data {
255 struct clk_hw hw;
256 unsigned long freq;
257 struct stm32_sai_sub_data *sai_data;
258 };
259
260 #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw)
261 #define STM32_SAI_MAX_CLKS 1
262
stm32_sai_get_clk_div(struct stm32_sai_sub_data * sai,unsigned long input_rate,unsigned long output_rate)263 static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai,
264 unsigned long input_rate,
265 unsigned long output_rate)
266 {
267 int version = sai->pdata->conf.version;
268 int div;
269
270 div = DIV_ROUND_CLOSEST(input_rate, output_rate);
271 if (div > SAI_XCR1_MCKDIV_MAX(version)) {
272 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
273 return -EINVAL;
274 }
275 dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div);
276
277 if (input_rate % div)
278 dev_dbg(&sai->pdev->dev,
279 "Rate not accurate. requested (%ld), actual (%ld)\n",
280 output_rate, input_rate / div);
281
282 return div;
283 }
284
stm32_sai_set_clk_div(struct stm32_sai_sub_data * sai,unsigned int div)285 static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai,
286 unsigned int div)
287 {
288 int version = sai->pdata->conf.version;
289 int ret, cr1, mask;
290
291 if (div > SAI_XCR1_MCKDIV_MAX(version)) {
292 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
293 return -EINVAL;
294 }
295
296 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version));
297 cr1 = SAI_XCR1_MCKDIV_SET(div);
298 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1);
299 if (ret < 0)
300 dev_err(&sai->pdev->dev, "Failed to update CR1 register\n");
301
302 return ret;
303 }
304
stm32_sai_set_parent_clock(struct stm32_sai_sub_data * sai,unsigned int rate)305 static int stm32_sai_set_parent_clock(struct stm32_sai_sub_data *sai,
306 unsigned int rate)
307 {
308 struct platform_device *pdev = sai->pdev;
309 struct clk *parent_clk = sai->pdata->clk_x8k;
310 int ret;
311
312 if (!(rate % SAI_RATE_11K))
313 parent_clk = sai->pdata->clk_x11k;
314
315 ret = clk_set_parent(sai->sai_ck, parent_clk);
316 if (ret)
317 dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s",
318 ret, ret == -EBUSY ?
319 "Active stream rates conflict\n" : "\n");
320
321 return ret;
322 }
323
stm32_sai_mclk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)324 static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate,
325 unsigned long *prate)
326 {
327 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
328 struct stm32_sai_sub_data *sai = mclk->sai_data;
329 int div;
330
331 div = stm32_sai_get_clk_div(sai, *prate, rate);
332 if (div < 0)
333 return div;
334
335 mclk->freq = *prate / div;
336
337 return mclk->freq;
338 }
339
stm32_sai_mclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)340 static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw,
341 unsigned long parent_rate)
342 {
343 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
344
345 return mclk->freq;
346 }
347
stm32_sai_mclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)348 static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate,
349 unsigned long parent_rate)
350 {
351 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
352 struct stm32_sai_sub_data *sai = mclk->sai_data;
353 int div, ret;
354
355 div = stm32_sai_get_clk_div(sai, parent_rate, rate);
356 if (div < 0)
357 return div;
358
359 ret = stm32_sai_set_clk_div(sai, div);
360 if (ret)
361 return ret;
362
363 mclk->freq = rate;
364
365 return 0;
366 }
367
stm32_sai_mclk_enable(struct clk_hw * hw)368 static int stm32_sai_mclk_enable(struct clk_hw *hw)
369 {
370 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
371 struct stm32_sai_sub_data *sai = mclk->sai_data;
372
373 dev_dbg(&sai->pdev->dev, "Enable master clock\n");
374
375 return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
376 SAI_XCR1_MCKEN, SAI_XCR1_MCKEN);
377 }
378
stm32_sai_mclk_disable(struct clk_hw * hw)379 static void stm32_sai_mclk_disable(struct clk_hw *hw)
380 {
381 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
382 struct stm32_sai_sub_data *sai = mclk->sai_data;
383
384 dev_dbg(&sai->pdev->dev, "Disable master clock\n");
385
386 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0);
387 }
388
389 static const struct clk_ops mclk_ops = {
390 .enable = stm32_sai_mclk_enable,
391 .disable = stm32_sai_mclk_disable,
392 .recalc_rate = stm32_sai_mclk_recalc_rate,
393 .round_rate = stm32_sai_mclk_round_rate,
394 .set_rate = stm32_sai_mclk_set_rate,
395 };
396
stm32_sai_add_mclk_provider(struct stm32_sai_sub_data * sai)397 static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai)
398 {
399 struct clk_hw *hw;
400 struct stm32_sai_mclk_data *mclk;
401 struct device *dev = &sai->pdev->dev;
402 const char *pname = __clk_get_name(sai->sai_ck);
403 char *mclk_name, *p, *s = (char *)pname;
404 int ret, i = 0;
405
406 mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL);
407 if (!mclk)
408 return -ENOMEM;
409
410 mclk_name = devm_kcalloc(dev, sizeof(char),
411 SAI_MCLK_NAME_LEN, GFP_KERNEL);
412 if (!mclk_name)
413 return -ENOMEM;
414
415 /*
416 * Forge mclk clock name from parent clock name and suffix.
417 * String after "_" char is stripped in parent name.
418 */
419 p = mclk_name;
420 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) {
421 *p++ = *s++;
422 i++;
423 }
424 STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk");
425
426 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
427 mclk->sai_data = sai;
428 hw = &mclk->hw;
429
430 dev_dbg(dev, "Register master clock %s\n", mclk_name);
431 ret = devm_clk_hw_register(&sai->pdev->dev, hw);
432 if (ret) {
433 dev_err(dev, "mclk register returned %d\n", ret);
434 return ret;
435 }
436 sai->sai_mclk = hw->clk;
437
438 /* register mclk provider */
439 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
440 }
441
stm32_sai_isr(int irq,void * devid)442 static irqreturn_t stm32_sai_isr(int irq, void *devid)
443 {
444 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid;
445 struct platform_device *pdev = sai->pdev;
446 unsigned int sr, imr, flags;
447 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING;
448
449 regmap_read(sai->regmap, STM_SAI_IMR_REGX, &imr);
450 regmap_read(sai->regmap, STM_SAI_SR_REGX, &sr);
451
452 flags = sr & imr;
453 if (!flags)
454 return IRQ_NONE;
455
456 regmap_write_bits(sai->regmap, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK,
457 SAI_XCLRFR_MASK);
458
459 if (!sai->substream) {
460 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr);
461 return IRQ_NONE;
462 }
463
464 if (flags & SAI_XIMR_OVRUDRIE) {
465 dev_err(&pdev->dev, "IRQ %s\n",
466 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun");
467 status = SNDRV_PCM_STATE_XRUN;
468 }
469
470 if (flags & SAI_XIMR_MUTEDETIE)
471 dev_dbg(&pdev->dev, "IRQ mute detected\n");
472
473 if (flags & SAI_XIMR_WCKCFGIE) {
474 dev_err(&pdev->dev, "IRQ wrong clock configuration\n");
475 status = SNDRV_PCM_STATE_DISCONNECTED;
476 }
477
478 if (flags & SAI_XIMR_CNRDYIE)
479 dev_err(&pdev->dev, "IRQ Codec not ready\n");
480
481 if (flags & SAI_XIMR_AFSDETIE) {
482 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n");
483 status = SNDRV_PCM_STATE_XRUN;
484 }
485
486 if (flags & SAI_XIMR_LFSDETIE) {
487 dev_err(&pdev->dev, "IRQ Late frame synchro\n");
488 status = SNDRV_PCM_STATE_XRUN;
489 }
490
491 spin_lock(&sai->irq_lock);
492 if (status != SNDRV_PCM_STATE_RUNNING && sai->substream)
493 snd_pcm_stop_xrun(sai->substream);
494 spin_unlock(&sai->irq_lock);
495
496 return IRQ_HANDLED;
497 }
498
stm32_sai_set_sysclk(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int dir)499 static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai,
500 int clk_id, unsigned int freq, int dir)
501 {
502 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
503 int ret;
504
505 if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) {
506 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
507 SAI_XCR1_NODIV,
508 freq ? 0 : SAI_XCR1_NODIV);
509 if (ret < 0)
510 return ret;
511
512 /* Assume shutdown if requested frequency is 0Hz */
513 if (!freq) {
514 /* Release mclk rate only if rate was actually set */
515 if (sai->mclk_rate) {
516 clk_rate_exclusive_put(sai->sai_mclk);
517 sai->mclk_rate = 0;
518 }
519 return 0;
520 }
521
522 /* If master clock is used, set parent clock now */
523 ret = stm32_sai_set_parent_clock(sai, freq);
524 if (ret)
525 return ret;
526
527 ret = clk_set_rate_exclusive(sai->sai_mclk, freq);
528 if (ret) {
529 dev_err(cpu_dai->dev,
530 ret == -EBUSY ?
531 "Active streams have incompatible rates" :
532 "Could not set mclk rate\n");
533 return ret;
534 }
535
536 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq);
537 sai->mclk_rate = freq;
538 }
539
540 return 0;
541 }
542
stm32_sai_set_dai_tdm_slot(struct snd_soc_dai * cpu_dai,u32 tx_mask,u32 rx_mask,int slots,int slot_width)543 static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
544 u32 rx_mask, int slots, int slot_width)
545 {
546 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
547 int slotr, slotr_mask, slot_size;
548
549 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
550 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n");
551 return 0;
552 }
553
554 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n",
555 tx_mask, rx_mask, slots, slot_width);
556
557 switch (slot_width) {
558 case 16:
559 slot_size = SAI_SLOT_SIZE_16;
560 break;
561 case 32:
562 slot_size = SAI_SLOT_SIZE_32;
563 break;
564 default:
565 slot_size = SAI_SLOT_SIZE_AUTO;
566 break;
567 }
568
569 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) |
570 SAI_XSLOTR_NBSLOT_SET(slots - 1);
571 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK;
572
573 /* tx/rx mask set in machine init, if slot number defined in DT */
574 if (STM_SAI_IS_PLAYBACK(sai)) {
575 sai->slot_mask = tx_mask;
576 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask);
577 }
578
579 if (STM_SAI_IS_CAPTURE(sai)) {
580 sai->slot_mask = rx_mask;
581 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask);
582 }
583
584 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK;
585
586 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, slotr_mask, slotr);
587
588 sai->slot_width = slot_width;
589 sai->slots = slots;
590
591 return 0;
592 }
593
stm32_sai_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)594 static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
595 {
596 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
597 int cr1, frcr = 0;
598 int cr1_mask, frcr_mask = 0;
599 int ret;
600
601 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt);
602
603 /* Do not generate master by default */
604 cr1 = SAI_XCR1_NODIV;
605 cr1_mask = SAI_XCR1_NODIV;
606
607 cr1_mask |= SAI_XCR1_PRTCFG_MASK;
608 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
609 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL);
610 goto conf_update;
611 }
612
613 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL);
614
615 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
616 /* SCK active high for all protocols */
617 case SND_SOC_DAIFMT_I2S:
618 cr1 |= SAI_XCR1_CKSTR;
619 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF;
620 break;
621 /* Left justified */
622 case SND_SOC_DAIFMT_MSB:
623 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
624 break;
625 /* Right justified */
626 case SND_SOC_DAIFMT_LSB:
627 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF;
628 break;
629 case SND_SOC_DAIFMT_DSP_A:
630 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF;
631 break;
632 case SND_SOC_DAIFMT_DSP_B:
633 frcr |= SAI_XFRCR_FSPOL;
634 break;
635 default:
636 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n",
637 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
638 return -EINVAL;
639 }
640
641 cr1_mask |= SAI_XCR1_CKSTR;
642 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF |
643 SAI_XFRCR_FSDEF;
644
645 /* DAI clock strobing. Invert setting previously set */
646 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
647 case SND_SOC_DAIFMT_NB_NF:
648 break;
649 case SND_SOC_DAIFMT_IB_NF:
650 cr1 ^= SAI_XCR1_CKSTR;
651 break;
652 case SND_SOC_DAIFMT_NB_IF:
653 frcr ^= SAI_XFRCR_FSPOL;
654 break;
655 case SND_SOC_DAIFMT_IB_IF:
656 /* Invert fs & sck */
657 cr1 ^= SAI_XCR1_CKSTR;
658 frcr ^= SAI_XFRCR_FSPOL;
659 break;
660 default:
661 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n",
662 fmt & SND_SOC_DAIFMT_INV_MASK);
663 return -EINVAL;
664 }
665 cr1_mask |= SAI_XCR1_CKSTR;
666 frcr_mask |= SAI_XFRCR_FSPOL;
667
668 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr);
669
670 /* DAI clock master masks */
671 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
672 case SND_SOC_DAIFMT_CBM_CFM:
673 /* codec is master */
674 cr1 |= SAI_XCR1_SLAVE;
675 sai->master = false;
676 break;
677 case SND_SOC_DAIFMT_CBS_CFS:
678 sai->master = true;
679 break;
680 default:
681 dev_err(cpu_dai->dev, "Unsupported mode %#x\n",
682 fmt & SND_SOC_DAIFMT_MASTER_MASK);
683 return -EINVAL;
684 }
685
686 /* Set slave mode if sub-block is synchronized with another SAI */
687 if (sai->sync) {
688 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n");
689 cr1 |= SAI_XCR1_SLAVE;
690 sai->master = false;
691 }
692
693 cr1_mask |= SAI_XCR1_SLAVE;
694
695 conf_update:
696 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
697 if (ret < 0) {
698 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
699 return ret;
700 }
701
702 sai->fmt = fmt;
703
704 return 0;
705 }
706
stm32_sai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)707 static int stm32_sai_startup(struct snd_pcm_substream *substream,
708 struct snd_soc_dai *cpu_dai)
709 {
710 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
711 int imr, cr2, ret;
712 unsigned long flags;
713
714 spin_lock_irqsave(&sai->irq_lock, flags);
715 sai->substream = substream;
716 spin_unlock_irqrestore(&sai->irq_lock, flags);
717
718 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
719 snd_pcm_hw_constraint_mask64(substream->runtime,
720 SNDRV_PCM_HW_PARAM_FORMAT,
721 SNDRV_PCM_FMTBIT_S32_LE);
722 snd_pcm_hw_constraint_single(substream->runtime,
723 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
724 }
725
726 ret = clk_prepare_enable(sai->sai_ck);
727 if (ret < 0) {
728 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret);
729 return ret;
730 }
731
732 /* Enable ITs */
733 regmap_write_bits(sai->regmap, STM_SAI_CLRFR_REGX,
734 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK);
735
736 imr = SAI_XIMR_OVRUDRIE;
737 if (STM_SAI_IS_CAPTURE(sai)) {
738 regmap_read(sai->regmap, STM_SAI_CR2_REGX, &cr2);
739 if (cr2 & SAI_XCR2_MUTECNT_MASK)
740 imr |= SAI_XIMR_MUTEDETIE;
741 }
742
743 if (sai->master)
744 imr |= SAI_XIMR_WCKCFGIE;
745 else
746 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE;
747
748 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX,
749 SAI_XIMR_MASK, imr);
750
751 return 0;
752 }
753
stm32_sai_set_config(struct snd_soc_dai * cpu_dai,struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params)754 static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai,
755 struct snd_pcm_substream *substream,
756 struct snd_pcm_hw_params *params)
757 {
758 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
759 int cr1, cr1_mask, ret;
760
761 /*
762 * DMA bursts increment is set to 4 words.
763 * SAI fifo threshold is set to half fifo, to keep enough space
764 * for DMA incoming bursts.
765 */
766 regmap_write_bits(sai->regmap, STM_SAI_CR2_REGX,
767 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK,
768 SAI_XCR2_FFLUSH |
769 SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF));
770
771 /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/
772 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
773 sai->spdif_frm_cnt = 0;
774 return 0;
775 }
776
777 /* Mode, data format and channel config */
778 cr1_mask = SAI_XCR1_DS_MASK;
779 switch (params_format(params)) {
780 case SNDRV_PCM_FORMAT_S8:
781 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8);
782 break;
783 case SNDRV_PCM_FORMAT_S16_LE:
784 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16);
785 break;
786 case SNDRV_PCM_FORMAT_S32_LE:
787 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32);
788 break;
789 default:
790 dev_err(cpu_dai->dev, "Data format not supported");
791 return -EINVAL;
792 }
793
794 cr1_mask |= SAI_XCR1_MONO;
795 if ((sai->slots == 2) && (params_channels(params) == 1))
796 cr1 |= SAI_XCR1_MONO;
797
798 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
799 if (ret < 0) {
800 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
801 return ret;
802 }
803
804 return 0;
805 }
806
stm32_sai_set_slots(struct snd_soc_dai * cpu_dai)807 static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai)
808 {
809 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
810 int slotr, slot_sz;
811
812 regmap_read(sai->regmap, STM_SAI_SLOTR_REGX, &slotr);
813
814 /*
815 * If SLOTSZ is set to auto in SLOTR, align slot width on data size
816 * By default slot width = data size, if not forced from DT
817 */
818 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK;
819 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO))
820 sai->slot_width = sai->data_size;
821
822 if (sai->slot_width < sai->data_size) {
823 dev_err(cpu_dai->dev,
824 "Data size %d larger than slot width\n",
825 sai->data_size);
826 return -EINVAL;
827 }
828
829 /* Slot number is set to 2, if not specified in DT */
830 if (!sai->slots)
831 sai->slots = 2;
832
833 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/
834 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX,
835 SAI_XSLOTR_NBSLOT_MASK,
836 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1)));
837
838 /* Set default slots mask if not already set from DT */
839 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) {
840 sai->slot_mask = (1 << sai->slots) - 1;
841 regmap_update_bits(sai->regmap,
842 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK,
843 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask));
844 }
845
846 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n",
847 sai->slots, sai->slot_width);
848
849 return 0;
850 }
851
stm32_sai_set_frame(struct snd_soc_dai * cpu_dai)852 static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai)
853 {
854 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
855 int fs_active, offset, format;
856 int frcr, frcr_mask;
857
858 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
859 sai->fs_length = sai->slot_width * sai->slots;
860
861 fs_active = sai->fs_length / 2;
862 if ((format == SND_SOC_DAIFMT_DSP_A) ||
863 (format == SND_SOC_DAIFMT_DSP_B))
864 fs_active = 1;
865
866 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1));
867 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1));
868 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK;
869
870 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n",
871 sai->fs_length, fs_active);
872
873 regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr);
874
875 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) {
876 offset = sai->slot_width - sai->data_size;
877
878 regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX,
879 SAI_XSLOTR_FBOFF_MASK,
880 SAI_XSLOTR_FBOFF_SET(offset));
881 }
882 }
883
stm32_sai_init_iec958_status(struct stm32_sai_sub_data * sai)884 static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai)
885 {
886 unsigned char *cs = sai->iec958.status;
887
888 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;
889 cs[1] = IEC958_AES1_CON_GENERAL;
890 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC;
891 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID;
892 }
893
stm32_sai_set_iec958_status(struct stm32_sai_sub_data * sai,struct snd_pcm_runtime * runtime)894 static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai,
895 struct snd_pcm_runtime *runtime)
896 {
897 if (!runtime)
898 return;
899
900 /* Force the sample rate according to runtime rate */
901 mutex_lock(&sai->ctrl_lock);
902 switch (runtime->rate) {
903 case 22050:
904 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050;
905 break;
906 case 44100:
907 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100;
908 break;
909 case 88200:
910 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200;
911 break;
912 case 176400:
913 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400;
914 break;
915 case 24000:
916 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000;
917 break;
918 case 48000:
919 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000;
920 break;
921 case 96000:
922 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000;
923 break;
924 case 192000:
925 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000;
926 break;
927 case 32000:
928 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000;
929 break;
930 default:
931 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID;
932 break;
933 }
934 mutex_unlock(&sai->ctrl_lock);
935 }
936
stm32_sai_configure_clock(struct snd_soc_dai * cpu_dai,struct snd_pcm_hw_params * params)937 static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
938 struct snd_pcm_hw_params *params)
939 {
940 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
941 int div = 0, cr1 = 0;
942 int sai_clk_rate, mclk_ratio, den;
943 unsigned int rate = params_rate(params);
944 int ret;
945
946 if (!sai->sai_mclk) {
947 ret = stm32_sai_set_parent_clock(sai, rate);
948 if (ret)
949 return ret;
950 }
951 sai_clk_rate = clk_get_rate(sai->sai_ck);
952
953 if (STM_SAI_IS_F4(sai->pdata)) {
954 /* mclk on (NODIV=0)
955 * mclk_rate = 256 * fs
956 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate
957 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise
958 * mclk off (NODIV=1)
959 * MCKDIV ignored. sck = sai_ck
960 */
961 if (!sai->mclk_rate)
962 return 0;
963
964 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) {
965 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
966 2 * sai->mclk_rate);
967 if (div < 0)
968 return div;
969 }
970 } else {
971 /*
972 * TDM mode :
973 * mclk on
974 * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0)
975 * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1)
976 * mclk off
977 * MCKDIV = sai_ck / (frl x ws) (NOMCK=1)
978 * Note: NOMCK/NODIV correspond to same bit.
979 */
980 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
981 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
982 rate * 128);
983 if (div < 0)
984 return div;
985 } else {
986 if (sai->mclk_rate) {
987 mclk_ratio = sai->mclk_rate / rate;
988 if (mclk_ratio == 512) {
989 cr1 = SAI_XCR1_OSR;
990 } else if (mclk_ratio != 256) {
991 dev_err(cpu_dai->dev,
992 "Wrong mclk ratio %d\n",
993 mclk_ratio);
994 return -EINVAL;
995 }
996
997 regmap_update_bits(sai->regmap,
998 STM_SAI_CR1_REGX,
999 SAI_XCR1_OSR, cr1);
1000
1001 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
1002 sai->mclk_rate);
1003 if (div < 0)
1004 return div;
1005 } else {
1006 /* mclk-fs not set, master clock not active */
1007 den = sai->fs_length * params_rate(params);
1008 div = stm32_sai_get_clk_div(sai, sai_clk_rate,
1009 den);
1010 if (div < 0)
1011 return div;
1012 }
1013 }
1014 }
1015
1016 return stm32_sai_set_clk_div(sai, div);
1017 }
1018
stm32_sai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)1019 static int stm32_sai_hw_params(struct snd_pcm_substream *substream,
1020 struct snd_pcm_hw_params *params,
1021 struct snd_soc_dai *cpu_dai)
1022 {
1023 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1024 int ret;
1025
1026 sai->data_size = params_width(params);
1027
1028 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
1029 /* Rate not already set in runtime structure */
1030 substream->runtime->rate = params_rate(params);
1031 stm32_sai_set_iec958_status(sai, substream->runtime);
1032 } else {
1033 ret = stm32_sai_set_slots(cpu_dai);
1034 if (ret < 0)
1035 return ret;
1036 stm32_sai_set_frame(cpu_dai);
1037 }
1038
1039 ret = stm32_sai_set_config(cpu_dai, substream, params);
1040 if (ret)
1041 return ret;
1042
1043 if (sai->master)
1044 ret = stm32_sai_configure_clock(cpu_dai, params);
1045
1046 return ret;
1047 }
1048
stm32_sai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)1049 static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd,
1050 struct snd_soc_dai *cpu_dai)
1051 {
1052 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1053 int ret;
1054
1055 switch (cmd) {
1056 case SNDRV_PCM_TRIGGER_START:
1057 case SNDRV_PCM_TRIGGER_RESUME:
1058 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1059 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n");
1060
1061 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
1062 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN);
1063
1064 /* Enable SAI */
1065 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
1066 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN);
1067 if (ret < 0)
1068 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
1069 break;
1070 case SNDRV_PCM_TRIGGER_SUSPEND:
1071 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1072 case SNDRV_PCM_TRIGGER_STOP:
1073 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n");
1074
1075 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX,
1076 SAI_XIMR_MASK, 0);
1077
1078 regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
1079 SAI_XCR1_SAIEN,
1080 (unsigned int)~SAI_XCR1_SAIEN);
1081
1082 ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
1083 SAI_XCR1_DMAEN,
1084 (unsigned int)~SAI_XCR1_DMAEN);
1085 if (ret < 0)
1086 dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
1087
1088 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1089 sai->spdif_frm_cnt = 0;
1090 break;
1091 default:
1092 return -EINVAL;
1093 }
1094
1095 return ret;
1096 }
1097
stm32_sai_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)1098 static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
1099 struct snd_soc_dai *cpu_dai)
1100 {
1101 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
1102 unsigned long flags;
1103
1104 regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0);
1105
1106 clk_disable_unprepare(sai->sai_ck);
1107
1108 spin_lock_irqsave(&sai->irq_lock, flags);
1109 sai->substream = NULL;
1110 spin_unlock_irqrestore(&sai->irq_lock, flags);
1111 }
1112
stm32_sai_pcm_new(struct snd_soc_pcm_runtime * rtd,struct snd_soc_dai * cpu_dai)1113 static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd,
1114 struct snd_soc_dai *cpu_dai)
1115 {
1116 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1117 struct snd_kcontrol_new knew = iec958_ctls;
1118
1119 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
1120 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__);
1121 knew.device = rtd->pcm->device;
1122 return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai));
1123 }
1124
1125 return 0;
1126 }
1127
stm32_sai_dai_probe(struct snd_soc_dai * cpu_dai)1128 static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai)
1129 {
1130 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1131 int cr1 = 0, cr1_mask, ret;
1132
1133 sai->cpu_dai = cpu_dai;
1134
1135 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX);
1136 /*
1137 * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice,
1138 * as it allows bytes, half-word and words transfers. (See DMA fifos
1139 * constraints).
1140 */
1141 sai->dma_params.maxburst = 4;
1142 if (sai->pdata->conf.fifo_size < 8)
1143 sai->dma_params.maxburst = 1;
1144 /* Buswidth will be set by framework at runtime */
1145 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
1146
1147 if (STM_SAI_IS_PLAYBACK(sai))
1148 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL);
1149 else
1150 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params);
1151
1152 /* Next settings are not relevant for spdif mode */
1153 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1154 return 0;
1155
1156 cr1_mask = SAI_XCR1_RX_TX;
1157 if (STM_SAI_IS_CAPTURE(sai))
1158 cr1 |= SAI_XCR1_RX_TX;
1159
1160 /* Configure synchronization */
1161 if (sai->sync == SAI_SYNC_EXTERNAL) {
1162 /* Configure synchro client and provider */
1163 ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider,
1164 sai->synco, sai->synci);
1165 if (ret)
1166 return ret;
1167 }
1168
1169 cr1_mask |= SAI_XCR1_SYNCEN_MASK;
1170 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync);
1171
1172 return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1);
1173 }
1174
1175 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = {
1176 .set_sysclk = stm32_sai_set_sysclk,
1177 .set_fmt = stm32_sai_set_dai_fmt,
1178 .set_tdm_slot = stm32_sai_set_dai_tdm_slot,
1179 .startup = stm32_sai_startup,
1180 .hw_params = stm32_sai_hw_params,
1181 .trigger = stm32_sai_trigger,
1182 .shutdown = stm32_sai_shutdown,
1183 };
1184
stm32_sai_pcm_process_spdif(struct snd_pcm_substream * substream,int channel,unsigned long hwoff,void * buf,unsigned long bytes)1185 static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream,
1186 int channel, unsigned long hwoff,
1187 void *buf, unsigned long bytes)
1188 {
1189 struct snd_pcm_runtime *runtime = substream->runtime;
1190 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1191 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
1192 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
1193 int *ptr = (int *)(runtime->dma_area + hwoff +
1194 channel * (runtime->dma_bytes / runtime->channels));
1195 ssize_t cnt = bytes_to_samples(runtime, bytes);
1196 unsigned int frm_cnt = sai->spdif_frm_cnt;
1197 unsigned int byte;
1198 unsigned int mask;
1199
1200 do {
1201 *ptr = ((*ptr >> 8) & 0x00ffffff);
1202
1203 /* Set channel status bit */
1204 byte = frm_cnt >> 3;
1205 mask = 1 << (frm_cnt - (byte << 3));
1206 if (sai->iec958.status[byte] & mask)
1207 *ptr |= 0x04000000;
1208 ptr++;
1209
1210 if (!(cnt % 2))
1211 frm_cnt++;
1212
1213 if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES)
1214 frm_cnt = 0;
1215 } while (--cnt);
1216 sai->spdif_frm_cnt = frm_cnt;
1217
1218 return 0;
1219 }
1220
1221 /* No support of mmap in S/PDIF mode */
1222 static const struct snd_pcm_hardware stm32_sai_pcm_hw_spdif = {
1223 .info = SNDRV_PCM_INFO_INTERLEAVED,
1224 .buffer_bytes_max = 8 * PAGE_SIZE,
1225 .period_bytes_min = 1024,
1226 .period_bytes_max = PAGE_SIZE,
1227 .periods_min = 2,
1228 .periods_max = 8,
1229 };
1230
1231 static const struct snd_pcm_hardware stm32_sai_pcm_hw = {
1232 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
1233 .buffer_bytes_max = 8 * PAGE_SIZE,
1234 .period_bytes_min = 1024, /* 5ms at 48kHz */
1235 .period_bytes_max = PAGE_SIZE,
1236 .periods_min = 2,
1237 .periods_max = 8,
1238 };
1239
1240 static struct snd_soc_dai_driver stm32_sai_playback_dai = {
1241 .probe = stm32_sai_dai_probe,
1242 .pcm_new = stm32_sai_pcm_new,
1243 .id = 1, /* avoid call to fmt_single_name() */
1244 .playback = {
1245 .channels_min = 1,
1246 .channels_max = 2,
1247 .rate_min = 8000,
1248 .rate_max = 192000,
1249 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1250 /* DMA does not support 24 bits transfers */
1251 .formats =
1252 SNDRV_PCM_FMTBIT_S8 |
1253 SNDRV_PCM_FMTBIT_S16_LE |
1254 SNDRV_PCM_FMTBIT_S32_LE,
1255 },
1256 .ops = &stm32_sai_pcm_dai_ops,
1257 };
1258
1259 static struct snd_soc_dai_driver stm32_sai_capture_dai = {
1260 .probe = stm32_sai_dai_probe,
1261 .id = 1, /* avoid call to fmt_single_name() */
1262 .capture = {
1263 .channels_min = 1,
1264 .channels_max = 2,
1265 .rate_min = 8000,
1266 .rate_max = 192000,
1267 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1268 /* DMA does not support 24 bits transfers */
1269 .formats =
1270 SNDRV_PCM_FMTBIT_S8 |
1271 SNDRV_PCM_FMTBIT_S16_LE |
1272 SNDRV_PCM_FMTBIT_S32_LE,
1273 },
1274 .ops = &stm32_sai_pcm_dai_ops,
1275 };
1276
1277 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = {
1278 .pcm_hardware = &stm32_sai_pcm_hw,
1279 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1280 };
1281
1282 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = {
1283 .pcm_hardware = &stm32_sai_pcm_hw_spdif,
1284 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1285 .process = stm32_sai_pcm_process_spdif,
1286 };
1287
1288 static const struct snd_soc_component_driver stm32_component = {
1289 .name = "stm32-sai",
1290 };
1291
1292 static const struct of_device_id stm32_sai_sub_ids[] = {
1293 { .compatible = "st,stm32-sai-sub-a",
1294 .data = (void *)STM_SAI_A_ID},
1295 { .compatible = "st,stm32-sai-sub-b",
1296 .data = (void *)STM_SAI_B_ID},
1297 {}
1298 };
1299 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids);
1300
stm32_sai_sub_parse_of(struct platform_device * pdev,struct stm32_sai_sub_data * sai)1301 static int stm32_sai_sub_parse_of(struct platform_device *pdev,
1302 struct stm32_sai_sub_data *sai)
1303 {
1304 struct device_node *np = pdev->dev.of_node;
1305 struct resource *res;
1306 void __iomem *base;
1307 struct of_phandle_args args;
1308 int ret;
1309
1310 if (!np)
1311 return -ENODEV;
1312
1313 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1314 base = devm_ioremap_resource(&pdev->dev, res);
1315 if (IS_ERR(base))
1316 return PTR_ERR(base);
1317
1318 sai->phys_addr = res->start;
1319
1320 sai->regmap_config = &stm32_sai_sub_regmap_config_f4;
1321 /* Note: PDM registers not available for sub-block B */
1322 if (STM_SAI_HAS_PDM(sai) && STM_SAI_IS_SUB_A(sai))
1323 sai->regmap_config = &stm32_sai_sub_regmap_config_h7;
1324
1325 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck",
1326 base, sai->regmap_config);
1327 if (IS_ERR(sai->regmap)) {
1328 dev_err(&pdev->dev, "Failed to initialize MMIO\n");
1329 return PTR_ERR(sai->regmap);
1330 }
1331
1332 /* Get direction property */
1333 if (of_property_match_string(np, "dma-names", "tx") >= 0) {
1334 sai->dir = SNDRV_PCM_STREAM_PLAYBACK;
1335 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) {
1336 sai->dir = SNDRV_PCM_STREAM_CAPTURE;
1337 } else {
1338 dev_err(&pdev->dev, "Unsupported direction\n");
1339 return -EINVAL;
1340 }
1341
1342 /* Get spdif iec60958 property */
1343 sai->spdif = false;
1344 if (of_get_property(np, "st,iec60958", NULL)) {
1345 if (!STM_SAI_HAS_SPDIF(sai) ||
1346 sai->dir == SNDRV_PCM_STREAM_CAPTURE) {
1347 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n");
1348 return -EINVAL;
1349 }
1350 stm32_sai_init_iec958_status(sai);
1351 sai->spdif = true;
1352 sai->master = true;
1353 }
1354
1355 /* Get synchronization property */
1356 args.np = NULL;
1357 ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args);
1358 if (ret < 0 && ret != -ENOENT) {
1359 dev_err(&pdev->dev, "Failed to get st,sync property\n");
1360 return ret;
1361 }
1362
1363 sai->sync = SAI_SYNC_NONE;
1364 if (args.np) {
1365 if (args.np == np) {
1366 dev_err(&pdev->dev, "%pOFn sync own reference\n", np);
1367 of_node_put(args.np);
1368 return -EINVAL;
1369 }
1370
1371 sai->np_sync_provider = of_get_parent(args.np);
1372 if (!sai->np_sync_provider) {
1373 dev_err(&pdev->dev, "%pOFn parent node not found\n",
1374 np);
1375 of_node_put(args.np);
1376 return -ENODEV;
1377 }
1378
1379 sai->sync = SAI_SYNC_INTERNAL;
1380 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) {
1381 if (!STM_SAI_HAS_EXT_SYNC(sai)) {
1382 dev_err(&pdev->dev,
1383 "External synchro not supported\n");
1384 of_node_put(args.np);
1385 return -EINVAL;
1386 }
1387 sai->sync = SAI_SYNC_EXTERNAL;
1388
1389 sai->synci = args.args[0];
1390 if (sai->synci < 1 ||
1391 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) {
1392 dev_err(&pdev->dev, "Wrong SAI index\n");
1393 of_node_put(args.np);
1394 return -EINVAL;
1395 }
1396
1397 if (of_property_match_string(args.np, "compatible",
1398 "st,stm32-sai-sub-a") >= 0)
1399 sai->synco = STM_SAI_SYNC_OUT_A;
1400
1401 if (of_property_match_string(args.np, "compatible",
1402 "st,stm32-sai-sub-b") >= 0)
1403 sai->synco = STM_SAI_SYNC_OUT_B;
1404
1405 if (!sai->synco) {
1406 dev_err(&pdev->dev, "Unknown SAI sub-block\n");
1407 of_node_put(args.np);
1408 return -EINVAL;
1409 }
1410 }
1411
1412 dev_dbg(&pdev->dev, "%s synchronized with %s\n",
1413 pdev->name, args.np->full_name);
1414 }
1415
1416 of_node_put(args.np);
1417 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck");
1418 if (IS_ERR(sai->sai_ck)) {
1419 dev_err(&pdev->dev, "Missing kernel clock sai_ck\n");
1420 return PTR_ERR(sai->sai_ck);
1421 }
1422
1423 if (STM_SAI_IS_F4(sai->pdata))
1424 return 0;
1425
1426 /* Register mclk provider if requested */
1427 if (of_find_property(np, "#clock-cells", NULL)) {
1428 ret = stm32_sai_add_mclk_provider(sai);
1429 if (ret < 0)
1430 return ret;
1431 } else {
1432 sai->sai_mclk = devm_clk_get(&pdev->dev, "MCLK");
1433 if (IS_ERR(sai->sai_mclk)) {
1434 if (PTR_ERR(sai->sai_mclk) != -ENOENT)
1435 return PTR_ERR(sai->sai_mclk);
1436 sai->sai_mclk = NULL;
1437 }
1438 }
1439
1440 return 0;
1441 }
1442
stm32_sai_sub_probe(struct platform_device * pdev)1443 static int stm32_sai_sub_probe(struct platform_device *pdev)
1444 {
1445 struct stm32_sai_sub_data *sai;
1446 const struct of_device_id *of_id;
1447 const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config;
1448 int ret;
1449
1450 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
1451 if (!sai)
1452 return -ENOMEM;
1453
1454 of_id = of_match_device(stm32_sai_sub_ids, &pdev->dev);
1455 if (!of_id)
1456 return -EINVAL;
1457 sai->id = (uintptr_t)of_id->data;
1458
1459 sai->pdev = pdev;
1460 mutex_init(&sai->ctrl_lock);
1461 spin_lock_init(&sai->irq_lock);
1462 platform_set_drvdata(pdev, sai);
1463
1464 sai->pdata = dev_get_drvdata(pdev->dev.parent);
1465 if (!sai->pdata) {
1466 dev_err(&pdev->dev, "Parent device data not available\n");
1467 return -EINVAL;
1468 }
1469
1470 ret = stm32_sai_sub_parse_of(pdev, sai);
1471 if (ret)
1472 return ret;
1473
1474 if (STM_SAI_IS_PLAYBACK(sai))
1475 sai->cpu_dai_drv = stm32_sai_playback_dai;
1476 else
1477 sai->cpu_dai_drv = stm32_sai_capture_dai;
1478 sai->cpu_dai_drv.name = dev_name(&pdev->dev);
1479
1480 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr,
1481 IRQF_SHARED, dev_name(&pdev->dev), sai);
1482 if (ret) {
1483 dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
1484 return ret;
1485 }
1486
1487 ret = devm_snd_soc_register_component(&pdev->dev, &stm32_component,
1488 &sai->cpu_dai_drv, 1);
1489 if (ret)
1490 return ret;
1491
1492 if (STM_SAI_PROTOCOL_IS_SPDIF(sai))
1493 conf = &stm32_sai_pcm_config_spdif;
1494
1495 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, conf, 0);
1496 if (ret) {
1497 dev_err(&pdev->dev, "Could not register pcm dma\n");
1498 return ret;
1499 }
1500
1501 return 0;
1502 }
1503
1504 #ifdef CONFIG_PM_SLEEP
stm32_sai_sub_suspend(struct device * dev)1505 static int stm32_sai_sub_suspend(struct device *dev)
1506 {
1507 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev);
1508
1509 regcache_cache_only(sai->regmap, true);
1510 regcache_mark_dirty(sai->regmap);
1511 return 0;
1512 }
1513
stm32_sai_sub_resume(struct device * dev)1514 static int stm32_sai_sub_resume(struct device *dev)
1515 {
1516 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev);
1517
1518 regcache_cache_only(sai->regmap, false);
1519 return regcache_sync(sai->regmap);
1520 }
1521 #endif /* CONFIG_PM_SLEEP */
1522
1523 static const struct dev_pm_ops stm32_sai_sub_pm_ops = {
1524 SET_SYSTEM_SLEEP_PM_OPS(stm32_sai_sub_suspend, stm32_sai_sub_resume)
1525 };
1526
1527 static struct platform_driver stm32_sai_sub_driver = {
1528 .driver = {
1529 .name = "st,stm32-sai-sub",
1530 .of_match_table = stm32_sai_sub_ids,
1531 .pm = &stm32_sai_sub_pm_ops,
1532 },
1533 .probe = stm32_sai_sub_probe,
1534 };
1535
1536 module_platform_driver(stm32_sai_sub_driver);
1537
1538 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface");
1539 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>");
1540 MODULE_ALIAS("platform:st,stm32-sai-sub");
1541 MODULE_LICENSE("GPL v2");
1542
