1 /* Copyright Statement:
2 *
3 * This software/firmware and related documentation ("MediaTek Software") are
4 * protected under relevant copyright laws. The information contained herein
5 * is confidential and proprietary to MediaTek Inc. and/or its licensors.
6 * Without the prior written permission of MediaTek inc. and/or its licensors,
7 * any reproduction, modification, use or disclosure of MediaTek Software,
8 * and information contained herein, in whole or in part, shall be strictly prohibited.
9 *
10 * MediaTek Inc. (C) 2010. All rights reserved.
11 *
12 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
13 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
14 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
15 * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
18 * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
19 * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
20 * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
21 * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
22 * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
23 * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
24 * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
25 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
26 * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
27 * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
28 * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
29 * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
30 *
31 * The following software/firmware and/or related documentation ("MediaTek Software")
32 * have been modified by MediaTek Inc. All revisions are subject to any receiver's
33 * applicable license agreements with MediaTek Inc.
34 */
35
36 #include <linux/module.h>
37 #include <linux/delay.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/spinlock.h>
40 #include <linux/platform_device.h>
41
42 #include <linux/mmc/host.h>
43 #include <linux/mmc/mmc.h>
44 #include <linux/mmc/sd.h>
45 #include <linux/mmc/sdio.h>
46
47 #include <asm/mach-ralink/ralink_regs.h>
48
49 #include "board.h"
50 #include "dbg.h"
51 #include "mt6575_sd.h"
52
53 #ifdef CONFIG_SOC_MT7621
54 #define RALINK_SYSCTL_BASE 0xbe000000
55 #else
56 #define RALINK_SYSCTL_BASE 0xb0000000
57 #endif
58
59 #define DRV_NAME "mtk-sd"
60
61 #if defined(CONFIG_SOC_MT7620)
62 #define HOST_MAX_MCLK (48000000) /* +/- by chhung */
63 #elif defined(CONFIG_SOC_MT7621)
64 #define HOST_MAX_MCLK (50000000) /* +/- by chhung */
65 #endif
66 #define HOST_MIN_MCLK (260000)
67
68 #define HOST_MAX_BLKSZ (2048)
69
70 #define MSDC_OCR_AVAIL (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)
71
72 #define GPIO_PULL_DOWN (0)
73 #define GPIO_PULL_UP (1)
74
75 #if 0 /* --- by chhung */
76 #define MSDC_CLKSRC_REG (0xf100000C)
77 #define PDN_REG (0xF1000010)
78 #endif /* end of --- */
79
80 #define DEFAULT_DEBOUNCE (8) /* 8 cycles */
81 #define DEFAULT_DTOC (40) /* data timeout counter. 65536x40 sclk. */
82
83 #define CMD_TIMEOUT (HZ / 10) /* 100ms */
84 #define DAT_TIMEOUT (HZ / 2 * 5) /* 500ms x5 */
85
86 #define MAX_DMA_CNT (64 * 1024 - 512) /* a single transaction for WIFI may be 50K*/
87
88 #define MAX_GPD_NUM (1 + 1) /* one null gpd */
89 #define MAX_BD_NUM (1024)
90
91 #define MAX_HW_SGMTS (MAX_BD_NUM)
92 #define MAX_SGMT_SZ (MAX_DMA_CNT)
93 #define MAX_REQ_SZ (MAX_SGMT_SZ * 8)
94
95 static int cd_active_low = 1;
96
97 //=================================
98 #define PERI_MSDC0_PDN (15)
99 //#define PERI_MSDC1_PDN (16)
100 //#define PERI_MSDC2_PDN (17)
101 //#define PERI_MSDC3_PDN (18)
102
103 #if 0 /* --- by chhung */
104 /* gate means clock power down */
105 static int g_clk_gate = 0;
106 #define msdc_gate_clock(id) \
107 do { \
108 g_clk_gate &= ~(1 << ((id) + PERI_MSDC0_PDN)); \
109 } while (0)
110 /* not like power down register. 1 means clock on. */
111 #define msdc_ungate_clock(id) \
112 do { \
113 g_clk_gate |= 1 << ((id) + PERI_MSDC0_PDN); \
114 } while (0)
115
116 // do we need sync object or not
117 void msdc_clk_status(int *status)
118 {
119 *status = g_clk_gate;
120 }
121 #endif /* end of --- */
122
123 /* +++ by chhung */
124 struct msdc_hw msdc0_hw = {
125 .clk_src = 0,
126 .flags = MSDC_CD_PIN_EN | MSDC_REMOVABLE,
127 // .flags = MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE,
128 };
129
130 /* end of +++ */
131
132 static int msdc_rsp[] = {
133 0, /* RESP_NONE */
134 1, /* RESP_R1 */
135 2, /* RESP_R2 */
136 3, /* RESP_R3 */
137 4, /* RESP_R4 */
138 1, /* RESP_R5 */
139 1, /* RESP_R6 */
140 1, /* RESP_R7 */
141 7, /* RESP_R1b */
142 };
143
144 #define msdc_dma_on() sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO)
145
msdc_reset_hw(struct msdc_host * host)146 static void msdc_reset_hw(struct msdc_host *host)
147 {
148 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
149 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
150 cpu_relax();
151 }
152
153 #define msdc_clr_int() \
154 do { \
155 volatile u32 val = readl(host->base + MSDC_INT); \
156 writel(val, host->base + MSDC_INT); \
157 } while (0)
158
msdc_clr_fifo(struct msdc_host * host)159 static void msdc_clr_fifo(struct msdc_host *host)
160 {
161 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
162 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
163 cpu_relax();
164 }
165
166 #define msdc_irq_save(val) \
167 do { \
168 val = readl(host->base + MSDC_INTEN); \
169 sdr_clr_bits(host->base + MSDC_INTEN, val); \
170 } while (0)
171
172 #define msdc_irq_restore(val) \
173 do { \
174 sdr_set_bits(host->base + MSDC_INTEN, val); \
175 } while (0)
176
177 /* clock source for host: global */
178 #if defined(CONFIG_SOC_MT7620)
179 static u32 hclks[] = {48000000}; /* +/- by chhung */
180 #elif defined(CONFIG_SOC_MT7621)
181 static u32 hclks[] = {50000000}; /* +/- by chhung */
182 #endif
183
184 //============================================
185 // the power for msdc host controller: global
186 // always keep the VMC on.
187 //============================================
188 #define msdc_vcore_on(host) \
189 do { \
190 INIT_MSG("[+]VMC ref. count<%d>", ++host->pwr_ref); \
191 (void)hwPowerOn(MT65XX_POWER_LDO_VMC, VOL_3300, "SD"); \
192 } while (0)
193 #define msdc_vcore_off(host) \
194 do { \
195 INIT_MSG("[-]VMC ref. count<%d>", --host->pwr_ref); \
196 (void)hwPowerDown(MT65XX_POWER_LDO_VMC, "SD"); \
197 } while (0)
198
199 //====================================
200 // the vdd output for card: global
201 // always keep the VMCH on.
202 //====================================
203 #define msdc_vdd_on(host) \
204 do { \
205 (void)hwPowerOn(MT65XX_POWER_LDO_VMCH, VOL_3300, "SD"); \
206 } while (0)
207 #define msdc_vdd_off(host) \
208 do { \
209 (void)hwPowerDown(MT65XX_POWER_LDO_VMCH, "SD"); \
210 } while (0)
211
212 #define sdc_is_busy() (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY)
213 #define sdc_is_cmd_busy() (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY)
214
215 #define sdc_send_cmd(cmd, arg) \
216 do { \
217 writel((arg), host->base + SDC_ARG); \
218 writel((cmd), host->base + SDC_CMD); \
219 } while (0)
220
221 /* +++ by chhung */
222 #ifndef __ASSEMBLY__
223 #define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
224 #else
225 #define PHYSADDR(a) ((a) & 0x1fffffff)
226 #endif
227 /* end of +++ */
228 static unsigned int msdc_do_command(struct msdc_host *host,
229 struct mmc_command *cmd,
230 int tune,
231 unsigned long timeout);
232
233 static int msdc_tune_cmdrsp(struct msdc_host *host, struct mmc_command *cmd);
234
235 #ifdef MT6575_SD_DEBUG
msdc_dump_card_status(struct msdc_host * host,u32 status)236 static void msdc_dump_card_status(struct msdc_host *host, u32 status)
237 {
238 /* N_MSG is currently a no-op */
239 #if 0
240 static char *state[] = {
241 "Idle", /* 0 */
242 "Ready", /* 1 */
243 "Ident", /* 2 */
244 "Stby", /* 3 */
245 "Tran", /* 4 */
246 "Data", /* 5 */
247 "Rcv", /* 6 */
248 "Prg", /* 7 */
249 "Dis", /* 8 */
250 "Reserved", /* 9 */
251 "Reserved", /* 10 */
252 "Reserved", /* 11 */
253 "Reserved", /* 12 */
254 "Reserved", /* 13 */
255 "Reserved", /* 14 */
256 "I/O mode", /* 15 */
257 };
258 #endif
259 if (status & R1_OUT_OF_RANGE)
260 N_MSG(RSP, "[CARD_STATUS] Out of Range");
261 if (status & R1_ADDRESS_ERROR)
262 N_MSG(RSP, "[CARD_STATUS] Address Error");
263 if (status & R1_BLOCK_LEN_ERROR)
264 N_MSG(RSP, "[CARD_STATUS] Block Len Error");
265 if (status & R1_ERASE_SEQ_ERROR)
266 N_MSG(RSP, "[CARD_STATUS] Erase Seq Error");
267 if (status & R1_ERASE_PARAM)
268 N_MSG(RSP, "[CARD_STATUS] Erase Param");
269 if (status & R1_WP_VIOLATION)
270 N_MSG(RSP, "[CARD_STATUS] WP Violation");
271 if (status & R1_CARD_IS_LOCKED)
272 N_MSG(RSP, "[CARD_STATUS] Card is Locked");
273 if (status & R1_LOCK_UNLOCK_FAILED)
274 N_MSG(RSP, "[CARD_STATUS] Lock/Unlock Failed");
275 if (status & R1_COM_CRC_ERROR)
276 N_MSG(RSP, "[CARD_STATUS] Command CRC Error");
277 if (status & R1_ILLEGAL_COMMAND)
278 N_MSG(RSP, "[CARD_STATUS] Illegal Command");
279 if (status & R1_CARD_ECC_FAILED)
280 N_MSG(RSP, "[CARD_STATUS] Card ECC Failed");
281 if (status & R1_CC_ERROR)
282 N_MSG(RSP, "[CARD_STATUS] CC Error");
283 if (status & R1_ERROR)
284 N_MSG(RSP, "[CARD_STATUS] Error");
285 if (status & R1_UNDERRUN)
286 N_MSG(RSP, "[CARD_STATUS] Underrun");
287 if (status & R1_OVERRUN)
288 N_MSG(RSP, "[CARD_STATUS] Overrun");
289 if (status & R1_CID_CSD_OVERWRITE)
290 N_MSG(RSP, "[CARD_STATUS] CID/CSD Overwrite");
291 if (status & R1_WP_ERASE_SKIP)
292 N_MSG(RSP, "[CARD_STATUS] WP Eraser Skip");
293 if (status & R1_CARD_ECC_DISABLED)
294 N_MSG(RSP, "[CARD_STATUS] Card ECC Disabled");
295 if (status & R1_ERASE_RESET)
296 N_MSG(RSP, "[CARD_STATUS] Erase Reset");
297 if (status & R1_READY_FOR_DATA)
298 N_MSG(RSP, "[CARD_STATUS] Ready for Data");
299 if (status & R1_SWITCH_ERROR)
300 N_MSG(RSP, "[CARD_STATUS] Switch error");
301 if (status & R1_APP_CMD)
302 N_MSG(RSP, "[CARD_STATUS] App Command");
303
304 N_MSG(RSP, "[CARD_STATUS] '%s' State", state[R1_CURRENT_STATE(status)]);
305 }
306
msdc_dump_ocr_reg(struct msdc_host * host,u32 resp)307 static void msdc_dump_ocr_reg(struct msdc_host *host, u32 resp)
308 {
309 if (resp & (1 << 7))
310 N_MSG(RSP, "[OCR] Low Voltage Range");
311 if (resp & (1 << 15))
312 N_MSG(RSP, "[OCR] 2.7-2.8 volt");
313 if (resp & (1 << 16))
314 N_MSG(RSP, "[OCR] 2.8-2.9 volt");
315 if (resp & (1 << 17))
316 N_MSG(RSP, "[OCR] 2.9-3.0 volt");
317 if (resp & (1 << 18))
318 N_MSG(RSP, "[OCR] 3.0-3.1 volt");
319 if (resp & (1 << 19))
320 N_MSG(RSP, "[OCR] 3.1-3.2 volt");
321 if (resp & (1 << 20))
322 N_MSG(RSP, "[OCR] 3.2-3.3 volt");
323 if (resp & (1 << 21))
324 N_MSG(RSP, "[OCR] 3.3-3.4 volt");
325 if (resp & (1 << 22))
326 N_MSG(RSP, "[OCR] 3.4-3.5 volt");
327 if (resp & (1 << 23))
328 N_MSG(RSP, "[OCR] 3.5-3.6 volt");
329 if (resp & (1 << 24))
330 N_MSG(RSP, "[OCR] Switching to 1.8V Accepted (S18A)");
331 if (resp & (1 << 30))
332 N_MSG(RSP, "[OCR] Card Capacity Status (CCS)");
333 if (resp & (1 << 31))
334 N_MSG(RSP, "[OCR] Card Power Up Status (Idle)");
335 else
336 N_MSG(RSP, "[OCR] Card Power Up Status (Busy)");
337 }
338
msdc_dump_rca_resp(struct msdc_host * host,u32 resp)339 static void msdc_dump_rca_resp(struct msdc_host *host, u32 resp)
340 {
341 u32 status = (((resp >> 15) & 0x1) << 23) |
342 (((resp >> 14) & 0x1) << 22) |
343 (((resp >> 13) & 0x1) << 19) |
344 (resp & 0x1fff);
345
346 N_MSG(RSP, "[RCA] 0x%.4x", resp >> 16);
347 msdc_dump_card_status(host, status);
348 }
349
msdc_dump_io_resp(struct msdc_host * host,u32 resp)350 static void msdc_dump_io_resp(struct msdc_host *host, u32 resp)
351 {
352 u32 flags = (resp >> 8) & 0xFF;
353 #if 0
354 char *state[] = {"DIS", "CMD", "TRN", "RFU"};
355 #endif
356 if (flags & (1 << 7))
357 N_MSG(RSP, "[IO] COM_CRC_ERR");
358 if (flags & (1 << 6))
359 N_MSG(RSP, "[IO] Illegal command");
360 if (flags & (1 << 3))
361 N_MSG(RSP, "[IO] Error");
362 if (flags & (1 << 2))
363 N_MSG(RSP, "[IO] RFU");
364 if (flags & (1 << 1))
365 N_MSG(RSP, "[IO] Function number error");
366 if (flags & (1 << 0))
367 N_MSG(RSP, "[IO] Out of range");
368
369 N_MSG(RSP, "[IO] State: %s, Data:0x%x", state[(resp >> 12) & 0x3], resp & 0xFF);
370 }
371 #endif
372
msdc_set_timeout(struct msdc_host * host,u32 ns,u32 clks)373 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
374 {
375 u32 timeout, clk_ns;
376
377 host->timeout_ns = ns;
378 host->timeout_clks = clks;
379
380 clk_ns = 1000000000UL / host->sclk;
381 timeout = ns / clk_ns + clks;
382 timeout = timeout >> 16; /* in 65536 sclk cycle unit */
383 timeout = timeout > 1 ? timeout - 1 : 0;
384 timeout = timeout > 255 ? 255 : timeout;
385
386 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout);
387
388 N_MSG(OPS, "Set read data timeout: %dns %dclks -> %d x 65536 cycles",
389 ns, clks, timeout + 1);
390 }
391
msdc_tasklet_card(struct work_struct * work)392 static void msdc_tasklet_card(struct work_struct *work)
393 {
394 struct msdc_host *host = (struct msdc_host *)container_of(work,
395 struct msdc_host, card_delaywork.work);
396 u32 inserted;
397 u32 status = 0;
398 //u32 change = 0;
399
400 spin_lock(&host->lock);
401
402 status = readl(host->base + MSDC_PS);
403 if (cd_active_low)
404 inserted = (status & MSDC_PS_CDSTS) ? 0 : 1;
405 else
406 inserted = (status & MSDC_PS_CDSTS) ? 1 : 0;
407
408 #if 0
409 change = host->card_inserted ^ inserted;
410 host->card_inserted = inserted;
411
412 if (change && !host->suspend) {
413 if (inserted)
414 host->mmc->f_max = HOST_MAX_MCLK; // work around
415 mmc_detect_change(host->mmc, msecs_to_jiffies(20));
416 }
417 #else /* Make sure: handle the last interrupt */
418 host->card_inserted = inserted;
419
420 if (!host->suspend) {
421 host->mmc->f_max = HOST_MAX_MCLK;
422 mmc_detect_change(host->mmc, msecs_to_jiffies(20));
423 }
424
425 IRQ_MSG("card found<%s>", inserted ? "inserted" : "removed");
426 #endif
427
428 spin_unlock(&host->lock);
429 }
430
431 #if 0 /* --- by chhung */
432 /* For E2 only */
433 static u8 clk_src_bit[4] = {
434 0, 3, 5, 7
435 };
436
437 static void msdc_select_clksrc(struct msdc_host *host, unsigned char clksrc)
438 {
439 u32 val;
440
441 BUG_ON(clksrc > 3);
442 INIT_MSG("set clock source to <%d>", clksrc);
443
444 val = readl(host->base + MSDC_CLKSRC_REG);
445 if (readl(host->base + MSDC_ECO_VER) >= 4) {
446 val &= ~(0x3 << clk_src_bit[host->id]);
447 val |= clksrc << clk_src_bit[host->id];
448 } else {
449 val &= ~0x3; val |= clksrc;
450 }
451 writel(val, host->base + MSDC_CLKSRC_REG);
452
453 host->hclk = hclks[clksrc];
454 host->hw->clk_src = clksrc;
455 }
456 #endif /* end of --- */
457
msdc_set_mclk(struct msdc_host * host,int ddr,unsigned int hz)458 static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz)
459 {
460 //struct msdc_hw *hw = host->hw;
461 u32 mode;
462 u32 flags;
463 u32 div;
464 u32 sclk;
465 u32 hclk = host->hclk;
466 //u8 clksrc = hw->clk_src;
467
468 if (!hz) { // set mmc system clock to 0 ?
469 //ERR_MSG("set mclk to 0!!!");
470 msdc_reset_hw(host);
471 return;
472 }
473
474 msdc_irq_save(flags);
475
476 if (ddr) {
477 mode = 0x2; /* ddr mode and use divisor */
478 if (hz >= (hclk >> 2)) {
479 div = 1; /* mean div = 1/4 */
480 sclk = hclk >> 2; /* sclk = clk / 4 */
481 } else {
482 div = (hclk + ((hz << 2) - 1)) / (hz << 2);
483 sclk = (hclk >> 2) / div;
484 }
485 } else if (hz >= hclk) { /* bug fix */
486 mode = 0x1; /* no divisor and divisor is ignored */
487 div = 0;
488 sclk = hclk;
489 } else {
490 mode = 0x0; /* use divisor */
491 if (hz >= (hclk >> 1)) {
492 div = 0; /* mean div = 1/2 */
493 sclk = hclk >> 1; /* sclk = clk / 2 */
494 } else {
495 div = (hclk + ((hz << 2) - 1)) / (hz << 2);
496 sclk = (hclk >> 2) / div;
497 }
498 }
499
500 /* set clock mode and divisor */
501 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, mode);
502 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKDIV, div);
503
504 /* wait clock stable */
505 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
506 cpu_relax();
507
508 host->sclk = sclk;
509 host->mclk = hz;
510 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); // need?
511
512 INIT_MSG("================");
513 INIT_MSG("!!! Set<%dKHz> Source<%dKHz> -> sclk<%dKHz>", hz / 1000, hclk / 1000, sclk / 1000);
514 INIT_MSG("================");
515
516 msdc_irq_restore(flags);
517 }
518
519 /* Fix me. when need to abort */
msdc_abort_data(struct msdc_host * host)520 static void msdc_abort_data(struct msdc_host *host)
521 {
522 struct mmc_command *stop = host->mrq->stop;
523
524 ERR_MSG("Need to Abort.");
525
526 msdc_reset_hw(host);
527 msdc_clr_fifo(host);
528 msdc_clr_int();
529
530 // need to check FIFO count 0 ?
531
532 if (stop) { /* try to stop, but may not success */
533 ERR_MSG("stop when abort CMD<%d>", stop->opcode);
534 (void)msdc_do_command(host, stop, 0, CMD_TIMEOUT);
535 }
536
537 //if (host->mclk >= 25000000) {
538 // msdc_set_mclk(host, 0, host->mclk >> 1);
539 //}
540 }
541
542 #if 0 /* --- by chhung */
543 static void msdc_pin_config(struct msdc_host *host, int mode)
544 {
545 struct msdc_hw *hw = host->hw;
546 int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
547
548 /* Config WP pin */
549 if (hw->flags & MSDC_WP_PIN_EN) {
550 if (hw->config_gpio_pin) /* NULL */
551 hw->config_gpio_pin(MSDC_WP_PIN, pull);
552 }
553
554 switch (mode) {
555 case MSDC_PIN_PULL_UP:
556 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 1); /* Check & FIXME */
557 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
558 sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 1);
559 sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
560 sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 1);
561 sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
562 break;
563 case MSDC_PIN_PULL_DOWN:
564 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
565 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 1); /* Check & FIXME */
566 sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
567 sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 1);
568 sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
569 sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 1);
570 break;
571 case MSDC_PIN_PULL_NONE:
572 default:
573 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
574 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
575 sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
576 sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
577 sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
578 sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
579 break;
580 }
581
582 N_MSG(CFG, "Pins mode(%d), down(%d), up(%d)",
583 mode, MSDC_PIN_PULL_DOWN, MSDC_PIN_PULL_UP);
584 }
585
586 void msdc_pin_reset(struct msdc_host *host, int mode)
587 {
588 struct msdc_hw *hw = (struct msdc_hw *)host->hw;
589 int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
590
591 /* Config reset pin */
592 if (hw->flags & MSDC_RST_PIN_EN) {
593 if (hw->config_gpio_pin) /* NULL */
594 hw->config_gpio_pin(MSDC_RST_PIN, pull);
595
596 if (mode == MSDC_PIN_PULL_UP)
597 sdr_clr_bits(host->base + EMMC_IOCON, EMMC_IOCON_BOOTRST);
598 else
599 sdr_set_bits(host->base + EMMC_IOCON, EMMC_IOCON_BOOTRST);
600 }
601 }
602
603 static void msdc_core_power(struct msdc_host *host, int on)
604 {
605 N_MSG(CFG, "Turn %s %s power (copower: %d -> %d)",
606 on ? "on" : "off", "core", host->core_power, on);
607
608 if (on && host->core_power == 0) {
609 msdc_vcore_on(host);
610 host->core_power = 1;
611 msleep(1);
612 } else if (!on && host->core_power == 1) {
613 msdc_vcore_off(host);
614 host->core_power = 0;
615 msleep(1);
616 }
617 }
618
619 static void msdc_host_power(struct msdc_host *host, int on)
620 {
621 N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "host");
622
623 if (on) {
624 //msdc_core_power(host, 1); // need do card detection.
625 msdc_pin_reset(host, MSDC_PIN_PULL_UP);
626 } else {
627 msdc_pin_reset(host, MSDC_PIN_PULL_DOWN);
628 //msdc_core_power(host, 0);
629 }
630 }
631
632 static void msdc_card_power(struct msdc_host *host, int on)
633 {
634 N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "card");
635
636 if (on) {
637 msdc_pin_config(host, MSDC_PIN_PULL_UP);
638 //msdc_vdd_on(host); // need todo card detection.
639 msleep(1);
640 } else {
641 //msdc_vdd_off(host);
642 msdc_pin_config(host, MSDC_PIN_PULL_DOWN);
643 msleep(1);
644 }
645 }
646
647 static void msdc_set_power_mode(struct msdc_host *host, u8 mode)
648 {
649 N_MSG(CFG, "Set power mode(%d)", mode);
650
651 if (host->power_mode == MMC_POWER_OFF && mode != MMC_POWER_OFF) {
652 msdc_host_power(host, 1);
653 msdc_card_power(host, 1);
654 } else if (host->power_mode != MMC_POWER_OFF && mode == MMC_POWER_OFF) {
655 msdc_card_power(host, 0);
656 msdc_host_power(host, 0);
657 }
658 host->power_mode = mode;
659 }
660 #endif /* end of --- */
661
662 #ifdef CONFIG_PM
663 /*
664 register as callback function of WIFI(combo_sdio_register_pm) .
665 can called by msdc_drv_suspend/resume too.
666 */
msdc_pm(pm_message_t state,void * data)667 static void msdc_pm(pm_message_t state, void *data)
668 {
669 struct msdc_host *host = (struct msdc_host *)data;
670 int evt = state.event;
671
672 if (evt == PM_EVENT_USER_RESUME || evt == PM_EVENT_USER_SUSPEND) {
673 INIT_MSG("USR_%s: suspend<%d> power<%d>",
674 evt == PM_EVENT_USER_RESUME ? "EVENT_USER_RESUME" : "EVENT_USER_SUSPEND",
675 host->suspend, host->power_mode);
676 }
677
678 if (evt == PM_EVENT_SUSPEND || evt == PM_EVENT_USER_SUSPEND) {
679 if (host->suspend) /* already suspend */ /* default 0*/
680 return;
681
682 /* for memory card. already power off by mmc */
683 if (evt == PM_EVENT_SUSPEND && host->power_mode == MMC_POWER_OFF)
684 return;
685
686 host->suspend = 1;
687 host->pm_state = state; /* default PMSG_RESUME */
688
689 } else if (evt == PM_EVENT_RESUME || evt == PM_EVENT_USER_RESUME) {
690 if (!host->suspend) {
691 //ERR_MSG("warning: already resume");
692 return;
693 }
694
695 /* No PM resume when USR suspend */
696 if (evt == PM_EVENT_RESUME && host->pm_state.event == PM_EVENT_USER_SUSPEND) {
697 ERR_MSG("PM Resume when in USR Suspend"); /* won't happen. */
698 return;
699 }
700
701 host->suspend = 0;
702 host->pm_state = state;
703
704 }
705 }
706 #endif
707
msdc_cmd_find_resp(struct mmc_command * cmd)708 static inline u32 msdc_cmd_find_resp(struct mmc_command *cmd)
709 {
710 u32 opcode = cmd->opcode;
711 u32 resp;
712
713 if (opcode == MMC_SET_RELATIVE_ADDR) {
714 resp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1;
715 } else if (opcode == MMC_FAST_IO) {
716 resp = RESP_R4;
717 } else if (opcode == MMC_GO_IRQ_STATE) {
718 resp = RESP_R5;
719 } else if (opcode == MMC_SELECT_CARD) {
720 resp = (cmd->arg != 0) ? RESP_R1B : RESP_NONE;
721 } else if (opcode == SD_IO_RW_DIRECT || opcode == SD_IO_RW_EXTENDED) {
722 resp = RESP_R1; /* SDIO workaround. */
723 } else if (opcode == SD_SEND_IF_COND && (mmc_cmd_type(cmd) == MMC_CMD_BCR)) {
724 resp = RESP_R1;
725 } else {
726 switch (mmc_resp_type(cmd)) {
727 case MMC_RSP_R1:
728 resp = RESP_R1;
729 break;
730 case MMC_RSP_R1B:
731 resp = RESP_R1B;
732 break;
733 case MMC_RSP_R2:
734 resp = RESP_R2;
735 break;
736 case MMC_RSP_R3:
737 resp = RESP_R3;
738 break;
739 case MMC_RSP_NONE:
740 default:
741 resp = RESP_NONE;
742 break;
743 }
744 }
745
746 return resp;
747 }
748
749 /*--------------------------------------------------------------------------*/
750 /* mmc_host_ops members */
751 /*--------------------------------------------------------------------------*/
msdc_command_start(struct msdc_host * host,struct mmc_command * cmd,unsigned long timeout)752 static unsigned int msdc_command_start(struct msdc_host *host,
753 struct mmc_command *cmd,
754 unsigned long timeout)
755 {
756 u32 opcode = cmd->opcode;
757 u32 rawcmd;
758 u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
759 MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
760 MSDC_INT_ACMD19_DONE;
761
762 u32 resp;
763 unsigned long tmo;
764
765 /* Protocol layer does not provide response type, but our hardware needs
766 * to know exact type, not just size!
767 */
768 resp = msdc_cmd_find_resp(cmd);
769
770 cmd->error = 0;
771 /* rawcmd :
772 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
773 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
774 */
775 rawcmd = opcode | msdc_rsp[resp] << 7 | host->blksz << 16;
776
777 if (opcode == MMC_READ_MULTIPLE_BLOCK) {
778 rawcmd |= (2 << 11);
779 } else if (opcode == MMC_READ_SINGLE_BLOCK) {
780 rawcmd |= (1 << 11);
781 } else if (opcode == MMC_WRITE_MULTIPLE_BLOCK) {
782 rawcmd |= ((2 << 11) | (1 << 13));
783 } else if (opcode == MMC_WRITE_BLOCK) {
784 rawcmd |= ((1 << 11) | (1 << 13));
785 } else if (opcode == SD_IO_RW_EXTENDED) {
786 if (cmd->data->flags & MMC_DATA_WRITE)
787 rawcmd |= (1 << 13);
788 if (cmd->data->blocks > 1)
789 rawcmd |= (2 << 11);
790 else
791 rawcmd |= (1 << 11);
792 } else if (opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int)-1) {
793 rawcmd |= (1 << 14);
794 } else if ((opcode == SD_APP_SEND_SCR) ||
795 (opcode == SD_APP_SEND_NUM_WR_BLKS) ||
796 (opcode == SD_SWITCH && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
797 (opcode == SD_APP_SD_STATUS && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
798 (opcode == MMC_SEND_EXT_CSD && (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) {
799 rawcmd |= (1 << 11);
800 } else if (opcode == MMC_STOP_TRANSMISSION) {
801 rawcmd |= (1 << 14);
802 rawcmd &= ~(0x0FFF << 16);
803 }
804
805 N_MSG(CMD, "CMD<%d><0x%.8x> Arg<0x%.8x>", opcode, rawcmd, cmd->arg);
806
807 tmo = jiffies + timeout;
808
809 if (opcode == MMC_SEND_STATUS) {
810 for (;;) {
811 if (!sdc_is_cmd_busy())
812 break;
813
814 if (time_after(jiffies, tmo)) {
815 ERR_MSG("XXX cmd_busy timeout: before CMD<%d>", opcode);
816 cmd->error = -ETIMEDOUT;
817 msdc_reset_hw(host);
818 goto end;
819 }
820 }
821 } else {
822 for (;;) {
823 if (!sdc_is_busy())
824 break;
825 if (time_after(jiffies, tmo)) {
826 ERR_MSG("XXX sdc_busy timeout: before CMD<%d>", opcode);
827 cmd->error = -ETIMEDOUT;
828 msdc_reset_hw(host);
829 goto end;
830 }
831 }
832 }
833
834 //BUG_ON(in_interrupt());
835 host->cmd = cmd;
836 host->cmd_rsp = resp;
837
838 init_completion(&host->cmd_done);
839
840 sdr_set_bits(host->base + MSDC_INTEN, wints);
841 sdc_send_cmd(rawcmd, cmd->arg);
842
843 end:
844 return cmd->error;
845 }
846
msdc_command_resp(struct msdc_host * host,struct mmc_command * cmd,int tune,unsigned long timeout)847 static unsigned int msdc_command_resp(struct msdc_host *host,
848 struct mmc_command *cmd,
849 int tune,
850 unsigned long timeout)
851 __must_hold(&host->lock)
852 {
853 u32 opcode = cmd->opcode;
854 //u32 rawcmd;
855 u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
856 MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
857 MSDC_INT_ACMD19_DONE;
858
859 BUG_ON(in_interrupt());
860 //init_completion(&host->cmd_done);
861 //sdr_set_bits(host->base + MSDC_INTEN, wints);
862
863 spin_unlock(&host->lock);
864 if (!wait_for_completion_timeout(&host->cmd_done, 10 * timeout)) {
865 ERR_MSG("XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>", opcode, cmd->arg);
866 cmd->error = -ETIMEDOUT;
867 msdc_reset_hw(host);
868 }
869 spin_lock(&host->lock);
870
871 sdr_clr_bits(host->base + MSDC_INTEN, wints);
872 host->cmd = NULL;
873
874 //end:
875 #ifdef MT6575_SD_DEBUG
876 switch (resp) {
877 case RESP_NONE:
878 N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)", opcode, cmd->error, resp);
879 break;
880 case RESP_R2:
881 N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= %.8x %.8x %.8x %.8x",
882 opcode, cmd->error, resp, cmd->resp[0], cmd->resp[1],
883 cmd->resp[2], cmd->resp[3]);
884 break;
885 default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
886 N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= 0x%.8x",
887 opcode, cmd->error, resp, cmd->resp[0]);
888 if (cmd->error == 0) {
889 switch (resp) {
890 case RESP_R1:
891 case RESP_R1B:
892 msdc_dump_card_status(host, cmd->resp[0]);
893 break;
894 case RESP_R3:
895 msdc_dump_ocr_reg(host, cmd->resp[0]);
896 break;
897 case RESP_R5:
898 msdc_dump_io_resp(host, cmd->resp[0]);
899 break;
900 case RESP_R6:
901 msdc_dump_rca_resp(host, cmd->resp[0]);
902 break;
903 }
904 }
905 break;
906 }
907 #endif
908
909 /* do we need to save card's RCA when SD_SEND_RELATIVE_ADDR */
910
911 if (!tune)
912 return cmd->error;
913
914 /* memory card CRC */
915 if (host->hw->flags & MSDC_REMOVABLE && cmd->error == -EIO) {
916 /* check if has data phase */
917 if (readl(host->base + SDC_CMD) & 0x1800) {
918 msdc_abort_data(host);
919 } else {
920 /* do basic: reset*/
921 msdc_reset_hw(host);
922 msdc_clr_fifo(host);
923 msdc_clr_int();
924 }
925 cmd->error = msdc_tune_cmdrsp(host, cmd);
926 }
927
928 // check DAT0
929 /* if (resp == RESP_R1B) {
930 while ((readl(host->base + MSDC_PS) & 0x10000) != 0x10000);
931 } */
932 /* CMD12 Error Handle */
933
934 return cmd->error;
935 }
936
msdc_do_command(struct msdc_host * host,struct mmc_command * cmd,int tune,unsigned long timeout)937 static unsigned int msdc_do_command(struct msdc_host *host,
938 struct mmc_command *cmd,
939 int tune,
940 unsigned long timeout)
941 {
942 if (msdc_command_start(host, cmd, timeout))
943 goto end;
944
945 if (msdc_command_resp(host, cmd, tune, timeout))
946 goto end;
947
948 end:
949
950 N_MSG(CMD, " return<%d> resp<0x%.8x>", cmd->error, cmd->resp[0]);
951 return cmd->error;
952 }
953
954 #if 0 /* --- by chhung */
955 // DMA resume / start / stop
956 static void msdc_dma_resume(struct msdc_host *host)
957 {
958 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_RESUME, 1);
959
960 N_MSG(DMA, "DMA resume");
961 }
962 #endif /* end of --- */
963
msdc_dma_start(struct msdc_host * host)964 static void msdc_dma_start(struct msdc_host *host)
965 {
966 u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
967
968 sdr_set_bits(host->base + MSDC_INTEN, wints);
969 //dsb(); /* --- by chhung */
970 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
971
972 N_MSG(DMA, "DMA start");
973 }
974
msdc_dma_stop(struct msdc_host * host)975 static void msdc_dma_stop(struct msdc_host *host)
976 {
977 //u32 retries=500;
978 u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
979
980 N_MSG(DMA, "DMA status: 0x%.8x", readl(host->base + MSDC_DMA_CFG));
981 //while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
982
983 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);
984 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
985 ;
986
987 //dsb(); /* --- by chhung */
988 sdr_clr_bits(host->base + MSDC_INTEN, wints); /* Not just xfer_comp */
989
990 N_MSG(DMA, "DMA stop");
991 }
992
993 /* calc checksum */
msdc_dma_calcs(u8 * buf,u32 len)994 static u8 msdc_dma_calcs(u8 *buf, u32 len)
995 {
996 u32 i, sum = 0;
997
998 for (i = 0; i < len; i++)
999 sum += buf[i];
1000 return 0xFF - (u8)sum;
1001 }
1002
msdc_dma_setup(struct msdc_host * host,struct msdc_dma * dma,struct scatterlist * sg_cmd,unsigned int sglen)1003 static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
1004 struct scatterlist *sg_cmd, unsigned int sglen)
1005 {
1006 struct scatterlist *sg;
1007 struct gpd *gpd;
1008 struct bd *bd;
1009 u32 j;
1010
1011 BUG_ON(sglen > MAX_BD_NUM); /* not support currently */
1012
1013 N_MSG(DMA, "DMA sglen<%d> xfersz<%d>", sglen, host->xfer_size);
1014
1015 gpd = dma->gpd;
1016 bd = dma->bd;
1017
1018 /* modify gpd*/
1019 //gpd->intr = 0;
1020 gpd->hwo = 1; /* hw will clear it */
1021 gpd->bdp = 1;
1022 gpd->chksum = 0; /* need to clear first. */
1023 gpd->chksum = msdc_dma_calcs((u8 *)gpd, 16);
1024
1025 /* modify bd*/
1026 for_each_sg(sg_cmd, sg, sglen, j) {
1027 bd[j].blkpad = 0;
1028 bd[j].dwpad = 0;
1029 bd[j].ptr = (void *)sg_dma_address(sg);
1030 bd[j].buflen = sg_dma_len(sg);
1031
1032 if (j == sglen - 1)
1033 bd[j].eol = 1; /* the last bd */
1034 else
1035 bd[j].eol = 0;
1036
1037 bd[j].chksum = 0; /* checksume need to clear first */
1038 bd[j].chksum = msdc_dma_calcs((u8 *)(&bd[j]), 16);
1039 }
1040
1041 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
1042 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ,
1043 MSDC_BRUST_64B);
1044 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
1045
1046 writel(PHYSADDR((u32)dma->gpd_addr), host->base + MSDC_DMA_SA);
1047
1048 N_MSG(DMA, "DMA_CTRL = 0x%x", readl(host->base + MSDC_DMA_CTRL));
1049 N_MSG(DMA, "DMA_CFG = 0x%x", readl(host->base + MSDC_DMA_CFG));
1050 N_MSG(DMA, "DMA_SA = 0x%x", readl(host->base + MSDC_DMA_SA));
1051 }
1052
msdc_do_request(struct mmc_host * mmc,struct mmc_request * mrq)1053 static int msdc_do_request(struct mmc_host *mmc, struct mmc_request *mrq)
1054 __must_hold(&host->lock)
1055 {
1056 struct msdc_host *host = mmc_priv(mmc);
1057 struct mmc_command *cmd;
1058 struct mmc_data *data;
1059 //u32 intsts = 0;
1060 int read = 1, send_type = 0;
1061
1062 #define SND_DAT 0
1063 #define SND_CMD 1
1064
1065 BUG_ON(mmc == NULL);
1066 BUG_ON(mrq == NULL);
1067
1068 host->error = 0;
1069
1070 cmd = mrq->cmd;
1071 data = mrq->cmd->data;
1072
1073 #if 0 /* --- by chhung */
1074 //if(host->id ==1){
1075 N_MSG(OPS, "enable clock!");
1076 msdc_ungate_clock(host->id);
1077 //}
1078 #endif /* end of --- */
1079
1080 if (!data) {
1081 send_type = SND_CMD;
1082 if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0)
1083 goto done;
1084 } else {
1085 BUG_ON(data->blksz > HOST_MAX_BLKSZ);
1086 send_type = SND_DAT;
1087
1088 data->error = 0;
1089 read = data->flags & MMC_DATA_READ ? 1 : 0;
1090 host->data = data;
1091 host->xfer_size = data->blocks * data->blksz;
1092 host->blksz = data->blksz;
1093
1094 if (read) {
1095 if ((host->timeout_ns != data->timeout_ns) ||
1096 (host->timeout_clks != data->timeout_clks)) {
1097 msdc_set_timeout(host, data->timeout_ns, data->timeout_clks);
1098 }
1099 }
1100
1101 writel(data->blocks, host->base + SDC_BLK_NUM);
1102 //msdc_clr_fifo(host); /* no need */
1103
1104 msdc_dma_on(); /* enable DMA mode first!! */
1105 init_completion(&host->xfer_done);
1106
1107 /* start the command first*/
1108 if (msdc_command_start(host, cmd, CMD_TIMEOUT) != 0)
1109 goto done;
1110
1111 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg,
1112 data->sg_len,
1113 mmc_get_dma_dir(data));
1114 msdc_dma_setup(host, &host->dma, data->sg,
1115 data->sg_count);
1116
1117 /* then wait command done */
1118 if (msdc_command_resp(host, cmd, 1, CMD_TIMEOUT) != 0)
1119 goto done;
1120
1121 /* for read, the data coming too fast, then CRC error
1122 start DMA no business with CRC. */
1123 //init_completion(&host->xfer_done);
1124 msdc_dma_start(host);
1125
1126 spin_unlock(&host->lock);
1127 if (!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)) {
1128 ERR_MSG("XXX CMD<%d> wait xfer_done<%d> timeout!!", cmd->opcode, data->blocks * data->blksz);
1129 ERR_MSG(" DMA_SA = 0x%x",
1130 readl(host->base + MSDC_DMA_SA));
1131 ERR_MSG(" DMA_CA = 0x%x",
1132 readl(host->base + MSDC_DMA_CA));
1133 ERR_MSG(" DMA_CTRL = 0x%x",
1134 readl(host->base + MSDC_DMA_CTRL));
1135 ERR_MSG(" DMA_CFG = 0x%x",
1136 readl(host->base + MSDC_DMA_CFG));
1137 data->error = -ETIMEDOUT;
1138
1139 msdc_reset_hw(host);
1140 msdc_clr_fifo(host);
1141 msdc_clr_int();
1142 }
1143 spin_lock(&host->lock);
1144 msdc_dma_stop(host);
1145
1146 /* Last: stop transfer */
1147 if (data->stop) {
1148 if (msdc_do_command(host, data->stop, 0, CMD_TIMEOUT) != 0)
1149 goto done;
1150 }
1151 }
1152
1153 done:
1154 if (data != NULL) {
1155 host->data = NULL;
1156 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
1157 mmc_get_dma_dir(data));
1158 host->blksz = 0;
1159
1160 #if 0 // don't stop twice!
1161 if (host->hw->flags & MSDC_REMOVABLE && data->error) {
1162 msdc_abort_data(host);
1163 /* reset in IRQ, stop command has issued. -> No need */
1164 }
1165 #endif
1166
1167 N_MSG(OPS, "CMD<%d> data<%s %s> blksz<%d> block<%d> error<%d>", cmd->opcode, (dma ? "dma" : "pio"),
1168 (read ? "read " : "write"), data->blksz, data->blocks, data->error);
1169 }
1170
1171 #if 0 /* --- by chhung */
1172 #if 1
1173 //if(host->id==1) {
1174 if (send_type == SND_CMD) {
1175 if (cmd->opcode == MMC_SEND_STATUS) {
1176 if ((cmd->resp[0] & CARD_READY_FOR_DATA) || (CARD_CURRENT_STATE(cmd->resp[0]) != 7)) {
1177 N_MSG(OPS, "disable clock, CMD13 IDLE");
1178 msdc_gate_clock(host->id);
1179 }
1180 } else {
1181 N_MSG(OPS, "disable clock, CMD<%d>", cmd->opcode);
1182 msdc_gate_clock(host->id);
1183 }
1184 } else {
1185 if (read) {
1186 N_MSG(OPS, "disable clock!!! Read CMD<%d>", cmd->opcode);
1187 msdc_gate_clock(host->id);
1188 }
1189 }
1190 //}
1191 #else
1192 msdc_gate_clock(host->id);
1193 #endif
1194 #endif /* end of --- */
1195
1196 if (mrq->cmd->error)
1197 host->error = 0x001;
1198 if (mrq->data && mrq->data->error)
1199 host->error |= 0x010;
1200 if (mrq->stop && mrq->stop->error)
1201 host->error |= 0x100;
1202
1203 //if (host->error) ERR_MSG("host->error<%d>", host->error);
1204
1205 return host->error;
1206 }
1207
msdc_app_cmd(struct mmc_host * mmc,struct msdc_host * host)1208 static int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host)
1209 {
1210 struct mmc_command cmd;
1211 struct mmc_request mrq;
1212 u32 err;
1213
1214 memset(&cmd, 0, sizeof(struct mmc_command));
1215 cmd.opcode = MMC_APP_CMD;
1216 #if 0 /* bug: we meet mmc->card is null when ACMD6 */
1217 cmd.arg = mmc->card->rca << 16;
1218 #else
1219 cmd.arg = host->app_cmd_arg;
1220 #endif
1221 cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
1222
1223 memset(&mrq, 0, sizeof(struct mmc_request));
1224 mrq.cmd = &cmd; cmd.mrq = &mrq;
1225 cmd.data = NULL;
1226
1227 err = msdc_do_command(host, &cmd, 0, CMD_TIMEOUT);
1228 return err;
1229 }
1230
msdc_tune_cmdrsp(struct msdc_host * host,struct mmc_command * cmd)1231 static int msdc_tune_cmdrsp(struct msdc_host *host, struct mmc_command *cmd)
1232 {
1233 int result = -1;
1234 u32 rsmpl, cur_rsmpl, orig_rsmpl;
1235 u32 rrdly, cur_rrdly = 0xffffffff, orig_rrdly;
1236 u32 skip = 1;
1237
1238 /* ==== don't support 3.0 now ====
1239 1: R_SMPL[1]
1240 2: PAD_CMD_RESP_RXDLY[26:22]
1241 ==========================*/
1242
1243 // save the previous tune result
1244 sdr_get_field(host->base + MSDC_IOCON, MSDC_IOCON_RSPL, &orig_rsmpl);
1245 sdr_get_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY,
1246 &orig_rrdly);
1247
1248 rrdly = 0;
1249 do {
1250 for (rsmpl = 0; rsmpl < 2; rsmpl++) {
1251 /* Lv1: R_SMPL[1] */
1252 cur_rsmpl = (orig_rsmpl + rsmpl) % 2;
1253 if (skip == 1) {
1254 skip = 0;
1255 continue;
1256 }
1257 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_RSPL,
1258 cur_rsmpl);
1259
1260 if (host->app_cmd) {
1261 result = msdc_app_cmd(host->mmc, host);
1262 if (result) {
1263 ERR_MSG("TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>",
1264 host->mrq->cmd->opcode, cur_rrdly, cur_rsmpl);
1265 continue;
1266 }
1267 }
1268 result = msdc_do_command(host, cmd, 0, CMD_TIMEOUT); // not tune.
1269 ERR_MSG("TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>", cmd->opcode,
1270 (result == 0) ? "PASS" : "FAIL", cur_rrdly, cur_rsmpl);
1271
1272 if (result == 0)
1273 return 0;
1274 if (result != -EIO) {
1275 ERR_MSG("TUNE_CMD<%d> Error<%d> not -EIO", cmd->opcode, result);
1276 return result;
1277 }
1278
1279 /* should be EIO */
1280 /* check if has data phase */
1281 if (readl(host->base + SDC_CMD) & 0x1800)
1282 msdc_abort_data(host);
1283 }
1284
1285 /* Lv2: PAD_CMD_RESP_RXDLY[26:22] */
1286 cur_rrdly = (orig_rrdly + rrdly + 1) % 32;
1287 sdr_set_field(host->base + MSDC_PAD_TUNE,
1288 MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly);
1289 } while (++rrdly < 32);
1290
1291 return result;
1292 }
1293
1294 /* Support SD2.0 Only */
msdc_tune_bread(struct mmc_host * mmc,struct mmc_request * mrq)1295 static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq)
1296 {
1297 struct msdc_host *host = mmc_priv(mmc);
1298 u32 ddr = 0;
1299 u32 dcrc = 0;
1300 u32 rxdly, cur_rxdly0, cur_rxdly1;
1301 u32 dsmpl, cur_dsmpl, orig_dsmpl;
1302 u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
1303 u32 cur_dat4, cur_dat5, cur_dat6, cur_dat7;
1304 u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
1305 u32 orig_dat4, orig_dat5, orig_dat6, orig_dat7;
1306 int result = -1;
1307 u32 skip = 1;
1308
1309 sdr_get_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL, &orig_dsmpl);
1310
1311 /* Tune Method 2. */
1312 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
1313
1314 rxdly = 0;
1315 do {
1316 for (dsmpl = 0; dsmpl < 2; dsmpl++) {
1317 cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
1318 if (skip == 1) {
1319 skip = 0;
1320 continue;
1321 }
1322 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL,
1323 cur_dsmpl);
1324
1325 if (host->app_cmd) {
1326 result = msdc_app_cmd(host->mmc, host);
1327 if (result) {
1328 ERR_MSG("TUNE_BREAD app_cmd<%d> failed", host->mrq->cmd->opcode);
1329 continue;
1330 }
1331 }
1332 result = msdc_do_request(mmc, mrq);
1333
1334 sdr_get_field(host->base + SDC_DCRC_STS,
1335 SDC_DCRC_STS_POS | SDC_DCRC_STS_NEG,
1336 &dcrc); /* RO */
1337 if (!ddr)
1338 dcrc &= ~SDC_DCRC_STS_NEG;
1339 ERR_MSG("TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>",
1340 (result == 0 && dcrc == 0) ? "PASS" : "FAIL", dcrc,
1341 readl(host->base + MSDC_DAT_RDDLY0),
1342 readl(host->base + MSDC_DAT_RDDLY1), cur_dsmpl);
1343
1344 /* Fix me: result is 0, but dcrc is still exist */
1345 if (result == 0 && dcrc == 0) {
1346 goto done;
1347 } else {
1348 /* there is a case: command timeout, and data phase not processed */
1349 if (mrq->data->error != 0 &&
1350 mrq->data->error != -EIO) {
1351 ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
1352 result, mrq->cmd->error, mrq->data->error);
1353 goto done;
1354 }
1355 }
1356 }
1357
1358 cur_rxdly0 = readl(host->base + MSDC_DAT_RDDLY0);
1359 cur_rxdly1 = readl(host->base + MSDC_DAT_RDDLY1);
1360
1361 /* E1 ECO. YD: Reverse */
1362 if (readl(host->base + MSDC_ECO_VER) >= 4) {
1363 orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
1364 orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
1365 orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
1366 orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
1367 orig_dat4 = (cur_rxdly1 >> 24) & 0x1F;
1368 orig_dat5 = (cur_rxdly1 >> 16) & 0x1F;
1369 orig_dat6 = (cur_rxdly1 >> 8) & 0x1F;
1370 orig_dat7 = (cur_rxdly1 >> 0) & 0x1F;
1371 } else {
1372 orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
1373 orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
1374 orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
1375 orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
1376 orig_dat4 = (cur_rxdly1 >> 0) & 0x1F;
1377 orig_dat5 = (cur_rxdly1 >> 8) & 0x1F;
1378 orig_dat6 = (cur_rxdly1 >> 16) & 0x1F;
1379 orig_dat7 = (cur_rxdly1 >> 24) & 0x1F;
1380 }
1381
1382 if (ddr) {
1383 cur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
1384 cur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
1385 cur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
1386 cur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
1387 } else {
1388 cur_dat0 = (dcrc & (1 << 0)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
1389 cur_dat1 = (dcrc & (1 << 1)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
1390 cur_dat2 = (dcrc & (1 << 2)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
1391 cur_dat3 = (dcrc & (1 << 3)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
1392 }
1393 cur_dat4 = (dcrc & (1 << 4)) ? ((orig_dat4 + 1) % 32) : orig_dat4;
1394 cur_dat5 = (dcrc & (1 << 5)) ? ((orig_dat5 + 1) % 32) : orig_dat5;
1395 cur_dat6 = (dcrc & (1 << 6)) ? ((orig_dat6 + 1) % 32) : orig_dat6;
1396 cur_dat7 = (dcrc & (1 << 7)) ? ((orig_dat7 + 1) % 32) : orig_dat7;
1397
1398 cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
1399 cur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0);
1400
1401 writel(cur_rxdly0, host->base + MSDC_DAT_RDDLY0);
1402 writel(cur_rxdly1, host->base + MSDC_DAT_RDDLY1);
1403
1404 } while (++rxdly < 32);
1405
1406 done:
1407 return result;
1408 }
1409
msdc_tune_bwrite(struct mmc_host * mmc,struct mmc_request * mrq)1410 static int msdc_tune_bwrite(struct mmc_host *mmc, struct mmc_request *mrq)
1411 {
1412 struct msdc_host *host = mmc_priv(mmc);
1413
1414 u32 wrrdly, cur_wrrdly = 0xffffffff, orig_wrrdly;
1415 u32 dsmpl, cur_dsmpl, orig_dsmpl;
1416 u32 rxdly, cur_rxdly0;
1417 u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
1418 u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
1419 int result = -1;
1420 u32 skip = 1;
1421
1422 // MSDC_IOCON_DDR50CKD need to check. [Fix me]
1423
1424 sdr_get_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY,
1425 &orig_wrrdly);
1426 sdr_get_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL, &orig_dsmpl);
1427
1428 /* Tune Method 2. just DAT0 */
1429 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
1430 cur_rxdly0 = readl(host->base + MSDC_DAT_RDDLY0);
1431
1432 /* E1 ECO. YD: Reverse */
1433 if (readl(host->base + MSDC_ECO_VER) >= 4) {
1434 orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
1435 orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
1436 orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
1437 orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
1438 } else {
1439 orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
1440 orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
1441 orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
1442 orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
1443 }
1444
1445 rxdly = 0;
1446 do {
1447 wrrdly = 0;
1448 do {
1449 for (dsmpl = 0; dsmpl < 2; dsmpl++) {
1450 cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
1451 if (skip == 1) {
1452 skip = 0;
1453 continue;
1454 }
1455 sdr_set_field(host->base + MSDC_IOCON,
1456 MSDC_IOCON_DSPL, cur_dsmpl);
1457
1458 if (host->app_cmd) {
1459 result = msdc_app_cmd(host->mmc, host);
1460 if (result) {
1461 ERR_MSG("TUNE_BWRITE app_cmd<%d> failed", host->mrq->cmd->opcode);
1462 continue;
1463 }
1464 }
1465 result = msdc_do_request(mmc, mrq);
1466
1467 ERR_MSG("TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>",
1468 result == 0 ? "PASS" : "FAIL",
1469 cur_dsmpl, cur_wrrdly, cur_rxdly0);
1470
1471 if (result == 0) {
1472 goto done;
1473 } else {
1474 /* there is a case: command timeout, and data phase not processed */
1475 if (mrq->data->error != -EIO) {
1476 ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
1477 result, mrq->cmd->error, mrq->data->error);
1478 goto done;
1479 }
1480 }
1481 }
1482 cur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32;
1483 sdr_set_field(host->base + MSDC_PAD_TUNE,
1484 MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly);
1485 } while (++wrrdly < 32);
1486
1487 cur_dat0 = (orig_dat0 + rxdly) % 32; /* only adjust bit-1 for crc */
1488 cur_dat1 = orig_dat1;
1489 cur_dat2 = orig_dat2;
1490 cur_dat3 = orig_dat3;
1491
1492 cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
1493 writel(cur_rxdly0, host->base + MSDC_DAT_RDDLY0);
1494 } while (++rxdly < 32);
1495
1496 done:
1497 return result;
1498 }
1499
msdc_get_card_status(struct mmc_host * mmc,struct msdc_host * host,u32 * status)1500 static int msdc_get_card_status(struct mmc_host *mmc, struct msdc_host *host, u32 *status)
1501 {
1502 struct mmc_command cmd;
1503 struct mmc_request mrq;
1504 u32 err;
1505
1506 memset(&cmd, 0, sizeof(struct mmc_command));
1507 cmd.opcode = MMC_SEND_STATUS;
1508 if (mmc->card) {
1509 cmd.arg = mmc->card->rca << 16;
1510 } else {
1511 ERR_MSG("cmd13 mmc card is null");
1512 cmd.arg = host->app_cmd_arg;
1513 }
1514 cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
1515
1516 memset(&mrq, 0, sizeof(struct mmc_request));
1517 mrq.cmd = &cmd; cmd.mrq = &mrq;
1518 cmd.data = NULL;
1519
1520 err = msdc_do_command(host, &cmd, 1, CMD_TIMEOUT);
1521
1522 if (status)
1523 *status = cmd.resp[0];
1524
1525 return err;
1526 }
1527
msdc_check_busy(struct mmc_host * mmc,struct msdc_host * host)1528 static int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host)
1529 {
1530 u32 err = 0;
1531 u32 status = 0;
1532
1533 do {
1534 err = msdc_get_card_status(mmc, host, &status);
1535 if (err)
1536 return err;
1537 /* need cmd12? */
1538 ERR_MSG("cmd<13> resp<0x%x>", status);
1539 } while (R1_CURRENT_STATE(status) == 7);
1540
1541 return err;
1542 }
1543
1544 /* failed when msdc_do_request */
msdc_tune_request(struct mmc_host * mmc,struct mmc_request * mrq)1545 static int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq)
1546 {
1547 struct msdc_host *host = mmc_priv(mmc);
1548 struct mmc_data *data;
1549 //u32 base = host->base;
1550 int ret = 0, read;
1551
1552 data = mrq->cmd->data;
1553
1554 read = data->flags & MMC_DATA_READ ? 1 : 0;
1555
1556 if (read) {
1557 if (data->error == -EIO)
1558 ret = msdc_tune_bread(mmc, mrq);
1559 } else {
1560 ret = msdc_check_busy(mmc, host);
1561 if (ret) {
1562 ERR_MSG("XXX cmd13 wait program done failed");
1563 return ret;
1564 }
1565 /* CRC and TO */
1566 /* Fix me: don't care card status? */
1567 ret = msdc_tune_bwrite(mmc, mrq);
1568 }
1569
1570 return ret;
1571 }
1572
1573 /* ops.request */
msdc_ops_request(struct mmc_host * mmc,struct mmc_request * mrq)1574 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1575 {
1576 struct msdc_host *host = mmc_priv(mmc);
1577
1578 //=== for sdio profile ===
1579 #if 0 /* --- by chhung */
1580 u32 old_H32, old_L32, new_H32, new_L32;
1581 u32 ticks = 0, opcode = 0, sizes = 0, bRx = 0;
1582 #endif /* end of --- */
1583
1584 WARN_ON(host->mrq);
1585
1586 /* start to process */
1587 spin_lock(&host->lock);
1588 #if 0 /* --- by chhung */
1589 if (sdio_pro_enable) { //=== for sdio profile ===
1590 if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53)
1591 GPT_GetCounter64(&old_L32, &old_H32);
1592 }
1593 #endif /* end of --- */
1594
1595 host->mrq = mrq;
1596
1597 if (msdc_do_request(mmc, mrq)) {
1598 if (host->hw->flags & MSDC_REMOVABLE && ralink_soc == MT762X_SOC_MT7621AT && mrq->data && mrq->data->error)
1599 msdc_tune_request(mmc, mrq);
1600 }
1601
1602 /* ==== when request done, check if app_cmd ==== */
1603 if (mrq->cmd->opcode == MMC_APP_CMD) {
1604 host->app_cmd = 1;
1605 host->app_cmd_arg = mrq->cmd->arg; /* save the RCA */
1606 } else {
1607 host->app_cmd = 0;
1608 //host->app_cmd_arg = 0;
1609 }
1610
1611 host->mrq = NULL;
1612
1613 #if 0 /* --- by chhung */
1614 //=== for sdio profile ===
1615 if (sdio_pro_enable) {
1616 if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {
1617 GPT_GetCounter64(&new_L32, &new_H32);
1618 ticks = msdc_time_calc(old_L32, old_H32, new_L32, new_H32);
1619
1620 opcode = mrq->cmd->opcode;
1621 if (mrq->cmd->data) {
1622 sizes = mrq->cmd->data->blocks * mrq->cmd->data->blksz;
1623 bRx = mrq->cmd->data->flags & MMC_DATA_READ ? 1 : 0;
1624 } else {
1625 bRx = mrq->cmd->arg & 0x80000000 ? 1 : 0;
1626 }
1627
1628 if (!mrq->cmd->error)
1629 msdc_performance(opcode, sizes, bRx, ticks);
1630 }
1631 }
1632 #endif /* end of --- */
1633 spin_unlock(&host->lock);
1634
1635 mmc_request_done(mmc, mrq);
1636
1637 return;
1638 }
1639
1640 /* called by ops.set_ios */
msdc_set_buswidth(struct msdc_host * host,u32 width)1641 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1642 {
1643 u32 val = readl(host->base + SDC_CFG);
1644
1645 val &= ~SDC_CFG_BUSWIDTH;
1646
1647 switch (width) {
1648 default:
1649 case MMC_BUS_WIDTH_1:
1650 width = 1;
1651 val |= (MSDC_BUS_1BITS << 16);
1652 break;
1653 case MMC_BUS_WIDTH_4:
1654 val |= (MSDC_BUS_4BITS << 16);
1655 break;
1656 case MMC_BUS_WIDTH_8:
1657 val |= (MSDC_BUS_8BITS << 16);
1658 break;
1659 }
1660
1661 writel(val, host->base + SDC_CFG);
1662
1663 N_MSG(CFG, "Bus Width = %d", width);
1664 }
1665
1666 /* ops.set_ios */
msdc_ops_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1667 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1668 {
1669 struct msdc_host *host = mmc_priv(mmc);
1670 u32 ddr = 0;
1671
1672 #ifdef MT6575_SD_DEBUG
1673 static char *vdd[] = {
1674 "1.50v", "1.55v", "1.60v", "1.65v", "1.70v", "1.80v", "1.90v",
1675 "2.00v", "2.10v", "2.20v", "2.30v", "2.40v", "2.50v", "2.60v",
1676 "2.70v", "2.80v", "2.90v", "3.00v", "3.10v", "3.20v", "3.30v",
1677 "3.40v", "3.50v", "3.60v"
1678 };
1679 static char *power_mode[] = {
1680 "OFF", "UP", "ON"
1681 };
1682 static char *bus_mode[] = {
1683 "UNKNOWN", "OPENDRAIN", "PUSHPULL"
1684 };
1685 static char *timing[] = {
1686 "LEGACY", "MMC_HS", "SD_HS"
1687 };
1688
1689 printk("SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)",
1690 ios->clock / 1000, bus_mode[ios->bus_mode],
1691 (ios->bus_width == MMC_BUS_WIDTH_4) ? 4 : 1,
1692 power_mode[ios->power_mode], vdd[ios->vdd], timing[ios->timing]);
1693 #endif
1694
1695 msdc_set_buswidth(host, ios->bus_width);
1696
1697 /* Power control ??? */
1698 switch (ios->power_mode) {
1699 case MMC_POWER_OFF:
1700 case MMC_POWER_UP:
1701 // msdc_set_power_mode(host, ios->power_mode); /* --- by chhung */
1702 break;
1703 case MMC_POWER_ON:
1704 host->power_mode = MMC_POWER_ON;
1705 break;
1706 default:
1707 break;
1708 }
1709
1710 /* Clock control */
1711 if (host->mclk != ios->clock) {
1712 if (ios->clock > 25000000) {
1713 //if (!(host->hw->flags & MSDC_REMOVABLE)) {
1714 INIT_MSG("SD data latch edge<%d>", MSDC_SMPL_FALLING);
1715 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_RSPL,
1716 MSDC_SMPL_FALLING);
1717 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL,
1718 MSDC_SMPL_FALLING);
1719 //} /* for tuning debug */
1720 } else { /* default value */
1721 writel(0x00000000, host->base + MSDC_IOCON);
1722 // writel(0x00000000, host->base + MSDC_DAT_RDDLY0);
1723
1724 // for MT7620 E2 and afterward
1725 writel(0x10101010, host->base + MSDC_DAT_RDDLY0);
1726
1727 writel(0x00000000, host->base + MSDC_DAT_RDDLY1);
1728 // writel(0x00000000, host->base + MSDC_PAD_TUNE);
1729
1730 // for MT7620 E2 and afterward
1731 writel(0x84101010, host->base + MSDC_PAD_TUNE);
1732 }
1733 msdc_set_mclk(host, ddr, ios->clock);
1734 }
1735 }
1736
1737 /* ops.get_ro */
msdc_ops_get_ro(struct mmc_host * mmc)1738 static int msdc_ops_get_ro(struct mmc_host *mmc)
1739 {
1740 struct msdc_host *host = mmc_priv(mmc);
1741 unsigned long flags;
1742 int ro = 0;
1743
1744 if (host->hw->flags & MSDC_WP_PIN_EN) { /* set for card */
1745 spin_lock_irqsave(&host->lock, flags);
1746 ro = (readl(host->base + MSDC_PS) >> 31);
1747 spin_unlock_irqrestore(&host->lock, flags);
1748 }
1749 return ro;
1750 }
1751
1752 /* ops.get_cd */
msdc_ops_get_cd(struct mmc_host * mmc)1753 static int msdc_ops_get_cd(struct mmc_host *mmc)
1754 {
1755 struct msdc_host *host = mmc_priv(mmc);
1756 unsigned long flags;
1757 int present = 1;
1758
1759 /* for sdio, MSDC_REMOVABLE not set, always return 1 */
1760 if (!(host->hw->flags & MSDC_REMOVABLE)) {
1761 /* For sdio, read H/W always get<1>, but may timeout some times */
1762 #if 1
1763 host->card_inserted = 1;
1764 return 1;
1765 #else
1766 host->card_inserted = (host->pm_state.event == PM_EVENT_USER_RESUME) ? 1 : 0;
1767 INIT_MSG("sdio ops_get_cd<%d>", host->card_inserted);
1768 return host->card_inserted;
1769 #endif
1770 }
1771
1772 /* MSDC_CD_PIN_EN set for card */
1773 if (host->hw->flags & MSDC_CD_PIN_EN) {
1774 spin_lock_irqsave(&host->lock, flags);
1775 #if 0
1776 present = host->card_inserted; /* why not read from H/W: Fix me*/
1777 #else
1778 // CD
1779 present = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
1780 if (cd_active_low)
1781 present = present ? 0 : 1;
1782 else
1783 present = present ? 1 : 0;
1784 host->card_inserted = present;
1785 #endif
1786 spin_unlock_irqrestore(&host->lock, flags);
1787 } else {
1788 present = 0; /* TODO? Check DAT3 pins for card detection */
1789 }
1790
1791 INIT_MSG("ops_get_cd return<%d>", present);
1792 return present;
1793 }
1794
1795 static struct mmc_host_ops mt_msdc_ops = {
1796 .request = msdc_ops_request,
1797 .set_ios = msdc_ops_set_ios,
1798 .get_ro = msdc_ops_get_ro,
1799 .get_cd = msdc_ops_get_cd,
1800 };
1801
1802 /*--------------------------------------------------------------------------*/
1803 /* interrupt handler */
1804 /*--------------------------------------------------------------------------*/
msdc_irq(int irq,void * dev_id)1805 static irqreturn_t msdc_irq(int irq, void *dev_id)
1806 {
1807 struct msdc_host *host = (struct msdc_host *)dev_id;
1808 struct mmc_data *data = host->data;
1809 struct mmc_command *cmd = host->cmd;
1810
1811 u32 cmdsts = MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | MSDC_INT_CMDRDY |
1812 MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY |
1813 MSDC_INT_ACMD19_DONE;
1814 u32 datsts = MSDC_INT_DATCRCERR | MSDC_INT_DATTMO;
1815
1816 u32 intsts = readl(host->base + MSDC_INT);
1817 u32 inten = readl(host->base + MSDC_INTEN); inten &= intsts;
1818
1819 writel(intsts, host->base + MSDC_INT); /* clear interrupts */
1820 /* MSG will cause fatal error */
1821
1822 /* card change interrupt */
1823 if (intsts & MSDC_INT_CDSC) {
1824 if (host->mmc->caps & MMC_CAP_NEEDS_POLL)
1825 return IRQ_HANDLED;
1826 IRQ_MSG("MSDC_INT_CDSC irq<0x%.8x>", intsts);
1827 schedule_delayed_work(&host->card_delaywork, HZ);
1828 /* tuning when plug card ? */
1829 }
1830
1831 /* sdio interrupt */
1832 if (intsts & MSDC_INT_SDIOIRQ) {
1833 IRQ_MSG("XXX MSDC_INT_SDIOIRQ"); /* seems not sdio irq */
1834 //mmc_signal_sdio_irq(host->mmc);
1835 }
1836
1837 /* transfer complete interrupt */
1838 if (data != NULL) {
1839 if (inten & MSDC_INT_XFER_COMPL) {
1840 data->bytes_xfered = host->xfer_size;
1841 complete(&host->xfer_done);
1842 }
1843
1844 if (intsts & datsts) {
1845 /* do basic reset, or stop command will sdc_busy */
1846 msdc_reset_hw(host);
1847 msdc_clr_fifo(host);
1848 msdc_clr_int();
1849
1850 if (intsts & MSDC_INT_DATTMO) {
1851 IRQ_MSG("XXX CMD<%d> MSDC_INT_DATTMO", host->mrq->cmd->opcode);
1852 data->error = -ETIMEDOUT;
1853 } else if (intsts & MSDC_INT_DATCRCERR) {
1854 IRQ_MSG("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>", host->mrq->cmd->opcode, readl(host->base + SDC_DCRC_STS));
1855 data->error = -EIO;
1856 }
1857
1858 //if(readl(MSDC_INTEN) & MSDC_INT_XFER_COMPL) {
1859 complete(&host->xfer_done); /* Read CRC come fast, XFER_COMPL not enabled */
1860 }
1861 }
1862
1863 /* command interrupts */
1864 if ((cmd != NULL) && (intsts & cmdsts)) {
1865 if ((intsts & MSDC_INT_CMDRDY) || (intsts & MSDC_INT_ACMDRDY) ||
1866 (intsts & MSDC_INT_ACMD19_DONE)) {
1867 u32 *rsp = &cmd->resp[0];
1868
1869 switch (host->cmd_rsp) {
1870 case RESP_NONE:
1871 break;
1872 case RESP_R2:
1873 *rsp++ = readl(host->base + SDC_RESP3);
1874 *rsp++ = readl(host->base + SDC_RESP2);
1875 *rsp++ = readl(host->base + SDC_RESP1);
1876 *rsp++ = readl(host->base + SDC_RESP0);
1877 break;
1878 default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
1879 if ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE))
1880 *rsp = readl(host->base + SDC_ACMD_RESP);
1881 else
1882 *rsp = readl(host->base + SDC_RESP0);
1883 break;
1884 }
1885 } else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) {
1886 if (intsts & MSDC_INT_ACMDCRCERR)
1887 IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDCRCERR", cmd->opcode);
1888 else
1889 IRQ_MSG("XXX CMD<%d> MSDC_INT_RSPCRCERR", cmd->opcode);
1890 cmd->error = -EIO;
1891 } else if ((intsts & MSDC_INT_CMDTMO) || (intsts & MSDC_INT_ACMDTMO)) {
1892 if (intsts & MSDC_INT_ACMDTMO)
1893 IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDTMO", cmd->opcode);
1894 else
1895 IRQ_MSG("XXX CMD<%d> MSDC_INT_CMDTMO", cmd->opcode);
1896 cmd->error = -ETIMEDOUT;
1897 msdc_reset_hw(host);
1898 msdc_clr_fifo(host);
1899 msdc_clr_int();
1900 }
1901 complete(&host->cmd_done);
1902 }
1903
1904 /* mmc irq interrupts */
1905 if (intsts & MSDC_INT_MMCIRQ)
1906 printk(KERN_INFO "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n",
1907 host->id, readl(host->base + SDC_CSTS));
1908
1909 #ifdef MT6575_SD_DEBUG
1910 {
1911 /* msdc_int_reg *int_reg = (msdc_int_reg*)&intsts;*/
1912 N_MSG(INT, "IRQ_EVT(0x%x): MMCIRQ(%d) CDSC(%d), ACRDY(%d), ACTMO(%d), ACCRE(%d) AC19DN(%d)",
1913 intsts,
1914 int_reg->mmcirq,
1915 int_reg->cdsc,
1916 int_reg->atocmdrdy,
1917 int_reg->atocmdtmo,
1918 int_reg->atocmdcrc,
1919 int_reg->atocmd19done);
1920 N_MSG(INT, "IRQ_EVT(0x%x): SDIO(%d) CMDRDY(%d), CMDTMO(%d), RSPCRC(%d), CSTA(%d)",
1921 intsts,
1922 int_reg->sdioirq,
1923 int_reg->cmdrdy,
1924 int_reg->cmdtmo,
1925 int_reg->rspcrc,
1926 int_reg->csta);
1927 N_MSG(INT, "IRQ_EVT(0x%x): XFCMP(%d) DXDONE(%d), DATTMO(%d), DATCRC(%d), DMAEMP(%d)",
1928 intsts,
1929 int_reg->xfercomp,
1930 int_reg->dxferdone,
1931 int_reg->dattmo,
1932 int_reg->datcrc,
1933 int_reg->dmaqempty);
1934 }
1935 #endif
1936
1937 return IRQ_HANDLED;
1938 }
1939
1940 /*--------------------------------------------------------------------------*/
1941 /* platform_driver members */
1942 /*--------------------------------------------------------------------------*/
1943 /* called by msdc_drv_probe/remove */
msdc_enable_cd_irq(struct msdc_host * host,int enable)1944 static void msdc_enable_cd_irq(struct msdc_host *host, int enable)
1945 {
1946 struct msdc_hw *hw = host->hw;
1947
1948 /* for sdio, not set */
1949 if ((hw->flags & MSDC_CD_PIN_EN) == 0) {
1950 /* Pull down card detection pin since it is not avaiable */
1951 /*
1952 if (hw->config_gpio_pin)
1953 hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
1954 */
1955 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1956 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1957 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1958 return;
1959 }
1960
1961 N_MSG(CFG, "CD IRQ Enable(%d)", enable);
1962
1963 if (enable) {
1964 /* card detection circuit relies on the core power so that the core power
1965 * shouldn't be turned off. Here adds a reference count to keep
1966 * the core power alive.
1967 */
1968 //msdc_vcore_on(host); //did in msdc_init_hw()
1969
1970 if (hw->config_gpio_pin) /* NULL */
1971 hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP);
1972
1973 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1974 DEFAULT_DEBOUNCE);
1975 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1976 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1977
1978 /* not in document! Fix me */
1979 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1980 } else {
1981 if (hw->config_gpio_pin) /* NULL */
1982 hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
1983
1984 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1985 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1986 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1987
1988 /* Here decreases a reference count to core power since card
1989 * detection circuit is shutdown.
1990 */
1991 //msdc_vcore_off(host);
1992 }
1993 }
1994
1995 /* called by msdc_drv_probe */
msdc_init_hw(struct msdc_host * host)1996 static void msdc_init_hw(struct msdc_host *host)
1997 {
1998
1999 /* Power on */
2000 #if 0 /* --- by chhung */
2001 msdc_vcore_on(host);
2002 msdc_pin_reset(host, MSDC_PIN_PULL_UP);
2003 msdc_select_clksrc(host, hw->clk_src);
2004 enable_clock(PERI_MSDC0_PDN + host->id, "SD");
2005 msdc_vdd_on(host);
2006 #endif /* end of --- */
2007 /* Configure to MMC/SD mode */
2008 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC);
2009
2010 /* Reset */
2011 msdc_reset_hw(host);
2012 msdc_clr_fifo(host);
2013
2014 /* Disable card detection */
2015 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
2016
2017 /* Disable and clear all interrupts */
2018 sdr_clr_bits(host->base + MSDC_INTEN, readl(host->base + MSDC_INTEN));
2019 writel(readl(host->base + MSDC_INT), host->base + MSDC_INT);
2020
2021 #if 1
2022 /* reset tuning parameter */
2023 writel(0x00090000, host->base + MSDC_PAD_CTL0);
2024 writel(0x000A0000, host->base + MSDC_PAD_CTL1);
2025 writel(0x000A0000, host->base + MSDC_PAD_CTL2);
2026 // writel( 0x00000000, host->base + MSDC_PAD_TUNE);
2027
2028 // for MT7620 E2 and afterward
2029 writel(0x84101010, host->base + MSDC_PAD_TUNE);
2030
2031 // writel(0x00000000, host->base + MSDC_DAT_RDDLY0);
2032
2033 // for MT7620 E2 and afterward
2034 writel(0x10101010, host->base + MSDC_DAT_RDDLY0);
2035
2036 writel(0x00000000, host->base + MSDC_DAT_RDDLY1);
2037 writel(0x00000000, host->base + MSDC_IOCON);
2038 #if 0 // use MT7620 default value: 0x403c004f
2039 /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/
2040 writel(0x003C000F, host->base + MSDC_PATCH_BIT0);
2041 #endif
2042
2043 if (readl(host->base + MSDC_ECO_VER) >= 4) {
2044 if (host->id == 1) {
2045 sdr_set_field(host->base + MSDC_PATCH_BIT1,
2046 MSDC_PATCH_BIT1_WRDAT_CRCS, 1);
2047 sdr_set_field(host->base + MSDC_PATCH_BIT1,
2048 MSDC_PATCH_BIT1_CMD_RSP, 1);
2049
2050 /* internal clock: latch read data */
2051 sdr_set_bits(host->base + MSDC_PATCH_BIT0,
2052 MSDC_PATCH_BIT_CKGEN_CK);
2053 }
2054 }
2055 #endif
2056
2057 /* for safety, should clear SDC_CFG.SDIO_INT_DET_EN & set SDC_CFG.SDIO in
2058 pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only
2059 set when kernel driver wants to use SDIO bus interrupt */
2060 /* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */
2061 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
2062
2063 /* disable detect SDIO device interupt function */
2064 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
2065
2066 /* eneable SMT for glitch filter */
2067 sdr_set_bits(host->base + MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT);
2068 sdr_set_bits(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT);
2069 sdr_set_bits(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT);
2070
2071 #if 1
2072 /* set clk, cmd, dat pad driving */
2073 sdr_set_field(host->base + MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 4);
2074 sdr_set_field(host->base + MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 4);
2075 sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 4);
2076 sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 4);
2077 sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 4);
2078 sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 4);
2079 #else
2080 sdr_set_field(host->base + MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0);
2081 sdr_set_field(host->base + MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0);
2082 sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0);
2083 sdr_set_field(host->base + MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0);
2084 sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0);
2085 sdr_set_field(host->base + MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0);
2086 #endif
2087
2088 /* set sampling edge */
2089
2090 /* write crc timeout detection */
2091 sdr_set_field(host->base + MSDC_PATCH_BIT0, 1 << 30, 1);
2092
2093 /* Configure to default data timeout */
2094 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC);
2095
2096 msdc_set_buswidth(host, MMC_BUS_WIDTH_1);
2097
2098 N_MSG(FUC, "init hardware done!");
2099 }
2100
2101 /* called by msdc_drv_remove */
msdc_deinit_hw(struct msdc_host * host)2102 static void msdc_deinit_hw(struct msdc_host *host)
2103 {
2104 /* Disable and clear all interrupts */
2105 sdr_clr_bits(host->base + MSDC_INTEN, readl(host->base + MSDC_INTEN));
2106 writel(readl(host->base + MSDC_INT), host->base + MSDC_INT);
2107
2108 /* Disable card detection */
2109 msdc_enable_cd_irq(host, 0);
2110 // msdc_set_power_mode(host, MMC_POWER_OFF); /* make sure power down */ /* --- by chhung */
2111 }
2112
2113 /* init gpd and bd list in msdc_drv_probe */
msdc_init_gpd_bd(struct msdc_host * host,struct msdc_dma * dma)2114 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
2115 {
2116 struct gpd *gpd = dma->gpd;
2117 struct bd *bd = dma->bd;
2118 int i;
2119
2120 /* we just support one gpd, but gpd->next must be set for desc
2121 * DMA. That's why we alloc 2 gpd structurs.
2122 */
2123
2124 memset(gpd, 0, sizeof(struct gpd) * 2);
2125
2126 gpd->bdp = 1; /* hwo, cs, bd pointer */
2127 gpd->ptr = (void *)dma->bd_addr; /* physical address */
2128 gpd->next = (void *)((u32)dma->gpd_addr + sizeof(struct gpd));
2129
2130 memset(bd, 0, sizeof(struct bd) * MAX_BD_NUM);
2131 for (i = 0; i < (MAX_BD_NUM - 1); i++)
2132 bd[i].next = (void *)(dma->bd_addr + sizeof(*bd) * (i + 1));
2133 }
2134
msdc_drv_probe(struct platform_device * pdev)2135 static int msdc_drv_probe(struct platform_device *pdev)
2136 {
2137 struct resource *res;
2138 __iomem void *base;
2139 struct mmc_host *mmc;
2140 struct msdc_host *host;
2141 struct msdc_hw *hw;
2142 int ret;
2143
2144 hw = &msdc0_hw;
2145
2146 if (of_property_read_bool(pdev->dev.of_node, "mtk,wp-en"))
2147 msdc0_hw.flags |= MSDC_WP_PIN_EN;
2148
2149 /* Allocate MMC host for this device */
2150 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
2151 if (!mmc)
2152 return -ENOMEM;
2153
2154 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2155 base = devm_ioremap_resource(&pdev->dev, res);
2156 if (IS_ERR(base)) {
2157 ret = PTR_ERR(base);
2158 goto host_free;
2159 }
2160
2161 /* Set host parameters to mmc */
2162 mmc->ops = &mt_msdc_ops;
2163 mmc->f_min = HOST_MIN_MCLK;
2164 mmc->f_max = HOST_MAX_MCLK;
2165 mmc->ocr_avail = MSDC_OCR_AVAIL;
2166
2167 mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
2168
2169 //TODO: read this as bus-width from dt (via mmc_of_parse)
2170 mmc->caps |= MMC_CAP_4_BIT_DATA;
2171
2172 cd_active_low = !of_property_read_bool(pdev->dev.of_node, "mediatek,cd-high");
2173
2174 if (of_property_read_bool(pdev->dev.of_node, "mediatek,cd-poll"))
2175 mmc->caps |= MMC_CAP_NEEDS_POLL;
2176
2177 /* MMC core transfer sizes tunable parameters */
2178 mmc->max_segs = MAX_HW_SGMTS;
2179
2180 mmc->max_seg_size = MAX_SGMT_SZ;
2181 mmc->max_blk_size = HOST_MAX_BLKSZ;
2182 mmc->max_req_size = MAX_REQ_SZ;
2183 mmc->max_blk_count = mmc->max_req_size;
2184
2185 host = mmc_priv(mmc);
2186 host->hw = hw;
2187 host->mmc = mmc;
2188 host->id = pdev->id;
2189 if (host->id < 0 || host->id >= 4)
2190 host->id = 0;
2191 host->error = 0;
2192
2193 host->irq = platform_get_irq(pdev, 0);
2194 if (host->irq < 0) {
2195 ret = -EINVAL;
2196 goto host_free;
2197 }
2198
2199 host->base = base;
2200 host->mclk = 0; /* mclk: the request clock of mmc sub-system */
2201 host->hclk = hclks[hw->clk_src]; /* hclk: clock of clock source to msdc controller */
2202 host->sclk = 0; /* sclk: the really clock after divition */
2203 host->pm_state = PMSG_RESUME;
2204 host->suspend = 0;
2205 host->core_clkon = 0;
2206 host->card_clkon = 0;
2207 host->core_power = 0;
2208 host->power_mode = MMC_POWER_OFF;
2209 // host->card_inserted = hw->flags & MSDC_REMOVABLE ? 0 : 1;
2210 host->timeout_ns = 0;
2211 host->timeout_clks = DEFAULT_DTOC * 65536;
2212
2213 host->mrq = NULL;
2214 //init_MUTEX(&host->sem); /* we don't need to support multiple threads access */
2215
2216 mmc_dev(mmc)->dma_mask = NULL;
2217
2218 /* using dma_alloc_coherent*/ /* todo: using 1, for all 4 slots */
2219 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2220 MAX_GPD_NUM * sizeof(struct gpd),
2221 &host->dma.gpd_addr, GFP_KERNEL);
2222 host->dma.bd = dma_alloc_coherent(&pdev->dev,
2223 MAX_BD_NUM * sizeof(struct bd),
2224 &host->dma.bd_addr, GFP_KERNEL);
2225 if (!host->dma.gpd || !host->dma.bd) {
2226 ret = -ENOMEM;
2227 goto release_mem;
2228 }
2229 msdc_init_gpd_bd(host, &host->dma);
2230
2231 INIT_DELAYED_WORK(&host->card_delaywork, msdc_tasklet_card);
2232 spin_lock_init(&host->lock);
2233 msdc_init_hw(host);
2234
2235 /* TODO check weather flags 0 is correct, the mtk-sd driver uses
2236 * IRQF_TRIGGER_LOW | IRQF_ONESHOT for flags
2237 *
2238 * for flags 0 the trigger polarity is determined by the
2239 * device tree, but not the oneshot flag, but maybe it is also
2240 * not needed because the soc could be oneshot safe.
2241 */
2242 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 0, pdev->name,
2243 host);
2244 if (ret)
2245 goto release;
2246
2247 platform_set_drvdata(pdev, mmc);
2248
2249 ret = mmc_add_host(mmc);
2250 if (ret)
2251 goto release;
2252
2253 /* Config card detection pin and enable interrupts */
2254 if (hw->flags & MSDC_CD_PIN_EN) { /* set for card */
2255 msdc_enable_cd_irq(host, 1);
2256 } else {
2257 msdc_enable_cd_irq(host, 0);
2258 }
2259
2260 return 0;
2261
2262 release:
2263 platform_set_drvdata(pdev, NULL);
2264 msdc_deinit_hw(host);
2265 cancel_delayed_work_sync(&host->card_delaywork);
2266
2267 release_mem:
2268 if (host->dma.gpd)
2269 dma_free_coherent(&pdev->dev, MAX_GPD_NUM * sizeof(struct gpd),
2270 host->dma.gpd, host->dma.gpd_addr);
2271 if (host->dma.bd)
2272 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct bd),
2273 host->dma.bd, host->dma.bd_addr);
2274 host_free:
2275 mmc_free_host(mmc);
2276
2277 return ret;
2278 }
2279
2280 /* 4 device share one driver, using "drvdata" to show difference */
msdc_drv_remove(struct platform_device * pdev)2281 static int msdc_drv_remove(struct platform_device *pdev)
2282 {
2283 struct mmc_host *mmc;
2284 struct msdc_host *host;
2285
2286 mmc = platform_get_drvdata(pdev);
2287 BUG_ON(!mmc);
2288
2289 host = mmc_priv(mmc);
2290 BUG_ON(!host);
2291
2292 ERR_MSG("removed !!!");
2293
2294 platform_set_drvdata(pdev, NULL);
2295 mmc_remove_host(host->mmc);
2296 msdc_deinit_hw(host);
2297
2298 cancel_delayed_work_sync(&host->card_delaywork);
2299
2300 dma_free_coherent(&pdev->dev, MAX_GPD_NUM * sizeof(struct gpd),
2301 host->dma.gpd, host->dma.gpd_addr);
2302 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct bd),
2303 host->dma.bd, host->dma.bd_addr);
2304
2305 mmc_free_host(host->mmc);
2306
2307 return 0;
2308 }
2309
2310 /* Fix me: Power Flow */
2311 #ifdef CONFIG_PM
2312
msdc_drv_pm(struct platform_device * pdev,pm_message_t state)2313 static void msdc_drv_pm(struct platform_device *pdev, pm_message_t state)
2314 {
2315 struct mmc_host *mmc = platform_get_drvdata(pdev);
2316 if (mmc) {
2317 struct msdc_host *host = mmc_priv(mmc);
2318 msdc_pm(state, (void *)host);
2319 }
2320 }
2321
msdc_drv_suspend(struct platform_device * pdev,pm_message_t state)2322 static int msdc_drv_suspend(struct platform_device *pdev, pm_message_t state)
2323 {
2324 if (state.event == PM_EVENT_SUSPEND)
2325 msdc_drv_pm(pdev, state);
2326 return 0;
2327 }
2328
msdc_drv_resume(struct platform_device * pdev)2329 static int msdc_drv_resume(struct platform_device *pdev)
2330 {
2331 struct pm_message state;
2332
2333 state.event = PM_EVENT_RESUME;
2334 msdc_drv_pm(pdev, state);
2335 return 0;
2336 }
2337 #endif
2338
2339 static const struct of_device_id mt7620_sdhci_match[] = {
2340 { .compatible = "ralink,mt7620-sdhci" },
2341 {},
2342 };
2343 MODULE_DEVICE_TABLE(of, mt7620_sdhci_match);
2344
2345 static struct platform_driver mt_msdc_driver = {
2346 .probe = msdc_drv_probe,
2347 .remove = msdc_drv_remove,
2348 #ifdef CONFIG_PM
2349 .suspend = msdc_drv_suspend,
2350 .resume = msdc_drv_resume,
2351 #endif
2352 .driver = {
2353 .name = DRV_NAME,
2354 .of_match_table = mt7620_sdhci_match,
2355 },
2356 };
2357
2358 /*--------------------------------------------------------------------------*/
2359 /* module init/exit */
2360 /*--------------------------------------------------------------------------*/
mt_msdc_init(void)2361 static int __init mt_msdc_init(void)
2362 {
2363 int ret;
2364 u32 reg;
2365
2366 // Set the pins for sdxc to sdxc mode
2367 //FIXME: this should be done by pinctl and not by the sd driver
2368 reg = readl((void __iomem *)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3 << 18);
2369 writel(reg, (void __iomem *)(RALINK_SYSCTL_BASE + 0x60));
2370
2371 ret = platform_driver_register(&mt_msdc_driver);
2372 if (ret) {
2373 printk(KERN_ERR DRV_NAME ": Can't register driver");
2374 return ret;
2375 }
2376
2377 #if defined(MT6575_SD_DEBUG)
2378 msdc_debug_proc_init();
2379 #endif
2380 return 0;
2381 }
2382
mt_msdc_exit(void)2383 static void __exit mt_msdc_exit(void)
2384 {
2385 platform_driver_unregister(&mt_msdc_driver);
2386 }
2387
2388 module_init(mt_msdc_init);
2389 module_exit(mt_msdc_exit);
2390 MODULE_LICENSE("GPL");
2391 MODULE_DESCRIPTION("MediaTek MT6575 SD/MMC Card Driver");
2392 MODULE_AUTHOR("Infinity Chen <infinity.chen@mediatek.com>");
2393
