1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author: Jacob Chen <jacob-chen@iotwrt.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/debugfs.h>
9 #include <linux/delay.h>
10 #include <linux/fs.h>
11 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/reset.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/timer.h>
19
20 #include <linux/platform_device.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-event.h>
23 #include <media/v4l2-ioctl.h>
24 #include <media/v4l2-mem2mem.h>
25 #include <media/videobuf2-dma-sg.h>
26 #include <media/videobuf2-v4l2.h>
27
28 #include "rga-hw.h"
29 #include "rga.h"
30
31 static int debug;
32 module_param(debug, int, 0644);
33
device_run(void * prv)34 static void device_run(void *prv)
35 {
36 struct rga_ctx *ctx = prv;
37 struct rockchip_rga *rga = ctx->rga;
38 struct vb2_v4l2_buffer *src, *dst;
39 unsigned long flags;
40
41 spin_lock_irqsave(&rga->ctrl_lock, flags);
42
43 rga->curr = ctx;
44
45 src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
46 dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
47
48 rga_buf_map(&src->vb2_buf);
49 rga_buf_map(&dst->vb2_buf);
50
51 rga_hw_start(rga);
52
53 spin_unlock_irqrestore(&rga->ctrl_lock, flags);
54 }
55
rga_isr(int irq,void * prv)56 static irqreturn_t rga_isr(int irq, void *prv)
57 {
58 struct rockchip_rga *rga = prv;
59 int intr;
60
61 intr = rga_read(rga, RGA_INT) & 0xf;
62
63 rga_mod(rga, RGA_INT, intr << 4, 0xf << 4);
64
65 if (intr & 0x04) {
66 struct vb2_v4l2_buffer *src, *dst;
67 struct rga_ctx *ctx = rga->curr;
68
69 WARN_ON(!ctx);
70
71 rga->curr = NULL;
72
73 src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
74 dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
75
76 WARN_ON(!src);
77 WARN_ON(!dst);
78
79 v4l2_m2m_buf_copy_metadata(src, dst, true);
80
81 v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE);
82 v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE);
83 v4l2_m2m_job_finish(rga->m2m_dev, ctx->fh.m2m_ctx);
84 }
85
86 return IRQ_HANDLED;
87 }
88
89 static const struct v4l2_m2m_ops rga_m2m_ops = {
90 .device_run = device_run,
91 };
92
93 static int
queue_init(void * priv,struct vb2_queue * src_vq,struct vb2_queue * dst_vq)94 queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
95 {
96 struct rga_ctx *ctx = priv;
97 int ret;
98
99 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
100 src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
101 src_vq->drv_priv = ctx;
102 src_vq->ops = &rga_qops;
103 src_vq->mem_ops = &vb2_dma_sg_memops;
104 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
105 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
106 src_vq->lock = &ctx->rga->mutex;
107 src_vq->dev = ctx->rga->v4l2_dev.dev;
108
109 ret = vb2_queue_init(src_vq);
110 if (ret)
111 return ret;
112
113 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
114 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
115 dst_vq->drv_priv = ctx;
116 dst_vq->ops = &rga_qops;
117 dst_vq->mem_ops = &vb2_dma_sg_memops;
118 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
119 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
120 dst_vq->lock = &ctx->rga->mutex;
121 dst_vq->dev = ctx->rga->v4l2_dev.dev;
122
123 return vb2_queue_init(dst_vq);
124 }
125
rga_s_ctrl(struct v4l2_ctrl * ctrl)126 static int rga_s_ctrl(struct v4l2_ctrl *ctrl)
127 {
128 struct rga_ctx *ctx = container_of(ctrl->handler, struct rga_ctx,
129 ctrl_handler);
130 unsigned long flags;
131
132 spin_lock_irqsave(&ctx->rga->ctrl_lock, flags);
133 switch (ctrl->id) {
134 case V4L2_CID_HFLIP:
135 ctx->hflip = ctrl->val;
136 break;
137 case V4L2_CID_VFLIP:
138 ctx->vflip = ctrl->val;
139 break;
140 case V4L2_CID_ROTATE:
141 ctx->rotate = ctrl->val;
142 break;
143 case V4L2_CID_BG_COLOR:
144 ctx->fill_color = ctrl->val;
145 break;
146 }
147 spin_unlock_irqrestore(&ctx->rga->ctrl_lock, flags);
148 return 0;
149 }
150
151 static const struct v4l2_ctrl_ops rga_ctrl_ops = {
152 .s_ctrl = rga_s_ctrl,
153 };
154
rga_setup_ctrls(struct rga_ctx * ctx)155 static int rga_setup_ctrls(struct rga_ctx *ctx)
156 {
157 struct rockchip_rga *rga = ctx->rga;
158
159 v4l2_ctrl_handler_init(&ctx->ctrl_handler, 4);
160
161 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
162 V4L2_CID_HFLIP, 0, 1, 1, 0);
163
164 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
165 V4L2_CID_VFLIP, 0, 1, 1, 0);
166
167 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
168 V4L2_CID_ROTATE, 0, 270, 90, 0);
169
170 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
171 V4L2_CID_BG_COLOR, 0, 0xffffffff, 1, 0);
172
173 if (ctx->ctrl_handler.error) {
174 int err = ctx->ctrl_handler.error;
175
176 v4l2_err(&rga->v4l2_dev, "%s failed\n", __func__);
177 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
178 return err;
179 }
180
181 return 0;
182 }
183
184 static struct rga_fmt formats[] = {
185 {
186 .fourcc = V4L2_PIX_FMT_ARGB32,
187 .color_swap = RGA_COLOR_RB_SWAP,
188 .hw_format = RGA_COLOR_FMT_ABGR8888,
189 .depth = 32,
190 .uv_factor = 1,
191 .y_div = 1,
192 .x_div = 1,
193 },
194 {
195 .fourcc = V4L2_PIX_FMT_XRGB32,
196 .color_swap = RGA_COLOR_RB_SWAP,
197 .hw_format = RGA_COLOR_FMT_XBGR8888,
198 .depth = 32,
199 .uv_factor = 1,
200 .y_div = 1,
201 .x_div = 1,
202 },
203 {
204 .fourcc = V4L2_PIX_FMT_ABGR32,
205 .color_swap = RGA_COLOR_ALPHA_SWAP,
206 .hw_format = RGA_COLOR_FMT_ABGR8888,
207 .depth = 32,
208 .uv_factor = 1,
209 .y_div = 1,
210 .x_div = 1,
211 },
212 {
213 .fourcc = V4L2_PIX_FMT_XBGR32,
214 .color_swap = RGA_COLOR_ALPHA_SWAP,
215 .hw_format = RGA_COLOR_FMT_XBGR8888,
216 .depth = 32,
217 .uv_factor = 1,
218 .y_div = 1,
219 .x_div = 1,
220 },
221 {
222 .fourcc = V4L2_PIX_FMT_RGB24,
223 .color_swap = RGA_COLOR_NONE_SWAP,
224 .hw_format = RGA_COLOR_FMT_RGB888,
225 .depth = 24,
226 .uv_factor = 1,
227 .y_div = 1,
228 .x_div = 1,
229 },
230 {
231 .fourcc = V4L2_PIX_FMT_BGR24,
232 .color_swap = RGA_COLOR_RB_SWAP,
233 .hw_format = RGA_COLOR_FMT_RGB888,
234 .depth = 24,
235 .uv_factor = 1,
236 .y_div = 1,
237 .x_div = 1,
238 },
239 {
240 .fourcc = V4L2_PIX_FMT_ARGB444,
241 .color_swap = RGA_COLOR_RB_SWAP,
242 .hw_format = RGA_COLOR_FMT_ABGR4444,
243 .depth = 16,
244 .uv_factor = 1,
245 .y_div = 1,
246 .x_div = 1,
247 },
248 {
249 .fourcc = V4L2_PIX_FMT_ARGB555,
250 .color_swap = RGA_COLOR_RB_SWAP,
251 .hw_format = RGA_COLOR_FMT_ABGR1555,
252 .depth = 16,
253 .uv_factor = 1,
254 .y_div = 1,
255 .x_div = 1,
256 },
257 {
258 .fourcc = V4L2_PIX_FMT_RGB565,
259 .color_swap = RGA_COLOR_RB_SWAP,
260 .hw_format = RGA_COLOR_FMT_BGR565,
261 .depth = 16,
262 .uv_factor = 1,
263 .y_div = 1,
264 .x_div = 1,
265 },
266 {
267 .fourcc = V4L2_PIX_FMT_NV21,
268 .color_swap = RGA_COLOR_UV_SWAP,
269 .hw_format = RGA_COLOR_FMT_YUV420SP,
270 .depth = 12,
271 .uv_factor = 4,
272 .y_div = 2,
273 .x_div = 1,
274 },
275 {
276 .fourcc = V4L2_PIX_FMT_NV61,
277 .color_swap = RGA_COLOR_UV_SWAP,
278 .hw_format = RGA_COLOR_FMT_YUV422SP,
279 .depth = 16,
280 .uv_factor = 2,
281 .y_div = 1,
282 .x_div = 1,
283 },
284 {
285 .fourcc = V4L2_PIX_FMT_NV12,
286 .color_swap = RGA_COLOR_NONE_SWAP,
287 .hw_format = RGA_COLOR_FMT_YUV420SP,
288 .depth = 12,
289 .uv_factor = 4,
290 .y_div = 2,
291 .x_div = 1,
292 },
293 {
294 .fourcc = V4L2_PIX_FMT_NV16,
295 .color_swap = RGA_COLOR_NONE_SWAP,
296 .hw_format = RGA_COLOR_FMT_YUV422SP,
297 .depth = 16,
298 .uv_factor = 2,
299 .y_div = 1,
300 .x_div = 1,
301 },
302 {
303 .fourcc = V4L2_PIX_FMT_YUV420,
304 .color_swap = RGA_COLOR_NONE_SWAP,
305 .hw_format = RGA_COLOR_FMT_YUV420P,
306 .depth = 12,
307 .uv_factor = 4,
308 .y_div = 2,
309 .x_div = 2,
310 },
311 {
312 .fourcc = V4L2_PIX_FMT_YUV422P,
313 .color_swap = RGA_COLOR_NONE_SWAP,
314 .hw_format = RGA_COLOR_FMT_YUV422P,
315 .depth = 16,
316 .uv_factor = 2,
317 .y_div = 1,
318 .x_div = 2,
319 },
320 {
321 .fourcc = V4L2_PIX_FMT_YVU420,
322 .color_swap = RGA_COLOR_UV_SWAP,
323 .hw_format = RGA_COLOR_FMT_YUV420P,
324 .depth = 12,
325 .uv_factor = 4,
326 .y_div = 2,
327 .x_div = 2,
328 },
329 };
330
331 #define NUM_FORMATS ARRAY_SIZE(formats)
332
rga_fmt_find(struct v4l2_format * f)333 static struct rga_fmt *rga_fmt_find(struct v4l2_format *f)
334 {
335 unsigned int i;
336
337 for (i = 0; i < NUM_FORMATS; i++) {
338 if (formats[i].fourcc == f->fmt.pix.pixelformat)
339 return &formats[i];
340 }
341 return NULL;
342 }
343
344 static struct rga_frame def_frame = {
345 .width = DEFAULT_WIDTH,
346 .height = DEFAULT_HEIGHT,
347 .colorspace = V4L2_COLORSPACE_DEFAULT,
348 .crop.left = 0,
349 .crop.top = 0,
350 .crop.width = DEFAULT_WIDTH,
351 .crop.height = DEFAULT_HEIGHT,
352 .fmt = &formats[0],
353 };
354
rga_get_frame(struct rga_ctx * ctx,enum v4l2_buf_type type)355 struct rga_frame *rga_get_frame(struct rga_ctx *ctx, enum v4l2_buf_type type)
356 {
357 switch (type) {
358 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
359 return &ctx->in;
360 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
361 return &ctx->out;
362 default:
363 return ERR_PTR(-EINVAL);
364 }
365 }
366
rga_open(struct file * file)367 static int rga_open(struct file *file)
368 {
369 struct rockchip_rga *rga = video_drvdata(file);
370 struct rga_ctx *ctx = NULL;
371 int ret = 0;
372
373 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
374 if (!ctx)
375 return -ENOMEM;
376 ctx->rga = rga;
377 /* Set default formats */
378 ctx->in = def_frame;
379 ctx->out = def_frame;
380
381 if (mutex_lock_interruptible(&rga->mutex)) {
382 kfree(ctx);
383 return -ERESTARTSYS;
384 }
385 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(rga->m2m_dev, ctx, &queue_init);
386 if (IS_ERR(ctx->fh.m2m_ctx)) {
387 ret = PTR_ERR(ctx->fh.m2m_ctx);
388 mutex_unlock(&rga->mutex);
389 kfree(ctx);
390 return ret;
391 }
392 v4l2_fh_init(&ctx->fh, video_devdata(file));
393 file->private_data = &ctx->fh;
394 v4l2_fh_add(&ctx->fh);
395
396 rga_setup_ctrls(ctx);
397
398 /* Write the default values to the ctx struct */
399 v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
400
401 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
402 mutex_unlock(&rga->mutex);
403
404 return 0;
405 }
406
rga_release(struct file * file)407 static int rga_release(struct file *file)
408 {
409 struct rga_ctx *ctx =
410 container_of(file->private_data, struct rga_ctx, fh);
411 struct rockchip_rga *rga = ctx->rga;
412
413 mutex_lock(&rga->mutex);
414
415 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
416
417 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
418 v4l2_fh_del(&ctx->fh);
419 v4l2_fh_exit(&ctx->fh);
420 kfree(ctx);
421
422 mutex_unlock(&rga->mutex);
423
424 return 0;
425 }
426
427 static const struct v4l2_file_operations rga_fops = {
428 .owner = THIS_MODULE,
429 .open = rga_open,
430 .release = rga_release,
431 .poll = v4l2_m2m_fop_poll,
432 .unlocked_ioctl = video_ioctl2,
433 .mmap = v4l2_m2m_fop_mmap,
434 };
435
436 static int
vidioc_querycap(struct file * file,void * priv,struct v4l2_capability * cap)437 vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
438 {
439 strscpy(cap->driver, RGA_NAME, sizeof(cap->driver));
440 strscpy(cap->card, "rockchip-rga", sizeof(cap->card));
441 strscpy(cap->bus_info, "platform:rga", sizeof(cap->bus_info));
442
443 return 0;
444 }
445
vidioc_enum_fmt(struct file * file,void * prv,struct v4l2_fmtdesc * f)446 static int vidioc_enum_fmt(struct file *file, void *prv, struct v4l2_fmtdesc *f)
447 {
448 struct rga_fmt *fmt;
449
450 if (f->index >= NUM_FORMATS)
451 return -EINVAL;
452
453 fmt = &formats[f->index];
454 f->pixelformat = fmt->fourcc;
455
456 return 0;
457 }
458
vidioc_g_fmt(struct file * file,void * prv,struct v4l2_format * f)459 static int vidioc_g_fmt(struct file *file, void *prv, struct v4l2_format *f)
460 {
461 struct rga_ctx *ctx = prv;
462 struct vb2_queue *vq;
463 struct rga_frame *frm;
464
465 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
466 if (!vq)
467 return -EINVAL;
468 frm = rga_get_frame(ctx, f->type);
469 if (IS_ERR(frm))
470 return PTR_ERR(frm);
471
472 f->fmt.pix.width = frm->width;
473 f->fmt.pix.height = frm->height;
474 f->fmt.pix.field = V4L2_FIELD_NONE;
475 f->fmt.pix.pixelformat = frm->fmt->fourcc;
476 f->fmt.pix.bytesperline = frm->stride;
477 f->fmt.pix.sizeimage = frm->size;
478 f->fmt.pix.colorspace = frm->colorspace;
479
480 return 0;
481 }
482
vidioc_try_fmt(struct file * file,void * prv,struct v4l2_format * f)483 static int vidioc_try_fmt(struct file *file, void *prv, struct v4l2_format *f)
484 {
485 struct rga_fmt *fmt;
486
487 fmt = rga_fmt_find(f);
488 if (!fmt) {
489 fmt = &formats[0];
490 f->fmt.pix.pixelformat = fmt->fourcc;
491 }
492
493 f->fmt.pix.field = V4L2_FIELD_NONE;
494
495 if (f->fmt.pix.width > MAX_WIDTH)
496 f->fmt.pix.width = MAX_WIDTH;
497 if (f->fmt.pix.height > MAX_HEIGHT)
498 f->fmt.pix.height = MAX_HEIGHT;
499
500 if (f->fmt.pix.width < MIN_WIDTH)
501 f->fmt.pix.width = MIN_WIDTH;
502 if (f->fmt.pix.height < MIN_HEIGHT)
503 f->fmt.pix.height = MIN_HEIGHT;
504
505 if (fmt->hw_format >= RGA_COLOR_FMT_YUV422SP)
506 f->fmt.pix.bytesperline = f->fmt.pix.width;
507 else
508 f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3;
509
510 f->fmt.pix.sizeimage =
511 f->fmt.pix.height * (f->fmt.pix.width * fmt->depth) >> 3;
512
513 return 0;
514 }
515
vidioc_s_fmt(struct file * file,void * prv,struct v4l2_format * f)516 static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f)
517 {
518 struct rga_ctx *ctx = prv;
519 struct rockchip_rga *rga = ctx->rga;
520 struct vb2_queue *vq;
521 struct rga_frame *frm;
522 struct rga_fmt *fmt;
523 int ret = 0;
524
525 /* Adjust all values accordingly to the hardware capabilities
526 * and chosen format.
527 */
528 ret = vidioc_try_fmt(file, prv, f);
529 if (ret)
530 return ret;
531 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
532 if (vb2_is_busy(vq)) {
533 v4l2_err(&rga->v4l2_dev, "queue (%d) bust\n", f->type);
534 return -EBUSY;
535 }
536 frm = rga_get_frame(ctx, f->type);
537 if (IS_ERR(frm))
538 return PTR_ERR(frm);
539 fmt = rga_fmt_find(f);
540 if (!fmt)
541 return -EINVAL;
542 frm->width = f->fmt.pix.width;
543 frm->height = f->fmt.pix.height;
544 frm->size = f->fmt.pix.sizeimage;
545 frm->fmt = fmt;
546 frm->stride = f->fmt.pix.bytesperline;
547 frm->colorspace = f->fmt.pix.colorspace;
548
549 /* Reset crop settings */
550 frm->crop.left = 0;
551 frm->crop.top = 0;
552 frm->crop.width = frm->width;
553 frm->crop.height = frm->height;
554
555 return 0;
556 }
557
vidioc_g_selection(struct file * file,void * prv,struct v4l2_selection * s)558 static int vidioc_g_selection(struct file *file, void *prv,
559 struct v4l2_selection *s)
560 {
561 struct rga_ctx *ctx = prv;
562 struct rga_frame *f;
563 bool use_frame = false;
564
565 f = rga_get_frame(ctx, s->type);
566 if (IS_ERR(f))
567 return PTR_ERR(f);
568
569 switch (s->target) {
570 case V4L2_SEL_TGT_COMPOSE_DEFAULT:
571 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
572 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
573 return -EINVAL;
574 break;
575 case V4L2_SEL_TGT_CROP_DEFAULT:
576 case V4L2_SEL_TGT_CROP_BOUNDS:
577 if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
578 return -EINVAL;
579 break;
580 case V4L2_SEL_TGT_COMPOSE:
581 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
582 return -EINVAL;
583 use_frame = true;
584 break;
585 case V4L2_SEL_TGT_CROP:
586 if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
587 return -EINVAL;
588 use_frame = true;
589 break;
590 default:
591 return -EINVAL;
592 }
593
594 if (use_frame) {
595 s->r = f->crop;
596 } else {
597 s->r.left = 0;
598 s->r.top = 0;
599 s->r.width = f->width;
600 s->r.height = f->height;
601 }
602
603 return 0;
604 }
605
vidioc_s_selection(struct file * file,void * prv,struct v4l2_selection * s)606 static int vidioc_s_selection(struct file *file, void *prv,
607 struct v4l2_selection *s)
608 {
609 struct rga_ctx *ctx = prv;
610 struct rockchip_rga *rga = ctx->rga;
611 struct rga_frame *f;
612 int ret = 0;
613
614 f = rga_get_frame(ctx, s->type);
615 if (IS_ERR(f))
616 return PTR_ERR(f);
617
618 switch (s->target) {
619 case V4L2_SEL_TGT_COMPOSE:
620 /*
621 * COMPOSE target is only valid for capture buffer type, return
622 * error for output buffer type
623 */
624 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
625 return -EINVAL;
626 break;
627 case V4L2_SEL_TGT_CROP:
628 /*
629 * CROP target is only valid for output buffer type, return
630 * error for capture buffer type
631 */
632 if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
633 return -EINVAL;
634 break;
635 /*
636 * bound and default crop/compose targets are invalid targets to
637 * try/set
638 */
639 default:
640 return -EINVAL;
641 }
642
643 if (s->r.top < 0 || s->r.left < 0) {
644 v4l2_dbg(debug, 1, &rga->v4l2_dev,
645 "doesn't support negative values for top & left.\n");
646 return -EINVAL;
647 }
648
649 if (s->r.left + s->r.width > f->width ||
650 s->r.top + s->r.height > f->height ||
651 s->r.width < MIN_WIDTH || s->r.height < MIN_HEIGHT) {
652 v4l2_dbg(debug, 1, &rga->v4l2_dev, "unsupported crop value.\n");
653 return -EINVAL;
654 }
655
656 f->crop = s->r;
657
658 return ret;
659 }
660
661 static const struct v4l2_ioctl_ops rga_ioctl_ops = {
662 .vidioc_querycap = vidioc_querycap,
663
664 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt,
665 .vidioc_g_fmt_vid_cap = vidioc_g_fmt,
666 .vidioc_try_fmt_vid_cap = vidioc_try_fmt,
667 .vidioc_s_fmt_vid_cap = vidioc_s_fmt,
668
669 .vidioc_enum_fmt_vid_out = vidioc_enum_fmt,
670 .vidioc_g_fmt_vid_out = vidioc_g_fmt,
671 .vidioc_try_fmt_vid_out = vidioc_try_fmt,
672 .vidioc_s_fmt_vid_out = vidioc_s_fmt,
673
674 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
675 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
676 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
677 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
678 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
679 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
680 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
681
682 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
683 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
684
685 .vidioc_streamon = v4l2_m2m_ioctl_streamon,
686 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
687
688 .vidioc_g_selection = vidioc_g_selection,
689 .vidioc_s_selection = vidioc_s_selection,
690 };
691
692 static const struct video_device rga_videodev = {
693 .name = "rockchip-rga",
694 .fops = &rga_fops,
695 .ioctl_ops = &rga_ioctl_ops,
696 .minor = -1,
697 .release = video_device_release,
698 .vfl_dir = VFL_DIR_M2M,
699 .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
700 };
701
rga_enable_clocks(struct rockchip_rga * rga)702 static int rga_enable_clocks(struct rockchip_rga *rga)
703 {
704 int ret;
705
706 ret = clk_prepare_enable(rga->sclk);
707 if (ret) {
708 dev_err(rga->dev, "Cannot enable rga sclk: %d\n", ret);
709 return ret;
710 }
711
712 ret = clk_prepare_enable(rga->aclk);
713 if (ret) {
714 dev_err(rga->dev, "Cannot enable rga aclk: %d\n", ret);
715 goto err_disable_sclk;
716 }
717
718 ret = clk_prepare_enable(rga->hclk);
719 if (ret) {
720 dev_err(rga->dev, "Cannot enable rga hclk: %d\n", ret);
721 goto err_disable_aclk;
722 }
723
724 return 0;
725
726 err_disable_aclk:
727 clk_disable_unprepare(rga->aclk);
728 err_disable_sclk:
729 clk_disable_unprepare(rga->sclk);
730
731 return ret;
732 }
733
rga_disable_clocks(struct rockchip_rga * rga)734 static void rga_disable_clocks(struct rockchip_rga *rga)
735 {
736 clk_disable_unprepare(rga->sclk);
737 clk_disable_unprepare(rga->hclk);
738 clk_disable_unprepare(rga->aclk);
739 }
740
rga_parse_dt(struct rockchip_rga * rga)741 static int rga_parse_dt(struct rockchip_rga *rga)
742 {
743 struct reset_control *core_rst, *axi_rst, *ahb_rst;
744
745 core_rst = devm_reset_control_get(rga->dev, "core");
746 if (IS_ERR(core_rst)) {
747 dev_err(rga->dev, "failed to get core reset controller\n");
748 return PTR_ERR(core_rst);
749 }
750
751 axi_rst = devm_reset_control_get(rga->dev, "axi");
752 if (IS_ERR(axi_rst)) {
753 dev_err(rga->dev, "failed to get axi reset controller\n");
754 return PTR_ERR(axi_rst);
755 }
756
757 ahb_rst = devm_reset_control_get(rga->dev, "ahb");
758 if (IS_ERR(ahb_rst)) {
759 dev_err(rga->dev, "failed to get ahb reset controller\n");
760 return PTR_ERR(ahb_rst);
761 }
762
763 reset_control_assert(core_rst);
764 udelay(1);
765 reset_control_deassert(core_rst);
766
767 reset_control_assert(axi_rst);
768 udelay(1);
769 reset_control_deassert(axi_rst);
770
771 reset_control_assert(ahb_rst);
772 udelay(1);
773 reset_control_deassert(ahb_rst);
774
775 rga->sclk = devm_clk_get(rga->dev, "sclk");
776 if (IS_ERR(rga->sclk)) {
777 dev_err(rga->dev, "failed to get sclk clock\n");
778 return PTR_ERR(rga->sclk);
779 }
780
781 rga->aclk = devm_clk_get(rga->dev, "aclk");
782 if (IS_ERR(rga->aclk)) {
783 dev_err(rga->dev, "failed to get aclk clock\n");
784 return PTR_ERR(rga->aclk);
785 }
786
787 rga->hclk = devm_clk_get(rga->dev, "hclk");
788 if (IS_ERR(rga->hclk)) {
789 dev_err(rga->dev, "failed to get hclk clock\n");
790 return PTR_ERR(rga->hclk);
791 }
792
793 return 0;
794 }
795
rga_probe(struct platform_device * pdev)796 static int rga_probe(struct platform_device *pdev)
797 {
798 struct rockchip_rga *rga;
799 struct video_device *vfd;
800 int ret = 0;
801 int irq;
802
803 if (!pdev->dev.of_node)
804 return -ENODEV;
805
806 rga = devm_kzalloc(&pdev->dev, sizeof(*rga), GFP_KERNEL);
807 if (!rga)
808 return -ENOMEM;
809
810 rga->dev = &pdev->dev;
811 spin_lock_init(&rga->ctrl_lock);
812 mutex_init(&rga->mutex);
813
814 ret = rga_parse_dt(rga);
815 if (ret)
816 return dev_err_probe(&pdev->dev, ret, "Unable to parse OF data\n");
817
818 pm_runtime_enable(rga->dev);
819
820 rga->regs = devm_platform_ioremap_resource(pdev, 0);
821 if (IS_ERR(rga->regs)) {
822 ret = PTR_ERR(rga->regs);
823 goto err_put_clk;
824 }
825
826 irq = platform_get_irq(pdev, 0);
827 if (irq < 0) {
828 ret = irq;
829 goto err_put_clk;
830 }
831
832 ret = devm_request_irq(rga->dev, irq, rga_isr, 0,
833 dev_name(rga->dev), rga);
834 if (ret < 0) {
835 dev_err(rga->dev, "failed to request irq\n");
836 goto err_put_clk;
837 }
838
839 ret = v4l2_device_register(&pdev->dev, &rga->v4l2_dev);
840 if (ret)
841 goto err_put_clk;
842 vfd = video_device_alloc();
843 if (!vfd) {
844 v4l2_err(&rga->v4l2_dev, "Failed to allocate video device\n");
845 ret = -ENOMEM;
846 goto unreg_v4l2_dev;
847 }
848 *vfd = rga_videodev;
849 vfd->lock = &rga->mutex;
850 vfd->v4l2_dev = &rga->v4l2_dev;
851
852 video_set_drvdata(vfd, rga);
853 rga->vfd = vfd;
854
855 platform_set_drvdata(pdev, rga);
856 rga->m2m_dev = v4l2_m2m_init(&rga_m2m_ops);
857 if (IS_ERR(rga->m2m_dev)) {
858 v4l2_err(&rga->v4l2_dev, "Failed to init mem2mem device\n");
859 ret = PTR_ERR(rga->m2m_dev);
860 goto rel_vdev;
861 }
862
863 ret = pm_runtime_resume_and_get(rga->dev);
864 if (ret < 0)
865 goto rel_m2m;
866
867 rga->version.major = (rga_read(rga, RGA_VERSION_INFO) >> 24) & 0xFF;
868 rga->version.minor = (rga_read(rga, RGA_VERSION_INFO) >> 20) & 0x0F;
869
870 v4l2_info(&rga->v4l2_dev, "HW Version: 0x%02x.%02x\n",
871 rga->version.major, rga->version.minor);
872
873 pm_runtime_put(rga->dev);
874
875 /* Create CMD buffer */
876 rga->cmdbuf_virt = dma_alloc_attrs(rga->dev, RGA_CMDBUF_SIZE,
877 &rga->cmdbuf_phy, GFP_KERNEL,
878 DMA_ATTR_WRITE_COMBINE);
879 if (!rga->cmdbuf_virt) {
880 ret = -ENOMEM;
881 goto rel_m2m;
882 }
883
884 rga->src_mmu_pages =
885 (unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
886 if (!rga->src_mmu_pages) {
887 ret = -ENOMEM;
888 goto free_dma;
889 }
890 rga->dst_mmu_pages =
891 (unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
892 if (!rga->dst_mmu_pages) {
893 ret = -ENOMEM;
894 goto free_src_pages;
895 }
896
897 def_frame.stride = (def_frame.width * def_frame.fmt->depth) >> 3;
898 def_frame.size = def_frame.stride * def_frame.height;
899
900 ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);
901 if (ret) {
902 v4l2_err(&rga->v4l2_dev, "Failed to register video device\n");
903 goto free_dst_pages;
904 }
905
906 v4l2_info(&rga->v4l2_dev, "Registered %s as /dev/%s\n",
907 vfd->name, video_device_node_name(vfd));
908
909 return 0;
910
911 free_dst_pages:
912 free_pages((unsigned long)rga->dst_mmu_pages, 3);
913 free_src_pages:
914 free_pages((unsigned long)rga->src_mmu_pages, 3);
915 free_dma:
916 dma_free_attrs(rga->dev, RGA_CMDBUF_SIZE, rga->cmdbuf_virt,
917 rga->cmdbuf_phy, DMA_ATTR_WRITE_COMBINE);
918 rel_m2m:
919 v4l2_m2m_release(rga->m2m_dev);
920 rel_vdev:
921 video_device_release(vfd);
922 unreg_v4l2_dev:
923 v4l2_device_unregister(&rga->v4l2_dev);
924 err_put_clk:
925 pm_runtime_disable(rga->dev);
926
927 return ret;
928 }
929
rga_remove(struct platform_device * pdev)930 static void rga_remove(struct platform_device *pdev)
931 {
932 struct rockchip_rga *rga = platform_get_drvdata(pdev);
933
934 dma_free_attrs(rga->dev, RGA_CMDBUF_SIZE, rga->cmdbuf_virt,
935 rga->cmdbuf_phy, DMA_ATTR_WRITE_COMBINE);
936
937 free_pages((unsigned long)rga->src_mmu_pages, 3);
938 free_pages((unsigned long)rga->dst_mmu_pages, 3);
939
940 v4l2_info(&rga->v4l2_dev, "Removing\n");
941
942 v4l2_m2m_release(rga->m2m_dev);
943 video_unregister_device(rga->vfd);
944 v4l2_device_unregister(&rga->v4l2_dev);
945
946 pm_runtime_disable(rga->dev);
947 }
948
rga_runtime_suspend(struct device * dev)949 static int __maybe_unused rga_runtime_suspend(struct device *dev)
950 {
951 struct rockchip_rga *rga = dev_get_drvdata(dev);
952
953 rga_disable_clocks(rga);
954
955 return 0;
956 }
957
rga_runtime_resume(struct device * dev)958 static int __maybe_unused rga_runtime_resume(struct device *dev)
959 {
960 struct rockchip_rga *rga = dev_get_drvdata(dev);
961
962 return rga_enable_clocks(rga);
963 }
964
965 static const struct dev_pm_ops rga_pm = {
966 SET_RUNTIME_PM_OPS(rga_runtime_suspend,
967 rga_runtime_resume, NULL)
968 };
969
970 static const struct of_device_id rockchip_rga_match[] = {
971 {
972 .compatible = "rockchip,rk3288-rga",
973 },
974 {
975 .compatible = "rockchip,rk3399-rga",
976 },
977 {},
978 };
979
980 MODULE_DEVICE_TABLE(of, rockchip_rga_match);
981
982 static struct platform_driver rga_pdrv = {
983 .probe = rga_probe,
984 .remove_new = rga_remove,
985 .driver = {
986 .name = RGA_NAME,
987 .pm = &rga_pm,
988 .of_match_table = rockchip_rga_match,
989 },
990 };
991
992 module_platform_driver(rga_pdrv);
993
994 MODULE_AUTHOR("Jacob Chen <jacob-chen@iotwrt.com>");
995 MODULE_DESCRIPTION("Rockchip Raster 2d Graphic Acceleration Unit");
996 MODULE_LICENSE("GPL");
997
