1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Tesla Full Self-Driving SoC device tree source 4 * 5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * Copyright (c) 2017-2022 Tesla, Inc. 8 * https://www.tesla.com 9 */ 10 11#include <dt-bindings/clock/fsd-clk.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/ { 15 compatible = "tesla,fsd"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 i2c0 = &hsi2c_0; 22 i2c1 = &hsi2c_1; 23 i2c2 = &hsi2c_2; 24 i2c3 = &hsi2c_3; 25 i2c4 = &hsi2c_4; 26 i2c5 = &hsi2c_5; 27 i2c6 = &hsi2c_6; 28 i2c7 = &hsi2c_7; 29 pinctrl0 = &pinctrl_fsys0; 30 pinctrl1 = &pinctrl_peric; 31 pinctrl2 = &pinctrl_pmu; 32 spi0 = &spi_0; 33 spi1 = &spi_1; 34 spi2 = &spi_2; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 cpu-map { 42 cluster0 { 43 core0 { 44 cpu = <&cpucl0_0>; 45 }; 46 core1 { 47 cpu = <&cpucl0_1>; 48 }; 49 core2 { 50 cpu = <&cpucl0_2>; 51 }; 52 core3 { 53 cpu = <&cpucl0_3>; 54 }; 55 }; 56 57 cluster1 { 58 core0 { 59 cpu = <&cpucl1_0>; 60 }; 61 core1 { 62 cpu = <&cpucl1_1>; 63 }; 64 core2 { 65 cpu = <&cpucl1_2>; 66 }; 67 core3 { 68 cpu = <&cpucl1_3>; 69 }; 70 }; 71 72 cluster2 { 73 core0 { 74 cpu = <&cpucl2_0>; 75 }; 76 core1 { 77 cpu = <&cpucl2_1>; 78 }; 79 core2 { 80 cpu = <&cpucl2_2>; 81 }; 82 core3 { 83 cpu = <&cpucl2_3>; 84 }; 85 }; 86 }; 87 88 /* Cluster 0 */ 89 cpucl0_0: cpu@0 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a72"; 92 reg = <0x0 0x000>; 93 enable-method = "psci"; 94 clock-frequency = <2400000000>; 95 cpu-idle-states = <&CPU_SLEEP>; 96 i-cache-size = <0xc000>; 97 i-cache-line-size = <64>; 98 i-cache-sets = <256>; 99 d-cache-size = <0x8000>; 100 d-cache-line-size = <64>; 101 d-cache-sets = <256>; 102 next-level-cache = <&cpucl_l2>; 103 }; 104 105 cpucl0_1: cpu@1 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a72"; 108 reg = <0x0 0x001>; 109 enable-method = "psci"; 110 clock-frequency = <2400000000>; 111 cpu-idle-states = <&CPU_SLEEP>; 112 i-cache-size = <0xc000>; 113 i-cache-line-size = <64>; 114 i-cache-sets = <256>; 115 d-cache-size = <0x8000>; 116 d-cache-line-size = <64>; 117 d-cache-sets = <256>; 118 next-level-cache = <&cpucl_l2>; 119 }; 120 121 cpucl0_2: cpu@2 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a72"; 124 reg = <0x0 0x002>; 125 enable-method = "psci"; 126 clock-frequency = <2400000000>; 127 cpu-idle-states = <&CPU_SLEEP>; 128 i-cache-size = <0xc000>; 129 i-cache-line-size = <64>; 130 i-cache-sets = <256>; 131 d-cache-size = <0x8000>; 132 d-cache-line-size = <64>; 133 d-cache-sets = <256>; 134 next-level-cache = <&cpucl_l2>; 135 }; 136 137 cpucl0_3: cpu@3 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a72"; 140 reg = <0x0 0x003>; 141 enable-method = "psci"; 142 cpu-idle-states = <&CPU_SLEEP>; 143 i-cache-size = <0xc000>; 144 i-cache-line-size = <64>; 145 i-cache-sets = <256>; 146 d-cache-size = <0x8000>; 147 d-cache-line-size = <64>; 148 d-cache-sets = <256>; 149 next-level-cache = <&cpucl_l2>; 150 }; 151 152 /* Cluster 1 */ 153 cpucl1_0: cpu@100 { 154 device_type = "cpu"; 155 compatible = "arm,cortex-a72"; 156 reg = <0x0 0x100>; 157 enable-method = "psci"; 158 clock-frequency = <2400000000>; 159 cpu-idle-states = <&CPU_SLEEP>; 160 i-cache-size = <0xc000>; 161 i-cache-line-size = <64>; 162 i-cache-sets = <256>; 163 d-cache-size = <0x8000>; 164 d-cache-line-size = <64>; 165 d-cache-sets = <256>; 166 next-level-cache = <&cpucl_l2>; 167 }; 168 169 cpucl1_1: cpu@101 { 170 device_type = "cpu"; 171 compatible = "arm,cortex-a72"; 172 reg = <0x0 0x101>; 173 enable-method = "psci"; 174 clock-frequency = <2400000000>; 175 cpu-idle-states = <&CPU_SLEEP>; 176 i-cache-size = <0xc000>; 177 i-cache-line-size = <64>; 178 i-cache-sets = <256>; 179 d-cache-size = <0x8000>; 180 d-cache-line-size = <64>; 181 d-cache-sets = <256>; 182 next-level-cache = <&cpucl_l2>; 183 }; 184 185 cpucl1_2: cpu@102 { 186 device_type = "cpu"; 187 compatible = "arm,cortex-a72"; 188 reg = <0x0 0x102>; 189 enable-method = "psci"; 190 clock-frequency = <2400000000>; 191 cpu-idle-states = <&CPU_SLEEP>; 192 i-cache-size = <0xc000>; 193 i-cache-line-size = <64>; 194 i-cache-sets = <256>; 195 d-cache-size = <0x8000>; 196 d-cache-line-size = <64>; 197 d-cache-sets = <256>; 198 next-level-cache = <&cpucl_l2>; 199 }; 200 201 cpucl1_3: cpu@103 { 202 device_type = "cpu"; 203 compatible = "arm,cortex-a72"; 204 reg = <0x0 0x103>; 205 enable-method = "psci"; 206 clock-frequency = <2400000000>; 207 cpu-idle-states = <&CPU_SLEEP>; 208 i-cache-size = <0xc000>; 209 i-cache-line-size = <64>; 210 i-cache-sets = <256>; 211 d-cache-size = <0x8000>; 212 d-cache-line-size = <64>; 213 d-cache-sets = <256>; 214 next-level-cache = <&cpucl_l2>; 215 }; 216 217 /* Cluster 2 */ 218 cpucl2_0: cpu@200 { 219 device_type = "cpu"; 220 compatible = "arm,cortex-a72"; 221 reg = <0x0 0x200>; 222 enable-method = "psci"; 223 clock-frequency = <2400000000>; 224 cpu-idle-states = <&CPU_SLEEP>; 225 i-cache-size = <0xc000>; 226 i-cache-line-size = <64>; 227 i-cache-sets = <256>; 228 d-cache-size = <0x8000>; 229 d-cache-line-size = <64>; 230 d-cache-sets = <256>; 231 next-level-cache = <&cpucl_l2>; 232 }; 233 234 cpucl2_1: cpu@201 { 235 device_type = "cpu"; 236 compatible = "arm,cortex-a72"; 237 reg = <0x0 0x201>; 238 enable-method = "psci"; 239 clock-frequency = <2400000000>; 240 cpu-idle-states = <&CPU_SLEEP>; 241 i-cache-size = <0xc000>; 242 i-cache-line-size = <64>; 243 i-cache-sets = <256>; 244 d-cache-size = <0x8000>; 245 d-cache-line-size = <64>; 246 d-cache-sets = <256>; 247 next-level-cache = <&cpucl_l2>; 248 }; 249 250 cpucl2_2: cpu@202 { 251 device_type = "cpu"; 252 compatible = "arm,cortex-a72"; 253 reg = <0x0 0x202>; 254 enable-method = "psci"; 255 clock-frequency = <2400000000>; 256 cpu-idle-states = <&CPU_SLEEP>; 257 i-cache-size = <0xc000>; 258 i-cache-line-size = <64>; 259 i-cache-sets = <256>; 260 d-cache-size = <0x8000>; 261 d-cache-line-size = <64>; 262 d-cache-sets = <256>; 263 next-level-cache = <&cpucl_l2>; 264 }; 265 266 cpucl2_3: cpu@203 { 267 device_type = "cpu"; 268 compatible = "arm,cortex-a72"; 269 reg = <0x0 0x203>; 270 enable-method = "psci"; 271 clock-frequency = <2400000000>; 272 cpu-idle-states = <&CPU_SLEEP>; 273 i-cache-size = <0xc000>; 274 i-cache-line-size = <64>; 275 i-cache-sets = <256>; 276 d-cache-size = <0x8000>; 277 d-cache-line-size = <64>; 278 d-cache-sets = <256>; 279 next-level-cache = <&cpucl_l2>; 280 }; 281 282 cpucl_l2: l2-cache0 { 283 compatible = "cache"; 284 cache-level = <2>; 285 cache-unified; 286 cache-size = <0x400000>; 287 cache-line-size = <64>; 288 cache-sets = <4096>; 289 }; 290 291 idle-states { 292 entry-method = "psci"; 293 294 CPU_SLEEP: cpu-sleep { 295 idle-state-name = "c2"; 296 compatible = "arm,idle-state"; 297 local-timer-stop; 298 arm,psci-suspend-param = <0x0010000>; 299 entry-latency-us = <30>; 300 exit-latency-us = <75>; 301 min-residency-us = <300>; 302 }; 303 }; 304 }; 305 306 arm-pmu { 307 compatible = "arm,armv8-pmuv3"; 308 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>; 320 interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>, 321 <&cpucl0_3>, <&cpucl1_0>, <&cpucl1_1>, 322 <&cpucl1_2>, <&cpucl1_3>, <&cpucl2_0>, 323 <&cpucl2_1>, <&cpucl2_2>, <&cpucl2_3>; 324 }; 325 326 psci { 327 compatible = "arm,psci-1.0"; 328 method = "smc"; 329 }; 330 331 timer { 332 compatible = "arm,armv8-timer"; 333 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 334 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 335 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 336 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 337 }; 338 339 fin_pll: clock { 340 compatible = "fixed-clock"; 341 clock-output-names = "fin_pll"; 342 #clock-cells = <0>; 343 }; 344 345 soc: soc@0 { 346 compatible = "simple-bus"; 347 #address-cells = <2>; 348 #size-cells = <2>; 349 ranges = <0x0 0x0 0x0 0x0 0x0 0x18000000>; 350 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 351 352 gic: interrupt-controller@10400000 { 353 compatible = "arm,gic-v3"; 354 #interrupt-cells = <3>; 355 interrupt-controller; 356 reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */ 357 <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */ 358 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 359 }; 360 361 smmu_imem: iommu@10200000 { 362 compatible = "arm,mmu-500"; 363 reg = <0x0 0x10200000 0x0 0x10000>; 364 #iommu-cells = <2>; 365 #global-interrupts = <7>; 366 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 367 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 368 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 369 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 370 /* Performance counter interrupts */ 371 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_0 */ 372 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_1 */ 373 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, /* for IMEM_0 */ 374 /* Per context non-secure context interrupts, 0-3 interrupts */ 375 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 376 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */ 377 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */ 378 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_3 */ 379 }; 380 381 smmu_isp: iommu@12100000 { 382 compatible = "arm,mmu-500"; 383 reg = <0x0 0x12100000 0x0 0x10000>; 384 #iommu-cells = <2>; 385 #global-interrupts = <11>; 386 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 387 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 388 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 389 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 390 /* Performance counter interrupts */ 391 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_CSI */ 392 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_0 */ 393 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_1 */ 394 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_0 */ 395 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_1 */ 396 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_0 */ 397 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_1 */ 398 /* Per context non-secure context interrupts, 0-7 interrupts */ 399 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 400 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */ 401 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */ 402 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_3 */ 403 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_4 */ 404 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_5 */ 405 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_6 */ 406 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_7 */ 407 }; 408 409 smmu_peric: iommu@14900000 { 410 compatible = "arm,mmu-500"; 411 reg = <0x0 0x14900000 0x0 0x10000>; 412 #iommu-cells = <2>; 413 #global-interrupts = <5>; 414 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 415 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 416 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 417 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 418 /* Performance counter interrupts */ 419 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, /* for PERIC */ 420 /* Per context non-secure context interrupts, 0-1 interrupts */ 421 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 422 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */ 423 }; 424 425 smmu_fsys0: iommu@15450000 { 426 compatible = "arm,mmu-500"; 427 reg = <0x0 0x15450000 0x0 0x10000>; 428 #iommu-cells = <2>; 429 #global-interrupts = <5>; 430 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 431 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 432 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 433 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 434 /* Performance counter interrupts */ 435 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS0 */ 436 /* Per context non-secure context interrupts, 0-1 interrupts */ 437 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 438 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */ 439 }; 440 441 clock_imem: clock-controller@10010000 { 442 compatible = "tesla,fsd-clock-imem"; 443 reg = <0x0 0x10010000 0x0 0x3000>; 444 #clock-cells = <1>; 445 clocks = <&fin_pll>, 446 <&clock_cmu DOUT_CMU_IMEM_TCUCLK>, 447 <&clock_cmu DOUT_CMU_IMEM_ACLK>, 448 <&clock_cmu DOUT_CMU_IMEM_DMACLK>; 449 clock-names = "fin_pll", 450 "dout_cmu_imem_tcuclk", 451 "dout_cmu_imem_aclk", 452 "dout_cmu_imem_dmaclk"; 453 }; 454 455 clock_cmu: clock-controller@11c10000 { 456 compatible = "tesla,fsd-clock-cmu"; 457 reg = <0x0 0x11c10000 0x0 0x3000>; 458 #clock-cells = <1>; 459 clocks = <&fin_pll>; 460 clock-names = "fin_pll"; 461 }; 462 463 clock_csi: clock-controller@12610000 { 464 compatible = "tesla,fsd-clock-cam_csi"; 465 reg = <0x0 0x12610000 0x0 0x3000>; 466 #clock-cells = <1>; 467 clocks = <&fin_pll>; 468 clock-names = "fin_pll"; 469 }; 470 471 sysreg_cam: system-controller@12630000 { 472 compatible = "tesla,fsd-cam-sysreg", "syscon"; 473 reg = <0x0 0x12630000 0x0 0x500>; 474 }; 475 476 clock_mfc: clock-controller@12810000 { 477 compatible = "tesla,fsd-clock-mfc"; 478 reg = <0x0 0x12810000 0x0 0x3000>; 479 #clock-cells = <1>; 480 clocks = <&fin_pll>; 481 clock-names = "fin_pll"; 482 }; 483 484 clock_peric: clock-controller@14010000 { 485 compatible = "tesla,fsd-clock-peric"; 486 reg = <0x0 0x14010000 0x0 0x3000>; 487 #clock-cells = <1>; 488 clocks = <&fin_pll>, 489 <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>, 490 <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>, 491 <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK>, 492 <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>, 493 <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>; 494 clock-names = "fin_pll", 495 "dout_cmu_pll_shared0_div4", 496 "dout_cmu_peric_shared1div36", 497 "dout_cmu_peric_shared0div3_tbuclk", 498 "dout_cmu_peric_shared0div20", 499 "dout_cmu_peric_shared1div4_dmaclk"; 500 }; 501 502 sysreg_peric: system-controller@14030000 { 503 compatible = "tesla,fsd-peric-sysreg", "syscon"; 504 reg = <0x0 0x14030000 0x0 0x1000>; 505 }; 506 507 clock_fsys0: clock-controller@15010000 { 508 compatible = "tesla,fsd-clock-fsys0"; 509 reg = <0x0 0x15010000 0x0 0x3000>; 510 #clock-cells = <1>; 511 clocks = <&fin_pll>, 512 <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>, 513 <&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>, 514 <&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>; 515 clock-names = "fin_pll", 516 "dout_cmu_pll_shared0_div6", 517 "dout_cmu_fsys0_shared1div4", 518 "dout_cmu_fsys0_shared0div4"; 519 }; 520 521 sysreg_fsys0: system-controller@15030000 { 522 compatible = "tesla,fsd-fsys0-sysreg", "syscon"; 523 reg = <0x0 0x15030000 0x0 0x1000>; 524 }; 525 526 clock_fsys1: clock-controller@16810000 { 527 compatible = "tesla,fsd-clock-fsys1"; 528 reg = <0x0 0x16810000 0x0 0x3000>; 529 #clock-cells = <1>; 530 clocks = <&fin_pll>, 531 <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>, 532 <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>; 533 clock-names = "fin_pll", 534 "dout_cmu_fsys1_shared0div8", 535 "dout_cmu_fsys1_shared0div4"; 536 }; 537 538 sysreg_fsys1: system-controller@16830000 { 539 compatible = "tesla,fsd-fsys1-sysreg", "syscon"; 540 reg = <0x0 0x16830000 0x0 0x1000>; 541 }; 542 543 mdma0: dma-controller@10100000 { 544 compatible = "arm,pl330", "arm,primecell"; 545 reg = <0x0 0x10100000 0x0 0x1000>; 546 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 547 #dma-cells = <1>; 548 clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>; 549 clock-names = "apb_pclk"; 550 iommus = <&smmu_imem 0x800 0x0>; 551 }; 552 553 mdma1: dma-controller@10110000 { 554 compatible = "arm,pl330", "arm,primecell"; 555 reg = <0x0 0x10110000 0x0 0x1000>; 556 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 557 #dma-cells = <1>; 558 clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>; 559 clock-names = "apb_pclk"; 560 iommus = <&smmu_imem 0x801 0x0>; 561 }; 562 563 pdma0: dma-controller@14280000 { 564 compatible = "arm,pl330", "arm,primecell"; 565 reg = <0x0 0x14280000 0x0 0x1000>; 566 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 567 #dma-cells = <1>; 568 clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>; 569 clock-names = "apb_pclk"; 570 iommus = <&smmu_peric 0x2 0x0>; 571 }; 572 573 pdma1: dma-controller@14290000 { 574 compatible = "arm,pl330", "arm,primecell"; 575 reg = <0x0 0x14290000 0x0 0x1000>; 576 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 577 #dma-cells = <1>; 578 clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>; 579 clock-names = "apb_pclk"; 580 iommus = <&smmu_peric 0x1 0x0>; 581 }; 582 583 serial_0: serial@14180000 { 584 compatible = "samsung,exynos4210-uart"; 585 reg = <0x0 0x14180000 0x0 0x100>; 586 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 587 dmas = <&pdma1 1>, <&pdma1 0>; 588 dma-names = "rx", "tx"; 589 clocks = <&clock_peric PERIC_PCLK_UART0>, 590 <&clock_peric PERIC_SCLK_UART0>; 591 clock-names = "uart", "clk_uart_baud0"; 592 status = "disabled"; 593 }; 594 595 serial_1: serial@14190000 { 596 compatible = "samsung,exynos4210-uart"; 597 reg = <0x0 0x14190000 0x0 0x100>; 598 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 599 dmas = <&pdma1 3>, <&pdma1 2>; 600 dma-names = "rx", "tx"; 601 clocks = <&clock_peric PERIC_PCLK_UART1>, 602 <&clock_peric PERIC_SCLK_UART1>; 603 clock-names = "uart", "clk_uart_baud0"; 604 status = "disabled"; 605 }; 606 607 pmu_system_controller: system-controller@11400000 { 608 compatible = "samsung,exynos7-pmu", "syscon"; 609 reg = <0x0 0x11400000 0x0 0x5000>; 610 }; 611 612 watchdog_0: watchdog@100a0000 { 613 compatible = "samsung,exynos7-wdt"; 614 reg = <0x0 0x100a0000 0x0 0x100>; 615 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 616 samsung,syscon-phandle = <&pmu_system_controller>; 617 clocks = <&fin_pll>; 618 clock-names = "watchdog"; 619 }; 620 621 watchdog_1: watchdog@100b0000 { 622 compatible = "samsung,exynos7-wdt"; 623 reg = <0x0 0x100b0000 0x0 0x100>; 624 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 625 samsung,syscon-phandle = <&pmu_system_controller>; 626 clocks = <&fin_pll>; 627 clock-names = "watchdog"; 628 }; 629 630 watchdog_2: watchdog@100c0000 { 631 compatible = "samsung,exynos7-wdt"; 632 reg = <0x0 0x100c0000 0x0 0x100>; 633 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 634 samsung,syscon-phandle = <&pmu_system_controller>; 635 clocks = <&fin_pll>; 636 clock-names = "watchdog"; 637 }; 638 639 pwm_0: pwm@14100000 { 640 compatible = "samsung,exynos4210-pwm"; 641 reg = <0x0 0x14100000 0x0 0x100>; 642 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 643 #pwm-cells = <3>; 644 clocks = <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>; 645 clock-names = "timers"; 646 status = "disabled"; 647 }; 648 649 pwm_1: pwm@14110000 { 650 compatible = "samsung,exynos4210-pwm"; 651 reg = <0x0 0x14110000 0x0 0x100>; 652 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 653 #pwm-cells = <3>; 654 clocks = <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>; 655 clock-names = "timers"; 656 status = "disabled"; 657 }; 658 659 hsi2c_0: i2c@14200000 { 660 compatible = "samsung,exynos7-hsi2c"; 661 reg = <0x0 0x14200000 0x0 0x1000>; 662 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 pinctrl-names = "default"; 666 pinctrl-0 = <&hs_i2c0_bus>; 667 clocks = <&clock_peric PERIC_PCLK_HSI2C0>; 668 clock-names = "hsi2c"; 669 status = "disabled"; 670 }; 671 672 hsi2c_1: i2c@14210000 { 673 compatible = "samsung,exynos7-hsi2c"; 674 reg = <0x0 0x14210000 0x0 0x1000>; 675 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 676 #address-cells = <1>; 677 #size-cells = <0>; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&hs_i2c1_bus>; 680 clocks = <&clock_peric PERIC_PCLK_HSI2C1>; 681 clock-names = "hsi2c"; 682 status = "disabled"; 683 }; 684 685 hsi2c_2: i2c@14220000 { 686 compatible = "samsung,exynos7-hsi2c"; 687 reg = <0x0 0x14220000 0x0 0x1000>; 688 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 pinctrl-names = "default"; 692 pinctrl-0 = <&hs_i2c2_bus>; 693 clocks = <&clock_peric PERIC_PCLK_HSI2C2>; 694 clock-names = "hsi2c"; 695 status = "disabled"; 696 }; 697 698 hsi2c_3: i2c@14230000 { 699 compatible = "samsung,exynos7-hsi2c"; 700 reg = <0x0 0x14230000 0x0 0x1000>; 701 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 pinctrl-names = "default"; 705 pinctrl-0 = <&hs_i2c3_bus>; 706 clocks = <&clock_peric PERIC_PCLK_HSI2C3>; 707 clock-names = "hsi2c"; 708 status = "disabled"; 709 }; 710 711 hsi2c_4: i2c@14240000 { 712 compatible = "samsung,exynos7-hsi2c"; 713 reg = <0x0 0x14240000 0x0 0x1000>; 714 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 715 #address-cells = <1>; 716 #size-cells = <0>; 717 pinctrl-names = "default"; 718 pinctrl-0 = <&hs_i2c4_bus>; 719 clocks = <&clock_peric PERIC_PCLK_HSI2C4>; 720 clock-names = "hsi2c"; 721 status = "disabled"; 722 }; 723 724 hsi2c_5: i2c@14250000 { 725 compatible = "samsung,exynos7-hsi2c"; 726 reg = <0x0 0x14250000 0x0 0x1000>; 727 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 728 #address-cells = <1>; 729 #size-cells = <0>; 730 pinctrl-names = "default"; 731 pinctrl-0 = <&hs_i2c5_bus>; 732 clocks = <&clock_peric PERIC_PCLK_HSI2C5>; 733 clock-names = "hsi2c"; 734 status = "disabled"; 735 }; 736 737 hsi2c_6: i2c@14260000 { 738 compatible = "samsung,exynos7-hsi2c"; 739 reg = <0x0 0x14260000 0x0 0x1000>; 740 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 741 #address-cells = <1>; 742 #size-cells = <0>; 743 pinctrl-names = "default"; 744 pinctrl-0 = <&hs_i2c6_bus>; 745 clocks = <&clock_peric PERIC_PCLK_HSI2C6>; 746 clock-names = "hsi2c"; 747 status = "disabled"; 748 }; 749 750 hsi2c_7: i2c@14270000 { 751 compatible = "samsung,exynos7-hsi2c"; 752 reg = <0x0 0x14270000 0x0 0x1000>; 753 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 754 #address-cells = <1>; 755 #size-cells = <0>; 756 pinctrl-names = "default"; 757 pinctrl-0 = <&hs_i2c7_bus>; 758 clocks = <&clock_peric PERIC_PCLK_HSI2C7>; 759 clock-names = "hsi2c"; 760 status = "disabled"; 761 }; 762 763 i2s_0: i2s@140e0000 { 764 compatible = "tesla,fsd-i2s"; 765 reg = <0x0 0x140e0000 0x0 0x100>; 766 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 767 dmas = <&pdma1 14>, <&pdma1 13>, <&pdma1 12>; 768 dma-names = "tx", "rx", "tx-sec"; 769 #clock-cells = <1>; 770 clocks = <&clock_peric PERIC_PCLK_TDM0>, 771 <&clock_peric PERIC_HCLK_TDM0>, 772 <&clock_peric PERIC_HCLK_TDM0>; 773 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 774 pinctrl-names = "default"; 775 pinctrl-0 = <&i2s0_bus>; 776 #sound-dai-cells = <1>; 777 status = "disabled"; 778 }; 779 780 i2s_1: i2s@140f0000 { 781 compatible = "tesla,fsd-i2s"; 782 reg = <0x0 0x140f0000 0x0 0x100>; 783 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 784 dmas = <&pdma1 17>, <&pdma1 16>, <&pdma1 15>; 785 dma-names = "tx", "rx", "tx-sec"; 786 #clock-cells = <1>; 787 clocks = <&clock_peric PERIC_PCLK_TDM1>, 788 <&clock_peric PERIC_HCLK_TDM1>, 789 <&clock_peric PERIC_HCLK_TDM1>; 790 clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 791 pinctrl-names = "default"; 792 pinctrl-0 = <&i2s1_bus>; 793 #sound-dai-cells = <1>; 794 status = "disabled"; 795 }; 796 797 pinctrl_pmu: pinctrl@114f0000 { 798 compatible = "tesla,fsd-pinctrl"; 799 reg = <0x0 0x114f0000 0x0 0x1000>; 800 }; 801 802 pinctrl_peric: pinctrl@141f0000 { 803 compatible = "tesla,fsd-pinctrl"; 804 reg = <0x0 0x141f0000 0x0 0x1000>; 805 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 806 }; 807 808 pinctrl_fsys0: pinctrl@15020000 { 809 compatible = "tesla,fsd-pinctrl"; 810 reg = <0x0 0x15020000 0x0 0x1000>; 811 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 812 }; 813 814 m_can0: can@14088000 { 815 compatible = "bosch,m_can"; 816 reg = <0x0 0x14088000 0x0 0x0200>, 817 <0x0 0x14080000 0x0 0x8000>; 818 reg-names = "m_can", "message_ram"; 819 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 821 interrupt-names = "int0", "int1"; 822 pinctrl-names = "default"; 823 pinctrl-0 = <&m_can0_bus>; 824 clocks = <&clock_peric PERIC_MCAN0_IPCLKPORT_PCLK>, 825 <&clock_peric PERIC_MCAN0_IPCLKPORT_CCLK>; 826 clock-names = "hclk", "cclk"; 827 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 828 status = "disabled"; 829 }; 830 831 m_can1: can@14098000 { 832 compatible = "bosch,m_can"; 833 reg = <0x0 0x14098000 0x0 0x0200>, 834 <0x0 0x14090000 0x0 0x8000>; 835 reg-names = "m_can", "message_ram"; 836 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 838 interrupt-names = "int0", "int1"; 839 pinctrl-names = "default"; 840 pinctrl-0 = <&m_can1_bus>; 841 clocks = <&clock_peric PERIC_MCAN1_IPCLKPORT_PCLK>, 842 <&clock_peric PERIC_MCAN1_IPCLKPORT_CCLK>; 843 clock-names = "hclk", "cclk"; 844 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 845 status = "disabled"; 846 }; 847 848 m_can2: can@140a8000 { 849 compatible = "bosch,m_can"; 850 reg = <0x0 0x140a8000 0x0 0x0200>, 851 <0x0 0x140a0000 0x0 0x8000>; 852 reg-names = "m_can", "message_ram"; 853 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 855 interrupt-names = "int0", "int1"; 856 pinctrl-names = "default"; 857 pinctrl-0 = <&m_can2_bus>; 858 clocks = <&clock_peric PERIC_MCAN2_IPCLKPORT_PCLK>, 859 <&clock_peric PERIC_MCAN2_IPCLKPORT_CCLK>; 860 clock-names = "hclk", "cclk"; 861 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 862 status = "disabled"; 863 }; 864 865 m_can3: can@140b8000 { 866 compatible = "bosch,m_can"; 867 reg = <0x0 0x140b8000 0x0 0x0200>, 868 <0x0 0x140b0000 0x0 0x8000>; 869 reg-names = "m_can", "message_ram"; 870 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 872 interrupt-names = "int0", "int1"; 873 pinctrl-names = "default"; 874 pinctrl-0 = <&m_can3_bus>; 875 clocks = <&clock_peric PERIC_MCAN3_IPCLKPORT_PCLK>, 876 <&clock_peric PERIC_MCAN3_IPCLKPORT_CCLK>; 877 clock-names = "hclk", "cclk"; 878 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 879 status = "disabled"; 880 }; 881 882 spi_0: spi@14140000 { 883 compatible = "tesla,fsd-spi"; 884 reg = <0x0 0x14140000 0x0 0x100>; 885 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 886 dmas = <&pdma1 4>, <&pdma1 5>; 887 dma-names = "tx", "rx"; 888 #address-cells = <1>; 889 #size-cells = <0>; 890 clocks = <&clock_peric PERIC_PCLK_SPI0>, 891 <&clock_peric PERIC_SCLK_SPI0>; 892 clock-names = "spi", "spi_busclk0"; 893 samsung,spi-src-clk = <0>; 894 pinctrl-names = "default"; 895 pinctrl-0 = <&spi0_bus>; 896 num-cs = <1>; 897 status = "disabled"; 898 }; 899 900 spi_1: spi@14150000 { 901 compatible = "tesla,fsd-spi"; 902 reg = <0x0 0x14150000 0x0 0x100>; 903 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 904 dmas = <&pdma1 6>, <&pdma1 7>; 905 dma-names = "tx", "rx"; 906 #address-cells = <1>; 907 #size-cells = <0>; 908 clocks = <&clock_peric PERIC_PCLK_SPI1>, 909 <&clock_peric PERIC_SCLK_SPI1>; 910 clock-names = "spi", "spi_busclk0"; 911 samsung,spi-src-clk = <0>; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&spi1_bus>; 914 num-cs = <1>; 915 status = "disabled"; 916 }; 917 918 spi_2: spi@14160000 { 919 compatible = "tesla,fsd-spi"; 920 reg = <0x0 0x14160000 0x0 0x100>; 921 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 922 dmas = <&pdma1 8>, <&pdma1 9>; 923 dma-names = "tx", "rx"; 924 #address-cells = <1>; 925 #size-cells = <0>; 926 clocks = <&clock_peric PERIC_PCLK_SPI2>, 927 <&clock_peric PERIC_SCLK_SPI2>; 928 clock-names = "spi", "spi_busclk0"; 929 samsung,spi-src-clk = <0>; 930 pinctrl-names = "default"; 931 pinctrl-0 = <&spi2_bus>; 932 num-cs = <1>; 933 status = "disabled"; 934 }; 935 936 timer@10040000 { 937 compatible = "tesla,fsd-mct", "samsung,exynos4210-mct"; 938 reg = <0x0 0x10040000 0x0 0x800>; 939 interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 955 clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>; 956 clock-names = "fin_pll", "mct"; 957 }; 958 959 ufs: ufs@15120000 { 960 compatible = "tesla,fsd-ufs"; 961 reg = <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */ 962 <0x0 0x15121100 0x0 0x200>, /* 1: Vendor specified */ 963 <0x0 0x15110000 0x0 0x8000>, /* 2: UNIPRO */ 964 <0x0 0x15130000 0x0 0x100>; /* 3: UFS protector */ 965 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 966 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>, 968 <&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>; 969 clock-names = "core_clk", "sclk_unipro_main"; 970 freq-table-hz = <0 0>, <0 0>; 971 pinctrl-names = "default"; 972 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 973 phys = <&ufs_phy>; 974 phy-names = "ufs-phy"; 975 status = "disabled"; 976 }; 977 978 ufs_phy: ufs-phy@15124000 { 979 compatible = "tesla,fsd-ufs-phy"; 980 reg = <0x0 0x15124000 0x0 0x800>; 981 reg-names = "phy-pma"; 982 samsung,pmu-syscon = <&pmu_system_controller>; 983 #phy-cells = <0>; 984 clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>; 985 clock-names = "ref_clk"; 986 }; 987 }; 988}; 989 990#include "fsd-pinctrl.dtsi" 991
