1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Physical Function ethernet driver
3 *
4 * Copyright (C) 2020 Marvell.
5 *
6 */
7
8 #include <linux/module.h>
9 #include <linux/interrupt.h>
10 #include <linux/pci.h>
11 #include <linux/etherdevice.h>
12 #include <linux/of.h>
13 #include <linux/if_vlan.h>
14 #include <linux/iommu.h>
15 #include <net/ip.h>
16 #include <linux/bpf.h>
17 #include <linux/bpf_trace.h>
18 #include <linux/bitfield.h>
19 #include <net/page_pool/types.h>
20
21 #include "otx2_reg.h"
22 #include "otx2_common.h"
23 #include "otx2_txrx.h"
24 #include "otx2_struct.h"
25 #include "otx2_ptp.h"
26 #include "cn10k.h"
27 #include "qos.h"
28 #include <rvu_trace.h>
29
30 #define DRV_NAME "rvu_nicpf"
31 #define DRV_STRING "Marvell RVU NIC Physical Function Driver"
32
33 /* Supported devices */
34 static const struct pci_device_id otx2_pf_id_table[] = {
35 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) },
36 { 0, } /* end of table */
37 };
38
39 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
40 MODULE_DESCRIPTION(DRV_STRING);
41 MODULE_LICENSE("GPL v2");
42 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table);
43
44 static void otx2_vf_link_event_task(struct work_struct *work);
45
46 enum {
47 TYPE_PFAF,
48 TYPE_PFVF,
49 };
50
51 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable);
52 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable);
53
otx2_change_mtu(struct net_device * netdev,int new_mtu)54 static int otx2_change_mtu(struct net_device *netdev, int new_mtu)
55 {
56 struct otx2_nic *pf = netdev_priv(netdev);
57 bool if_up = netif_running(netdev);
58 int err = 0;
59
60 if (pf->xdp_prog && new_mtu > MAX_XDP_MTU) {
61 netdev_warn(netdev, "Jumbo frames not yet supported with XDP, current MTU %d.\n",
62 netdev->mtu);
63 return -EINVAL;
64 }
65 if (if_up)
66 otx2_stop(netdev);
67
68 netdev_info(netdev, "Changing MTU from %d to %d\n",
69 netdev->mtu, new_mtu);
70 netdev->mtu = new_mtu;
71
72 if (if_up)
73 err = otx2_open(netdev);
74
75 return err;
76 }
77
otx2_disable_flr_me_intr(struct otx2_nic * pf)78 static void otx2_disable_flr_me_intr(struct otx2_nic *pf)
79 {
80 int irq, vfs = pf->total_vfs;
81
82 /* Disable VFs ME interrupts */
83 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs));
84 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0);
85 free_irq(irq, pf);
86
87 /* Disable VFs FLR interrupts */
88 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs));
89 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0);
90 free_irq(irq, pf);
91
92 if (vfs <= 64)
93 return;
94
95 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
96 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1);
97 free_irq(irq, pf);
98
99 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
100 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1);
101 free_irq(irq, pf);
102 }
103
otx2_flr_wq_destroy(struct otx2_nic * pf)104 static void otx2_flr_wq_destroy(struct otx2_nic *pf)
105 {
106 if (!pf->flr_wq)
107 return;
108 destroy_workqueue(pf->flr_wq);
109 pf->flr_wq = NULL;
110 devm_kfree(pf->dev, pf->flr_wrk);
111 }
112
otx2_flr_handler(struct work_struct * work)113 static void otx2_flr_handler(struct work_struct *work)
114 {
115 struct flr_work *flrwork = container_of(work, struct flr_work, work);
116 struct otx2_nic *pf = flrwork->pf;
117 struct mbox *mbox = &pf->mbox;
118 struct msg_req *req;
119 int vf, reg = 0;
120
121 vf = flrwork - pf->flr_wrk;
122
123 mutex_lock(&mbox->lock);
124 req = otx2_mbox_alloc_msg_vf_flr(mbox);
125 if (!req) {
126 mutex_unlock(&mbox->lock);
127 return;
128 }
129 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK;
130 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK;
131
132 if (!otx2_sync_mbox_msg(&pf->mbox)) {
133 if (vf >= 64) {
134 reg = 1;
135 vf = vf - 64;
136 }
137 /* clear transcation pending bit */
138 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
139 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf));
140 }
141
142 mutex_unlock(&mbox->lock);
143 }
144
otx2_pf_flr_intr_handler(int irq,void * pf_irq)145 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq)
146 {
147 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
148 int reg, dev, vf, start_vf, num_reg = 1;
149 u64 intr;
150
151 if (pf->total_vfs > 64)
152 num_reg = 2;
153
154 for (reg = 0; reg < num_reg; reg++) {
155 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg));
156 if (!intr)
157 continue;
158 start_vf = 64 * reg;
159 for (vf = 0; vf < 64; vf++) {
160 if (!(intr & BIT_ULL(vf)))
161 continue;
162 dev = vf + start_vf;
163 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work);
164 /* Clear interrupt */
165 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf));
166 /* Disable the interrupt */
167 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg),
168 BIT_ULL(vf));
169 }
170 }
171 return IRQ_HANDLED;
172 }
173
otx2_pf_me_intr_handler(int irq,void * pf_irq)174 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq)
175 {
176 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
177 int vf, reg, num_reg = 1;
178 u64 intr;
179
180 if (pf->total_vfs > 64)
181 num_reg = 2;
182
183 for (reg = 0; reg < num_reg; reg++) {
184 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg));
185 if (!intr)
186 continue;
187 for (vf = 0; vf < 64; vf++) {
188 if (!(intr & BIT_ULL(vf)))
189 continue;
190 /* clear trpend bit */
191 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
192 /* clear interrupt */
193 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf));
194 }
195 }
196 return IRQ_HANDLED;
197 }
198
otx2_register_flr_me_intr(struct otx2_nic * pf,int numvfs)199 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs)
200 {
201 struct otx2_hw *hw = &pf->hw;
202 char *irq_name;
203 int ret;
204
205 /* Register ME interrupt handler*/
206 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE];
207 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc));
208 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0),
209 otx2_pf_me_intr_handler, 0, irq_name, pf);
210 if (ret) {
211 dev_err(pf->dev,
212 "RVUPF: IRQ registration failed for ME0\n");
213 }
214
215 /* Register FLR interrupt handler */
216 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE];
217 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc));
218 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0),
219 otx2_pf_flr_intr_handler, 0, irq_name, pf);
220 if (ret) {
221 dev_err(pf->dev,
222 "RVUPF: IRQ registration failed for FLR0\n");
223 return ret;
224 }
225
226 if (numvfs > 64) {
227 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE];
228 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1",
229 rvu_get_pf(pf->pcifunc));
230 ret = request_irq(pci_irq_vector
231 (pf->pdev, RVU_PF_INT_VEC_VFME1),
232 otx2_pf_me_intr_handler, 0, irq_name, pf);
233 if (ret) {
234 dev_err(pf->dev,
235 "RVUPF: IRQ registration failed for ME1\n");
236 }
237 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE];
238 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1",
239 rvu_get_pf(pf->pcifunc));
240 ret = request_irq(pci_irq_vector
241 (pf->pdev, RVU_PF_INT_VEC_VFFLR1),
242 otx2_pf_flr_intr_handler, 0, irq_name, pf);
243 if (ret) {
244 dev_err(pf->dev,
245 "RVUPF: IRQ registration failed for FLR1\n");
246 return ret;
247 }
248 }
249
250 /* Enable ME interrupt for all VFs*/
251 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs));
252 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs));
253
254 /* Enable FLR interrupt for all VFs*/
255 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs));
256 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs));
257
258 if (numvfs > 64) {
259 numvfs -= 64;
260
261 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs));
262 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1),
263 INTR_MASK(numvfs));
264
265 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs));
266 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1),
267 INTR_MASK(numvfs));
268 }
269 return 0;
270 }
271
otx2_pf_flr_init(struct otx2_nic * pf,int num_vfs)272 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs)
273 {
274 int vf;
275
276 pf->flr_wq = alloc_ordered_workqueue("otx2_pf_flr_wq", WQ_HIGHPRI);
277 if (!pf->flr_wq)
278 return -ENOMEM;
279
280 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs,
281 sizeof(struct flr_work), GFP_KERNEL);
282 if (!pf->flr_wrk) {
283 destroy_workqueue(pf->flr_wq);
284 return -ENOMEM;
285 }
286
287 for (vf = 0; vf < num_vfs; vf++) {
288 pf->flr_wrk[vf].pf = pf;
289 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler);
290 }
291
292 return 0;
293 }
294
otx2_queue_work(struct mbox * mw,struct workqueue_struct * mbox_wq,int first,int mdevs,u64 intr,int type)295 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq,
296 int first, int mdevs, u64 intr, int type)
297 {
298 struct otx2_mbox_dev *mdev;
299 struct otx2_mbox *mbox;
300 struct mbox_hdr *hdr;
301 int i;
302
303 for (i = first; i < mdevs; i++) {
304 /* start from 0 */
305 if (!(intr & BIT_ULL(i - first)))
306 continue;
307
308 mbox = &mw->mbox;
309 mdev = &mbox->dev[i];
310 if (type == TYPE_PFAF)
311 otx2_sync_mbox_bbuf(mbox, i);
312 hdr = mdev->mbase + mbox->rx_start;
313 /* The hdr->num_msgs is set to zero immediately in the interrupt
314 * handler to ensure that it holds a correct value next time
315 * when the interrupt handler is called.
316 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler
317 * pf>mbox.up_num_msgs holds the data for use in
318 * pfaf_mbox_up_handler.
319 */
320 if (hdr->num_msgs) {
321 mw[i].num_msgs = hdr->num_msgs;
322 hdr->num_msgs = 0;
323 if (type == TYPE_PFAF)
324 memset(mbox->hwbase + mbox->rx_start, 0,
325 ALIGN(sizeof(struct mbox_hdr),
326 sizeof(u64)));
327
328 queue_work(mbox_wq, &mw[i].mbox_wrk);
329 }
330
331 mbox = &mw->mbox_up;
332 mdev = &mbox->dev[i];
333 if (type == TYPE_PFAF)
334 otx2_sync_mbox_bbuf(mbox, i);
335 hdr = mdev->mbase + mbox->rx_start;
336 if (hdr->num_msgs) {
337 mw[i].up_num_msgs = hdr->num_msgs;
338 hdr->num_msgs = 0;
339 if (type == TYPE_PFAF)
340 memset(mbox->hwbase + mbox->rx_start, 0,
341 ALIGN(sizeof(struct mbox_hdr),
342 sizeof(u64)));
343
344 queue_work(mbox_wq, &mw[i].mbox_up_wrk);
345 }
346 }
347 }
348
otx2_forward_msg_pfvf(struct otx2_mbox_dev * mdev,struct otx2_mbox * pfvf_mbox,void * bbuf_base,int devid)349 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev,
350 struct otx2_mbox *pfvf_mbox, void *bbuf_base,
351 int devid)
352 {
353 struct otx2_mbox_dev *src_mdev = mdev;
354 int offset;
355
356 /* Msgs are already copied, trigger VF's mbox irq */
357 smp_wmb();
358
359 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift);
360 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset);
361
362 /* Restore VF's mbox bounce buffer region address */
363 src_mdev->mbase = bbuf_base;
364 }
365
otx2_forward_vf_mbox_msgs(struct otx2_nic * pf,struct otx2_mbox * src_mbox,int dir,int vf,int num_msgs)366 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf,
367 struct otx2_mbox *src_mbox,
368 int dir, int vf, int num_msgs)
369 {
370 struct otx2_mbox_dev *src_mdev, *dst_mdev;
371 struct mbox_hdr *mbox_hdr;
372 struct mbox_hdr *req_hdr;
373 struct mbox *dst_mbox;
374 int dst_size, err;
375
376 if (dir == MBOX_DIR_PFAF) {
377 /* Set VF's mailbox memory as PF's bounce buffer memory, so
378 * that explicit copying of VF's msgs to PF=>AF mbox region
379 * and AF=>PF responses to VF's mbox region can be avoided.
380 */
381 src_mdev = &src_mbox->dev[vf];
382 mbox_hdr = src_mbox->hwbase +
383 src_mbox->rx_start + (vf * MBOX_SIZE);
384
385 dst_mbox = &pf->mbox;
386 dst_size = dst_mbox->mbox.tx_size -
387 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN);
388 /* Check if msgs fit into destination area and has valid size */
389 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size)
390 return -EINVAL;
391
392 dst_mdev = &dst_mbox->mbox.dev[0];
393
394 mutex_lock(&pf->mbox.lock);
395 dst_mdev->mbase = src_mdev->mbase;
396 dst_mdev->msg_size = mbox_hdr->msg_size;
397 dst_mdev->num_msgs = num_msgs;
398 err = otx2_sync_mbox_msg(dst_mbox);
399 /* Error code -EIO indicate there is a communication failure
400 * to the AF. Rest of the error codes indicate that AF processed
401 * VF messages and set the error codes in response messages
402 * (if any) so simply forward responses to VF.
403 */
404 if (err == -EIO) {
405 dev_warn(pf->dev,
406 "AF not responding to VF%d messages\n", vf);
407 /* restore PF mbase and exit */
408 dst_mdev->mbase = pf->mbox.bbuf_base;
409 mutex_unlock(&pf->mbox.lock);
410 return err;
411 }
412 /* At this point, all the VF messages sent to AF are acked
413 * with proper responses and responses are copied to VF
414 * mailbox hence raise interrupt to VF.
415 */
416 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase +
417 dst_mbox->mbox.rx_start);
418 req_hdr->num_msgs = num_msgs;
419
420 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox,
421 pf->mbox.bbuf_base, vf);
422 mutex_unlock(&pf->mbox.lock);
423 } else if (dir == MBOX_DIR_PFVF_UP) {
424 src_mdev = &src_mbox->dev[0];
425 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start;
426 req_hdr = (struct mbox_hdr *)(src_mdev->mbase +
427 src_mbox->rx_start);
428 req_hdr->num_msgs = num_msgs;
429
430 dst_mbox = &pf->mbox_pfvf[0];
431 dst_size = dst_mbox->mbox_up.tx_size -
432 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN);
433 /* Check if msgs fit into destination area */
434 if (mbox_hdr->msg_size > dst_size)
435 return -EINVAL;
436
437 dst_mdev = &dst_mbox->mbox_up.dev[vf];
438 dst_mdev->mbase = src_mdev->mbase;
439 dst_mdev->msg_size = mbox_hdr->msg_size;
440 dst_mdev->num_msgs = mbox_hdr->num_msgs;
441 err = otx2_sync_mbox_up_msg(dst_mbox, vf);
442 if (err) {
443 dev_warn(pf->dev,
444 "VF%d is not responding to mailbox\n", vf);
445 return err;
446 }
447 } else if (dir == MBOX_DIR_VFPF_UP) {
448 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase +
449 src_mbox->rx_start);
450 req_hdr->num_msgs = num_msgs;
451 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf],
452 &pf->mbox.mbox_up,
453 pf->mbox_pfvf[vf].bbuf_base,
454 0);
455 }
456
457 return 0;
458 }
459
otx2_pfvf_mbox_handler(struct work_struct * work)460 static void otx2_pfvf_mbox_handler(struct work_struct *work)
461 {
462 struct mbox_msghdr *msg = NULL;
463 int offset, vf_idx, id, err;
464 struct otx2_mbox_dev *mdev;
465 struct mbox_hdr *req_hdr;
466 struct otx2_mbox *mbox;
467 struct mbox *vf_mbox;
468 struct otx2_nic *pf;
469
470 vf_mbox = container_of(work, struct mbox, mbox_wrk);
471 pf = vf_mbox->pfvf;
472 vf_idx = vf_mbox - pf->mbox_pfvf;
473
474 mbox = &pf->mbox_pfvf[0].mbox;
475 mdev = &mbox->dev[vf_idx];
476 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
477
478 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
479
480 for (id = 0; id < vf_mbox->num_msgs; id++) {
481 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start +
482 offset);
483
484 if (msg->sig != OTX2_MBOX_REQ_SIG)
485 goto inval_msg;
486
487 /* Set VF's number in each of the msg */
488 msg->pcifunc &= RVU_PFVF_FUNC_MASK;
489 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK;
490 offset = msg->next_msgoff;
491 }
492 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx,
493 vf_mbox->num_msgs);
494 if (err)
495 goto inval_msg;
496 return;
497
498 inval_msg:
499 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id);
500 otx2_mbox_msg_send(mbox, vf_idx);
501 }
502
otx2_pfvf_mbox_up_handler(struct work_struct * work)503 static void otx2_pfvf_mbox_up_handler(struct work_struct *work)
504 {
505 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk);
506 struct otx2_nic *pf = vf_mbox->pfvf;
507 struct otx2_mbox_dev *mdev;
508 int offset, id, vf_idx = 0;
509 struct mbox_hdr *rsp_hdr;
510 struct mbox_msghdr *msg;
511 struct otx2_mbox *mbox;
512
513 vf_idx = vf_mbox - pf->mbox_pfvf;
514 mbox = &pf->mbox_pfvf[0].mbox_up;
515 mdev = &mbox->dev[vf_idx];
516
517 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
518 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
519
520 for (id = 0; id < vf_mbox->up_num_msgs; id++) {
521 msg = mdev->mbase + offset;
522
523 if (msg->id >= MBOX_MSG_MAX) {
524 dev_err(pf->dev,
525 "Mbox msg with unknown ID 0x%x\n", msg->id);
526 goto end;
527 }
528
529 if (msg->sig != OTX2_MBOX_RSP_SIG) {
530 dev_err(pf->dev,
531 "Mbox msg with wrong signature %x, ID 0x%x\n",
532 msg->sig, msg->id);
533 goto end;
534 }
535
536 switch (msg->id) {
537 case MBOX_MSG_CGX_LINK_EVENT:
538 break;
539 default:
540 if (msg->rc)
541 dev_err(pf->dev,
542 "Mbox msg response has err %d, ID 0x%x\n",
543 msg->rc, msg->id);
544 break;
545 }
546
547 end:
548 offset = mbox->rx_start + msg->next_msgoff;
549 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1))
550 __otx2_mbox_reset(mbox, 0);
551 mdev->msgs_acked++;
552 }
553 }
554
otx2_pfvf_mbox_intr_handler(int irq,void * pf_irq)555 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq)
556 {
557 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq);
558 int vfs = pf->total_vfs;
559 struct mbox *mbox;
560 u64 intr;
561
562 mbox = pf->mbox_pfvf;
563 /* Handle VF interrupts */
564 if (vfs > 64) {
565 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1));
566 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr);
567 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr,
568 TYPE_PFVF);
569 vfs -= 64;
570 }
571
572 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0));
573 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr);
574
575 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF);
576
577 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr);
578
579 return IRQ_HANDLED;
580 }
581
otx2_pfvf_mbox_init(struct otx2_nic * pf,int numvfs)582 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs)
583 {
584 void __iomem *hwbase;
585 struct mbox *mbox;
586 int err, vf;
587 u64 base;
588
589 if (!numvfs)
590 return -EINVAL;
591
592 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs,
593 sizeof(struct mbox), GFP_KERNEL);
594 if (!pf->mbox_pfvf)
595 return -ENOMEM;
596
597 pf->mbox_pfvf_wq = alloc_ordered_workqueue("otx2_pfvf_mailbox",
598 WQ_HIGHPRI | WQ_MEM_RECLAIM);
599 if (!pf->mbox_pfvf_wq)
600 return -ENOMEM;
601
602 /* On CN10K platform, PF <-> VF mailbox region follows after
603 * PF <-> AF mailbox region.
604 */
605 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag))
606 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) +
607 MBOX_SIZE;
608 else
609 base = readq((void __iomem *)((u64)pf->reg_base +
610 RVU_PF_VF_BAR4_ADDR));
611
612 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs);
613 if (!hwbase) {
614 err = -ENOMEM;
615 goto free_wq;
616 }
617
618 mbox = &pf->mbox_pfvf[0];
619 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base,
620 MBOX_DIR_PFVF, numvfs);
621 if (err)
622 goto free_iomem;
623
624 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base,
625 MBOX_DIR_PFVF_UP, numvfs);
626 if (err)
627 goto free_iomem;
628
629 for (vf = 0; vf < numvfs; vf++) {
630 mbox->pfvf = pf;
631 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler);
632 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler);
633 mbox++;
634 }
635
636 return 0;
637
638 free_iomem:
639 if (hwbase)
640 iounmap(hwbase);
641 free_wq:
642 destroy_workqueue(pf->mbox_pfvf_wq);
643 return err;
644 }
645
otx2_pfvf_mbox_destroy(struct otx2_nic * pf)646 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf)
647 {
648 struct mbox *mbox = &pf->mbox_pfvf[0];
649
650 if (!mbox)
651 return;
652
653 if (pf->mbox_pfvf_wq) {
654 destroy_workqueue(pf->mbox_pfvf_wq);
655 pf->mbox_pfvf_wq = NULL;
656 }
657
658 if (mbox->mbox.hwbase)
659 iounmap(mbox->mbox.hwbase);
660
661 otx2_mbox_destroy(&mbox->mbox);
662 }
663
otx2_enable_pfvf_mbox_intr(struct otx2_nic * pf,int numvfs)664 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
665 {
666 /* Clear PF <=> VF mailbox IRQ */
667 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull);
668 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull);
669
670 /* Enable PF <=> VF mailbox IRQ */
671 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs));
672 if (numvfs > 64) {
673 numvfs -= 64;
674 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1),
675 INTR_MASK(numvfs));
676 }
677 }
678
otx2_disable_pfvf_mbox_intr(struct otx2_nic * pf,int numvfs)679 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
680 {
681 int vector;
682
683 /* Disable PF <=> VF mailbox IRQ */
684 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull);
685 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull);
686
687 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull);
688 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0);
689 free_irq(vector, pf);
690
691 if (numvfs > 64) {
692 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull);
693 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1);
694 free_irq(vector, pf);
695 }
696 }
697
otx2_register_pfvf_mbox_intr(struct otx2_nic * pf,int numvfs)698 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
699 {
700 struct otx2_hw *hw = &pf->hw;
701 char *irq_name;
702 int err;
703
704 /* Register MBOX0 interrupt handler */
705 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE];
706 if (pf->pcifunc)
707 snprintf(irq_name, NAME_SIZE,
708 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc));
709 else
710 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0");
711 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0),
712 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf);
713 if (err) {
714 dev_err(pf->dev,
715 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n");
716 return err;
717 }
718
719 if (numvfs > 64) {
720 /* Register MBOX1 interrupt handler */
721 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE];
722 if (pf->pcifunc)
723 snprintf(irq_name, NAME_SIZE,
724 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc));
725 else
726 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1");
727 err = request_irq(pci_irq_vector(pf->pdev,
728 RVU_PF_INT_VEC_VFPF_MBOX1),
729 otx2_pfvf_mbox_intr_handler,
730 0, irq_name, pf);
731 if (err) {
732 dev_err(pf->dev,
733 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n");
734 return err;
735 }
736 }
737
738 otx2_enable_pfvf_mbox_intr(pf, numvfs);
739
740 return 0;
741 }
742
otx2_process_pfaf_mbox_msg(struct otx2_nic * pf,struct mbox_msghdr * msg)743 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf,
744 struct mbox_msghdr *msg)
745 {
746 int devid;
747
748 if (msg->id >= MBOX_MSG_MAX) {
749 dev_err(pf->dev,
750 "Mbox msg with unknown ID 0x%x\n", msg->id);
751 return;
752 }
753
754 if (msg->sig != OTX2_MBOX_RSP_SIG) {
755 dev_err(pf->dev,
756 "Mbox msg with wrong signature %x, ID 0x%x\n",
757 msg->sig, msg->id);
758 return;
759 }
760
761 /* message response heading VF */
762 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK;
763 if (devid) {
764 struct otx2_vf_config *config = &pf->vf_configs[devid - 1];
765 struct delayed_work *dwork;
766
767 switch (msg->id) {
768 case MBOX_MSG_NIX_LF_START_RX:
769 config->intf_down = false;
770 dwork = &config->link_event_work;
771 schedule_delayed_work(dwork, msecs_to_jiffies(100));
772 break;
773 case MBOX_MSG_NIX_LF_STOP_RX:
774 config->intf_down = true;
775 break;
776 }
777
778 return;
779 }
780
781 switch (msg->id) {
782 case MBOX_MSG_READY:
783 pf->pcifunc = msg->pcifunc;
784 break;
785 case MBOX_MSG_MSIX_OFFSET:
786 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg);
787 break;
788 case MBOX_MSG_NPA_LF_ALLOC:
789 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg);
790 break;
791 case MBOX_MSG_NIX_LF_ALLOC:
792 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg);
793 break;
794 case MBOX_MSG_NIX_BP_ENABLE:
795 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg);
796 break;
797 case MBOX_MSG_CGX_STATS:
798 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg);
799 break;
800 case MBOX_MSG_CGX_FEC_STATS:
801 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg);
802 break;
803 default:
804 if (msg->rc)
805 dev_err(pf->dev,
806 "Mbox msg response has err %d, ID 0x%x\n",
807 msg->rc, msg->id);
808 break;
809 }
810 }
811
otx2_pfaf_mbox_handler(struct work_struct * work)812 static void otx2_pfaf_mbox_handler(struct work_struct *work)
813 {
814 struct otx2_mbox_dev *mdev;
815 struct mbox_hdr *rsp_hdr;
816 struct mbox_msghdr *msg;
817 struct otx2_mbox *mbox;
818 struct mbox *af_mbox;
819 struct otx2_nic *pf;
820 int offset, id;
821
822 af_mbox = container_of(work, struct mbox, mbox_wrk);
823 mbox = &af_mbox->mbox;
824 mdev = &mbox->dev[0];
825 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
826
827 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
828 pf = af_mbox->pfvf;
829
830 for (id = 0; id < af_mbox->num_msgs; id++) {
831 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
832 otx2_process_pfaf_mbox_msg(pf, msg);
833 offset = mbox->rx_start + msg->next_msgoff;
834 if (mdev->msgs_acked == (af_mbox->num_msgs - 1))
835 __otx2_mbox_reset(mbox, 0);
836 mdev->msgs_acked++;
837 }
838
839 }
840
otx2_handle_link_event(struct otx2_nic * pf)841 static void otx2_handle_link_event(struct otx2_nic *pf)
842 {
843 struct cgx_link_user_info *linfo = &pf->linfo;
844 struct net_device *netdev = pf->netdev;
845
846 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name,
847 linfo->link_up ? "UP" : "DOWN", linfo->speed,
848 linfo->full_duplex ? "Full" : "Half");
849 if (linfo->link_up) {
850 netif_carrier_on(netdev);
851 netif_tx_start_all_queues(netdev);
852 } else {
853 netif_tx_stop_all_queues(netdev);
854 netif_carrier_off(netdev);
855 }
856 }
857
otx2_mbox_up_handler_mcs_intr_notify(struct otx2_nic * pf,struct mcs_intr_info * event,struct msg_rsp * rsp)858 int otx2_mbox_up_handler_mcs_intr_notify(struct otx2_nic *pf,
859 struct mcs_intr_info *event,
860 struct msg_rsp *rsp)
861 {
862 cn10k_handle_mcs_event(pf, event);
863
864 return 0;
865 }
866
otx2_mbox_up_handler_cgx_link_event(struct otx2_nic * pf,struct cgx_link_info_msg * msg,struct msg_rsp * rsp)867 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf,
868 struct cgx_link_info_msg *msg,
869 struct msg_rsp *rsp)
870 {
871 int i;
872
873 /* Copy the link info sent by AF */
874 pf->linfo = msg->link_info;
875
876 /* notify VFs about link event */
877 for (i = 0; i < pci_num_vf(pf->pdev); i++) {
878 struct otx2_vf_config *config = &pf->vf_configs[i];
879 struct delayed_work *dwork = &config->link_event_work;
880
881 if (config->intf_down)
882 continue;
883
884 schedule_delayed_work(dwork, msecs_to_jiffies(100));
885 }
886
887 /* interface has not been fully configured yet */
888 if (pf->flags & OTX2_FLAG_INTF_DOWN)
889 return 0;
890
891 otx2_handle_link_event(pf);
892 return 0;
893 }
894
otx2_process_mbox_msg_up(struct otx2_nic * pf,struct mbox_msghdr * req)895 static int otx2_process_mbox_msg_up(struct otx2_nic *pf,
896 struct mbox_msghdr *req)
897 {
898 /* Check if valid, if not reply with a invalid msg */
899 if (req->sig != OTX2_MBOX_REQ_SIG) {
900 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id);
901 return -ENODEV;
902 }
903
904 switch (req->id) {
905 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
906 case _id: { \
907 struct _rsp_type *rsp; \
908 int err; \
909 \
910 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \
911 &pf->mbox.mbox_up, 0, \
912 sizeof(struct _rsp_type)); \
913 if (!rsp) \
914 return -ENOMEM; \
915 \
916 rsp->hdr.id = _id; \
917 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \
918 rsp->hdr.pcifunc = 0; \
919 rsp->hdr.rc = 0; \
920 \
921 err = otx2_mbox_up_handler_ ## _fn_name( \
922 pf, (struct _req_type *)req, rsp); \
923 return err; \
924 }
925 MBOX_UP_CGX_MESSAGES
926 MBOX_UP_MCS_MESSAGES
927 #undef M
928 break;
929 default:
930 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id);
931 return -ENODEV;
932 }
933 return 0;
934 }
935
otx2_pfaf_mbox_up_handler(struct work_struct * work)936 static void otx2_pfaf_mbox_up_handler(struct work_struct *work)
937 {
938 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk);
939 struct otx2_mbox *mbox = &af_mbox->mbox_up;
940 struct otx2_mbox_dev *mdev = &mbox->dev[0];
941 struct otx2_nic *pf = af_mbox->pfvf;
942 int offset, id, devid = 0;
943 struct mbox_hdr *rsp_hdr;
944 struct mbox_msghdr *msg;
945
946 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
947
948 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
949
950 for (id = 0; id < af_mbox->up_num_msgs; id++) {
951 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
952
953 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK;
954 /* Skip processing VF's messages */
955 if (!devid)
956 otx2_process_mbox_msg_up(pf, msg);
957 offset = mbox->rx_start + msg->next_msgoff;
958 }
959 if (devid) {
960 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up,
961 MBOX_DIR_PFVF_UP, devid - 1,
962 af_mbox->up_num_msgs);
963 return;
964 }
965
966 otx2_mbox_msg_send(mbox, 0);
967 }
968
otx2_pfaf_mbox_intr_handler(int irq,void * pf_irq)969 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq)
970 {
971 struct otx2_nic *pf = (struct otx2_nic *)pf_irq;
972 struct mbox *mbox;
973
974 /* Clear the IRQ */
975 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0));
976
977 mbox = &pf->mbox;
978
979 trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0));
980
981 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF);
982
983 return IRQ_HANDLED;
984 }
985
otx2_disable_mbox_intr(struct otx2_nic * pf)986 static void otx2_disable_mbox_intr(struct otx2_nic *pf)
987 {
988 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX);
989
990 /* Disable AF => PF mailbox IRQ */
991 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0));
992 free_irq(vector, pf);
993 }
994
otx2_register_mbox_intr(struct otx2_nic * pf,bool probe_af)995 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af)
996 {
997 struct otx2_hw *hw = &pf->hw;
998 struct msg_req *req;
999 char *irq_name;
1000 int err;
1001
1002 /* Register mailbox interrupt handler */
1003 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE];
1004 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox");
1005 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX),
1006 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf);
1007 if (err) {
1008 dev_err(pf->dev,
1009 "RVUPF: IRQ registration failed for PFAF mbox irq\n");
1010 return err;
1011 }
1012
1013 /* Enable mailbox interrupt for msgs coming from AF.
1014 * First clear to avoid spurious interrupts, if any.
1015 */
1016 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0));
1017 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0));
1018
1019 if (!probe_af)
1020 return 0;
1021
1022 /* Check mailbox communication with AF */
1023 req = otx2_mbox_alloc_msg_ready(&pf->mbox);
1024 if (!req) {
1025 otx2_disable_mbox_intr(pf);
1026 return -ENOMEM;
1027 }
1028 err = otx2_sync_mbox_msg(&pf->mbox);
1029 if (err) {
1030 dev_warn(pf->dev,
1031 "AF not responding to mailbox, deferring probe\n");
1032 otx2_disable_mbox_intr(pf);
1033 return -EPROBE_DEFER;
1034 }
1035
1036 return 0;
1037 }
1038
otx2_pfaf_mbox_destroy(struct otx2_nic * pf)1039 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf)
1040 {
1041 struct mbox *mbox = &pf->mbox;
1042
1043 if (pf->mbox_wq) {
1044 destroy_workqueue(pf->mbox_wq);
1045 pf->mbox_wq = NULL;
1046 }
1047
1048 if (mbox->mbox.hwbase)
1049 iounmap((void __iomem *)mbox->mbox.hwbase);
1050
1051 otx2_mbox_destroy(&mbox->mbox);
1052 otx2_mbox_destroy(&mbox->mbox_up);
1053 }
1054
otx2_pfaf_mbox_init(struct otx2_nic * pf)1055 static int otx2_pfaf_mbox_init(struct otx2_nic *pf)
1056 {
1057 struct mbox *mbox = &pf->mbox;
1058 void __iomem *hwbase;
1059 int err;
1060
1061 mbox->pfvf = pf;
1062 pf->mbox_wq = alloc_ordered_workqueue("otx2_pfaf_mailbox",
1063 WQ_HIGHPRI | WQ_MEM_RECLAIM);
1064 if (!pf->mbox_wq)
1065 return -ENOMEM;
1066
1067 /* Mailbox is a reserved memory (in RAM) region shared between
1068 * admin function (i.e AF) and this PF, shouldn't be mapped as
1069 * device memory to allow unaligned accesses.
1070 */
1071 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM),
1072 MBOX_SIZE);
1073 if (!hwbase) {
1074 dev_err(pf->dev, "Unable to map PFAF mailbox region\n");
1075 err = -ENOMEM;
1076 goto exit;
1077 }
1078
1079 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base,
1080 MBOX_DIR_PFAF, 1);
1081 if (err)
1082 goto exit;
1083
1084 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base,
1085 MBOX_DIR_PFAF_UP, 1);
1086 if (err)
1087 goto exit;
1088
1089 err = otx2_mbox_bbuf_init(mbox, pf->pdev);
1090 if (err)
1091 goto exit;
1092
1093 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler);
1094 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler);
1095 mutex_init(&mbox->lock);
1096
1097 return 0;
1098 exit:
1099 otx2_pfaf_mbox_destroy(pf);
1100 return err;
1101 }
1102
otx2_cgx_config_linkevents(struct otx2_nic * pf,bool enable)1103 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable)
1104 {
1105 struct msg_req *msg;
1106 int err;
1107
1108 mutex_lock(&pf->mbox.lock);
1109 if (enable)
1110 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox);
1111 else
1112 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox);
1113
1114 if (!msg) {
1115 mutex_unlock(&pf->mbox.lock);
1116 return -ENOMEM;
1117 }
1118
1119 err = otx2_sync_mbox_msg(&pf->mbox);
1120 mutex_unlock(&pf->mbox.lock);
1121 return err;
1122 }
1123
otx2_cgx_config_loopback(struct otx2_nic * pf,bool enable)1124 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable)
1125 {
1126 struct msg_req *msg;
1127 int err;
1128
1129 if (enable && !bitmap_empty(pf->flow_cfg->dmacflt_bmap,
1130 pf->flow_cfg->dmacflt_max_flows))
1131 netdev_warn(pf->netdev,
1132 "CGX/RPM internal loopback might not work as DMAC filters are active\n");
1133
1134 mutex_lock(&pf->mbox.lock);
1135 if (enable)
1136 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox);
1137 else
1138 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox);
1139
1140 if (!msg) {
1141 mutex_unlock(&pf->mbox.lock);
1142 return -ENOMEM;
1143 }
1144
1145 err = otx2_sync_mbox_msg(&pf->mbox);
1146 mutex_unlock(&pf->mbox.lock);
1147 return err;
1148 }
1149
otx2_set_real_num_queues(struct net_device * netdev,int tx_queues,int rx_queues)1150 int otx2_set_real_num_queues(struct net_device *netdev,
1151 int tx_queues, int rx_queues)
1152 {
1153 int err;
1154
1155 err = netif_set_real_num_tx_queues(netdev, tx_queues);
1156 if (err) {
1157 netdev_err(netdev,
1158 "Failed to set no of Tx queues: %d\n", tx_queues);
1159 return err;
1160 }
1161
1162 err = netif_set_real_num_rx_queues(netdev, rx_queues);
1163 if (err)
1164 netdev_err(netdev,
1165 "Failed to set no of Rx queues: %d\n", rx_queues);
1166 return err;
1167 }
1168 EXPORT_SYMBOL(otx2_set_real_num_queues);
1169
1170 static char *nix_sqoperr_e_str[NIX_SQOPERR_MAX] = {
1171 "NIX_SQOPERR_OOR",
1172 "NIX_SQOPERR_CTX_FAULT",
1173 "NIX_SQOPERR_CTX_POISON",
1174 "NIX_SQOPERR_DISABLED",
1175 "NIX_SQOPERR_SIZE_ERR",
1176 "NIX_SQOPERR_OFLOW",
1177 "NIX_SQOPERR_SQB_NULL",
1178 "NIX_SQOPERR_SQB_FAULT",
1179 "NIX_SQOPERR_SQE_SZ_ZERO",
1180 };
1181
1182 static char *nix_mnqerr_e_str[NIX_MNQERR_MAX] = {
1183 "NIX_MNQERR_SQ_CTX_FAULT",
1184 "NIX_MNQERR_SQ_CTX_POISON",
1185 "NIX_MNQERR_SQB_FAULT",
1186 "NIX_MNQERR_SQB_POISON",
1187 "NIX_MNQERR_TOTAL_ERR",
1188 "NIX_MNQERR_LSO_ERR",
1189 "NIX_MNQERR_CQ_QUERY_ERR",
1190 "NIX_MNQERR_MAX_SQE_SIZE_ERR",
1191 "NIX_MNQERR_MAXLEN_ERR",
1192 "NIX_MNQERR_SQE_SIZEM1_ZERO",
1193 };
1194
1195 static char *nix_snd_status_e_str[NIX_SND_STATUS_MAX] = {
1196 "NIX_SND_STATUS_GOOD",
1197 "NIX_SND_STATUS_SQ_CTX_FAULT",
1198 "NIX_SND_STATUS_SQ_CTX_POISON",
1199 "NIX_SND_STATUS_SQB_FAULT",
1200 "NIX_SND_STATUS_SQB_POISON",
1201 "NIX_SND_STATUS_HDR_ERR",
1202 "NIX_SND_STATUS_EXT_ERR",
1203 "NIX_SND_STATUS_JUMP_FAULT",
1204 "NIX_SND_STATUS_JUMP_POISON",
1205 "NIX_SND_STATUS_CRC_ERR",
1206 "NIX_SND_STATUS_IMM_ERR",
1207 "NIX_SND_STATUS_SG_ERR",
1208 "NIX_SND_STATUS_MEM_ERR",
1209 "NIX_SND_STATUS_INVALID_SUBDC",
1210 "NIX_SND_STATUS_SUBDC_ORDER_ERR",
1211 "NIX_SND_STATUS_DATA_FAULT",
1212 "NIX_SND_STATUS_DATA_POISON",
1213 "NIX_SND_STATUS_NPC_DROP_ACTION",
1214 "NIX_SND_STATUS_LOCK_VIOL",
1215 "NIX_SND_STATUS_NPC_UCAST_CHAN_ERR",
1216 "NIX_SND_STATUS_NPC_MCAST_CHAN_ERR",
1217 "NIX_SND_STATUS_NPC_MCAST_ABORT",
1218 "NIX_SND_STATUS_NPC_VTAG_PTR_ERR",
1219 "NIX_SND_STATUS_NPC_VTAG_SIZE_ERR",
1220 "NIX_SND_STATUS_SEND_STATS_ERR",
1221 };
1222
otx2_q_intr_handler(int irq,void * data)1223 static irqreturn_t otx2_q_intr_handler(int irq, void *data)
1224 {
1225 struct otx2_nic *pf = data;
1226 struct otx2_snd_queue *sq;
1227 u64 val, *ptr;
1228 u64 qidx = 0;
1229
1230 /* CQ */
1231 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) {
1232 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT);
1233 val = otx2_atomic64_add((qidx << 44), ptr);
1234
1235 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) |
1236 (val & NIX_CQERRINT_BITS));
1237 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42))))
1238 continue;
1239
1240 if (val & BIT_ULL(42)) {
1241 netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n",
1242 qidx, otx2_read64(pf, NIX_LF_ERR_INT));
1243 } else {
1244 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR))
1245 netdev_err(pf->netdev, "CQ%lld: Doorbell error",
1246 qidx);
1247 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT))
1248 netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM",
1249 qidx);
1250 }
1251
1252 schedule_work(&pf->reset_task);
1253 }
1254
1255 /* SQ */
1256 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) {
1257 u64 sq_op_err_dbg, mnq_err_dbg, snd_err_dbg;
1258 u8 sq_op_err_code, mnq_err_code, snd_err_code;
1259
1260 sq = &pf->qset.sq[qidx];
1261 if (!sq->sqb_ptrs)
1262 continue;
1263
1264 /* Below debug registers captures first errors corresponding to
1265 * those registers. We don't have to check against SQ qid as
1266 * these are fatal errors.
1267 */
1268
1269 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT);
1270 val = otx2_atomic64_add((qidx << 44), ptr);
1271 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) |
1272 (val & NIX_SQINT_BITS));
1273
1274 if (val & BIT_ULL(42)) {
1275 netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n",
1276 qidx, otx2_read64(pf, NIX_LF_ERR_INT));
1277 goto done;
1278 }
1279
1280 sq_op_err_dbg = otx2_read64(pf, NIX_LF_SQ_OP_ERR_DBG);
1281 if (!(sq_op_err_dbg & BIT(44)))
1282 goto chk_mnq_err_dbg;
1283
1284 sq_op_err_code = FIELD_GET(GENMASK(7, 0), sq_op_err_dbg);
1285 netdev_err(pf->netdev, "SQ%lld: NIX_LF_SQ_OP_ERR_DBG(%llx) err=%s\n",
1286 qidx, sq_op_err_dbg, nix_sqoperr_e_str[sq_op_err_code]);
1287
1288 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, BIT_ULL(44));
1289
1290 if (sq_op_err_code == NIX_SQOPERR_SQB_NULL)
1291 goto chk_mnq_err_dbg;
1292
1293 /* Err is not NIX_SQOPERR_SQB_NULL, call aq function to read SQ structure.
1294 * TODO: But we are in irq context. How to call mbox functions which does sleep
1295 */
1296
1297 chk_mnq_err_dbg:
1298 mnq_err_dbg = otx2_read64(pf, NIX_LF_MNQ_ERR_DBG);
1299 if (!(mnq_err_dbg & BIT(44)))
1300 goto chk_snd_err_dbg;
1301
1302 mnq_err_code = FIELD_GET(GENMASK(7, 0), mnq_err_dbg);
1303 netdev_err(pf->netdev, "SQ%lld: NIX_LF_MNQ_ERR_DBG(%llx) err=%s\n",
1304 qidx, mnq_err_dbg, nix_mnqerr_e_str[mnq_err_code]);
1305 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, BIT_ULL(44));
1306
1307 chk_snd_err_dbg:
1308 snd_err_dbg = otx2_read64(pf, NIX_LF_SEND_ERR_DBG);
1309 if (snd_err_dbg & BIT(44)) {
1310 snd_err_code = FIELD_GET(GENMASK(7, 0), snd_err_dbg);
1311 netdev_err(pf->netdev, "SQ%lld: NIX_LF_SND_ERR_DBG:0x%llx err=%s\n",
1312 qidx, snd_err_dbg, nix_snd_status_e_str[snd_err_code]);
1313 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, BIT_ULL(44));
1314 }
1315
1316 done:
1317 /* Print values and reset */
1318 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL))
1319 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed",
1320 qidx);
1321
1322 schedule_work(&pf->reset_task);
1323 }
1324
1325 return IRQ_HANDLED;
1326 }
1327
otx2_cq_intr_handler(int irq,void * cq_irq)1328 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq)
1329 {
1330 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq;
1331 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev;
1332 int qidx = cq_poll->cint_idx;
1333
1334 /* Disable interrupts.
1335 *
1336 * Completion interrupts behave in a level-triggered interrupt
1337 * fashion, and hence have to be cleared only after it is serviced.
1338 */
1339 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0));
1340
1341 /* Schedule NAPI */
1342 pf->napi_events++;
1343 napi_schedule_irqoff(&cq_poll->napi);
1344
1345 return IRQ_HANDLED;
1346 }
1347
otx2_disable_napi(struct otx2_nic * pf)1348 static void otx2_disable_napi(struct otx2_nic *pf)
1349 {
1350 struct otx2_qset *qset = &pf->qset;
1351 struct otx2_cq_poll *cq_poll;
1352 int qidx;
1353
1354 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1355 cq_poll = &qset->napi[qidx];
1356 cancel_work_sync(&cq_poll->dim.work);
1357 napi_disable(&cq_poll->napi);
1358 netif_napi_del(&cq_poll->napi);
1359 }
1360 }
1361
otx2_free_cq_res(struct otx2_nic * pf)1362 static void otx2_free_cq_res(struct otx2_nic *pf)
1363 {
1364 struct otx2_qset *qset = &pf->qset;
1365 struct otx2_cq_queue *cq;
1366 int qidx;
1367
1368 /* Disable CQs */
1369 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false);
1370 for (qidx = 0; qidx < qset->cq_cnt; qidx++) {
1371 cq = &qset->cq[qidx];
1372 qmem_free(pf->dev, cq->cqe);
1373 }
1374 }
1375
otx2_free_sq_res(struct otx2_nic * pf)1376 static void otx2_free_sq_res(struct otx2_nic *pf)
1377 {
1378 struct otx2_qset *qset = &pf->qset;
1379 struct otx2_snd_queue *sq;
1380 int qidx;
1381
1382 /* Disable SQs */
1383 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false);
1384 /* Free SQB pointers */
1385 otx2_sq_free_sqbs(pf);
1386 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) {
1387 sq = &qset->sq[qidx];
1388 /* Skip freeing Qos queues if they are not initialized */
1389 if (!sq->sqe)
1390 continue;
1391 qmem_free(pf->dev, sq->sqe);
1392 qmem_free(pf->dev, sq->tso_hdrs);
1393 kfree(sq->sg);
1394 kfree(sq->sqb_ptrs);
1395 }
1396 }
1397
otx2_get_rbuf_size(struct otx2_nic * pf,int mtu)1398 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu)
1399 {
1400 int frame_size;
1401 int total_size;
1402 int rbuf_size;
1403
1404 if (pf->hw.rbuf_len)
1405 return ALIGN(pf->hw.rbuf_len, OTX2_ALIGN) + OTX2_HEAD_ROOM;
1406
1407 /* The data transferred by NIX to memory consists of actual packet
1408 * plus additional data which has timestamp and/or EDSA/HIGIG2
1409 * headers if interface is configured in corresponding modes.
1410 * NIX transfers entire data using 6 segments/buffers and writes
1411 * a CQE_RX descriptor with those segment addresses. First segment
1412 * has additional data prepended to packet. Also software omits a
1413 * headroom of 128 bytes in each segment. Hence the total size of
1414 * memory needed to receive a packet with 'mtu' is:
1415 * frame size = mtu + additional data;
1416 * memory = frame_size + headroom * 6;
1417 * each receive buffer size = memory / 6;
1418 */
1419 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN;
1420 total_size = frame_size + OTX2_HEAD_ROOM * 6;
1421 rbuf_size = total_size / 6;
1422
1423 return ALIGN(rbuf_size, 2048);
1424 }
1425
otx2_init_hw_resources(struct otx2_nic * pf)1426 static int otx2_init_hw_resources(struct otx2_nic *pf)
1427 {
1428 struct nix_lf_free_req *free_req;
1429 struct mbox *mbox = &pf->mbox;
1430 struct otx2_hw *hw = &pf->hw;
1431 struct msg_req *req;
1432 int err = 0, lvl;
1433
1434 /* Set required NPA LF's pool counts
1435 * Auras and Pools are used in a 1:1 mapping,
1436 * so, aura count = pool count.
1437 */
1438 hw->rqpool_cnt = hw->rx_queues;
1439 hw->sqpool_cnt = otx2_get_total_tx_queues(pf);
1440 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt;
1441
1442 /* Maximum hardware supported transmit length */
1443 pf->tx_max_pktlen = pf->netdev->max_mtu + OTX2_ETH_HLEN;
1444
1445 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu);
1446
1447 mutex_lock(&mbox->lock);
1448 /* NPA init */
1449 err = otx2_config_npa(pf);
1450 if (err)
1451 goto exit;
1452
1453 /* NIX init */
1454 err = otx2_config_nix(pf);
1455 if (err)
1456 goto err_free_npa_lf;
1457
1458 /* Enable backpressure for CGX mapped PF/VFs */
1459 if (!is_otx2_lbkvf(pf->pdev))
1460 otx2_nix_config_bp(pf, true);
1461
1462 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */
1463 err = otx2_rq_aura_pool_init(pf);
1464 if (err) {
1465 mutex_unlock(&mbox->lock);
1466 goto err_free_nix_lf;
1467 }
1468 /* Init Auras and pools used by NIX SQ, for queueing SQEs */
1469 err = otx2_sq_aura_pool_init(pf);
1470 if (err) {
1471 mutex_unlock(&mbox->lock);
1472 goto err_free_rq_ptrs;
1473 }
1474
1475 err = otx2_txsch_alloc(pf);
1476 if (err) {
1477 mutex_unlock(&mbox->lock);
1478 goto err_free_sq_ptrs;
1479 }
1480
1481 #ifdef CONFIG_DCB
1482 if (pf->pfc_en) {
1483 err = otx2_pfc_txschq_alloc(pf);
1484 if (err) {
1485 mutex_unlock(&mbox->lock);
1486 goto err_free_sq_ptrs;
1487 }
1488 }
1489 #endif
1490
1491 err = otx2_config_nix_queues(pf);
1492 if (err) {
1493 mutex_unlock(&mbox->lock);
1494 goto err_free_txsch;
1495 }
1496
1497 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
1498 err = otx2_txschq_config(pf, lvl, 0, false);
1499 if (err) {
1500 mutex_unlock(&mbox->lock);
1501 goto err_free_nix_queues;
1502 }
1503 }
1504
1505 #ifdef CONFIG_DCB
1506 if (pf->pfc_en) {
1507 err = otx2_pfc_txschq_config(pf);
1508 if (err) {
1509 mutex_unlock(&mbox->lock);
1510 goto err_free_nix_queues;
1511 }
1512 }
1513 #endif
1514
1515 mutex_unlock(&mbox->lock);
1516 return err;
1517
1518 err_free_nix_queues:
1519 otx2_free_sq_res(pf);
1520 otx2_free_cq_res(pf);
1521 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false);
1522 err_free_txsch:
1523 otx2_txschq_stop(pf);
1524 err_free_sq_ptrs:
1525 otx2_sq_free_sqbs(pf);
1526 err_free_rq_ptrs:
1527 otx2_free_aura_ptr(pf, AURA_NIX_RQ);
1528 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true);
1529 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true);
1530 otx2_aura_pool_free(pf);
1531 err_free_nix_lf:
1532 mutex_lock(&mbox->lock);
1533 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
1534 if (free_req) {
1535 free_req->flags = NIX_LF_DISABLE_FLOWS;
1536 if (otx2_sync_mbox_msg(mbox))
1537 dev_err(pf->dev, "%s failed to free nixlf\n", __func__);
1538 }
1539 err_free_npa_lf:
1540 /* Reset NPA LF */
1541 req = otx2_mbox_alloc_msg_npa_lf_free(mbox);
1542 if (req) {
1543 if (otx2_sync_mbox_msg(mbox))
1544 dev_err(pf->dev, "%s failed to free npalf\n", __func__);
1545 }
1546 exit:
1547 mutex_unlock(&mbox->lock);
1548 return err;
1549 }
1550
otx2_free_hw_resources(struct otx2_nic * pf)1551 static void otx2_free_hw_resources(struct otx2_nic *pf)
1552 {
1553 struct otx2_qset *qset = &pf->qset;
1554 struct nix_lf_free_req *free_req;
1555 struct mbox *mbox = &pf->mbox;
1556 struct otx2_cq_queue *cq;
1557 struct otx2_pool *pool;
1558 struct msg_req *req;
1559 int pool_id;
1560 int qidx;
1561
1562 /* Ensure all SQE are processed */
1563 otx2_sqb_flush(pf);
1564
1565 /* Stop transmission */
1566 otx2_txschq_stop(pf);
1567
1568 #ifdef CONFIG_DCB
1569 if (pf->pfc_en)
1570 otx2_pfc_txschq_stop(pf);
1571 #endif
1572
1573 otx2_clean_qos_queues(pf);
1574
1575 mutex_lock(&mbox->lock);
1576 /* Disable backpressure */
1577 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK))
1578 otx2_nix_config_bp(pf, false);
1579 mutex_unlock(&mbox->lock);
1580
1581 /* Disable RQs */
1582 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false);
1583
1584 /*Dequeue all CQEs */
1585 for (qidx = 0; qidx < qset->cq_cnt; qidx++) {
1586 cq = &qset->cq[qidx];
1587 if (cq->cq_type == CQ_RX)
1588 otx2_cleanup_rx_cqes(pf, cq, qidx);
1589 else
1590 otx2_cleanup_tx_cqes(pf, cq);
1591 }
1592
1593 otx2_free_sq_res(pf);
1594
1595 /* Free RQ buffer pointers*/
1596 otx2_free_aura_ptr(pf, AURA_NIX_RQ);
1597
1598 for (qidx = 0; qidx < pf->hw.rx_queues; qidx++) {
1599 pool_id = otx2_get_pool_idx(pf, AURA_NIX_RQ, qidx);
1600 pool = &pf->qset.pool[pool_id];
1601 page_pool_destroy(pool->page_pool);
1602 pool->page_pool = NULL;
1603 }
1604
1605 otx2_free_cq_res(pf);
1606
1607 /* Free all ingress bandwidth profiles allocated */
1608 cn10k_free_all_ipolicers(pf);
1609
1610 mutex_lock(&mbox->lock);
1611 /* Reset NIX LF */
1612 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
1613 if (free_req) {
1614 free_req->flags = NIX_LF_DISABLE_FLOWS;
1615 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN))
1616 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG;
1617 if (otx2_sync_mbox_msg(mbox))
1618 dev_err(pf->dev, "%s failed to free nixlf\n", __func__);
1619 }
1620 mutex_unlock(&mbox->lock);
1621
1622 /* Disable NPA Pool and Aura hw context */
1623 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true);
1624 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true);
1625 otx2_aura_pool_free(pf);
1626
1627 mutex_lock(&mbox->lock);
1628 /* Reset NPA LF */
1629 req = otx2_mbox_alloc_msg_npa_lf_free(mbox);
1630 if (req) {
1631 if (otx2_sync_mbox_msg(mbox))
1632 dev_err(pf->dev, "%s failed to free npalf\n", __func__);
1633 }
1634 mutex_unlock(&mbox->lock);
1635 }
1636
otx2_do_set_rx_mode(struct otx2_nic * pf)1637 static void otx2_do_set_rx_mode(struct otx2_nic *pf)
1638 {
1639 struct net_device *netdev = pf->netdev;
1640 struct nix_rx_mode *req;
1641 bool promisc = false;
1642
1643 if (!(netdev->flags & IFF_UP))
1644 return;
1645
1646 if ((netdev->flags & IFF_PROMISC) ||
1647 (netdev_uc_count(netdev) > OTX2_MAX_UNICAST_FLOWS)) {
1648 promisc = true;
1649 }
1650
1651 /* Write unicast address to mcam entries or del from mcam */
1652 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT)
1653 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter);
1654
1655 mutex_lock(&pf->mbox.lock);
1656 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox);
1657 if (!req) {
1658 mutex_unlock(&pf->mbox.lock);
1659 return;
1660 }
1661
1662 req->mode = NIX_RX_MODE_UCAST;
1663
1664 if (promisc)
1665 req->mode |= NIX_RX_MODE_PROMISC;
1666 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
1667 req->mode |= NIX_RX_MODE_ALLMULTI;
1668
1669 req->mode |= NIX_RX_MODE_USE_MCE;
1670
1671 otx2_sync_mbox_msg(&pf->mbox);
1672 mutex_unlock(&pf->mbox.lock);
1673 }
1674
otx2_dim_work(struct work_struct * w)1675 static void otx2_dim_work(struct work_struct *w)
1676 {
1677 struct dim_cq_moder cur_moder;
1678 struct otx2_cq_poll *cq_poll;
1679 struct otx2_nic *pfvf;
1680 struct dim *dim;
1681
1682 dim = container_of(w, struct dim, work);
1683 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
1684 cq_poll = container_of(dim, struct otx2_cq_poll, dim);
1685 pfvf = (struct otx2_nic *)cq_poll->dev;
1686 pfvf->hw.cq_time_wait = (cur_moder.usec > CQ_TIMER_THRESH_MAX) ?
1687 CQ_TIMER_THRESH_MAX : cur_moder.usec;
1688 pfvf->hw.cq_ecount_wait = (cur_moder.pkts > NAPI_POLL_WEIGHT) ?
1689 NAPI_POLL_WEIGHT : cur_moder.pkts;
1690 dim->state = DIM_START_MEASURE;
1691 }
1692
otx2_open(struct net_device * netdev)1693 int otx2_open(struct net_device *netdev)
1694 {
1695 struct otx2_nic *pf = netdev_priv(netdev);
1696 struct otx2_cq_poll *cq_poll = NULL;
1697 struct otx2_qset *qset = &pf->qset;
1698 int err = 0, qidx, vec;
1699 char *irq_name;
1700
1701 netif_carrier_off(netdev);
1702
1703 /* RQ and SQs are mapped to different CQs,
1704 * so find out max CQ IRQs (i.e CINTs) needed.
1705 */
1706 pf->hw.cint_cnt = max3(pf->hw.rx_queues, pf->hw.tx_queues,
1707 pf->hw.tc_tx_queues);
1708
1709 pf->qset.cq_cnt = pf->hw.rx_queues + otx2_get_total_tx_queues(pf);
1710
1711 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL);
1712 if (!qset->napi)
1713 return -ENOMEM;
1714
1715 /* CQ size of RQ */
1716 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256);
1717 /* CQ size of SQ */
1718 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K);
1719
1720 err = -ENOMEM;
1721 qset->cq = kcalloc(pf->qset.cq_cnt,
1722 sizeof(struct otx2_cq_queue), GFP_KERNEL);
1723 if (!qset->cq)
1724 goto err_free_mem;
1725
1726 qset->sq = kcalloc(otx2_get_total_tx_queues(pf),
1727 sizeof(struct otx2_snd_queue), GFP_KERNEL);
1728 if (!qset->sq)
1729 goto err_free_mem;
1730
1731 qset->rq = kcalloc(pf->hw.rx_queues,
1732 sizeof(struct otx2_rcv_queue), GFP_KERNEL);
1733 if (!qset->rq)
1734 goto err_free_mem;
1735
1736 err = otx2_init_hw_resources(pf);
1737 if (err)
1738 goto err_free_mem;
1739
1740 /* Register NAPI handler */
1741 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1742 cq_poll = &qset->napi[qidx];
1743 cq_poll->cint_idx = qidx;
1744 /* RQ0 & SQ0 are mapped to CINT0 and so on..
1745 * 'cq_ids[0]' points to RQ's CQ and
1746 * 'cq_ids[1]' points to SQ's CQ and
1747 * 'cq_ids[2]' points to XDP's CQ and
1748 */
1749 cq_poll->cq_ids[CQ_RX] =
1750 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ;
1751 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ?
1752 qidx + pf->hw.rx_queues : CINT_INVALID_CQ;
1753 if (pf->xdp_prog)
1754 cq_poll->cq_ids[CQ_XDP] = (qidx < pf->hw.xdp_queues) ?
1755 (qidx + pf->hw.rx_queues +
1756 pf->hw.tx_queues) :
1757 CINT_INVALID_CQ;
1758 else
1759 cq_poll->cq_ids[CQ_XDP] = CINT_INVALID_CQ;
1760
1761 cq_poll->cq_ids[CQ_QOS] = (qidx < pf->hw.tc_tx_queues) ?
1762 (qidx + pf->hw.rx_queues +
1763 pf->hw.non_qos_queues) :
1764 CINT_INVALID_CQ;
1765
1766 cq_poll->dev = (void *)pf;
1767 cq_poll->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
1768 INIT_WORK(&cq_poll->dim.work, otx2_dim_work);
1769 netif_napi_add(netdev, &cq_poll->napi, otx2_napi_handler);
1770 napi_enable(&cq_poll->napi);
1771 }
1772
1773 /* Set maximum frame size allowed in HW */
1774 err = otx2_hw_set_mtu(pf, netdev->mtu);
1775 if (err)
1776 goto err_disable_napi;
1777
1778 /* Setup segmentation algorithms, if failed, clear offload capability */
1779 otx2_setup_segmentation(pf);
1780
1781 /* Initialize RSS */
1782 err = otx2_rss_init(pf);
1783 if (err)
1784 goto err_disable_napi;
1785
1786 /* Register Queue IRQ handlers */
1787 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START;
1788 irq_name = &pf->hw.irq_name[vec * NAME_SIZE];
1789
1790 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name);
1791
1792 err = request_irq(pci_irq_vector(pf->pdev, vec),
1793 otx2_q_intr_handler, 0, irq_name, pf);
1794 if (err) {
1795 dev_err(pf->dev,
1796 "RVUPF%d: IRQ registration failed for QERR\n",
1797 rvu_get_pf(pf->pcifunc));
1798 goto err_disable_napi;
1799 }
1800
1801 /* Enable QINT IRQ */
1802 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0));
1803
1804 /* Register CQ IRQ handlers */
1805 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START;
1806 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1807 irq_name = &pf->hw.irq_name[vec * NAME_SIZE];
1808
1809 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name,
1810 qidx);
1811
1812 err = request_irq(pci_irq_vector(pf->pdev, vec),
1813 otx2_cq_intr_handler, 0, irq_name,
1814 &qset->napi[qidx]);
1815 if (err) {
1816 dev_err(pf->dev,
1817 "RVUPF%d: IRQ registration failed for CQ%d\n",
1818 rvu_get_pf(pf->pcifunc), qidx);
1819 goto err_free_cints;
1820 }
1821 vec++;
1822
1823 otx2_config_irq_coalescing(pf, qidx);
1824
1825 /* Enable CQ IRQ */
1826 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0));
1827 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0));
1828 }
1829
1830 otx2_set_cints_affinity(pf);
1831
1832 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT)
1833 otx2_enable_rxvlan(pf, true);
1834
1835 /* When reinitializing enable time stamping if it is enabled before */
1836 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) {
1837 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED;
1838 otx2_config_hw_tx_tstamp(pf, true);
1839 }
1840 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) {
1841 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED;
1842 otx2_config_hw_rx_tstamp(pf, true);
1843 }
1844
1845 pf->flags &= ~OTX2_FLAG_INTF_DOWN;
1846 /* 'intf_down' may be checked on any cpu */
1847 smp_wmb();
1848
1849 /* Enable QoS configuration before starting tx queues */
1850 otx2_qos_config_txschq(pf);
1851
1852 /* we have already received link status notification */
1853 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK))
1854 otx2_handle_link_event(pf);
1855
1856 /* Install DMAC Filters */
1857 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT)
1858 otx2_dmacflt_reinstall_flows(pf);
1859
1860 err = otx2_rxtx_enable(pf, true);
1861 /* If a mbox communication error happens at this point then interface
1862 * will end up in a state such that it is in down state but hardware
1863 * mcam entries are enabled to receive the packets. Hence disable the
1864 * packet I/O.
1865 */
1866 if (err == EIO)
1867 goto err_disable_rxtx;
1868 else if (err)
1869 goto err_tx_stop_queues;
1870
1871 otx2_do_set_rx_mode(pf);
1872
1873 return 0;
1874
1875 err_disable_rxtx:
1876 otx2_rxtx_enable(pf, false);
1877 err_tx_stop_queues:
1878 netif_tx_stop_all_queues(netdev);
1879 netif_carrier_off(netdev);
1880 pf->flags |= OTX2_FLAG_INTF_DOWN;
1881 err_free_cints:
1882 otx2_free_cints(pf, qidx);
1883 vec = pci_irq_vector(pf->pdev,
1884 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START);
1885 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0));
1886 free_irq(vec, pf);
1887 err_disable_napi:
1888 otx2_disable_napi(pf);
1889 otx2_free_hw_resources(pf);
1890 err_free_mem:
1891 kfree(qset->sq);
1892 kfree(qset->cq);
1893 kfree(qset->rq);
1894 kfree(qset->napi);
1895 return err;
1896 }
1897 EXPORT_SYMBOL(otx2_open);
1898
otx2_stop(struct net_device * netdev)1899 int otx2_stop(struct net_device *netdev)
1900 {
1901 struct otx2_nic *pf = netdev_priv(netdev);
1902 struct otx2_cq_poll *cq_poll = NULL;
1903 struct otx2_qset *qset = &pf->qset;
1904 struct otx2_rss_info *rss;
1905 int qidx, vec, wrk;
1906
1907 /* If the DOWN flag is set resources are already freed */
1908 if (pf->flags & OTX2_FLAG_INTF_DOWN)
1909 return 0;
1910
1911 netif_carrier_off(netdev);
1912 netif_tx_stop_all_queues(netdev);
1913
1914 pf->flags |= OTX2_FLAG_INTF_DOWN;
1915 /* 'intf_down' may be checked on any cpu */
1916 smp_wmb();
1917
1918 /* First stop packet Rx/Tx */
1919 otx2_rxtx_enable(pf, false);
1920
1921 /* Clear RSS enable flag */
1922 rss = &pf->hw.rss_info;
1923 rss->enable = false;
1924
1925 /* Cleanup Queue IRQ */
1926 vec = pci_irq_vector(pf->pdev,
1927 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START);
1928 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0));
1929 free_irq(vec, pf);
1930
1931 /* Cleanup CQ NAPI and IRQ */
1932 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START;
1933 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) {
1934 /* Disable interrupt */
1935 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0));
1936
1937 synchronize_irq(pci_irq_vector(pf->pdev, vec));
1938
1939 cq_poll = &qset->napi[qidx];
1940 napi_synchronize(&cq_poll->napi);
1941 vec++;
1942 }
1943
1944 netif_tx_disable(netdev);
1945
1946 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++)
1947 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work);
1948 devm_kfree(pf->dev, pf->refill_wrk);
1949
1950 otx2_free_hw_resources(pf);
1951 otx2_free_cints(pf, pf->hw.cint_cnt);
1952 otx2_disable_napi(pf);
1953
1954 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++)
1955 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx));
1956
1957
1958 kfree(qset->sq);
1959 kfree(qset->cq);
1960 kfree(qset->rq);
1961 kfree(qset->napi);
1962 /* Do not clear RQ/SQ ringsize settings */
1963 memset_startat(qset, 0, sqe_cnt);
1964 return 0;
1965 }
1966 EXPORT_SYMBOL(otx2_stop);
1967
otx2_xmit(struct sk_buff * skb,struct net_device * netdev)1968 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev)
1969 {
1970 struct otx2_nic *pf = netdev_priv(netdev);
1971 int qidx = skb_get_queue_mapping(skb);
1972 struct otx2_snd_queue *sq;
1973 struct netdev_queue *txq;
1974 int sq_idx;
1975
1976 /* XDP SQs are not mapped with TXQs
1977 * advance qid to derive correct sq mapped with QOS
1978 */
1979 sq_idx = (qidx >= pf->hw.tx_queues) ? (qidx + pf->hw.xdp_queues) : qidx;
1980
1981 /* Check for minimum and maximum packet length */
1982 if (skb->len <= ETH_HLEN ||
1983 (!skb_shinfo(skb)->gso_size && skb->len > pf->tx_max_pktlen)) {
1984 dev_kfree_skb(skb);
1985 return NETDEV_TX_OK;
1986 }
1987
1988 sq = &pf->qset.sq[sq_idx];
1989 txq = netdev_get_tx_queue(netdev, qidx);
1990
1991 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) {
1992 netif_tx_stop_queue(txq);
1993
1994 /* Check again, incase SQBs got freed up */
1995 smp_mb();
1996 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb)
1997 > sq->sqe_thresh)
1998 netif_tx_wake_queue(txq);
1999
2000 return NETDEV_TX_BUSY;
2001 }
2002
2003 return NETDEV_TX_OK;
2004 }
2005
otx2_qos_select_htb_queue(struct otx2_nic * pf,struct sk_buff * skb,u16 htb_maj_id)2006 static int otx2_qos_select_htb_queue(struct otx2_nic *pf, struct sk_buff *skb,
2007 u16 htb_maj_id)
2008 {
2009 u16 classid;
2010
2011 if ((TC_H_MAJ(skb->priority) >> 16) == htb_maj_id)
2012 classid = TC_H_MIN(skb->priority);
2013 else
2014 classid = READ_ONCE(pf->qos.defcls);
2015
2016 if (!classid)
2017 return 0;
2018
2019 return otx2_get_txq_by_classid(pf, classid);
2020 }
2021
otx2_select_queue(struct net_device * netdev,struct sk_buff * skb,struct net_device * sb_dev)2022 u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb,
2023 struct net_device *sb_dev)
2024 {
2025 struct otx2_nic *pf = netdev_priv(netdev);
2026 bool qos_enabled;
2027 #ifdef CONFIG_DCB
2028 u8 vlan_prio;
2029 #endif
2030 int txq;
2031
2032 qos_enabled = netdev->real_num_tx_queues > pf->hw.tx_queues;
2033 if (unlikely(qos_enabled)) {
2034 /* This smp_load_acquire() pairs with smp_store_release() in
2035 * otx2_qos_root_add() called from htb offload root creation
2036 */
2037 u16 htb_maj_id = smp_load_acquire(&pf->qos.maj_id);
2038
2039 if (unlikely(htb_maj_id)) {
2040 txq = otx2_qos_select_htb_queue(pf, skb, htb_maj_id);
2041 if (txq > 0)
2042 return txq;
2043 goto process_pfc;
2044 }
2045 }
2046
2047 process_pfc:
2048 #ifdef CONFIG_DCB
2049 if (!skb_vlan_tag_present(skb))
2050 goto pick_tx;
2051
2052 vlan_prio = skb->vlan_tci >> 13;
2053 if ((vlan_prio > pf->hw.tx_queues - 1) ||
2054 !pf->pfc_alloc_status[vlan_prio])
2055 goto pick_tx;
2056
2057 return vlan_prio;
2058
2059 pick_tx:
2060 #endif
2061 txq = netdev_pick_tx(netdev, skb, NULL);
2062 if (unlikely(qos_enabled))
2063 return txq % pf->hw.tx_queues;
2064
2065 return txq;
2066 }
2067 EXPORT_SYMBOL(otx2_select_queue);
2068
otx2_fix_features(struct net_device * dev,netdev_features_t features)2069 static netdev_features_t otx2_fix_features(struct net_device *dev,
2070 netdev_features_t features)
2071 {
2072 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2073 features |= NETIF_F_HW_VLAN_STAG_RX;
2074 else
2075 features &= ~NETIF_F_HW_VLAN_STAG_RX;
2076
2077 return features;
2078 }
2079
otx2_set_rx_mode(struct net_device * netdev)2080 static void otx2_set_rx_mode(struct net_device *netdev)
2081 {
2082 struct otx2_nic *pf = netdev_priv(netdev);
2083
2084 queue_work(pf->otx2_wq, &pf->rx_mode_work);
2085 }
2086
otx2_rx_mode_wrk_handler(struct work_struct * work)2087 static void otx2_rx_mode_wrk_handler(struct work_struct *work)
2088 {
2089 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work);
2090
2091 otx2_do_set_rx_mode(pf);
2092 }
2093
otx2_set_features(struct net_device * netdev,netdev_features_t features)2094 static int otx2_set_features(struct net_device *netdev,
2095 netdev_features_t features)
2096 {
2097 netdev_features_t changed = features ^ netdev->features;
2098 struct otx2_nic *pf = netdev_priv(netdev);
2099
2100 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev))
2101 return otx2_cgx_config_loopback(pf,
2102 features & NETIF_F_LOOPBACK);
2103
2104 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev))
2105 return otx2_enable_rxvlan(pf,
2106 features & NETIF_F_HW_VLAN_CTAG_RX);
2107
2108 return otx2_handle_ntuple_tc_features(netdev, features);
2109 }
2110
otx2_reset_task(struct work_struct * work)2111 static void otx2_reset_task(struct work_struct *work)
2112 {
2113 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task);
2114
2115 if (!netif_running(pf->netdev))
2116 return;
2117
2118 rtnl_lock();
2119 otx2_stop(pf->netdev);
2120 pf->reset_count++;
2121 otx2_open(pf->netdev);
2122 netif_trans_update(pf->netdev);
2123 rtnl_unlock();
2124 }
2125
otx2_config_hw_rx_tstamp(struct otx2_nic * pfvf,bool enable)2126 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable)
2127 {
2128 struct msg_req *req;
2129 int err;
2130
2131 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable)
2132 return 0;
2133
2134 mutex_lock(&pfvf->mbox.lock);
2135 if (enable)
2136 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox);
2137 else
2138 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox);
2139 if (!req) {
2140 mutex_unlock(&pfvf->mbox.lock);
2141 return -ENOMEM;
2142 }
2143
2144 err = otx2_sync_mbox_msg(&pfvf->mbox);
2145 if (err) {
2146 mutex_unlock(&pfvf->mbox.lock);
2147 return err;
2148 }
2149
2150 mutex_unlock(&pfvf->mbox.lock);
2151 if (enable)
2152 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED;
2153 else
2154 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED;
2155 return 0;
2156 }
2157
otx2_config_hw_tx_tstamp(struct otx2_nic * pfvf,bool enable)2158 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable)
2159 {
2160 struct msg_req *req;
2161 int err;
2162
2163 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable)
2164 return 0;
2165
2166 mutex_lock(&pfvf->mbox.lock);
2167 if (enable)
2168 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox);
2169 else
2170 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox);
2171 if (!req) {
2172 mutex_unlock(&pfvf->mbox.lock);
2173 return -ENOMEM;
2174 }
2175
2176 err = otx2_sync_mbox_msg(&pfvf->mbox);
2177 if (err) {
2178 mutex_unlock(&pfvf->mbox.lock);
2179 return err;
2180 }
2181
2182 mutex_unlock(&pfvf->mbox.lock);
2183 if (enable)
2184 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED;
2185 else
2186 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED;
2187 return 0;
2188 }
2189
otx2_config_hwtstamp(struct net_device * netdev,struct ifreq * ifr)2190 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr)
2191 {
2192 struct otx2_nic *pfvf = netdev_priv(netdev);
2193 struct hwtstamp_config config;
2194
2195 if (!pfvf->ptp)
2196 return -ENODEV;
2197
2198 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2199 return -EFAULT;
2200
2201 switch (config.tx_type) {
2202 case HWTSTAMP_TX_OFF:
2203 if (pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC)
2204 pfvf->flags &= ~OTX2_FLAG_PTP_ONESTEP_SYNC;
2205
2206 cancel_delayed_work(&pfvf->ptp->synctstamp_work);
2207 otx2_config_hw_tx_tstamp(pfvf, false);
2208 break;
2209 case HWTSTAMP_TX_ONESTEP_SYNC:
2210 if (!test_bit(CN10K_PTP_ONESTEP, &pfvf->hw.cap_flag))
2211 return -ERANGE;
2212 pfvf->flags |= OTX2_FLAG_PTP_ONESTEP_SYNC;
2213 schedule_delayed_work(&pfvf->ptp->synctstamp_work,
2214 msecs_to_jiffies(500));
2215 fallthrough;
2216 case HWTSTAMP_TX_ON:
2217 otx2_config_hw_tx_tstamp(pfvf, true);
2218 break;
2219 default:
2220 return -ERANGE;
2221 }
2222
2223 switch (config.rx_filter) {
2224 case HWTSTAMP_FILTER_NONE:
2225 otx2_config_hw_rx_tstamp(pfvf, false);
2226 break;
2227 case HWTSTAMP_FILTER_ALL:
2228 case HWTSTAMP_FILTER_SOME:
2229 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2230 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2231 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2232 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2233 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2234 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2235 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2236 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2237 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2238 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2239 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2240 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2241 otx2_config_hw_rx_tstamp(pfvf, true);
2242 config.rx_filter = HWTSTAMP_FILTER_ALL;
2243 break;
2244 default:
2245 return -ERANGE;
2246 }
2247
2248 memcpy(&pfvf->tstamp, &config, sizeof(config));
2249
2250 return copy_to_user(ifr->ifr_data, &config,
2251 sizeof(config)) ? -EFAULT : 0;
2252 }
2253 EXPORT_SYMBOL(otx2_config_hwtstamp);
2254
otx2_ioctl(struct net_device * netdev,struct ifreq * req,int cmd)2255 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
2256 {
2257 struct otx2_nic *pfvf = netdev_priv(netdev);
2258 struct hwtstamp_config *cfg = &pfvf->tstamp;
2259
2260 switch (cmd) {
2261 case SIOCSHWTSTAMP:
2262 return otx2_config_hwtstamp(netdev, req);
2263 case SIOCGHWTSTAMP:
2264 return copy_to_user(req->ifr_data, cfg,
2265 sizeof(*cfg)) ? -EFAULT : 0;
2266 default:
2267 return -EOPNOTSUPP;
2268 }
2269 }
2270 EXPORT_SYMBOL(otx2_ioctl);
2271
otx2_do_set_vf_mac(struct otx2_nic * pf,int vf,const u8 * mac)2272 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac)
2273 {
2274 struct npc_install_flow_req *req;
2275 int err;
2276
2277 mutex_lock(&pf->mbox.lock);
2278 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox);
2279 if (!req) {
2280 err = -ENOMEM;
2281 goto out;
2282 }
2283
2284 ether_addr_copy(req->packet.dmac, mac);
2285 eth_broadcast_addr((u8 *)&req->mask.dmac);
2286 req->features = BIT_ULL(NPC_DMAC);
2287 req->channel = pf->hw.rx_chan_base;
2288 req->intf = NIX_INTF_RX;
2289 req->default_rule = 1;
2290 req->append = 1;
2291 req->vf = vf + 1;
2292 req->op = NIX_RX_ACTION_DEFAULT;
2293
2294 err = otx2_sync_mbox_msg(&pf->mbox);
2295 out:
2296 mutex_unlock(&pf->mbox.lock);
2297 return err;
2298 }
2299
otx2_set_vf_mac(struct net_device * netdev,int vf,u8 * mac)2300 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
2301 {
2302 struct otx2_nic *pf = netdev_priv(netdev);
2303 struct pci_dev *pdev = pf->pdev;
2304 struct otx2_vf_config *config;
2305 int ret;
2306
2307 if (!netif_running(netdev))
2308 return -EAGAIN;
2309
2310 if (vf >= pf->total_vfs)
2311 return -EINVAL;
2312
2313 if (!is_valid_ether_addr(mac))
2314 return -EINVAL;
2315
2316 config = &pf->vf_configs[vf];
2317 ether_addr_copy(config->mac, mac);
2318
2319 ret = otx2_do_set_vf_mac(pf, vf, mac);
2320 if (ret == 0)
2321 dev_info(&pdev->dev,
2322 "Load/Reload VF driver\n");
2323
2324 return ret;
2325 }
2326
otx2_do_set_vf_vlan(struct otx2_nic * pf,int vf,u16 vlan,u8 qos,__be16 proto)2327 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos,
2328 __be16 proto)
2329 {
2330 struct otx2_flow_config *flow_cfg = pf->flow_cfg;
2331 struct nix_vtag_config_rsp *vtag_rsp;
2332 struct npc_delete_flow_req *del_req;
2333 struct nix_vtag_config *vtag_req;
2334 struct npc_install_flow_req *req;
2335 struct otx2_vf_config *config;
2336 int err = 0;
2337 u32 idx;
2338
2339 config = &pf->vf_configs[vf];
2340
2341 if (!vlan && !config->vlan)
2342 goto out;
2343
2344 mutex_lock(&pf->mbox.lock);
2345
2346 /* free old tx vtag entry */
2347 if (config->vlan) {
2348 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox);
2349 if (!vtag_req) {
2350 err = -ENOMEM;
2351 goto out;
2352 }
2353 vtag_req->cfg_type = 0;
2354 vtag_req->tx.free_vtag0 = 1;
2355 vtag_req->tx.vtag0_idx = config->tx_vtag_idx;
2356
2357 err = otx2_sync_mbox_msg(&pf->mbox);
2358 if (err)
2359 goto out;
2360 }
2361
2362 if (!vlan && config->vlan) {
2363 /* rx */
2364 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox);
2365 if (!del_req) {
2366 err = -ENOMEM;
2367 goto out;
2368 }
2369 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX);
2370 del_req->entry =
2371 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx];
2372 err = otx2_sync_mbox_msg(&pf->mbox);
2373 if (err)
2374 goto out;
2375
2376 /* tx */
2377 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox);
2378 if (!del_req) {
2379 err = -ENOMEM;
2380 goto out;
2381 }
2382 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX);
2383 del_req->entry =
2384 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx];
2385 err = otx2_sync_mbox_msg(&pf->mbox);
2386
2387 goto out;
2388 }
2389
2390 /* rx */
2391 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox);
2392 if (!req) {
2393 err = -ENOMEM;
2394 goto out;
2395 }
2396
2397 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX);
2398 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx];
2399 req->packet.vlan_tci = htons(vlan);
2400 req->mask.vlan_tci = htons(VLAN_VID_MASK);
2401 /* af fills the destination mac addr */
2402 eth_broadcast_addr((u8 *)&req->mask.dmac);
2403 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC);
2404 req->channel = pf->hw.rx_chan_base;
2405 req->intf = NIX_INTF_RX;
2406 req->vf = vf + 1;
2407 req->op = NIX_RX_ACTION_DEFAULT;
2408 req->vtag0_valid = true;
2409 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7;
2410 req->set_cntr = 1;
2411
2412 err = otx2_sync_mbox_msg(&pf->mbox);
2413 if (err)
2414 goto out;
2415
2416 /* tx */
2417 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox);
2418 if (!vtag_req) {
2419 err = -ENOMEM;
2420 goto out;
2421 }
2422
2423 /* configure tx vtag params */
2424 vtag_req->vtag_size = VTAGSIZE_T4;
2425 vtag_req->cfg_type = 0; /* tx vlan cfg */
2426 vtag_req->tx.cfg_vtag0 = 1;
2427 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan;
2428
2429 err = otx2_sync_mbox_msg(&pf->mbox);
2430 if (err)
2431 goto out;
2432
2433 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp
2434 (&pf->mbox.mbox, 0, &vtag_req->hdr);
2435 if (IS_ERR(vtag_rsp)) {
2436 err = PTR_ERR(vtag_rsp);
2437 goto out;
2438 }
2439 config->tx_vtag_idx = vtag_rsp->vtag0_idx;
2440
2441 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox);
2442 if (!req) {
2443 err = -ENOMEM;
2444 goto out;
2445 }
2446
2447 eth_zero_addr((u8 *)&req->mask.dmac);
2448 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX);
2449 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx];
2450 req->features = BIT_ULL(NPC_DMAC);
2451 req->channel = pf->hw.tx_chan_base;
2452 req->intf = NIX_INTF_TX;
2453 req->vf = vf + 1;
2454 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT;
2455 req->vtag0_def = vtag_rsp->vtag0_idx;
2456 req->vtag0_op = VTAG_INSERT;
2457 req->set_cntr = 1;
2458
2459 err = otx2_sync_mbox_msg(&pf->mbox);
2460 out:
2461 config->vlan = vlan;
2462 mutex_unlock(&pf->mbox.lock);
2463 return err;
2464 }
2465
otx2_set_vf_vlan(struct net_device * netdev,int vf,u16 vlan,u8 qos,__be16 proto)2466 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos,
2467 __be16 proto)
2468 {
2469 struct otx2_nic *pf = netdev_priv(netdev);
2470 struct pci_dev *pdev = pf->pdev;
2471
2472 if (!netif_running(netdev))
2473 return -EAGAIN;
2474
2475 if (vf >= pci_num_vf(pdev))
2476 return -EINVAL;
2477
2478 /* qos is currently unsupported */
2479 if (vlan >= VLAN_N_VID || qos)
2480 return -EINVAL;
2481
2482 if (proto != htons(ETH_P_8021Q))
2483 return -EPROTONOSUPPORT;
2484
2485 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT))
2486 return -EOPNOTSUPP;
2487
2488 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto);
2489 }
2490
otx2_get_vf_config(struct net_device * netdev,int vf,struct ifla_vf_info * ivi)2491 static int otx2_get_vf_config(struct net_device *netdev, int vf,
2492 struct ifla_vf_info *ivi)
2493 {
2494 struct otx2_nic *pf = netdev_priv(netdev);
2495 struct pci_dev *pdev = pf->pdev;
2496 struct otx2_vf_config *config;
2497
2498 if (!netif_running(netdev))
2499 return -EAGAIN;
2500
2501 if (vf >= pci_num_vf(pdev))
2502 return -EINVAL;
2503
2504 config = &pf->vf_configs[vf];
2505 ivi->vf = vf;
2506 ether_addr_copy(ivi->mac, config->mac);
2507 ivi->vlan = config->vlan;
2508 ivi->trusted = config->trusted;
2509
2510 return 0;
2511 }
2512
otx2_xdp_xmit_tx(struct otx2_nic * pf,struct xdp_frame * xdpf,int qidx)2513 static int otx2_xdp_xmit_tx(struct otx2_nic *pf, struct xdp_frame *xdpf,
2514 int qidx)
2515 {
2516 struct page *page;
2517 u64 dma_addr;
2518 int err = 0;
2519
2520 dma_addr = otx2_dma_map_page(pf, virt_to_page(xdpf->data),
2521 offset_in_page(xdpf->data), xdpf->len,
2522 DMA_TO_DEVICE);
2523 if (dma_mapping_error(pf->dev, dma_addr))
2524 return -ENOMEM;
2525
2526 err = otx2_xdp_sq_append_pkt(pf, dma_addr, xdpf->len, qidx);
2527 if (!err) {
2528 otx2_dma_unmap_page(pf, dma_addr, xdpf->len, DMA_TO_DEVICE);
2529 page = virt_to_page(xdpf->data);
2530 put_page(page);
2531 return -ENOMEM;
2532 }
2533 return 0;
2534 }
2535
otx2_xdp_xmit(struct net_device * netdev,int n,struct xdp_frame ** frames,u32 flags)2536 static int otx2_xdp_xmit(struct net_device *netdev, int n,
2537 struct xdp_frame **frames, u32 flags)
2538 {
2539 struct otx2_nic *pf = netdev_priv(netdev);
2540 int qidx = smp_processor_id();
2541 struct otx2_snd_queue *sq;
2542 int drops = 0, i;
2543
2544 if (!netif_running(netdev))
2545 return -ENETDOWN;
2546
2547 qidx += pf->hw.tx_queues;
2548 sq = pf->xdp_prog ? &pf->qset.sq[qidx] : NULL;
2549
2550 /* Abort xmit if xdp queue is not */
2551 if (unlikely(!sq))
2552 return -ENXIO;
2553
2554 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
2555 return -EINVAL;
2556
2557 for (i = 0; i < n; i++) {
2558 struct xdp_frame *xdpf = frames[i];
2559 int err;
2560
2561 err = otx2_xdp_xmit_tx(pf, xdpf, qidx);
2562 if (err)
2563 drops++;
2564 }
2565 return n - drops;
2566 }
2567
otx2_xdp_setup(struct otx2_nic * pf,struct bpf_prog * prog)2568 static int otx2_xdp_setup(struct otx2_nic *pf, struct bpf_prog *prog)
2569 {
2570 struct net_device *dev = pf->netdev;
2571 bool if_up = netif_running(pf->netdev);
2572 struct bpf_prog *old_prog;
2573
2574 if (prog && dev->mtu > MAX_XDP_MTU) {
2575 netdev_warn(dev, "Jumbo frames not yet supported with XDP\n");
2576 return -EOPNOTSUPP;
2577 }
2578
2579 if (if_up)
2580 otx2_stop(pf->netdev);
2581
2582 old_prog = xchg(&pf->xdp_prog, prog);
2583
2584 if (old_prog)
2585 bpf_prog_put(old_prog);
2586
2587 if (pf->xdp_prog)
2588 bpf_prog_add(pf->xdp_prog, pf->hw.rx_queues - 1);
2589
2590 /* Network stack and XDP shared same rx queues.
2591 * Use separate tx queues for XDP and network stack.
2592 */
2593 if (pf->xdp_prog) {
2594 pf->hw.xdp_queues = pf->hw.rx_queues;
2595 xdp_features_set_redirect_target(dev, false);
2596 } else {
2597 pf->hw.xdp_queues = 0;
2598 xdp_features_clear_redirect_target(dev);
2599 }
2600
2601 pf->hw.non_qos_queues += pf->hw.xdp_queues;
2602
2603 if (if_up)
2604 otx2_open(pf->netdev);
2605
2606 return 0;
2607 }
2608
otx2_xdp(struct net_device * netdev,struct netdev_bpf * xdp)2609 static int otx2_xdp(struct net_device *netdev, struct netdev_bpf *xdp)
2610 {
2611 struct otx2_nic *pf = netdev_priv(netdev);
2612
2613 switch (xdp->command) {
2614 case XDP_SETUP_PROG:
2615 return otx2_xdp_setup(pf, xdp->prog);
2616 default:
2617 return -EINVAL;
2618 }
2619 }
2620
otx2_set_vf_permissions(struct otx2_nic * pf,int vf,int req_perm)2621 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf,
2622 int req_perm)
2623 {
2624 struct set_vf_perm *req;
2625 int rc;
2626
2627 mutex_lock(&pf->mbox.lock);
2628 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox);
2629 if (!req) {
2630 rc = -ENOMEM;
2631 goto out;
2632 }
2633
2634 /* Let AF reset VF permissions as sriov is disabled */
2635 if (req_perm == OTX2_RESET_VF_PERM) {
2636 req->flags |= RESET_VF_PERM;
2637 } else if (req_perm == OTX2_TRUSTED_VF) {
2638 if (pf->vf_configs[vf].trusted)
2639 req->flags |= VF_TRUSTED;
2640 }
2641
2642 req->vf = vf;
2643 rc = otx2_sync_mbox_msg(&pf->mbox);
2644 out:
2645 mutex_unlock(&pf->mbox.lock);
2646 return rc;
2647 }
2648
otx2_ndo_set_vf_trust(struct net_device * netdev,int vf,bool enable)2649 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf,
2650 bool enable)
2651 {
2652 struct otx2_nic *pf = netdev_priv(netdev);
2653 struct pci_dev *pdev = pf->pdev;
2654 int rc;
2655
2656 if (vf >= pci_num_vf(pdev))
2657 return -EINVAL;
2658
2659 if (pf->vf_configs[vf].trusted == enable)
2660 return 0;
2661
2662 pf->vf_configs[vf].trusted = enable;
2663 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF);
2664
2665 if (rc)
2666 pf->vf_configs[vf].trusted = !enable;
2667 else
2668 netdev_info(pf->netdev, "VF %d is %strusted\n",
2669 vf, enable ? "" : "not ");
2670 return rc;
2671 }
2672
2673 static const struct net_device_ops otx2_netdev_ops = {
2674 .ndo_open = otx2_open,
2675 .ndo_stop = otx2_stop,
2676 .ndo_start_xmit = otx2_xmit,
2677 .ndo_select_queue = otx2_select_queue,
2678 .ndo_fix_features = otx2_fix_features,
2679 .ndo_set_mac_address = otx2_set_mac_address,
2680 .ndo_change_mtu = otx2_change_mtu,
2681 .ndo_set_rx_mode = otx2_set_rx_mode,
2682 .ndo_set_features = otx2_set_features,
2683 .ndo_tx_timeout = otx2_tx_timeout,
2684 .ndo_get_stats64 = otx2_get_stats64,
2685 .ndo_eth_ioctl = otx2_ioctl,
2686 .ndo_set_vf_mac = otx2_set_vf_mac,
2687 .ndo_set_vf_vlan = otx2_set_vf_vlan,
2688 .ndo_get_vf_config = otx2_get_vf_config,
2689 .ndo_bpf = otx2_xdp,
2690 .ndo_xdp_xmit = otx2_xdp_xmit,
2691 .ndo_setup_tc = otx2_setup_tc,
2692 .ndo_set_vf_trust = otx2_ndo_set_vf_trust,
2693 };
2694
otx2_wq_init(struct otx2_nic * pf)2695 static int otx2_wq_init(struct otx2_nic *pf)
2696 {
2697 pf->otx2_wq = create_singlethread_workqueue("otx2_wq");
2698 if (!pf->otx2_wq)
2699 return -ENOMEM;
2700
2701 INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler);
2702 INIT_WORK(&pf->reset_task, otx2_reset_task);
2703 return 0;
2704 }
2705
otx2_check_pf_usable(struct otx2_nic * nic)2706 static int otx2_check_pf_usable(struct otx2_nic *nic)
2707 {
2708 u64 rev;
2709
2710 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM));
2711 rev = (rev >> 12) & 0xFF;
2712 /* Check if AF has setup revision for RVUM block,
2713 * otherwise this driver probe should be deferred
2714 * until AF driver comes up.
2715 */
2716 if (!rev) {
2717 dev_warn(nic->dev,
2718 "AF is not initialized, deferring probe\n");
2719 return -EPROBE_DEFER;
2720 }
2721 return 0;
2722 }
2723
otx2_realloc_msix_vectors(struct otx2_nic * pf)2724 static int otx2_realloc_msix_vectors(struct otx2_nic *pf)
2725 {
2726 struct otx2_hw *hw = &pf->hw;
2727 int num_vec, err;
2728
2729 /* NPA interrupts are inot registered, so alloc only
2730 * upto NIX vector offset.
2731 */
2732 num_vec = hw->nix_msixoff;
2733 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues;
2734
2735 otx2_disable_mbox_intr(pf);
2736 pci_free_irq_vectors(hw->pdev);
2737 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX);
2738 if (err < 0) {
2739 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n",
2740 __func__, num_vec);
2741 return err;
2742 }
2743
2744 return otx2_register_mbox_intr(pf, false);
2745 }
2746
otx2_sriov_vfcfg_init(struct otx2_nic * pf)2747 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf)
2748 {
2749 int i;
2750
2751 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs,
2752 sizeof(struct otx2_vf_config),
2753 GFP_KERNEL);
2754 if (!pf->vf_configs)
2755 return -ENOMEM;
2756
2757 for (i = 0; i < pf->total_vfs; i++) {
2758 pf->vf_configs[i].pf = pf;
2759 pf->vf_configs[i].intf_down = true;
2760 pf->vf_configs[i].trusted = false;
2761 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work,
2762 otx2_vf_link_event_task);
2763 }
2764
2765 return 0;
2766 }
2767
otx2_sriov_vfcfg_cleanup(struct otx2_nic * pf)2768 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf)
2769 {
2770 int i;
2771
2772 if (!pf->vf_configs)
2773 return;
2774
2775 for (i = 0; i < pf->total_vfs; i++) {
2776 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work);
2777 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM);
2778 }
2779 }
2780
otx2_probe(struct pci_dev * pdev,const struct pci_device_id * id)2781 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2782 {
2783 struct device *dev = &pdev->dev;
2784 int err, qcount, qos_txqs;
2785 struct net_device *netdev;
2786 struct otx2_nic *pf;
2787 struct otx2_hw *hw;
2788 int num_vec;
2789
2790 err = pcim_enable_device(pdev);
2791 if (err) {
2792 dev_err(dev, "Failed to enable PCI device\n");
2793 return err;
2794 }
2795
2796 err = pci_request_regions(pdev, DRV_NAME);
2797 if (err) {
2798 dev_err(dev, "PCI request regions failed 0x%x\n", err);
2799 return err;
2800 }
2801
2802 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
2803 if (err) {
2804 dev_err(dev, "DMA mask config failed, abort\n");
2805 goto err_release_regions;
2806 }
2807
2808 pci_set_master(pdev);
2809
2810 /* Set number of queues */
2811 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT);
2812 qos_txqs = min_t(int, qcount, OTX2_QOS_MAX_LEAF_NODES);
2813
2814 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount + qos_txqs, qcount);
2815 if (!netdev) {
2816 err = -ENOMEM;
2817 goto err_release_regions;
2818 }
2819
2820 pci_set_drvdata(pdev, netdev);
2821 SET_NETDEV_DEV(netdev, &pdev->dev);
2822 pf = netdev_priv(netdev);
2823 pf->netdev = netdev;
2824 pf->pdev = pdev;
2825 pf->dev = dev;
2826 pf->total_vfs = pci_sriov_get_totalvfs(pdev);
2827 pf->flags |= OTX2_FLAG_INTF_DOWN;
2828
2829 hw = &pf->hw;
2830 hw->pdev = pdev;
2831 hw->rx_queues = qcount;
2832 hw->tx_queues = qcount;
2833 hw->non_qos_queues = qcount;
2834 hw->max_queues = qcount;
2835 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN;
2836 /* Use CQE of 128 byte descriptor size by default */
2837 hw->xqe_size = 128;
2838
2839 num_vec = pci_msix_vec_count(pdev);
2840 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE,
2841 GFP_KERNEL);
2842 if (!hw->irq_name) {
2843 err = -ENOMEM;
2844 goto err_free_netdev;
2845 }
2846
2847 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec,
2848 sizeof(cpumask_var_t), GFP_KERNEL);
2849 if (!hw->affinity_mask) {
2850 err = -ENOMEM;
2851 goto err_free_netdev;
2852 }
2853
2854 /* Map CSRs */
2855 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
2856 if (!pf->reg_base) {
2857 dev_err(dev, "Unable to map physical function CSRs, aborting\n");
2858 err = -ENOMEM;
2859 goto err_free_netdev;
2860 }
2861
2862 err = otx2_check_pf_usable(pf);
2863 if (err)
2864 goto err_free_netdev;
2865
2866 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT,
2867 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX);
2868 if (err < 0) {
2869 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n",
2870 __func__, num_vec);
2871 goto err_free_netdev;
2872 }
2873
2874 otx2_setup_dev_hw_settings(pf);
2875
2876 /* Init PF <=> AF mailbox stuff */
2877 err = otx2_pfaf_mbox_init(pf);
2878 if (err)
2879 goto err_free_irq_vectors;
2880
2881 /* Register mailbox interrupt */
2882 err = otx2_register_mbox_intr(pf, true);
2883 if (err)
2884 goto err_mbox_destroy;
2885
2886 /* Request AF to attach NPA and NIX LFs to this PF.
2887 * NIX and NPA LFs are needed for this PF to function as a NIC.
2888 */
2889 err = otx2_attach_npa_nix(pf);
2890 if (err)
2891 goto err_disable_mbox_intr;
2892
2893 err = otx2_realloc_msix_vectors(pf);
2894 if (err)
2895 goto err_detach_rsrc;
2896
2897 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues);
2898 if (err)
2899 goto err_detach_rsrc;
2900
2901 err = cn10k_lmtst_init(pf);
2902 if (err)
2903 goto err_detach_rsrc;
2904
2905 /* Assign default mac address */
2906 otx2_get_mac_from_af(netdev);
2907
2908 /* Don't check for error. Proceed without ptp */
2909 otx2_ptp_init(pf);
2910
2911 /* NPA's pool is a stack to which SW frees buffer pointers via Aura.
2912 * HW allocates buffer pointer from stack and uses it for DMA'ing
2913 * ingress packet. In some scenarios HW can free back allocated buffer
2914 * pointers to pool. This makes it impossible for SW to maintain a
2915 * parallel list where physical addresses of buffer pointers (IOVAs)
2916 * given to HW can be saved for later reference.
2917 *
2918 * So the only way to convert Rx packet's buffer address is to use
2919 * IOMMU's iova_to_phys() handler which translates the address by
2920 * walking through the translation tables.
2921 */
2922 pf->iommu_domain = iommu_get_domain_for_dev(dev);
2923
2924 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
2925 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH |
2926 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
2927 NETIF_F_GSO_UDP_L4);
2928 netdev->features |= netdev->hw_features;
2929
2930 err = otx2_mcam_flow_init(pf);
2931 if (err)
2932 goto err_ptp_destroy;
2933
2934 err = cn10k_mcs_init(pf);
2935 if (err)
2936 goto err_del_mcam_entries;
2937
2938 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT)
2939 netdev->hw_features |= NETIF_F_NTUPLE;
2940
2941 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT)
2942 netdev->priv_flags |= IFF_UNICAST_FLT;
2943
2944 /* Support TSO on tag interface */
2945 netdev->vlan_features |= netdev->features;
2946 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
2947 NETIF_F_HW_VLAN_STAG_TX;
2948 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT)
2949 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX |
2950 NETIF_F_HW_VLAN_STAG_RX;
2951 netdev->features |= netdev->hw_features;
2952
2953 /* HW supports tc offload but mutually exclusive with n-tuple filters */
2954 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT)
2955 netdev->hw_features |= NETIF_F_HW_TC;
2956
2957 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL;
2958
2959 netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS);
2960 netdev->watchdog_timeo = OTX2_TX_TIMEOUT;
2961
2962 netdev->netdev_ops = &otx2_netdev_ops;
2963 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT;
2964
2965 netdev->min_mtu = OTX2_MIN_MTU;
2966 netdev->max_mtu = otx2_get_max_mtu(pf);
2967
2968 err = register_netdev(netdev);
2969 if (err) {
2970 dev_err(dev, "Failed to register netdevice\n");
2971 goto err_mcs_free;
2972 }
2973
2974 err = otx2_wq_init(pf);
2975 if (err)
2976 goto err_unreg_netdev;
2977
2978 otx2_set_ethtool_ops(netdev);
2979
2980 err = otx2_init_tc(pf);
2981 if (err)
2982 goto err_mcam_flow_del;
2983
2984 err = otx2_register_dl(pf);
2985 if (err)
2986 goto err_mcam_flow_del;
2987
2988 /* Initialize SR-IOV resources */
2989 err = otx2_sriov_vfcfg_init(pf);
2990 if (err)
2991 goto err_pf_sriov_init;
2992
2993 /* Enable link notifications */
2994 otx2_cgx_config_linkevents(pf, true);
2995
2996 #ifdef CONFIG_DCB
2997 err = otx2_dcbnl_set_ops(netdev);
2998 if (err)
2999 goto err_pf_sriov_init;
3000 #endif
3001
3002 otx2_qos_init(pf, qos_txqs);
3003
3004 return 0;
3005
3006 err_pf_sriov_init:
3007 otx2_shutdown_tc(pf);
3008 err_mcam_flow_del:
3009 otx2_mcam_flow_del(pf);
3010 err_unreg_netdev:
3011 unregister_netdev(netdev);
3012 err_mcs_free:
3013 cn10k_mcs_free(pf);
3014 err_del_mcam_entries:
3015 otx2_mcam_flow_del(pf);
3016 err_ptp_destroy:
3017 otx2_ptp_destroy(pf);
3018 err_detach_rsrc:
3019 if (pf->hw.lmt_info)
3020 free_percpu(pf->hw.lmt_info);
3021 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag))
3022 qmem_free(pf->dev, pf->dync_lmt);
3023 otx2_detach_resources(&pf->mbox);
3024 err_disable_mbox_intr:
3025 otx2_disable_mbox_intr(pf);
3026 err_mbox_destroy:
3027 otx2_pfaf_mbox_destroy(pf);
3028 err_free_irq_vectors:
3029 pci_free_irq_vectors(hw->pdev);
3030 err_free_netdev:
3031 pci_set_drvdata(pdev, NULL);
3032 free_netdev(netdev);
3033 err_release_regions:
3034 pci_release_regions(pdev);
3035 return err;
3036 }
3037
otx2_vf_link_event_task(struct work_struct * work)3038 static void otx2_vf_link_event_task(struct work_struct *work)
3039 {
3040 struct otx2_vf_config *config;
3041 struct cgx_link_info_msg *req;
3042 struct mbox_msghdr *msghdr;
3043 struct otx2_nic *pf;
3044 int vf_idx;
3045
3046 config = container_of(work, struct otx2_vf_config,
3047 link_event_work.work);
3048 vf_idx = config - config->pf->vf_configs;
3049 pf = config->pf;
3050
3051 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx,
3052 sizeof(*req), sizeof(struct msg_rsp));
3053 if (!msghdr) {
3054 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx);
3055 return;
3056 }
3057
3058 req = (struct cgx_link_info_msg *)msghdr;
3059 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT;
3060 req->hdr.sig = OTX2_MBOX_REQ_SIG;
3061 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info));
3062
3063 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx);
3064 }
3065
otx2_sriov_enable(struct pci_dev * pdev,int numvfs)3066 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs)
3067 {
3068 struct net_device *netdev = pci_get_drvdata(pdev);
3069 struct otx2_nic *pf = netdev_priv(netdev);
3070 int ret;
3071
3072 /* Init PF <=> VF mailbox stuff */
3073 ret = otx2_pfvf_mbox_init(pf, numvfs);
3074 if (ret)
3075 return ret;
3076
3077 ret = otx2_register_pfvf_mbox_intr(pf, numvfs);
3078 if (ret)
3079 goto free_mbox;
3080
3081 ret = otx2_pf_flr_init(pf, numvfs);
3082 if (ret)
3083 goto free_intr;
3084
3085 ret = otx2_register_flr_me_intr(pf, numvfs);
3086 if (ret)
3087 goto free_flr;
3088
3089 ret = pci_enable_sriov(pdev, numvfs);
3090 if (ret)
3091 goto free_flr_intr;
3092
3093 return numvfs;
3094 free_flr_intr:
3095 otx2_disable_flr_me_intr(pf);
3096 free_flr:
3097 otx2_flr_wq_destroy(pf);
3098 free_intr:
3099 otx2_disable_pfvf_mbox_intr(pf, numvfs);
3100 free_mbox:
3101 otx2_pfvf_mbox_destroy(pf);
3102 return ret;
3103 }
3104
otx2_sriov_disable(struct pci_dev * pdev)3105 static int otx2_sriov_disable(struct pci_dev *pdev)
3106 {
3107 struct net_device *netdev = pci_get_drvdata(pdev);
3108 struct otx2_nic *pf = netdev_priv(netdev);
3109 int numvfs = pci_num_vf(pdev);
3110
3111 if (!numvfs)
3112 return 0;
3113
3114 pci_disable_sriov(pdev);
3115
3116 otx2_disable_flr_me_intr(pf);
3117 otx2_flr_wq_destroy(pf);
3118 otx2_disable_pfvf_mbox_intr(pf, numvfs);
3119 otx2_pfvf_mbox_destroy(pf);
3120
3121 return 0;
3122 }
3123
otx2_sriov_configure(struct pci_dev * pdev,int numvfs)3124 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs)
3125 {
3126 if (numvfs == 0)
3127 return otx2_sriov_disable(pdev);
3128 else
3129 return otx2_sriov_enable(pdev, numvfs);
3130 }
3131
otx2_remove(struct pci_dev * pdev)3132 static void otx2_remove(struct pci_dev *pdev)
3133 {
3134 struct net_device *netdev = pci_get_drvdata(pdev);
3135 struct otx2_nic *pf;
3136
3137 if (!netdev)
3138 return;
3139
3140 pf = netdev_priv(netdev);
3141
3142 pf->flags |= OTX2_FLAG_PF_SHUTDOWN;
3143
3144 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED)
3145 otx2_config_hw_tx_tstamp(pf, false);
3146 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED)
3147 otx2_config_hw_rx_tstamp(pf, false);
3148
3149 /* Disable 802.3x pause frames */
3150 if (pf->flags & OTX2_FLAG_RX_PAUSE_ENABLED ||
3151 (pf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) {
3152 pf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED;
3153 pf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED;
3154 otx2_config_pause_frm(pf);
3155 }
3156
3157 #ifdef CONFIG_DCB
3158 /* Disable PFC config */
3159 if (pf->pfc_en) {
3160 pf->pfc_en = 0;
3161 otx2_config_priority_flow_ctrl(pf);
3162 }
3163 #endif
3164 cancel_work_sync(&pf->reset_task);
3165 /* Disable link notifications */
3166 otx2_cgx_config_linkevents(pf, false);
3167
3168 otx2_unregister_dl(pf);
3169 unregister_netdev(netdev);
3170 cn10k_mcs_free(pf);
3171 otx2_sriov_disable(pf->pdev);
3172 otx2_sriov_vfcfg_cleanup(pf);
3173 if (pf->otx2_wq)
3174 destroy_workqueue(pf->otx2_wq);
3175
3176 otx2_ptp_destroy(pf);
3177 otx2_mcam_flow_del(pf);
3178 otx2_shutdown_tc(pf);
3179 otx2_shutdown_qos(pf);
3180 otx2_detach_resources(&pf->mbox);
3181 if (pf->hw.lmt_info)
3182 free_percpu(pf->hw.lmt_info);
3183 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag))
3184 qmem_free(pf->dev, pf->dync_lmt);
3185 otx2_disable_mbox_intr(pf);
3186 otx2_pfaf_mbox_destroy(pf);
3187 pci_free_irq_vectors(pf->pdev);
3188 pci_set_drvdata(pdev, NULL);
3189 free_netdev(netdev);
3190
3191 pci_release_regions(pdev);
3192 }
3193
3194 static struct pci_driver otx2_pf_driver = {
3195 .name = DRV_NAME,
3196 .id_table = otx2_pf_id_table,
3197 .probe = otx2_probe,
3198 .shutdown = otx2_remove,
3199 .remove = otx2_remove,
3200 .sriov_configure = otx2_sriov_configure
3201 };
3202
otx2_rvupf_init_module(void)3203 static int __init otx2_rvupf_init_module(void)
3204 {
3205 pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
3206
3207 return pci_register_driver(&otx2_pf_driver);
3208 }
3209
otx2_rvupf_cleanup_module(void)3210 static void __exit otx2_rvupf_cleanup_module(void)
3211 {
3212 pci_unregister_driver(&otx2_pf_driver);
3213 }
3214
3215 module_init(otx2_rvupf_init_module);
3216 module_exit(otx2_rvupf_cleanup_module);
3217
