1 /*
2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm80xx_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45 #include "pm80xx_tracepoints.h"
46
47 #define SMP_DIRECT 1
48 #define SMP_INDIRECT 2
49
50
pm80xx_bar4_shift(struct pm8001_hba_info * pm8001_ha,u32 shift_value)51 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
52 {
53 u32 reg_val;
54 unsigned long start;
55 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
56 /* confirm the setting is written */
57 start = jiffies + HZ; /* 1 sec */
58 do {
59 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
60 } while ((reg_val != shift_value) && time_before(jiffies, start));
61 if (reg_val != shift_value) {
62 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MEMBASE_II_SHIFT_REGISTER = 0x%x\n",
63 reg_val);
64 return -1;
65 }
66 return 0;
67 }
68
pm80xx_pci_mem_copy(struct pm8001_hba_info * pm8001_ha,u32 soffset,__le32 * destination,u32 dw_count,u32 bus_base_number)69 static void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset,
70 __le32 *destination,
71 u32 dw_count, u32 bus_base_number)
72 {
73 u32 index, value, offset;
74
75 for (index = 0; index < dw_count; index += 4, destination++) {
76 offset = (soffset + index);
77 if (offset < (64 * 1024)) {
78 value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
79 *destination = cpu_to_le32(value);
80 }
81 }
82 return;
83 }
84
pm80xx_get_fatal_dump(struct device * cdev,struct device_attribute * attr,char * buf)85 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
86 struct device_attribute *attr, char *buf)
87 {
88 struct Scsi_Host *shost = class_to_shost(cdev);
89 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
90 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
91 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
92 u32 accum_len, reg_val, index, *temp;
93 u32 status = 1;
94 unsigned long start;
95 u8 *direct_data;
96 char *fatal_error_data = buf;
97 u32 length_to_read;
98 u32 offset;
99
100 pm8001_ha->forensic_info.data_buf.direct_data = buf;
101 if (pm8001_ha->chip_id == chip_8001) {
102 pm8001_ha->forensic_info.data_buf.direct_data +=
103 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
104 "Not supported for SPC controller");
105 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
106 (char *)buf;
107 }
108 /* initialize variables for very first call from host application */
109 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
110 pm8001_dbg(pm8001_ha, IO,
111 "forensic_info TYPE_NON_FATAL..............\n");
112 direct_data = (u8 *)fatal_error_data;
113 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
114 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
115 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
116 pm8001_ha->forensic_info.data_buf.read_len = 0;
117 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
118
119 /* Write signature to fatal dump table */
120 pm8001_mw32(fatal_table_address,
121 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd);
122
123 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
124 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: status1 %d\n", status);
125 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: read_len 0x%x\n",
126 pm8001_ha->forensic_info.data_buf.read_len);
127 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_len 0x%x\n",
128 pm8001_ha->forensic_info.data_buf.direct_len);
129 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_offset 0x%x\n",
130 pm8001_ha->forensic_info.data_buf.direct_offset);
131 }
132 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
133 /* start to get data */
134 /* Program the MEMBASE II Shifting Register with 0x00.*/
135 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
136 pm8001_ha->fatal_forensic_shift_offset);
137 pm8001_ha->forensic_last_offset = 0;
138 pm8001_ha->forensic_fatal_step = 0;
139 pm8001_ha->fatal_bar_loc = 0;
140 }
141
142 /* Read until accum_len is retrieved */
143 accum_len = pm8001_mr32(fatal_table_address,
144 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
145 /* Determine length of data between previously stored transfer length
146 * and current accumulated transfer length
147 */
148 length_to_read =
149 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer;
150 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: accum_len 0x%x\n",
151 accum_len);
152 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: length_to_read 0x%x\n",
153 length_to_read);
154 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: last_offset 0x%x\n",
155 pm8001_ha->forensic_last_offset);
156 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: read_len 0x%x\n",
157 pm8001_ha->forensic_info.data_buf.read_len);
158 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_len 0x%x\n",
159 pm8001_ha->forensic_info.data_buf.direct_len);
160 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_offset 0x%x\n",
161 pm8001_ha->forensic_info.data_buf.direct_offset);
162
163 /* If accumulated length failed to read correctly fail the attempt.*/
164 if (accum_len == 0xFFFFFFFF) {
165 pm8001_dbg(pm8001_ha, IO,
166 "Possible PCI issue 0x%x not expected\n",
167 accum_len);
168 return status;
169 }
170 /* If accumulated length is zero fail the attempt */
171 if (accum_len == 0) {
172 pm8001_ha->forensic_info.data_buf.direct_data +=
173 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
174 "%08x ", 0xFFFFFFFF);
175 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
176 (char *)buf;
177 }
178 /* Accumulated length is good so start capturing the first data */
179 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
180 if (pm8001_ha->forensic_fatal_step == 0) {
181 moreData:
182 /* If data to read is less than SYSFS_OFFSET then reduce the
183 * length of dataLen
184 */
185 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET
186 > length_to_read) {
187 pm8001_ha->forensic_info.data_buf.direct_len =
188 length_to_read -
189 pm8001_ha->forensic_last_offset;
190 } else {
191 pm8001_ha->forensic_info.data_buf.direct_len =
192 SYSFS_OFFSET;
193 }
194 if (pm8001_ha->forensic_info.data_buf.direct_data) {
195 /* Data is in bar, copy to host memory */
196 pm80xx_pci_mem_copy(pm8001_ha,
197 pm8001_ha->fatal_bar_loc,
198 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
199 pm8001_ha->forensic_info.data_buf.direct_len, 1);
200 }
201 pm8001_ha->fatal_bar_loc +=
202 pm8001_ha->forensic_info.data_buf.direct_len;
203 pm8001_ha->forensic_info.data_buf.direct_offset +=
204 pm8001_ha->forensic_info.data_buf.direct_len;
205 pm8001_ha->forensic_last_offset +=
206 pm8001_ha->forensic_info.data_buf.direct_len;
207 pm8001_ha->forensic_info.data_buf.read_len =
208 pm8001_ha->forensic_info.data_buf.direct_len;
209
210 if (pm8001_ha->forensic_last_offset >= length_to_read) {
211 pm8001_ha->forensic_info.data_buf.direct_data +=
212 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
213 "%08x ", 3);
214 for (index = 0; index <
215 (pm8001_ha->forensic_info.data_buf.direct_len
216 / 4); index++) {
217 pm8001_ha->forensic_info.data_buf.direct_data +=
218 sprintf(
219 pm8001_ha->forensic_info.data_buf.direct_data,
220 "%08x ", *(temp + index));
221 }
222
223 pm8001_ha->fatal_bar_loc = 0;
224 pm8001_ha->forensic_fatal_step = 1;
225 pm8001_ha->fatal_forensic_shift_offset = 0;
226 pm8001_ha->forensic_last_offset = 0;
227 status = 0;
228 offset = (int)
229 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
230 - (char *)buf);
231 pm8001_dbg(pm8001_ha, IO,
232 "get_fatal_spcv:return1 0x%x\n", offset);
233 return (char *)pm8001_ha->
234 forensic_info.data_buf.direct_data -
235 (char *)buf;
236 }
237 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
238 pm8001_ha->forensic_info.data_buf.direct_data +=
239 sprintf(pm8001_ha->
240 forensic_info.data_buf.direct_data,
241 "%08x ", 2);
242 for (index = 0; index <
243 (pm8001_ha->forensic_info.data_buf.direct_len
244 / 4); index++) {
245 pm8001_ha->forensic_info.data_buf.direct_data
246 += sprintf(pm8001_ha->
247 forensic_info.data_buf.direct_data,
248 "%08x ", *(temp + index));
249 }
250 status = 0;
251 offset = (int)
252 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
253 - (char *)buf);
254 pm8001_dbg(pm8001_ha, IO,
255 "get_fatal_spcv:return2 0x%x\n", offset);
256 return (char *)pm8001_ha->
257 forensic_info.data_buf.direct_data -
258 (char *)buf;
259 }
260
261 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
262 pm8001_ha->forensic_info.data_buf.direct_data +=
263 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
264 "%08x ", 2);
265 for (index = 0; index <
266 (pm8001_ha->forensic_info.data_buf.direct_len
267 / 4) ; index++) {
268 pm8001_ha->forensic_info.data_buf.direct_data +=
269 sprintf(pm8001_ha->
270 forensic_info.data_buf.direct_data,
271 "%08x ", *(temp + index));
272 }
273 pm8001_ha->fatal_forensic_shift_offset += 0x100;
274 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
275 pm8001_ha->fatal_forensic_shift_offset);
276 pm8001_ha->fatal_bar_loc = 0;
277 status = 0;
278 offset = (int)
279 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
280 - (char *)buf);
281 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return3 0x%x\n",
282 offset);
283 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
284 (char *)buf;
285 }
286 if (pm8001_ha->forensic_fatal_step == 1) {
287 /* store previous accumulated length before triggering next
288 * accumulated length update
289 */
290 pm8001_ha->forensic_preserved_accumulated_transfer =
291 pm8001_mr32(fatal_table_address,
292 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
293
294 /* continue capturing the fatal log until Dump status is 0x3 */
295 if (pm8001_mr32(fatal_table_address,
296 MPI_FATAL_EDUMP_TABLE_STATUS) <
297 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
298
299 /* reset fddstat bit by writing to zero*/
300 pm8001_mw32(fatal_table_address,
301 MPI_FATAL_EDUMP_TABLE_STATUS, 0x0);
302
303 /* set dump control value to '1' so that new data will
304 * be transferred to shared memory
305 */
306 pm8001_mw32(fatal_table_address,
307 MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
308 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
309
310 /*Poll FDDHSHK until clear */
311 start = jiffies + (2 * HZ); /* 2 sec */
312
313 do {
314 reg_val = pm8001_mr32(fatal_table_address,
315 MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
316 } while ((reg_val) && time_before(jiffies, start));
317
318 if (reg_val != 0) {
319 pm8001_dbg(pm8001_ha, FAIL,
320 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n",
321 reg_val);
322 /* Fail the dump if a timeout occurs */
323 pm8001_ha->forensic_info.data_buf.direct_data +=
324 sprintf(
325 pm8001_ha->forensic_info.data_buf.direct_data,
326 "%08x ", 0xFFFFFFFF);
327 return((char *)
328 pm8001_ha->forensic_info.data_buf.direct_data
329 - (char *)buf);
330 }
331 /* Poll status register until set to 2 or
332 * 3 for up to 2 seconds
333 */
334 start = jiffies + (2 * HZ); /* 2 sec */
335
336 do {
337 reg_val = pm8001_mr32(fatal_table_address,
338 MPI_FATAL_EDUMP_TABLE_STATUS);
339 } while (((reg_val != 2) && (reg_val != 3)) &&
340 time_before(jiffies, start));
341
342 if (reg_val < 2) {
343 pm8001_dbg(pm8001_ha, FAIL,
344 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n",
345 reg_val);
346 /* Fail the dump if a timeout occurs */
347 pm8001_ha->forensic_info.data_buf.direct_data +=
348 sprintf(
349 pm8001_ha->forensic_info.data_buf.direct_data,
350 "%08x ", 0xFFFFFFFF);
351 return((char *)pm8001_ha->forensic_info.data_buf.direct_data -
352 (char *)buf);
353 }
354 /* reset fatal_forensic_shift_offset back to zero and reset MEMBASE 2 register to zero */
355 pm8001_ha->fatal_forensic_shift_offset = 0; /* location in 64k region */
356 pm8001_cw32(pm8001_ha, 0,
357 MEMBASE_II_SHIFT_REGISTER,
358 pm8001_ha->fatal_forensic_shift_offset);
359 }
360 /* Read the next block of the debug data.*/
361 length_to_read = pm8001_mr32(fatal_table_address,
362 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) -
363 pm8001_ha->forensic_preserved_accumulated_transfer;
364 if (length_to_read != 0x0) {
365 pm8001_ha->forensic_fatal_step = 0;
366 goto moreData;
367 } else {
368 pm8001_ha->forensic_info.data_buf.direct_data +=
369 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
370 "%08x ", 4);
371 pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
372 pm8001_ha->forensic_info.data_buf.direct_len = 0;
373 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
374 pm8001_ha->forensic_info.data_buf.read_len = 0;
375 }
376 }
377 offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data
378 - (char *)buf);
379 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset);
380 return ((char *)pm8001_ha->forensic_info.data_buf.direct_data -
381 (char *)buf);
382 }
383
384 /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma
385 * location by the firmware.
386 */
pm80xx_get_non_fatal_dump(struct device * cdev,struct device_attribute * attr,char * buf)387 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
388 struct device_attribute *attr, char *buf)
389 {
390 struct Scsi_Host *shost = class_to_shost(cdev);
391 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
392 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
393 void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr;
394 u32 accum_len = 0;
395 u32 total_len = 0;
396 u32 reg_val = 0;
397 u32 *temp = NULL;
398 u32 index = 0;
399 u32 output_length;
400 unsigned long start = 0;
401 char *buf_copy = buf;
402
403 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
404 if (++pm8001_ha->non_fatal_count == 1) {
405 if (pm8001_ha->chip_id == chip_8001) {
406 snprintf(pm8001_ha->forensic_info.data_buf.direct_data,
407 PAGE_SIZE, "Not supported for SPC controller");
408 return 0;
409 }
410 pm8001_dbg(pm8001_ha, IO, "forensic_info TYPE_NON_FATAL...\n");
411 /*
412 * Step 1: Write the host buffer parameters in the MPI Fatal and
413 * Non-Fatal Error Dump Capture Table.This is the buffer
414 * where debug data will be DMAed to.
415 */
416 pm8001_mw32(nonfatal_table_address,
417 MPI_FATAL_EDUMP_TABLE_LO_OFFSET,
418 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo);
419
420 pm8001_mw32(nonfatal_table_address,
421 MPI_FATAL_EDUMP_TABLE_HI_OFFSET,
422 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi);
423
424 pm8001_mw32(nonfatal_table_address,
425 MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET);
426
427 /* Optionally, set the DUMPCTRL bit to 1 if the host
428 * keeps sending active I/Os while capturing the non-fatal
429 * debug data. Otherwise, leave this bit set to zero
430 */
431 pm8001_mw32(nonfatal_table_address,
432 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY);
433
434 /*
435 * Step 2: Clear Accumulative Length of Debug Data Transferred
436 * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump
437 * Capture Table to zero.
438 */
439 pm8001_mw32(nonfatal_table_address,
440 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0);
441
442 /* initiallize previous accumulated length to 0 */
443 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
444 pm8001_ha->non_fatal_read_length = 0;
445 }
446
447 total_len = pm8001_mr32(nonfatal_table_address,
448 MPI_FATAL_EDUMP_TABLE_TOTAL_LEN);
449 /*
450 * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT]
451 * field and then request that the SPCv controller transfer the debug
452 * data by setting bit 7 of the Inbound Doorbell Set Register.
453 */
454 pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0);
455 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET,
456 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP);
457
458 /*
459 * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for
460 * 2 seconds) until register bit 7 is cleared.
461 * This step only indicates the request is accepted by the controller.
462 */
463 start = jiffies + (2 * HZ); /* 2 sec */
464 do {
465 reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) &
466 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP;
467 } while ((reg_val != 0) && time_before(jiffies, start));
468
469 /* Step 4.2: To check the completion of the transfer, poll the Fatal/Non
470 * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in
471 * the MPI Fatal and Non-Fatal Error Dump Capture Table.
472 */
473 start = jiffies + (2 * HZ); /* 2 sec */
474 do {
475 reg_val = pm8001_mr32(nonfatal_table_address,
476 MPI_FATAL_EDUMP_TABLE_STATUS);
477 } while ((!reg_val) && time_before(jiffies, start));
478
479 if ((reg_val == 0x00) ||
480 (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) ||
481 (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) {
482 pm8001_ha->non_fatal_read_length = 0;
483 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF);
484 pm8001_ha->non_fatal_count = 0;
485 return (buf_copy - buf);
486 } else if (reg_val ==
487 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) {
488 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2);
489 } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) ||
490 (pm8001_ha->non_fatal_read_length >= total_len)) {
491 pm8001_ha->non_fatal_read_length = 0;
492 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4);
493 pm8001_ha->non_fatal_count = 0;
494 }
495 accum_len = pm8001_mr32(nonfatal_table_address,
496 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
497 output_length = accum_len -
498 pm8001_ha->forensic_preserved_accumulated_transfer;
499
500 for (index = 0; index < output_length/4; index++)
501 buf_copy += snprintf(buf_copy, PAGE_SIZE,
502 "%08x ", *(temp+index));
503
504 pm8001_ha->non_fatal_read_length += output_length;
505
506 /* store current accumulated length to use in next iteration as
507 * the previous accumulated length
508 */
509 pm8001_ha->forensic_preserved_accumulated_transfer = accum_len;
510 return (buf_copy - buf);
511 }
512
513 /**
514 * read_main_config_table - read the configure table and save it.
515 * @pm8001_ha: our hba card information
516 */
read_main_config_table(struct pm8001_hba_info * pm8001_ha)517 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
518 {
519 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
520
521 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
522 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
523 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
524 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
525 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
526 pm8001_mr32(address, MAIN_FW_REVISION);
527 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
528 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
529 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
530 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
531 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
532 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
533 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
534 pm8001_mr32(address, MAIN_GST_OFFSET);
535 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
536 pm8001_mr32(address, MAIN_IBQ_OFFSET);
537 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
538 pm8001_mr32(address, MAIN_OBQ_OFFSET);
539
540 /* read Error Dump Offset and Length */
541 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
542 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
543 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
544 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
545 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
546 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
547 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
548 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
549
550 /* read GPIO LED settings from the configuration table */
551 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
552 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
553
554 /* read analog Setting offset from the configuration table */
555 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
556 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
557
558 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
559 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
560 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
561 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
562 /* read port recover and reset timeout */
563 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
564 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
565 /* read ILA and inactive firmware version */
566 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
567 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE);
568 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
569 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION);
570
571 pm8001_dbg(pm8001_ha, DEV,
572 "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n",
573 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature,
574 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev,
575 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev);
576
577 pm8001_dbg(pm8001_ha, DEV,
578 "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n",
579 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset,
580 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset,
581 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset,
582 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset,
583 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset);
584
585 pm8001_dbg(pm8001_ha, DEV,
586 "Main cfg table; ila rev:%x Inactive fw rev:%x\n",
587 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version,
588 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version);
589 }
590
591 /**
592 * read_general_status_table - read the general status table and save it.
593 * @pm8001_ha: our hba card information
594 */
read_general_status_table(struct pm8001_hba_info * pm8001_ha)595 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
596 {
597 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
598 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
599 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
600 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
601 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
602 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
603 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
604 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
605 pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
606 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
607 pm8001_mr32(address, GST_IOPTCNT_OFFSET);
608 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
609 pm8001_mr32(address, GST_GPIO_INPUT_VAL);
610 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
611 pm8001_mr32(address, GST_RERRINFO_OFFSET0);
612 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
613 pm8001_mr32(address, GST_RERRINFO_OFFSET1);
614 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
615 pm8001_mr32(address, GST_RERRINFO_OFFSET2);
616 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
617 pm8001_mr32(address, GST_RERRINFO_OFFSET3);
618 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
619 pm8001_mr32(address, GST_RERRINFO_OFFSET4);
620 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
621 pm8001_mr32(address, GST_RERRINFO_OFFSET5);
622 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
623 pm8001_mr32(address, GST_RERRINFO_OFFSET6);
624 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
625 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
626 }
627 /**
628 * read_phy_attr_table - read the phy attribute table and save it.
629 * @pm8001_ha: our hba card information
630 */
read_phy_attr_table(struct pm8001_hba_info * pm8001_ha)631 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
632 {
633 void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
634 pm8001_ha->phy_attr_table.phystart1_16[0] =
635 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
636 pm8001_ha->phy_attr_table.phystart1_16[1] =
637 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
638 pm8001_ha->phy_attr_table.phystart1_16[2] =
639 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
640 pm8001_ha->phy_attr_table.phystart1_16[3] =
641 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
642 pm8001_ha->phy_attr_table.phystart1_16[4] =
643 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
644 pm8001_ha->phy_attr_table.phystart1_16[5] =
645 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
646 pm8001_ha->phy_attr_table.phystart1_16[6] =
647 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
648 pm8001_ha->phy_attr_table.phystart1_16[7] =
649 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
650 pm8001_ha->phy_attr_table.phystart1_16[8] =
651 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
652 pm8001_ha->phy_attr_table.phystart1_16[9] =
653 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
654 pm8001_ha->phy_attr_table.phystart1_16[10] =
655 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
656 pm8001_ha->phy_attr_table.phystart1_16[11] =
657 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
658 pm8001_ha->phy_attr_table.phystart1_16[12] =
659 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
660 pm8001_ha->phy_attr_table.phystart1_16[13] =
661 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
662 pm8001_ha->phy_attr_table.phystart1_16[14] =
663 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
664 pm8001_ha->phy_attr_table.phystart1_16[15] =
665 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
666
667 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
668 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
669 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
670 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
671 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
672 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
673 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
674 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
675 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
676 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
677 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
678 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
679 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
680 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
681 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
682 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
683 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
684 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
685 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
686 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
687 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
688 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
689 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
690 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
691 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
692 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
693 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
694 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
695 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
696 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
697 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
698 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
699
700 }
701
702 /**
703 * read_inbnd_queue_table - read the inbound queue table and save it.
704 * @pm8001_ha: our hba card information
705 */
read_inbnd_queue_table(struct pm8001_hba_info * pm8001_ha)706 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
707 {
708 int i;
709 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
710 for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
711 u32 offset = i * 0x20;
712 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
713 get_pci_bar_index(pm8001_mr32(address,
714 (offset + IB_PIPCI_BAR)));
715 pm8001_ha->inbnd_q_tbl[i].pi_offset =
716 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
717 }
718 }
719
720 /**
721 * read_outbnd_queue_table - read the outbound queue table and save it.
722 * @pm8001_ha: our hba card information
723 */
read_outbnd_queue_table(struct pm8001_hba_info * pm8001_ha)724 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
725 {
726 int i;
727 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
728 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
729 u32 offset = i * 0x24;
730 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
731 get_pci_bar_index(pm8001_mr32(address,
732 (offset + OB_CIPCI_BAR)));
733 pm8001_ha->outbnd_q_tbl[i].ci_offset =
734 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
735 }
736 }
737
738 /**
739 * init_default_table_values - init the default table.
740 * @pm8001_ha: our hba card information
741 */
init_default_table_values(struct pm8001_hba_info * pm8001_ha)742 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
743 {
744 int i;
745 u32 offsetib, offsetob;
746 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
747 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
748 u32 ib_offset = pm8001_ha->ib_offset;
749 u32 ob_offset = pm8001_ha->ob_offset;
750 u32 ci_offset = pm8001_ha->ci_offset;
751 u32 pi_offset = pm8001_ha->pi_offset;
752
753 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
754 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
755 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
756 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
757 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
758 PM8001_EVENT_LOG_SIZE;
759 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
760 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
761 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
762 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
763 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
764 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
765 PM8001_EVENT_LOG_SIZE;
766 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
767 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
768
769 /* Enable higher IQs and OQs, 32 to 63, bit 16 */
770 if (pm8001_ha->max_q_num > 32)
771 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
772 1 << 16;
773 /* Disable end to end CRC checking */
774 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
775
776 for (i = 0; i < pm8001_ha->max_q_num; i++) {
777 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
778 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
779 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
780 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
781 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
782 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
783 pm8001_ha->inbnd_q_tbl[i].base_virt =
784 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
785 pm8001_ha->inbnd_q_tbl[i].total_length =
786 pm8001_ha->memoryMap.region[ib_offset + i].total_len;
787 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
788 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
789 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
790 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
791 pm8001_ha->inbnd_q_tbl[i].ci_virt =
792 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
793 pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0);
794 offsetib = i * 0x20;
795 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
796 get_pci_bar_index(pm8001_mr32(addressib,
797 (offsetib + 0x14)));
798 pm8001_ha->inbnd_q_tbl[i].pi_offset =
799 pm8001_mr32(addressib, (offsetib + 0x18));
800 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
801 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
802
803 pm8001_dbg(pm8001_ha, DEV,
804 "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i,
805 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar,
806 pm8001_ha->inbnd_q_tbl[i].pi_offset);
807 }
808 for (i = 0; i < pm8001_ha->max_q_num; i++) {
809 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
810 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
811 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
812 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
813 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
814 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
815 pm8001_ha->outbnd_q_tbl[i].base_virt =
816 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
817 pm8001_ha->outbnd_q_tbl[i].total_length =
818 pm8001_ha->memoryMap.region[ob_offset + i].total_len;
819 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
820 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
821 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
822 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
823 /* interrupt vector based on oq */
824 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
825 pm8001_ha->outbnd_q_tbl[i].pi_virt =
826 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
827 pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0);
828 offsetob = i * 0x24;
829 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
830 get_pci_bar_index(pm8001_mr32(addressob,
831 offsetob + 0x14));
832 pm8001_ha->outbnd_q_tbl[i].ci_offset =
833 pm8001_mr32(addressob, (offsetob + 0x18));
834 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
835 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
836
837 pm8001_dbg(pm8001_ha, DEV,
838 "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i,
839 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar,
840 pm8001_ha->outbnd_q_tbl[i].ci_offset);
841 }
842 }
843
844 /**
845 * update_main_config_table - update the main default table to the HBA.
846 * @pm8001_ha: our hba card information
847 */
update_main_config_table(struct pm8001_hba_info * pm8001_ha)848 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
849 {
850 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
851 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
852 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
853 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
854 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
855 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
856 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
857 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
858 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
859 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
860 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
861 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
862 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
863 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
864 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
865 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
866 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
867 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
868 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
869 /* Update Fatal error interrupt vector */
870 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
871 ((pm8001_ha->max_q_num - 1) << 8);
872 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
873 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
874 pm8001_dbg(pm8001_ha, DEV,
875 "Updated Fatal error interrupt vector 0x%x\n",
876 pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT));
877
878 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
879 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
880
881 /* SPCv specific */
882 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
883 /* Set GPIOLED to 0x2 for LED indicator */
884 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
885 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
886 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
887 pm8001_dbg(pm8001_ha, DEV,
888 "Programming DW 0x21 in main cfg table with 0x%x\n",
889 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET));
890
891 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
892 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
893 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
894 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
895
896 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
897 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
898 PORT_RECOVERY_TIMEOUT;
899 if (pm8001_ha->chip_id == chip_8006) {
900 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
901 0x0000ffff;
902 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
903 CHIP_8006_PORT_RECOVERY_TIMEOUT;
904 }
905 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
906 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
907 }
908
909 /**
910 * update_inbnd_queue_table - update the inbound queue table to the HBA.
911 * @pm8001_ha: our hba card information
912 * @number: entry in the queue
913 */
update_inbnd_queue_table(struct pm8001_hba_info * pm8001_ha,int number)914 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
915 int number)
916 {
917 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
918 u16 offset = number * 0x20;
919 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
920 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
921 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
922 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
923 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
924 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
925 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
926 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
927 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
928 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
929
930 pm8001_dbg(pm8001_ha, DEV,
931 "IQ %d: Element pri size 0x%x\n",
932 number,
933 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
934
935 pm8001_dbg(pm8001_ha, DEV,
936 "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n",
937 pm8001_ha->inbnd_q_tbl[number].upper_base_addr,
938 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
939
940 pm8001_dbg(pm8001_ha, DEV,
941 "CI upper base addr 0x%x CI lower base addr 0x%x\n",
942 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr,
943 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
944 }
945
946 /**
947 * update_outbnd_queue_table - update the outbound queue table to the HBA.
948 * @pm8001_ha: our hba card information
949 * @number: entry in the queue
950 */
update_outbnd_queue_table(struct pm8001_hba_info * pm8001_ha,int number)951 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
952 int number)
953 {
954 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
955 u16 offset = number * 0x24;
956 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
957 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
958 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
959 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
960 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
961 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
962 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
963 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
964 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
965 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
966 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
967 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
968
969 pm8001_dbg(pm8001_ha, DEV,
970 "OQ %d: Element pri size 0x%x\n",
971 number,
972 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
973
974 pm8001_dbg(pm8001_ha, DEV,
975 "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n",
976 pm8001_ha->outbnd_q_tbl[number].upper_base_addr,
977 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
978
979 pm8001_dbg(pm8001_ha, DEV,
980 "PI upper base addr 0x%x PI lower base addr 0x%x\n",
981 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr,
982 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
983 }
984
985 /**
986 * mpi_init_check - check firmware initialization status.
987 * @pm8001_ha: our hba card information
988 */
mpi_init_check(struct pm8001_hba_info * pm8001_ha)989 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
990 {
991 u32 max_wait_count;
992 u32 value;
993 u32 gst_len_mpistate;
994
995 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
996 table is updated */
997 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
998 /* wait until Inbound DoorBell Clear Register toggled */
999 if (IS_SPCV_12G(pm8001_ha->pdev)) {
1000 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
1001 } else {
1002 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
1003 }
1004 do {
1005 msleep(FW_READY_INTERVAL);
1006 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1007 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
1008 } while ((value != 0) && (--max_wait_count));
1009
1010 if (!max_wait_count) {
1011 /* additional check */
1012 pm8001_dbg(pm8001_ha, FAIL,
1013 "Inb doorbell clear not toggled[value:%x]\n",
1014 value);
1015 return -EBUSY;
1016 }
1017 /* check the MPI-State for initialization up to 100ms*/
1018 max_wait_count = 5;/* 100 msec */
1019 do {
1020 msleep(FW_READY_INTERVAL);
1021 gst_len_mpistate =
1022 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1023 GST_GSTLEN_MPIS_OFFSET);
1024 } while ((GST_MPI_STATE_INIT !=
1025 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
1026 if (!max_wait_count)
1027 return -EBUSY;
1028
1029 /* check MPI Initialization error */
1030 gst_len_mpistate = gst_len_mpistate >> 16;
1031 if (0x0000 != gst_len_mpistate)
1032 return -EBUSY;
1033
1034 /*
1035 * As per controller datasheet, after successful MPI
1036 * initialization minimum 500ms delay is required before
1037 * issuing commands.
1038 */
1039 msleep(500);
1040
1041 return 0;
1042 }
1043
1044 /**
1045 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
1046 * This function sleeps hence it must not be used in atomic context.
1047 * @pm8001_ha: our hba card information
1048 */
check_fw_ready(struct pm8001_hba_info * pm8001_ha)1049 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
1050 {
1051 u32 value;
1052 u32 max_wait_count;
1053 u32 max_wait_time;
1054 u32 expected_mask;
1055 int ret = 0;
1056
1057 /* reset / PCIe ready */
1058 max_wait_time = max_wait_count = 5; /* 100 milli sec */
1059 do {
1060 msleep(FW_READY_INTERVAL);
1061 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1062 } while ((value == 0xFFFFFFFF) && (--max_wait_count));
1063
1064 /* check ila, RAAE and iops status */
1065 if ((pm8001_ha->chip_id != chip_8008) &&
1066 (pm8001_ha->chip_id != chip_8009)) {
1067 max_wait_time = max_wait_count = 180; /* 3600 milli sec */
1068 expected_mask = SCRATCH_PAD_ILA_READY |
1069 SCRATCH_PAD_RAAE_READY |
1070 SCRATCH_PAD_IOP0_READY |
1071 SCRATCH_PAD_IOP1_READY;
1072 } else {
1073 max_wait_time = max_wait_count = 170; /* 3400 milli sec */
1074 expected_mask = SCRATCH_PAD_ILA_READY |
1075 SCRATCH_PAD_RAAE_READY |
1076 SCRATCH_PAD_IOP0_READY;
1077 }
1078 do {
1079 msleep(FW_READY_INTERVAL);
1080 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1081 } while (((value & expected_mask) !=
1082 expected_mask) && (--max_wait_count));
1083 if (!max_wait_count) {
1084 pm8001_dbg(pm8001_ha, INIT,
1085 "At least one FW component failed to load within %d millisec: Scratchpad1: 0x%x\n",
1086 max_wait_time * FW_READY_INTERVAL, value);
1087 ret = -1;
1088 } else {
1089 pm8001_dbg(pm8001_ha, MSG,
1090 "All FW components ready by %d ms\n",
1091 (max_wait_time - max_wait_count) * FW_READY_INTERVAL);
1092 }
1093 return ret;
1094 }
1095
init_pci_device_addresses(struct pm8001_hba_info * pm8001_ha)1096 static int init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
1097 {
1098 void __iomem *base_addr;
1099 u32 value;
1100 u32 offset;
1101 u32 pcibar;
1102 u32 pcilogic;
1103
1104 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1105
1106 /*
1107 * lower 26 bits of SCRATCHPAD0 register describes offset within the
1108 * PCIe BAR where the MPI configuration table is present
1109 */
1110 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
1111
1112 pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n",
1113 offset, value);
1114 /*
1115 * Upper 6 bits describe the offset within PCI config space where BAR
1116 * is located.
1117 */
1118 pcilogic = (value & 0xFC000000) >> 26;
1119 pcibar = get_pci_bar_index(pcilogic);
1120 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);
1121
1122 /*
1123 * Make sure the offset falls inside the ioremapped PCI BAR
1124 */
1125 if (offset > pm8001_ha->io_mem[pcibar].memsize) {
1126 pm8001_dbg(pm8001_ha, FAIL,
1127 "Main cfg tbl offset outside %u > %u\n",
1128 offset, pm8001_ha->io_mem[pcibar].memsize);
1129 return -EBUSY;
1130 }
1131 pm8001_ha->main_cfg_tbl_addr = base_addr =
1132 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
1133
1134 /*
1135 * Validate main configuration table address: first DWord should read
1136 * "PMCS"
1137 */
1138 value = pm8001_mr32(pm8001_ha->main_cfg_tbl_addr, 0);
1139 if (memcmp(&value, "PMCS", 4) != 0) {
1140 pm8001_dbg(pm8001_ha, FAIL,
1141 "BAD main config signature 0x%x\n",
1142 value);
1143 return -EBUSY;
1144 }
1145 pm8001_dbg(pm8001_ha, INIT,
1146 "VALID main config signature 0x%x\n", value);
1147 pm8001_ha->general_stat_tbl_addr =
1148 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
1149 0xFFFFFF);
1150 pm8001_ha->inbnd_q_tbl_addr =
1151 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
1152 0xFFFFFF);
1153 pm8001_ha->outbnd_q_tbl_addr =
1154 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
1155 0xFFFFFF);
1156 pm8001_ha->ivt_tbl_addr =
1157 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
1158 0xFFFFFF);
1159 pm8001_ha->pspa_q_tbl_addr =
1160 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
1161 0xFFFFFF);
1162 pm8001_ha->fatal_tbl_addr =
1163 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
1164 0xFFFFFF);
1165
1166 pm8001_dbg(pm8001_ha, INIT, "GST OFFSET 0x%x\n",
1167 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18));
1168 pm8001_dbg(pm8001_ha, INIT, "INBND OFFSET 0x%x\n",
1169 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C));
1170 pm8001_dbg(pm8001_ha, INIT, "OBND OFFSET 0x%x\n",
1171 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20));
1172 pm8001_dbg(pm8001_ha, INIT, "IVT OFFSET 0x%x\n",
1173 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C));
1174 pm8001_dbg(pm8001_ha, INIT, "PSPA OFFSET 0x%x\n",
1175 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90));
1176 pm8001_dbg(pm8001_ha, INIT, "addr - main cfg %p general status %p\n",
1177 pm8001_ha->main_cfg_tbl_addr,
1178 pm8001_ha->general_stat_tbl_addr);
1179 pm8001_dbg(pm8001_ha, INIT, "addr - inbnd %p obnd %p\n",
1180 pm8001_ha->inbnd_q_tbl_addr,
1181 pm8001_ha->outbnd_q_tbl_addr);
1182 pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n",
1183 pm8001_ha->pspa_q_tbl_addr,
1184 pm8001_ha->ivt_tbl_addr);
1185 return 0;
1186 }
1187
1188 /**
1189 * pm80xx_set_thermal_config - support the thermal configuration
1190 * @pm8001_ha: our hba card information.
1191 */
1192 int
pm80xx_set_thermal_config(struct pm8001_hba_info * pm8001_ha)1193 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
1194 {
1195 struct set_ctrl_cfg_req payload;
1196 int rc;
1197 u32 tag;
1198 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1199 u32 page_code;
1200
1201 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1202 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1203 if (rc)
1204 return rc;
1205
1206 payload.tag = cpu_to_le32(tag);
1207
1208 if (IS_SPCV_12G(pm8001_ha->pdev))
1209 page_code = THERMAL_PAGE_CODE_7H;
1210 else
1211 page_code = THERMAL_PAGE_CODE_8H;
1212
1213 payload.cfg_pg[0] =
1214 cpu_to_le32((THERMAL_LOG_ENABLE << 9) |
1215 (THERMAL_ENABLE << 8) | page_code);
1216 payload.cfg_pg[1] =
1217 cpu_to_le32((LTEMPHIL << 24) | (RTEMPHIL << 8));
1218
1219 pm8001_dbg(pm8001_ha, DEV,
1220 "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n",
1221 payload.cfg_pg[0], payload.cfg_pg[1]);
1222
1223 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
1224 sizeof(payload), 0);
1225 if (rc)
1226 pm8001_tag_free(pm8001_ha, tag);
1227 return rc;
1228
1229 }
1230
1231 /**
1232 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
1233 * Timer configuration page
1234 * @pm8001_ha: our hba card information.
1235 */
1236 static int
pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info * pm8001_ha)1237 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
1238 {
1239 struct set_ctrl_cfg_req payload;
1240 SASProtocolTimerConfig_t SASConfigPage;
1241 int rc;
1242 u32 tag;
1243 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1244
1245 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1246 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
1247
1248 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1249 if (rc)
1250 return rc;
1251
1252 payload.tag = cpu_to_le32(tag);
1253
1254 SASConfigPage.pageCode = cpu_to_le32(SAS_PROTOCOL_TIMER_CONFIG_PAGE);
1255 SASConfigPage.MST_MSI = cpu_to_le32(3 << 15);
1256 SASConfigPage.STP_SSP_MCT_TMO =
1257 cpu_to_le32((STP_MCT_TMO << 16) | SSP_MCT_TMO);
1258 SASConfigPage.STP_FRM_TMO =
1259 cpu_to_le32((SAS_MAX_OPEN_TIME << 24) |
1260 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER);
1261 SASConfigPage.STP_IDLE_TMO = cpu_to_le32(STP_IDLE_TIME);
1262
1263 SASConfigPage.OPNRJT_RTRY_INTVL =
1264 cpu_to_le32((SAS_MFD << 16) | SAS_OPNRJT_RTRY_INTVL);
1265 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO =
1266 cpu_to_le32((SAS_DOPNRJT_RTRY_TMO << 16) | SAS_COPNRJT_RTRY_TMO);
1267 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR =
1268 cpu_to_le32((SAS_DOPNRJT_RTRY_THR << 16) | SAS_COPNRJT_RTRY_THR);
1269 SASConfigPage.MAX_AIP = cpu_to_le32(SAS_MAX_AIP);
1270
1271 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.pageCode 0x%08x\n",
1272 le32_to_cpu(SASConfigPage.pageCode));
1273 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MST_MSI 0x%08x\n",
1274 le32_to_cpu(SASConfigPage.MST_MSI));
1275 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_SSP_MCT_TMO 0x%08x\n",
1276 le32_to_cpu(SASConfigPage.STP_SSP_MCT_TMO));
1277 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_FRM_TMO 0x%08x\n",
1278 le32_to_cpu(SASConfigPage.STP_FRM_TMO));
1279 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_IDLE_TMO 0x%08x\n",
1280 le32_to_cpu(SASConfigPage.STP_IDLE_TMO));
1281 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.OPNRJT_RTRY_INTVL 0x%08x\n",
1282 le32_to_cpu(SASConfigPage.OPNRJT_RTRY_INTVL));
1283 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO 0x%08x\n",
1284 le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
1285 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR 0x%08x\n",
1286 le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
1287 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MAX_AIP 0x%08x\n",
1288 le32_to_cpu(SASConfigPage.MAX_AIP));
1289
1290 memcpy(&payload.cfg_pg, &SASConfigPage,
1291 sizeof(SASProtocolTimerConfig_t));
1292
1293 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
1294 sizeof(payload), 0);
1295 if (rc)
1296 pm8001_tag_free(pm8001_ha, tag);
1297
1298 return rc;
1299 }
1300
1301 /**
1302 * pm80xx_get_encrypt_info - Check for encryption
1303 * @pm8001_ha: our hba card information.
1304 */
1305 static int
pm80xx_get_encrypt_info(struct pm8001_hba_info * pm8001_ha)1306 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
1307 {
1308 u32 scratch3_value;
1309 int ret = -1;
1310
1311 /* Read encryption status from SCRATCH PAD 3 */
1312 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1313
1314 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1315 SCRATCH_PAD3_ENC_READY) {
1316 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1317 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1318 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1319 SCRATCH_PAD3_SMF_ENABLED)
1320 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1321 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1322 SCRATCH_PAD3_SMA_ENABLED)
1323 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1324 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1325 SCRATCH_PAD3_SMB_ENABLED)
1326 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1327 pm8001_ha->encrypt_info.status = 0;
1328 pm8001_dbg(pm8001_ha, INIT,
1329 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X.Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
1330 scratch3_value,
1331 pm8001_ha->encrypt_info.cipher_mode,
1332 pm8001_ha->encrypt_info.sec_mode,
1333 pm8001_ha->encrypt_info.status);
1334 ret = 0;
1335 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
1336 SCRATCH_PAD3_ENC_DISABLED) {
1337 pm8001_dbg(pm8001_ha, INIT,
1338 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1339 scratch3_value);
1340 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1341 pm8001_ha->encrypt_info.cipher_mode = 0;
1342 pm8001_ha->encrypt_info.sec_mode = 0;
1343 ret = 0;
1344 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1345 SCRATCH_PAD3_ENC_DIS_ERR) {
1346 pm8001_ha->encrypt_info.status =
1347 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1348 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1349 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1350 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1351 SCRATCH_PAD3_SMF_ENABLED)
1352 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1353 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1354 SCRATCH_PAD3_SMA_ENABLED)
1355 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1356 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1357 SCRATCH_PAD3_SMB_ENABLED)
1358 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1359 pm8001_dbg(pm8001_ha, INIT,
1360 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1361 scratch3_value,
1362 pm8001_ha->encrypt_info.cipher_mode,
1363 pm8001_ha->encrypt_info.sec_mode,
1364 pm8001_ha->encrypt_info.status);
1365 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1366 SCRATCH_PAD3_ENC_ENA_ERR) {
1367
1368 pm8001_ha->encrypt_info.status =
1369 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1370 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1371 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1372 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1373 SCRATCH_PAD3_SMF_ENABLED)
1374 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1375 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1376 SCRATCH_PAD3_SMA_ENABLED)
1377 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1378 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1379 SCRATCH_PAD3_SMB_ENABLED)
1380 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1381
1382 pm8001_dbg(pm8001_ha, INIT,
1383 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1384 scratch3_value,
1385 pm8001_ha->encrypt_info.cipher_mode,
1386 pm8001_ha->encrypt_info.sec_mode,
1387 pm8001_ha->encrypt_info.status);
1388 }
1389 return ret;
1390 }
1391
1392 /**
1393 * pm80xx_encrypt_update - update flash with encryption information
1394 * @pm8001_ha: our hba card information.
1395 */
pm80xx_encrypt_update(struct pm8001_hba_info * pm8001_ha)1396 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1397 {
1398 struct kek_mgmt_req payload;
1399 int rc;
1400 u32 tag;
1401 u32 opc = OPC_INB_KEK_MANAGEMENT;
1402
1403 memset(&payload, 0, sizeof(struct kek_mgmt_req));
1404 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1405 if (rc)
1406 return rc;
1407
1408 payload.tag = cpu_to_le32(tag);
1409 /* Currently only one key is used. New KEK index is 1.
1410 * Current KEK index is 1. Store KEK to NVRAM is 1.
1411 */
1412 payload.new_curidx_ksop =
1413 cpu_to_le32(((1 << 24) | (1 << 16) | (1 << 8) |
1414 KEK_MGMT_SUBOP_KEYCARDUPDATE));
1415
1416 pm8001_dbg(pm8001_ha, DEV,
1417 "Saving Encryption info to flash. payload 0x%x\n",
1418 le32_to_cpu(payload.new_curidx_ksop));
1419
1420 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
1421 sizeof(payload), 0);
1422 if (rc)
1423 pm8001_tag_free(pm8001_ha, tag);
1424
1425 return rc;
1426 }
1427
1428 /**
1429 * pm80xx_chip_init - the main init function that initializes whole PM8001 chip.
1430 * @pm8001_ha: our hba card information
1431 */
pm80xx_chip_init(struct pm8001_hba_info * pm8001_ha)1432 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1433 {
1434 int ret;
1435 u8 i = 0;
1436
1437 /* check the firmware status */
1438 if (-1 == check_fw_ready(pm8001_ha)) {
1439 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
1440 return -EBUSY;
1441 }
1442
1443 /* Initialize the controller fatal error flag */
1444 pm8001_ha->controller_fatal_error = false;
1445
1446 /* Initialize pci space address eg: mpi offset */
1447 ret = init_pci_device_addresses(pm8001_ha);
1448 if (ret) {
1449 pm8001_dbg(pm8001_ha, FAIL,
1450 "Failed to init pci addresses");
1451 return ret;
1452 }
1453 init_default_table_values(pm8001_ha);
1454 read_main_config_table(pm8001_ha);
1455 read_general_status_table(pm8001_ha);
1456 read_inbnd_queue_table(pm8001_ha);
1457 read_outbnd_queue_table(pm8001_ha);
1458 read_phy_attr_table(pm8001_ha);
1459
1460 /* update main config table ,inbound table and outbound table */
1461 update_main_config_table(pm8001_ha);
1462 for (i = 0; i < pm8001_ha->max_q_num; i++) {
1463 update_inbnd_queue_table(pm8001_ha, i);
1464 update_outbnd_queue_table(pm8001_ha, i);
1465 }
1466 /* notify firmware update finished and check initialization status */
1467 if (0 == mpi_init_check(pm8001_ha)) {
1468 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n");
1469 } else
1470 return -EBUSY;
1471
1472 return 0;
1473 }
1474
pm80xx_chip_post_init(struct pm8001_hba_info * pm8001_ha)1475 static void pm80xx_chip_post_init(struct pm8001_hba_info *pm8001_ha)
1476 {
1477 /* send SAS protocol timer configuration page to FW */
1478 pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1479
1480 /* Check for encryption */
1481 if (pm8001_ha->chip->encrypt) {
1482 int ret;
1483
1484 pm8001_dbg(pm8001_ha, INIT, "Checking for encryption\n");
1485 ret = pm80xx_get_encrypt_info(pm8001_ha);
1486 if (ret == -1) {
1487 pm8001_dbg(pm8001_ha, INIT, "Encryption error !!\n");
1488 if (pm8001_ha->encrypt_info.status == 0x81) {
1489 pm8001_dbg(pm8001_ha, INIT,
1490 "Encryption enabled with error.Saving encryption key to flash\n");
1491 pm80xx_encrypt_update(pm8001_ha);
1492 }
1493 }
1494 }
1495 }
1496
mpi_uninit_check(struct pm8001_hba_info * pm8001_ha)1497 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1498 {
1499 u32 max_wait_count;
1500 u32 value;
1501 u32 gst_len_mpistate;
1502 int ret;
1503
1504 ret = init_pci_device_addresses(pm8001_ha);
1505 if (ret) {
1506 pm8001_dbg(pm8001_ha, FAIL,
1507 "Failed to init pci addresses");
1508 return ret;
1509 }
1510
1511 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1512 table is stop */
1513 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1514
1515 /* wait until Inbound DoorBell Clear Register toggled */
1516 if (IS_SPCV_12G(pm8001_ha->pdev)) {
1517 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
1518 } else {
1519 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
1520 }
1521 do {
1522 msleep(FW_READY_INTERVAL);
1523 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1524 value &= SPCv_MSGU_CFG_TABLE_RESET;
1525 } while ((value != 0) && (--max_wait_count));
1526
1527 if (!max_wait_count) {
1528 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=%x\n", value);
1529 return -1;
1530 }
1531
1532 /* check the MPI-State for termination in progress */
1533 /* wait until Inbound DoorBell Clear Register toggled */
1534 max_wait_count = 100; /* 2 sec for spcv/ve */
1535 do {
1536 msleep(FW_READY_INTERVAL);
1537 gst_len_mpistate =
1538 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1539 GST_GSTLEN_MPIS_OFFSET);
1540 if (GST_MPI_STATE_UNINIT ==
1541 (gst_len_mpistate & GST_MPI_STATE_MASK))
1542 break;
1543 } while (--max_wait_count);
1544 if (!max_wait_count) {
1545 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",
1546 gst_len_mpistate & GST_MPI_STATE_MASK);
1547 return -1;
1548 }
1549
1550 return 0;
1551 }
1552
1553 /**
1554 * pm80xx_fatal_errors - returns non-zero *ONLY* when fatal errors
1555 * @pm8001_ha: our hba card information
1556 *
1557 * Fatal errors are recoverable only after a host reboot.
1558 */
1559 int
pm80xx_fatal_errors(struct pm8001_hba_info * pm8001_ha)1560 pm80xx_fatal_errors(struct pm8001_hba_info *pm8001_ha)
1561 {
1562 int ret = 0;
1563 u32 scratch_pad_rsvd0 = pm8001_cr32(pm8001_ha, 0,
1564 MSGU_SCRATCH_PAD_RSVD_0);
1565 u32 scratch_pad_rsvd1 = pm8001_cr32(pm8001_ha, 0,
1566 MSGU_SCRATCH_PAD_RSVD_1);
1567 u32 scratch_pad1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1568 u32 scratch_pad2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1569 u32 scratch_pad3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1570
1571 if (pm8001_ha->chip_id != chip_8006 &&
1572 pm8001_ha->chip_id != chip_8074 &&
1573 pm8001_ha->chip_id != chip_8076) {
1574 return 0;
1575 }
1576
1577 if (MSGU_SCRATCHPAD1_STATE_FATAL_ERROR(scratch_pad1)) {
1578 pm8001_dbg(pm8001_ha, FAIL,
1579 "Fatal error SCRATCHPAD1 = 0x%x SCRATCHPAD2 = 0x%x SCRATCHPAD3 = 0x%x SCRATCHPAD_RSVD0 = 0x%x SCRATCHPAD_RSVD1 = 0x%x\n",
1580 scratch_pad1, scratch_pad2, scratch_pad3,
1581 scratch_pad_rsvd0, scratch_pad_rsvd1);
1582 ret = 1;
1583 }
1584
1585 return ret;
1586 }
1587
1588 /**
1589 * pm80xx_chip_soft_rst - soft reset the PM8001 chip, so that all
1590 * FW register status are reset to the originated status.
1591 * @pm8001_ha: our hba card information
1592 */
1593
1594 static int
pm80xx_chip_soft_rst(struct pm8001_hba_info * pm8001_ha)1595 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1596 {
1597 u32 regval;
1598 u32 bootloader_state;
1599 u32 ibutton0, ibutton1;
1600
1601 /* Process MPI table uninitialization only if FW is ready */
1602 if (!pm8001_ha->controller_fatal_error) {
1603 /* Check if MPI is in ready state to reset */
1604 if (mpi_uninit_check(pm8001_ha) != 0) {
1605 u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1606 u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1607 u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1608 u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1609 pm8001_dbg(pm8001_ha, FAIL,
1610 "MPI state is not ready scratch: %x:%x:%x:%x\n",
1611 r0, r1, r2, r3);
1612 /* if things aren't ready but the bootloader is ok then
1613 * try the reset anyway.
1614 */
1615 if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK)
1616 return -1;
1617 }
1618 }
1619 /* checked for reset register normal state; 0x0 */
1620 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1621 pm8001_dbg(pm8001_ha, INIT, "reset register before write : 0x%x\n",
1622 regval);
1623
1624 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1625 msleep(500);
1626
1627 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1628 pm8001_dbg(pm8001_ha, INIT, "reset register after write 0x%x\n",
1629 regval);
1630
1631 if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1632 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1633 pm8001_dbg(pm8001_ha, MSG,
1634 " soft reset successful [regval: 0x%x]\n",
1635 regval);
1636 } else {
1637 pm8001_dbg(pm8001_ha, MSG,
1638 " soft reset failed [regval: 0x%x]\n",
1639 regval);
1640
1641 /* check bootloader is successfully executed or in HDA mode */
1642 bootloader_state =
1643 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1644 SCRATCH_PAD1_BOOTSTATE_MASK;
1645
1646 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1647 pm8001_dbg(pm8001_ha, MSG,
1648 "Bootloader state - HDA mode SEEPROM\n");
1649 } else if (bootloader_state ==
1650 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1651 pm8001_dbg(pm8001_ha, MSG,
1652 "Bootloader state - HDA mode Bootstrap Pin\n");
1653 } else if (bootloader_state ==
1654 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1655 pm8001_dbg(pm8001_ha, MSG,
1656 "Bootloader state - HDA mode soft reset\n");
1657 } else if (bootloader_state ==
1658 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1659 pm8001_dbg(pm8001_ha, MSG,
1660 "Bootloader state-HDA mode critical error\n");
1661 }
1662 return -EBUSY;
1663 }
1664
1665 /* check the firmware status after reset */
1666 if (-1 == check_fw_ready(pm8001_ha)) {
1667 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
1668 /* check iButton feature support for motherboard controller */
1669 if (pm8001_ha->pdev->subsystem_vendor !=
1670 PCI_VENDOR_ID_ADAPTEC2 &&
1671 pm8001_ha->pdev->subsystem_vendor !=
1672 PCI_VENDOR_ID_ATTO &&
1673 pm8001_ha->pdev->subsystem_vendor != 0) {
1674 ibutton0 = pm8001_cr32(pm8001_ha, 0,
1675 MSGU_SCRATCH_PAD_RSVD_0);
1676 ibutton1 = pm8001_cr32(pm8001_ha, 0,
1677 MSGU_SCRATCH_PAD_RSVD_1);
1678 if (!ibutton0 && !ibutton1) {
1679 pm8001_dbg(pm8001_ha, FAIL,
1680 "iButton Feature is not Available!!!\n");
1681 return -EBUSY;
1682 }
1683 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1684 pm8001_dbg(pm8001_ha, FAIL,
1685 "CRC Check for iButton Feature Failed!!!\n");
1686 return -EBUSY;
1687 }
1688 }
1689 }
1690 pm8001_dbg(pm8001_ha, INIT, "SPCv soft reset Complete\n");
1691 return 0;
1692 }
1693
pm80xx_hw_chip_rst(struct pm8001_hba_info * pm8001_ha)1694 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1695 {
1696 u32 i;
1697
1698 pm8001_dbg(pm8001_ha, INIT, "chip reset start\n");
1699
1700 /* do SPCv chip reset. */
1701 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1702 pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n");
1703
1704 /* Check this ..whether delay is required or no */
1705 /* delay 10 usec */
1706 udelay(10);
1707
1708 /* wait for 20 msec until the firmware gets reloaded */
1709 i = 20;
1710 do {
1711 mdelay(1);
1712 } while ((--i) != 0);
1713
1714 pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
1715 }
1716
1717 /**
1718 * pm80xx_chip_intx_interrupt_enable - enable PM8001 chip interrupt
1719 * @pm8001_ha: our hba card information
1720 */
1721 static void
pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info * pm8001_ha)1722 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1723 {
1724 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1725 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1726 }
1727
1728 /**
1729 * pm80xx_chip_intx_interrupt_disable - disable PM8001 chip interrupt
1730 * @pm8001_ha: our hba card information
1731 */
1732 static void
pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info * pm8001_ha)1733 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1734 {
1735 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1736 }
1737
1738 /**
1739 * pm80xx_chip_interrupt_enable - enable PM8001 chip interrupt
1740 * @pm8001_ha: our hba card information
1741 * @vec: interrupt number to enable
1742 */
1743 static void
pm80xx_chip_interrupt_enable(struct pm8001_hba_info * pm8001_ha,u8 vec)1744 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1745 {
1746 #ifdef PM8001_USE_MSIX
1747 if (vec < 32)
1748 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec);
1749 else
1750 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U,
1751 1U << (vec - 32));
1752 return;
1753 #endif
1754 pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1755
1756 }
1757
1758 /**
1759 * pm80xx_chip_interrupt_disable - disable PM8001 chip interrupt
1760 * @pm8001_ha: our hba card information
1761 * @vec: interrupt number to disable
1762 */
1763 static void
pm80xx_chip_interrupt_disable(struct pm8001_hba_info * pm8001_ha,u8 vec)1764 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1765 {
1766 #ifdef PM8001_USE_MSIX
1767 if (vec == 0xFF) {
1768 /* disable all vectors 0-31, 32-63 */
1769 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF);
1770 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF);
1771 } else if (vec < 32)
1772 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec);
1773 else
1774 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U,
1775 1U << (vec - 32));
1776 return;
1777 #endif
1778 pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1779 }
1780
1781 /**
1782 * mpi_ssp_completion - process the event that FW response to the SSP request.
1783 * @pm8001_ha: our hba card information
1784 * @piomb: the message contents of this outbound message.
1785 *
1786 * When FW has completed a ssp request for example a IO request, after it has
1787 * filled the SG data with the data, it will trigger this event representing
1788 * that he has finished the job; please check the corresponding buffer.
1789 * So we will tell the caller who maybe waiting the result to tell upper layer
1790 * that the task has been finished.
1791 */
1792 static void
mpi_ssp_completion(struct pm8001_hba_info * pm8001_ha,void * piomb)1793 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1794 {
1795 struct sas_task *t;
1796 struct pm8001_ccb_info *ccb;
1797 unsigned long flags;
1798 u32 status;
1799 u32 param;
1800 u32 tag;
1801 struct ssp_completion_resp *psspPayload;
1802 struct task_status_struct *ts;
1803 struct ssp_response_iu *iu;
1804 struct pm8001_device *pm8001_dev;
1805 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1806 status = le32_to_cpu(psspPayload->status);
1807 tag = le32_to_cpu(psspPayload->tag);
1808 ccb = &pm8001_ha->ccb_info[tag];
1809 if ((status == IO_ABORTED) && ccb->open_retry) {
1810 /* Being completed by another */
1811 ccb->open_retry = 0;
1812 return;
1813 }
1814 pm8001_dev = ccb->device;
1815 param = le32_to_cpu(psspPayload->param);
1816 t = ccb->task;
1817
1818 if (status && status != IO_UNDERFLOW)
1819 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);
1820 if (unlikely(!t || !t->lldd_task || !t->dev))
1821 return;
1822 ts = &t->task_status;
1823
1824 pm8001_dbg(pm8001_ha, DEV,
1825 "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t);
1826
1827 /* Print sas address of IO failed device */
1828 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1829 (status != IO_UNDERFLOW))
1830 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n",
1831 SAS_ADDR(t->dev->sas_addr));
1832
1833 switch (status) {
1834 case IO_SUCCESS:
1835 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS ,param = 0x%x\n",
1836 param);
1837 if (param == 0) {
1838 ts->resp = SAS_TASK_COMPLETE;
1839 ts->stat = SAS_SAM_STAT_GOOD;
1840 } else {
1841 ts->resp = SAS_TASK_COMPLETE;
1842 ts->stat = SAS_PROTO_RESPONSE;
1843 ts->residual = param;
1844 iu = &psspPayload->ssp_resp_iu;
1845 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1846 }
1847 if (pm8001_dev)
1848 atomic_dec(&pm8001_dev->running_req);
1849 break;
1850 case IO_ABORTED:
1851 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
1852 ts->resp = SAS_TASK_COMPLETE;
1853 ts->stat = SAS_ABORTED_TASK;
1854 if (pm8001_dev)
1855 atomic_dec(&pm8001_dev->running_req);
1856 break;
1857 case IO_UNDERFLOW:
1858 /* SSP Completion with error */
1859 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW ,param = 0x%x\n",
1860 param);
1861 ts->resp = SAS_TASK_COMPLETE;
1862 ts->stat = SAS_DATA_UNDERRUN;
1863 ts->residual = param;
1864 if (pm8001_dev)
1865 atomic_dec(&pm8001_dev->running_req);
1866 break;
1867 case IO_NO_DEVICE:
1868 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
1869 ts->resp = SAS_TASK_UNDELIVERED;
1870 ts->stat = SAS_PHY_DOWN;
1871 if (pm8001_dev)
1872 atomic_dec(&pm8001_dev->running_req);
1873 break;
1874 case IO_XFER_ERROR_BREAK:
1875 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
1876 ts->resp = SAS_TASK_COMPLETE;
1877 ts->stat = SAS_OPEN_REJECT;
1878 /* Force the midlayer to retry */
1879 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1880 if (pm8001_dev)
1881 atomic_dec(&pm8001_dev->running_req);
1882 break;
1883 case IO_XFER_ERROR_PHY_NOT_READY:
1884 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
1885 ts->resp = SAS_TASK_COMPLETE;
1886 ts->stat = SAS_OPEN_REJECT;
1887 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1888 if (pm8001_dev)
1889 atomic_dec(&pm8001_dev->running_req);
1890 break;
1891 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
1892 pm8001_dbg(pm8001_ha, IO,
1893 "IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n");
1894 ts->resp = SAS_TASK_COMPLETE;
1895 ts->stat = SAS_OPEN_REJECT;
1896 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1897 if (pm8001_dev)
1898 atomic_dec(&pm8001_dev->running_req);
1899 break;
1900 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1901 pm8001_dbg(pm8001_ha, IO,
1902 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
1903 ts->resp = SAS_TASK_COMPLETE;
1904 ts->stat = SAS_OPEN_REJECT;
1905 ts->open_rej_reason = SAS_OREJ_EPROTO;
1906 if (pm8001_dev)
1907 atomic_dec(&pm8001_dev->running_req);
1908 break;
1909 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1910 pm8001_dbg(pm8001_ha, IO,
1911 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
1912 ts->resp = SAS_TASK_COMPLETE;
1913 ts->stat = SAS_OPEN_REJECT;
1914 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1915 if (pm8001_dev)
1916 atomic_dec(&pm8001_dev->running_req);
1917 break;
1918 case IO_OPEN_CNX_ERROR_BREAK:
1919 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
1920 ts->resp = SAS_TASK_COMPLETE;
1921 ts->stat = SAS_OPEN_REJECT;
1922 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1923 if (pm8001_dev)
1924 atomic_dec(&pm8001_dev->running_req);
1925 break;
1926 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1927 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1928 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1929 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1930 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1931 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1932 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
1933 ts->resp = SAS_TASK_COMPLETE;
1934 ts->stat = SAS_OPEN_REJECT;
1935 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1936 if (!t->uldd_task)
1937 pm8001_handle_event(pm8001_ha,
1938 pm8001_dev,
1939 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1940 break;
1941 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1942 pm8001_dbg(pm8001_ha, IO,
1943 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
1944 ts->resp = SAS_TASK_COMPLETE;
1945 ts->stat = SAS_OPEN_REJECT;
1946 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1947 if (pm8001_dev)
1948 atomic_dec(&pm8001_dev->running_req);
1949 break;
1950 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1951 pm8001_dbg(pm8001_ha, IO,
1952 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
1953 ts->resp = SAS_TASK_COMPLETE;
1954 ts->stat = SAS_OPEN_REJECT;
1955 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1956 if (pm8001_dev)
1957 atomic_dec(&pm8001_dev->running_req);
1958 break;
1959 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1960 pm8001_dbg(pm8001_ha, IO,
1961 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
1962 ts->resp = SAS_TASK_UNDELIVERED;
1963 ts->stat = SAS_OPEN_REJECT;
1964 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1965 if (pm8001_dev)
1966 atomic_dec(&pm8001_dev->running_req);
1967 break;
1968 case IO_XFER_ERROR_NAK_RECEIVED:
1969 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
1970 ts->resp = SAS_TASK_COMPLETE;
1971 ts->stat = SAS_OPEN_REJECT;
1972 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1973 if (pm8001_dev)
1974 atomic_dec(&pm8001_dev->running_req);
1975 break;
1976 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1977 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
1978 ts->resp = SAS_TASK_COMPLETE;
1979 ts->stat = SAS_NAK_R_ERR;
1980 if (pm8001_dev)
1981 atomic_dec(&pm8001_dev->running_req);
1982 break;
1983 case IO_XFER_ERROR_DMA:
1984 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
1985 ts->resp = SAS_TASK_COMPLETE;
1986 ts->stat = SAS_OPEN_REJECT;
1987 if (pm8001_dev)
1988 atomic_dec(&pm8001_dev->running_req);
1989 break;
1990 case IO_XFER_OPEN_RETRY_TIMEOUT:
1991 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
1992 ts->resp = SAS_TASK_COMPLETE;
1993 ts->stat = SAS_OPEN_REJECT;
1994 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1995 if (pm8001_dev)
1996 atomic_dec(&pm8001_dev->running_req);
1997 break;
1998 case IO_XFER_ERROR_OFFSET_MISMATCH:
1999 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2000 ts->resp = SAS_TASK_COMPLETE;
2001 ts->stat = SAS_OPEN_REJECT;
2002 if (pm8001_dev)
2003 atomic_dec(&pm8001_dev->running_req);
2004 break;
2005 case IO_PORT_IN_RESET:
2006 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2007 ts->resp = SAS_TASK_COMPLETE;
2008 ts->stat = SAS_OPEN_REJECT;
2009 if (pm8001_dev)
2010 atomic_dec(&pm8001_dev->running_req);
2011 break;
2012 case IO_DS_NON_OPERATIONAL:
2013 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2014 ts->resp = SAS_TASK_COMPLETE;
2015 ts->stat = SAS_OPEN_REJECT;
2016 if (!t->uldd_task)
2017 pm8001_handle_event(pm8001_ha,
2018 pm8001_dev,
2019 IO_DS_NON_OPERATIONAL);
2020 break;
2021 case IO_DS_IN_RECOVERY:
2022 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2023 ts->resp = SAS_TASK_COMPLETE;
2024 ts->stat = SAS_OPEN_REJECT;
2025 if (pm8001_dev)
2026 atomic_dec(&pm8001_dev->running_req);
2027 break;
2028 case IO_TM_TAG_NOT_FOUND:
2029 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n");
2030 ts->resp = SAS_TASK_COMPLETE;
2031 ts->stat = SAS_OPEN_REJECT;
2032 if (pm8001_dev)
2033 atomic_dec(&pm8001_dev->running_req);
2034 break;
2035 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2036 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n");
2037 ts->resp = SAS_TASK_COMPLETE;
2038 ts->stat = SAS_OPEN_REJECT;
2039 if (pm8001_dev)
2040 atomic_dec(&pm8001_dev->running_req);
2041 break;
2042 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2043 pm8001_dbg(pm8001_ha, IO,
2044 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2045 ts->resp = SAS_TASK_COMPLETE;
2046 ts->stat = SAS_OPEN_REJECT;
2047 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2048 if (pm8001_dev)
2049 atomic_dec(&pm8001_dev->running_req);
2050 break;
2051 default:
2052 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2053 /* not allowed case. Therefore, return failed status */
2054 ts->resp = SAS_TASK_COMPLETE;
2055 ts->stat = SAS_OPEN_REJECT;
2056 if (pm8001_dev)
2057 atomic_dec(&pm8001_dev->running_req);
2058 break;
2059 }
2060 pm8001_dbg(pm8001_ha, IO, "scsi_status = 0x%x\n ",
2061 psspPayload->ssp_resp_iu.status);
2062 spin_lock_irqsave(&t->task_state_lock, flags);
2063 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2064 t->task_state_flags |= SAS_TASK_STATE_DONE;
2065 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2066 spin_unlock_irqrestore(&t->task_state_lock, flags);
2067 pm8001_dbg(pm8001_ha, FAIL,
2068 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2069 t, status, ts->resp, ts->stat);
2070 pm8001_ccb_task_free(pm8001_ha, ccb);
2071 if (t->slow_task)
2072 complete(&t->slow_task->completion);
2073 } else {
2074 spin_unlock_irqrestore(&t->task_state_lock, flags);
2075 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2076 }
2077 }
2078
2079 /*See the comments for mpi_ssp_completion */
mpi_ssp_event(struct pm8001_hba_info * pm8001_ha,void * piomb)2080 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2081 {
2082 struct sas_task *t;
2083 unsigned long flags;
2084 struct task_status_struct *ts;
2085 struct pm8001_ccb_info *ccb;
2086 struct pm8001_device *pm8001_dev;
2087 struct ssp_event_resp *psspPayload =
2088 (struct ssp_event_resp *)(piomb + 4);
2089 u32 event = le32_to_cpu(psspPayload->event);
2090 u32 tag = le32_to_cpu(psspPayload->tag);
2091 u32 port_id = le32_to_cpu(psspPayload->port_id);
2092
2093 ccb = &pm8001_ha->ccb_info[tag];
2094 t = ccb->task;
2095 pm8001_dev = ccb->device;
2096 if (event)
2097 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);
2098 if (unlikely(!t || !t->lldd_task || !t->dev))
2099 return;
2100 ts = &t->task_status;
2101 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
2102 port_id, tag, event);
2103 switch (event) {
2104 case IO_OVERFLOW:
2105 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2106 ts->resp = SAS_TASK_COMPLETE;
2107 ts->stat = SAS_DATA_OVERRUN;
2108 ts->residual = 0;
2109 if (pm8001_dev)
2110 atomic_dec(&pm8001_dev->running_req);
2111 break;
2112 case IO_XFER_ERROR_BREAK:
2113 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2114 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2115 return;
2116 case IO_XFER_ERROR_PHY_NOT_READY:
2117 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2118 ts->resp = SAS_TASK_COMPLETE;
2119 ts->stat = SAS_OPEN_REJECT;
2120 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2121 break;
2122 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2123 pm8001_dbg(pm8001_ha, IO,
2124 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2125 ts->resp = SAS_TASK_COMPLETE;
2126 ts->stat = SAS_OPEN_REJECT;
2127 ts->open_rej_reason = SAS_OREJ_EPROTO;
2128 break;
2129 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2130 pm8001_dbg(pm8001_ha, IO,
2131 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2132 ts->resp = SAS_TASK_COMPLETE;
2133 ts->stat = SAS_OPEN_REJECT;
2134 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2135 break;
2136 case IO_OPEN_CNX_ERROR_BREAK:
2137 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2138 ts->resp = SAS_TASK_COMPLETE;
2139 ts->stat = SAS_OPEN_REJECT;
2140 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2141 break;
2142 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2143 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2144 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2145 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2146 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2147 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2148 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2149 ts->resp = SAS_TASK_COMPLETE;
2150 ts->stat = SAS_OPEN_REJECT;
2151 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2152 if (!t->uldd_task)
2153 pm8001_handle_event(pm8001_ha,
2154 pm8001_dev,
2155 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2156 break;
2157 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2158 pm8001_dbg(pm8001_ha, IO,
2159 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2160 ts->resp = SAS_TASK_COMPLETE;
2161 ts->stat = SAS_OPEN_REJECT;
2162 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2163 break;
2164 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2165 pm8001_dbg(pm8001_ha, IO,
2166 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2167 ts->resp = SAS_TASK_COMPLETE;
2168 ts->stat = SAS_OPEN_REJECT;
2169 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2170 break;
2171 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2172 pm8001_dbg(pm8001_ha, IO,
2173 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2174 ts->resp = SAS_TASK_COMPLETE;
2175 ts->stat = SAS_OPEN_REJECT;
2176 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2177 break;
2178 case IO_XFER_ERROR_NAK_RECEIVED:
2179 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2180 ts->resp = SAS_TASK_COMPLETE;
2181 ts->stat = SAS_OPEN_REJECT;
2182 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2183 break;
2184 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2185 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2186 ts->resp = SAS_TASK_COMPLETE;
2187 ts->stat = SAS_NAK_R_ERR;
2188 break;
2189 case IO_XFER_OPEN_RETRY_TIMEOUT:
2190 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2191 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2192 return;
2193 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2194 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2195 ts->resp = SAS_TASK_COMPLETE;
2196 ts->stat = SAS_DATA_OVERRUN;
2197 break;
2198 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2199 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2200 ts->resp = SAS_TASK_COMPLETE;
2201 ts->stat = SAS_DATA_OVERRUN;
2202 break;
2203 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2204 pm8001_dbg(pm8001_ha, IO,
2205 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2206 ts->resp = SAS_TASK_COMPLETE;
2207 ts->stat = SAS_DATA_OVERRUN;
2208 break;
2209 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2210 pm8001_dbg(pm8001_ha, IO,
2211 "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n");
2212 ts->resp = SAS_TASK_COMPLETE;
2213 ts->stat = SAS_DATA_OVERRUN;
2214 break;
2215 case IO_XFER_ERROR_OFFSET_MISMATCH:
2216 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2217 ts->resp = SAS_TASK_COMPLETE;
2218 ts->stat = SAS_DATA_OVERRUN;
2219 break;
2220 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2221 pm8001_dbg(pm8001_ha, IO,
2222 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2223 ts->resp = SAS_TASK_COMPLETE;
2224 ts->stat = SAS_DATA_OVERRUN;
2225 break;
2226 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2227 pm8001_dbg(pm8001_ha, IOERR,
2228 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
2229 /* TBC: used default set values */
2230 ts->resp = SAS_TASK_COMPLETE;
2231 ts->stat = SAS_DATA_OVERRUN;
2232 break;
2233 case IO_XFER_CMD_FRAME_ISSUED:
2234 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2235 return;
2236 default:
2237 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2238 /* not allowed case. Therefore, return failed status */
2239 ts->resp = SAS_TASK_COMPLETE;
2240 ts->stat = SAS_DATA_OVERRUN;
2241 break;
2242 }
2243 spin_lock_irqsave(&t->task_state_lock, flags);
2244 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2245 t->task_state_flags |= SAS_TASK_STATE_DONE;
2246 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2247 spin_unlock_irqrestore(&t->task_state_lock, flags);
2248 pm8001_dbg(pm8001_ha, FAIL,
2249 "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2250 t, event, ts->resp, ts->stat);
2251 pm8001_ccb_task_free(pm8001_ha, ccb);
2252 } else {
2253 spin_unlock_irqrestore(&t->task_state_lock, flags);
2254 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2255 }
2256 }
2257
2258 /*See the comments for mpi_ssp_completion */
2259 static void
mpi_sata_completion(struct pm8001_hba_info * pm8001_ha,struct outbound_queue_table * circularQ,void * piomb)2260 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha,
2261 struct outbound_queue_table *circularQ, void *piomb)
2262 {
2263 struct sas_task *t;
2264 struct pm8001_ccb_info *ccb;
2265 u32 param;
2266 u32 status;
2267 u32 tag;
2268 int i, j;
2269 u8 sata_addr_low[4];
2270 u32 temp_sata_addr_low, temp_sata_addr_hi;
2271 u8 sata_addr_hi[4];
2272 struct sata_completion_resp *psataPayload;
2273 struct task_status_struct *ts;
2274 struct ata_task_resp *resp ;
2275 u32 *sata_resp;
2276 struct pm8001_device *pm8001_dev;
2277 unsigned long flags;
2278
2279 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2280 status = le32_to_cpu(psataPayload->status);
2281 param = le32_to_cpu(psataPayload->param);
2282 tag = le32_to_cpu(psataPayload->tag);
2283
2284 ccb = &pm8001_ha->ccb_info[tag];
2285 t = ccb->task;
2286 pm8001_dev = ccb->device;
2287
2288 if (t) {
2289 if (t->dev && (t->dev->lldd_dev))
2290 pm8001_dev = t->dev->lldd_dev;
2291 } else {
2292 pm8001_dbg(pm8001_ha, FAIL, "task null, freeing CCB tag %d\n",
2293 ccb->ccb_tag);
2294 pm8001_ccb_free(pm8001_ha, ccb);
2295 return;
2296 }
2297
2298
2299 if (pm8001_dev && unlikely(!t->lldd_task || !t->dev))
2300 return;
2301
2302 ts = &t->task_status;
2303
2304 if (status != IO_SUCCESS) {
2305 pm8001_dbg(pm8001_ha, FAIL,
2306 "IO failed device_id %u status 0x%x tag %d\n",
2307 pm8001_dev->device_id, status, tag);
2308 }
2309
2310 /* Print sas address of IO failed device */
2311 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2312 (status != IO_UNDERFLOW)) {
2313 if (!((t->dev->parent) &&
2314 (dev_is_expander(t->dev->parent->dev_type)))) {
2315 for (i = 0, j = 4; i <= 3 && j <= 7; i++, j++)
2316 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2317 for (i = 0, j = 0; i <= 3 && j <= 3; i++, j++)
2318 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2319 memcpy(&temp_sata_addr_low, sata_addr_low,
2320 sizeof(sata_addr_low));
2321 memcpy(&temp_sata_addr_hi, sata_addr_hi,
2322 sizeof(sata_addr_hi));
2323 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2324 |((temp_sata_addr_hi << 8) &
2325 0xff0000) |
2326 ((temp_sata_addr_hi >> 8)
2327 & 0xff00) |
2328 ((temp_sata_addr_hi << 24) &
2329 0xff000000));
2330 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2331 & 0xff) |
2332 ((temp_sata_addr_low << 8)
2333 & 0xff0000) |
2334 ((temp_sata_addr_low >> 8)
2335 & 0xff00) |
2336 ((temp_sata_addr_low << 24)
2337 & 0xff000000)) +
2338 pm8001_dev->attached_phy +
2339 0x10);
2340 pm8001_dbg(pm8001_ha, FAIL,
2341 "SAS Address of IO Failure Drive:%08x%08x\n",
2342 temp_sata_addr_hi,
2343 temp_sata_addr_low);
2344
2345 } else {
2346 pm8001_dbg(pm8001_ha, FAIL,
2347 "SAS Address of IO Failure Drive:%016llx\n",
2348 SAS_ADDR(t->dev->sas_addr));
2349 }
2350 }
2351 switch (status) {
2352 case IO_SUCCESS:
2353 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2354 if (param == 0) {
2355 ts->resp = SAS_TASK_COMPLETE;
2356 ts->stat = SAS_SAM_STAT_GOOD;
2357 } else {
2358 u8 len;
2359 ts->resp = SAS_TASK_COMPLETE;
2360 ts->stat = SAS_PROTO_RESPONSE;
2361 ts->residual = param;
2362 pm8001_dbg(pm8001_ha, IO,
2363 "SAS_PROTO_RESPONSE len = %d\n",
2364 param);
2365 sata_resp = &psataPayload->sata_resp[0];
2366 resp = (struct ata_task_resp *)ts->buf;
2367 if (t->ata_task.dma_xfer == 0 &&
2368 t->data_dir == DMA_FROM_DEVICE) {
2369 len = sizeof(struct pio_setup_fis);
2370 pm8001_dbg(pm8001_ha, IO,
2371 "PIO read len = %d\n", len);
2372 } else if (t->ata_task.use_ncq &&
2373 t->data_dir != DMA_NONE) {
2374 len = sizeof(struct set_dev_bits_fis);
2375 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n",
2376 len);
2377 } else {
2378 len = sizeof(struct dev_to_host_fis);
2379 pm8001_dbg(pm8001_ha, IO, "other len = %d\n",
2380 len);
2381 }
2382 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2383 resp->frame_len = len;
2384 memcpy(&resp->ending_fis[0], sata_resp, len);
2385 ts->buf_valid_size = sizeof(*resp);
2386 } else
2387 pm8001_dbg(pm8001_ha, IO,
2388 "response too large\n");
2389 }
2390 if (pm8001_dev)
2391 atomic_dec(&pm8001_dev->running_req);
2392 break;
2393 case IO_ABORTED:
2394 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
2395 ts->resp = SAS_TASK_COMPLETE;
2396 ts->stat = SAS_ABORTED_TASK;
2397 if (pm8001_dev)
2398 atomic_dec(&pm8001_dev->running_req);
2399 break;
2400 /* following cases are to do cases */
2401 case IO_UNDERFLOW:
2402 /* SATA Completion with error */
2403 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param);
2404 ts->resp = SAS_TASK_COMPLETE;
2405 ts->stat = SAS_DATA_UNDERRUN;
2406 ts->residual = param;
2407 if (pm8001_dev)
2408 atomic_dec(&pm8001_dev->running_req);
2409 break;
2410 case IO_NO_DEVICE:
2411 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2412 ts->resp = SAS_TASK_UNDELIVERED;
2413 ts->stat = SAS_PHY_DOWN;
2414 if (pm8001_dev)
2415 atomic_dec(&pm8001_dev->running_req);
2416 break;
2417 case IO_XFER_ERROR_BREAK:
2418 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2419 ts->resp = SAS_TASK_COMPLETE;
2420 ts->stat = SAS_INTERRUPTED;
2421 if (pm8001_dev)
2422 atomic_dec(&pm8001_dev->running_req);
2423 break;
2424 case IO_XFER_ERROR_PHY_NOT_READY:
2425 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2426 ts->resp = SAS_TASK_COMPLETE;
2427 ts->stat = SAS_OPEN_REJECT;
2428 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2429 if (pm8001_dev)
2430 atomic_dec(&pm8001_dev->running_req);
2431 break;
2432 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2433 pm8001_dbg(pm8001_ha, IO,
2434 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2435 ts->resp = SAS_TASK_COMPLETE;
2436 ts->stat = SAS_OPEN_REJECT;
2437 ts->open_rej_reason = SAS_OREJ_EPROTO;
2438 if (pm8001_dev)
2439 atomic_dec(&pm8001_dev->running_req);
2440 break;
2441 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2442 pm8001_dbg(pm8001_ha, IO,
2443 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2444 ts->resp = SAS_TASK_COMPLETE;
2445 ts->stat = SAS_OPEN_REJECT;
2446 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2447 if (pm8001_dev)
2448 atomic_dec(&pm8001_dev->running_req);
2449 break;
2450 case IO_OPEN_CNX_ERROR_BREAK:
2451 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2452 ts->resp = SAS_TASK_COMPLETE;
2453 ts->stat = SAS_OPEN_REJECT;
2454 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2455 if (pm8001_dev)
2456 atomic_dec(&pm8001_dev->running_req);
2457 break;
2458 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2459 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2460 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2461 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2462 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2463 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2464 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2465 ts->resp = SAS_TASK_COMPLETE;
2466 ts->stat = SAS_DEV_NO_RESPONSE;
2467 if (!t->uldd_task) {
2468 pm8001_handle_event(pm8001_ha,
2469 pm8001_dev,
2470 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2471 ts->resp = SAS_TASK_UNDELIVERED;
2472 ts->stat = SAS_QUEUE_FULL;
2473 spin_unlock_irqrestore(&circularQ->oq_lock,
2474 circularQ->lock_flags);
2475 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2476 spin_lock_irqsave(&circularQ->oq_lock,
2477 circularQ->lock_flags);
2478 return;
2479 }
2480 break;
2481 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2482 pm8001_dbg(pm8001_ha, IO,
2483 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2484 ts->resp = SAS_TASK_UNDELIVERED;
2485 ts->stat = SAS_OPEN_REJECT;
2486 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2487 if (!t->uldd_task) {
2488 pm8001_handle_event(pm8001_ha,
2489 pm8001_dev,
2490 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2491 ts->resp = SAS_TASK_UNDELIVERED;
2492 ts->stat = SAS_QUEUE_FULL;
2493 spin_unlock_irqrestore(&circularQ->oq_lock,
2494 circularQ->lock_flags);
2495 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2496 spin_lock_irqsave(&circularQ->oq_lock,
2497 circularQ->lock_flags);
2498 return;
2499 }
2500 break;
2501 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2502 pm8001_dbg(pm8001_ha, IO,
2503 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2504 ts->resp = SAS_TASK_COMPLETE;
2505 ts->stat = SAS_OPEN_REJECT;
2506 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2507 if (pm8001_dev)
2508 atomic_dec(&pm8001_dev->running_req);
2509 break;
2510 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2511 pm8001_dbg(pm8001_ha, IO,
2512 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n");
2513 ts->resp = SAS_TASK_COMPLETE;
2514 ts->stat = SAS_DEV_NO_RESPONSE;
2515 if (!t->uldd_task) {
2516 pm8001_handle_event(pm8001_ha,
2517 pm8001_dev,
2518 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2519 ts->resp = SAS_TASK_UNDELIVERED;
2520 ts->stat = SAS_QUEUE_FULL;
2521 spin_unlock_irqrestore(&circularQ->oq_lock,
2522 circularQ->lock_flags);
2523 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2524 spin_lock_irqsave(&circularQ->oq_lock,
2525 circularQ->lock_flags);
2526 return;
2527 }
2528 break;
2529 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2530 pm8001_dbg(pm8001_ha, IO,
2531 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2532 ts->resp = SAS_TASK_COMPLETE;
2533 ts->stat = SAS_OPEN_REJECT;
2534 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2535 if (pm8001_dev)
2536 atomic_dec(&pm8001_dev->running_req);
2537 break;
2538 case IO_XFER_ERROR_NAK_RECEIVED:
2539 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2540 ts->resp = SAS_TASK_COMPLETE;
2541 ts->stat = SAS_NAK_R_ERR;
2542 if (pm8001_dev)
2543 atomic_dec(&pm8001_dev->running_req);
2544 break;
2545 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2546 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2547 ts->resp = SAS_TASK_COMPLETE;
2548 ts->stat = SAS_NAK_R_ERR;
2549 if (pm8001_dev)
2550 atomic_dec(&pm8001_dev->running_req);
2551 break;
2552 case IO_XFER_ERROR_DMA:
2553 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2554 ts->resp = SAS_TASK_COMPLETE;
2555 ts->stat = SAS_ABORTED_TASK;
2556 if (pm8001_dev)
2557 atomic_dec(&pm8001_dev->running_req);
2558 break;
2559 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2560 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n");
2561 ts->resp = SAS_TASK_UNDELIVERED;
2562 ts->stat = SAS_DEV_NO_RESPONSE;
2563 if (pm8001_dev)
2564 atomic_dec(&pm8001_dev->running_req);
2565 break;
2566 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2567 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2568 ts->resp = SAS_TASK_COMPLETE;
2569 ts->stat = SAS_DATA_UNDERRUN;
2570 if (pm8001_dev)
2571 atomic_dec(&pm8001_dev->running_req);
2572 break;
2573 case IO_XFER_OPEN_RETRY_TIMEOUT:
2574 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2575 ts->resp = SAS_TASK_COMPLETE;
2576 ts->stat = SAS_OPEN_TO;
2577 if (pm8001_dev)
2578 atomic_dec(&pm8001_dev->running_req);
2579 break;
2580 case IO_PORT_IN_RESET:
2581 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2582 ts->resp = SAS_TASK_COMPLETE;
2583 ts->stat = SAS_DEV_NO_RESPONSE;
2584 if (pm8001_dev)
2585 atomic_dec(&pm8001_dev->running_req);
2586 break;
2587 case IO_DS_NON_OPERATIONAL:
2588 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2589 ts->resp = SAS_TASK_COMPLETE;
2590 ts->stat = SAS_DEV_NO_RESPONSE;
2591 if (!t->uldd_task) {
2592 pm8001_handle_event(pm8001_ha, pm8001_dev,
2593 IO_DS_NON_OPERATIONAL);
2594 ts->resp = SAS_TASK_UNDELIVERED;
2595 ts->stat = SAS_QUEUE_FULL;
2596 spin_unlock_irqrestore(&circularQ->oq_lock,
2597 circularQ->lock_flags);
2598 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2599 spin_lock_irqsave(&circularQ->oq_lock,
2600 circularQ->lock_flags);
2601 return;
2602 }
2603 break;
2604 case IO_DS_IN_RECOVERY:
2605 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2606 ts->resp = SAS_TASK_COMPLETE;
2607 ts->stat = SAS_DEV_NO_RESPONSE;
2608 if (pm8001_dev)
2609 atomic_dec(&pm8001_dev->running_req);
2610 break;
2611 case IO_DS_IN_ERROR:
2612 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n");
2613 ts->resp = SAS_TASK_COMPLETE;
2614 ts->stat = SAS_DEV_NO_RESPONSE;
2615 if (!t->uldd_task) {
2616 pm8001_handle_event(pm8001_ha, pm8001_dev,
2617 IO_DS_IN_ERROR);
2618 ts->resp = SAS_TASK_UNDELIVERED;
2619 ts->stat = SAS_QUEUE_FULL;
2620 spin_unlock_irqrestore(&circularQ->oq_lock,
2621 circularQ->lock_flags);
2622 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2623 spin_lock_irqsave(&circularQ->oq_lock,
2624 circularQ->lock_flags);
2625 return;
2626 }
2627 break;
2628 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2629 pm8001_dbg(pm8001_ha, IO,
2630 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2631 ts->resp = SAS_TASK_COMPLETE;
2632 ts->stat = SAS_OPEN_REJECT;
2633 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2634 if (pm8001_dev)
2635 atomic_dec(&pm8001_dev->running_req);
2636 break;
2637 default:
2638 pm8001_dbg(pm8001_ha, DEVIO,
2639 "Unknown status device_id %u status 0x%x tag %d\n",
2640 pm8001_dev->device_id, status, tag);
2641 /* not allowed case. Therefore, return failed status */
2642 ts->resp = SAS_TASK_COMPLETE;
2643 ts->stat = SAS_DEV_NO_RESPONSE;
2644 if (pm8001_dev)
2645 atomic_dec(&pm8001_dev->running_req);
2646 break;
2647 }
2648 spin_lock_irqsave(&t->task_state_lock, flags);
2649 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2650 t->task_state_flags |= SAS_TASK_STATE_DONE;
2651 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2652 spin_unlock_irqrestore(&t->task_state_lock, flags);
2653 pm8001_dbg(pm8001_ha, FAIL,
2654 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2655 t, status, ts->resp, ts->stat);
2656 pm8001_ccb_task_free(pm8001_ha, ccb);
2657 if (t->slow_task)
2658 complete(&t->slow_task->completion);
2659 } else {
2660 spin_unlock_irqrestore(&t->task_state_lock, flags);
2661 spin_unlock_irqrestore(&circularQ->oq_lock,
2662 circularQ->lock_flags);
2663 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2664 spin_lock_irqsave(&circularQ->oq_lock,
2665 circularQ->lock_flags);
2666 }
2667 }
2668
2669 /*See the comments for mpi_ssp_completion */
mpi_sata_event(struct pm8001_hba_info * pm8001_ha,struct outbound_queue_table * circularQ,void * piomb)2670 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha,
2671 struct outbound_queue_table *circularQ, void *piomb)
2672 {
2673 struct sas_task *t;
2674 struct task_status_struct *ts;
2675 struct pm8001_ccb_info *ccb;
2676 struct pm8001_device *pm8001_dev;
2677 struct sata_event_resp *psataPayload =
2678 (struct sata_event_resp *)(piomb + 4);
2679 u32 event = le32_to_cpu(psataPayload->event);
2680 u32 tag = le32_to_cpu(psataPayload->tag);
2681 u32 port_id = le32_to_cpu(psataPayload->port_id);
2682 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2683
2684 if (event)
2685 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
2686
2687 /* Check if this is NCQ error */
2688 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2689 /* find device using device id */
2690 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2691 /* send read log extension by aborting the link - libata does what we want */
2692 if (pm8001_dev)
2693 pm8001_handle_event(pm8001_ha,
2694 pm8001_dev,
2695 IO_XFER_ERROR_ABORTED_NCQ_MODE);
2696 return;
2697 }
2698
2699 ccb = &pm8001_ha->ccb_info[tag];
2700 t = ccb->task;
2701 pm8001_dev = ccb->device;
2702 if (unlikely(!t)) {
2703 pm8001_dbg(pm8001_ha, FAIL, "task null, freeing CCB tag %d\n",
2704 ccb->ccb_tag);
2705 pm8001_ccb_free(pm8001_ha, ccb);
2706 return;
2707 }
2708
2709 if (unlikely(!t->lldd_task || !t->dev))
2710 return;
2711
2712 ts = &t->task_status;
2713 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
2714 port_id, tag, event);
2715 switch (event) {
2716 case IO_OVERFLOW:
2717 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2718 ts->resp = SAS_TASK_COMPLETE;
2719 ts->stat = SAS_DATA_OVERRUN;
2720 ts->residual = 0;
2721 break;
2722 case IO_XFER_ERROR_BREAK:
2723 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2724 ts->resp = SAS_TASK_COMPLETE;
2725 ts->stat = SAS_INTERRUPTED;
2726 break;
2727 case IO_XFER_ERROR_PHY_NOT_READY:
2728 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2729 ts->resp = SAS_TASK_COMPLETE;
2730 ts->stat = SAS_OPEN_REJECT;
2731 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2732 break;
2733 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2734 pm8001_dbg(pm8001_ha, IO,
2735 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2736 ts->resp = SAS_TASK_COMPLETE;
2737 ts->stat = SAS_OPEN_REJECT;
2738 ts->open_rej_reason = SAS_OREJ_EPROTO;
2739 break;
2740 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2741 pm8001_dbg(pm8001_ha, IO,
2742 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2743 ts->resp = SAS_TASK_COMPLETE;
2744 ts->stat = SAS_OPEN_REJECT;
2745 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2746 break;
2747 case IO_OPEN_CNX_ERROR_BREAK:
2748 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2749 ts->resp = SAS_TASK_COMPLETE;
2750 ts->stat = SAS_OPEN_REJECT;
2751 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2752 break;
2753 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2754 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2755 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2756 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2757 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2758 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2759 pm8001_dbg(pm8001_ha, FAIL,
2760 "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2761 ts->resp = SAS_TASK_UNDELIVERED;
2762 ts->stat = SAS_DEV_NO_RESPONSE;
2763 if (!t->uldd_task) {
2764 pm8001_handle_event(pm8001_ha,
2765 pm8001_dev,
2766 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2767 ts->resp = SAS_TASK_COMPLETE;
2768 ts->stat = SAS_QUEUE_FULL;
2769 return;
2770 }
2771 break;
2772 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2773 pm8001_dbg(pm8001_ha, IO,
2774 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2775 ts->resp = SAS_TASK_UNDELIVERED;
2776 ts->stat = SAS_OPEN_REJECT;
2777 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2778 break;
2779 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2780 pm8001_dbg(pm8001_ha, IO,
2781 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2782 ts->resp = SAS_TASK_COMPLETE;
2783 ts->stat = SAS_OPEN_REJECT;
2784 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2785 break;
2786 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2787 pm8001_dbg(pm8001_ha, IO,
2788 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2789 ts->resp = SAS_TASK_COMPLETE;
2790 ts->stat = SAS_OPEN_REJECT;
2791 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2792 break;
2793 case IO_XFER_ERROR_NAK_RECEIVED:
2794 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2795 ts->resp = SAS_TASK_COMPLETE;
2796 ts->stat = SAS_NAK_R_ERR;
2797 break;
2798 case IO_XFER_ERROR_PEER_ABORTED:
2799 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n");
2800 ts->resp = SAS_TASK_COMPLETE;
2801 ts->stat = SAS_NAK_R_ERR;
2802 break;
2803 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2804 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2805 ts->resp = SAS_TASK_COMPLETE;
2806 ts->stat = SAS_DATA_UNDERRUN;
2807 break;
2808 case IO_XFER_OPEN_RETRY_TIMEOUT:
2809 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2810 ts->resp = SAS_TASK_COMPLETE;
2811 ts->stat = SAS_OPEN_TO;
2812 break;
2813 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2814 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2815 ts->resp = SAS_TASK_COMPLETE;
2816 ts->stat = SAS_OPEN_TO;
2817 break;
2818 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2819 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2820 ts->resp = SAS_TASK_COMPLETE;
2821 ts->stat = SAS_OPEN_TO;
2822 break;
2823 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2824 pm8001_dbg(pm8001_ha, IO,
2825 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2826 ts->resp = SAS_TASK_COMPLETE;
2827 ts->stat = SAS_OPEN_TO;
2828 break;
2829 case IO_XFER_ERROR_OFFSET_MISMATCH:
2830 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2831 ts->resp = SAS_TASK_COMPLETE;
2832 ts->stat = SAS_OPEN_TO;
2833 break;
2834 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2835 pm8001_dbg(pm8001_ha, IO,
2836 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2837 ts->resp = SAS_TASK_COMPLETE;
2838 ts->stat = SAS_OPEN_TO;
2839 break;
2840 case IO_XFER_CMD_FRAME_ISSUED:
2841 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2842 break;
2843 case IO_XFER_PIO_SETUP_ERROR:
2844 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n");
2845 ts->resp = SAS_TASK_COMPLETE;
2846 ts->stat = SAS_OPEN_TO;
2847 break;
2848 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2849 pm8001_dbg(pm8001_ha, FAIL,
2850 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
2851 /* TBC: used default set values */
2852 ts->resp = SAS_TASK_COMPLETE;
2853 ts->stat = SAS_OPEN_TO;
2854 break;
2855 case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2856 pm8001_dbg(pm8001_ha, FAIL, "IO_XFR_DMA_ACTIVATE_TIMEOUT\n");
2857 /* TBC: used default set values */
2858 ts->resp = SAS_TASK_COMPLETE;
2859 ts->stat = SAS_OPEN_TO;
2860 break;
2861 default:
2862 pm8001_dbg(pm8001_ha, IO, "Unknown status 0x%x\n", event);
2863 /* not allowed case. Therefore, return failed status */
2864 ts->resp = SAS_TASK_COMPLETE;
2865 ts->stat = SAS_OPEN_TO;
2866 break;
2867 }
2868 }
2869
2870 /*See the comments for mpi_ssp_completion */
2871 static void
mpi_smp_completion(struct pm8001_hba_info * pm8001_ha,void * piomb)2872 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2873 {
2874 u32 param, i;
2875 struct sas_task *t;
2876 struct pm8001_ccb_info *ccb;
2877 unsigned long flags;
2878 u32 status;
2879 u32 tag;
2880 struct smp_completion_resp *psmpPayload;
2881 struct task_status_struct *ts;
2882 struct pm8001_device *pm8001_dev;
2883
2884 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2885 status = le32_to_cpu(psmpPayload->status);
2886 tag = le32_to_cpu(psmpPayload->tag);
2887
2888 ccb = &pm8001_ha->ccb_info[tag];
2889 param = le32_to_cpu(psmpPayload->param);
2890 t = ccb->task;
2891 ts = &t->task_status;
2892 pm8001_dev = ccb->device;
2893 if (status)
2894 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);
2895 if (unlikely(!t || !t->lldd_task || !t->dev))
2896 return;
2897
2898 pm8001_dbg(pm8001_ha, DEV, "tag::0x%x status::0x%x\n", tag, status);
2899
2900 switch (status) {
2901
2902 case IO_SUCCESS:
2903 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2904 ts->resp = SAS_TASK_COMPLETE;
2905 ts->stat = SAS_SAM_STAT_GOOD;
2906 if (pm8001_dev)
2907 atomic_dec(&pm8001_dev->running_req);
2908 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2909 struct scatterlist *sg_resp = &t->smp_task.smp_resp;
2910 u8 *payload;
2911 void *to;
2912
2913 pm8001_dbg(pm8001_ha, IO,
2914 "DIRECT RESPONSE Length:%d\n",
2915 param);
2916 to = kmap_atomic(sg_page(sg_resp));
2917 payload = to + sg_resp->offset;
2918 for (i = 0; i < param; i++) {
2919 *(payload + i) = psmpPayload->_r_a[i];
2920 pm8001_dbg(pm8001_ha, IO,
2921 "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2922 i, *(payload + i),
2923 psmpPayload->_r_a[i]);
2924 }
2925 kunmap_atomic(to);
2926 }
2927 break;
2928 case IO_ABORTED:
2929 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n");
2930 ts->resp = SAS_TASK_COMPLETE;
2931 ts->stat = SAS_ABORTED_TASK;
2932 if (pm8001_dev)
2933 atomic_dec(&pm8001_dev->running_req);
2934 break;
2935 case IO_OVERFLOW:
2936 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2937 ts->resp = SAS_TASK_COMPLETE;
2938 ts->stat = SAS_DATA_OVERRUN;
2939 ts->residual = 0;
2940 if (pm8001_dev)
2941 atomic_dec(&pm8001_dev->running_req);
2942 break;
2943 case IO_NO_DEVICE:
2944 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2945 ts->resp = SAS_TASK_COMPLETE;
2946 ts->stat = SAS_PHY_DOWN;
2947 break;
2948 case IO_ERROR_HW_TIMEOUT:
2949 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n");
2950 ts->resp = SAS_TASK_COMPLETE;
2951 ts->stat = SAS_SAM_STAT_BUSY;
2952 break;
2953 case IO_XFER_ERROR_BREAK:
2954 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2955 ts->resp = SAS_TASK_COMPLETE;
2956 ts->stat = SAS_SAM_STAT_BUSY;
2957 break;
2958 case IO_XFER_ERROR_PHY_NOT_READY:
2959 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2960 ts->resp = SAS_TASK_COMPLETE;
2961 ts->stat = SAS_SAM_STAT_BUSY;
2962 break;
2963 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2964 pm8001_dbg(pm8001_ha, IO,
2965 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2966 ts->resp = SAS_TASK_COMPLETE;
2967 ts->stat = SAS_OPEN_REJECT;
2968 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2969 break;
2970 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2971 pm8001_dbg(pm8001_ha, IO,
2972 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2973 ts->resp = SAS_TASK_COMPLETE;
2974 ts->stat = SAS_OPEN_REJECT;
2975 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2976 break;
2977 case IO_OPEN_CNX_ERROR_BREAK:
2978 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2979 ts->resp = SAS_TASK_COMPLETE;
2980 ts->stat = SAS_OPEN_REJECT;
2981 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2982 break;
2983 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2984 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2985 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2986 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2987 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2988 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2989 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2990 ts->resp = SAS_TASK_COMPLETE;
2991 ts->stat = SAS_OPEN_REJECT;
2992 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2993 pm8001_handle_event(pm8001_ha,
2994 pm8001_dev,
2995 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2996 break;
2997 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2998 pm8001_dbg(pm8001_ha, IO,
2999 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
3000 ts->resp = SAS_TASK_COMPLETE;
3001 ts->stat = SAS_OPEN_REJECT;
3002 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
3003 break;
3004 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
3005 pm8001_dbg(pm8001_ha, IO,
3006 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
3007 ts->resp = SAS_TASK_COMPLETE;
3008 ts->stat = SAS_OPEN_REJECT;
3009 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
3010 break;
3011 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
3012 pm8001_dbg(pm8001_ha, IO,
3013 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
3014 ts->resp = SAS_TASK_COMPLETE;
3015 ts->stat = SAS_OPEN_REJECT;
3016 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3017 break;
3018 case IO_XFER_ERROR_RX_FRAME:
3019 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n");
3020 ts->resp = SAS_TASK_COMPLETE;
3021 ts->stat = SAS_DEV_NO_RESPONSE;
3022 break;
3023 case IO_XFER_OPEN_RETRY_TIMEOUT:
3024 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
3025 ts->resp = SAS_TASK_COMPLETE;
3026 ts->stat = SAS_OPEN_REJECT;
3027 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3028 break;
3029 case IO_ERROR_INTERNAL_SMP_RESOURCE:
3030 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n");
3031 ts->resp = SAS_TASK_COMPLETE;
3032 ts->stat = SAS_QUEUE_FULL;
3033 break;
3034 case IO_PORT_IN_RESET:
3035 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
3036 ts->resp = SAS_TASK_COMPLETE;
3037 ts->stat = SAS_OPEN_REJECT;
3038 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3039 break;
3040 case IO_DS_NON_OPERATIONAL:
3041 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
3042 ts->resp = SAS_TASK_COMPLETE;
3043 ts->stat = SAS_DEV_NO_RESPONSE;
3044 break;
3045 case IO_DS_IN_RECOVERY:
3046 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
3047 ts->resp = SAS_TASK_COMPLETE;
3048 ts->stat = SAS_OPEN_REJECT;
3049 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3050 break;
3051 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3052 pm8001_dbg(pm8001_ha, IO,
3053 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
3054 ts->resp = SAS_TASK_COMPLETE;
3055 ts->stat = SAS_OPEN_REJECT;
3056 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3057 break;
3058 default:
3059 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
3060 ts->resp = SAS_TASK_COMPLETE;
3061 ts->stat = SAS_DEV_NO_RESPONSE;
3062 /* not allowed case. Therefore, return failed status */
3063 break;
3064 }
3065 spin_lock_irqsave(&t->task_state_lock, flags);
3066 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3067 t->task_state_flags |= SAS_TASK_STATE_DONE;
3068 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3069 spin_unlock_irqrestore(&t->task_state_lock, flags);
3070 pm8001_dbg(pm8001_ha, FAIL,
3071 "task 0x%p done with io_status 0x%x resp 0x%xstat 0x%x but aborted by upper layer!\n",
3072 t, status, ts->resp, ts->stat);
3073 pm8001_ccb_task_free(pm8001_ha, ccb);
3074 } else {
3075 spin_unlock_irqrestore(&t->task_state_lock, flags);
3076 pm8001_ccb_task_free(pm8001_ha, ccb);
3077 mb();/* in order to force CPU ordering */
3078 t->task_done(t);
3079 }
3080 }
3081
3082 /**
3083 * pm80xx_hw_event_ack_req- For PM8001, some events need to acknowledge to FW.
3084 * @pm8001_ha: our hba card information
3085 * @Qnum: the outbound queue message number.
3086 * @SEA: source of event to ack
3087 * @port_id: port id.
3088 * @phyId: phy id.
3089 * @param0: parameter 0.
3090 * @param1: parameter 1.
3091 */
pm80xx_hw_event_ack_req(struct pm8001_hba_info * pm8001_ha,u32 Qnum,u32 SEA,u32 port_id,u32 phyId,u32 param0,u32 param1)3092 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3093 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3094 {
3095 struct hw_event_ack_req payload;
3096 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3097
3098 memset((u8 *)&payload, 0, sizeof(payload));
3099 payload.tag = cpu_to_le32(1);
3100 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3101 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
3102 payload.param0 = cpu_to_le32(param0);
3103 payload.param1 = cpu_to_le32(param1);
3104
3105 pm8001_mpi_build_cmd(pm8001_ha, Qnum, opc, &payload,
3106 sizeof(payload), 0);
3107 }
3108
3109 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3110 u32 phyId, u32 phy_op);
3111
hw_event_port_recover(struct pm8001_hba_info * pm8001_ha,void * piomb)3112 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
3113 void *piomb)
3114 {
3115 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
3116 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3117 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3118 u32 lr_status_evt_portid =
3119 le32_to_cpu(pPayload->lr_status_evt_portid);
3120 u8 deviceType = pPayload->sas_identify.dev_type;
3121 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3122 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3123 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3124 struct pm8001_port *port = &pm8001_ha->port[port_id];
3125
3126 if (deviceType == SAS_END_DEVICE) {
3127 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3128 PHY_NOTIFY_ENABLE_SPINUP);
3129 }
3130
3131 port->wide_port_phymap |= (1U << phy_id);
3132 pm8001_get_lrate_mode(phy, link_rate);
3133 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3134 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3135 phy->phy_attached = 1;
3136 }
3137
3138 /**
3139 * hw_event_sas_phy_up - FW tells me a SAS phy up event.
3140 * @pm8001_ha: our hba card information
3141 * @piomb: IO message buffer
3142 */
3143 static void
hw_event_sas_phy_up(struct pm8001_hba_info * pm8001_ha,void * piomb)3144 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3145 {
3146 struct hw_event_resp *pPayload =
3147 (struct hw_event_resp *)(piomb + 4);
3148 u32 lr_status_evt_portid =
3149 le32_to_cpu(pPayload->lr_status_evt_portid);
3150 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3151
3152 u8 link_rate =
3153 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3154 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3155 u8 phy_id =
3156 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3157 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3158
3159 struct pm8001_port *port = &pm8001_ha->port[port_id];
3160 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3161 unsigned long flags;
3162 u8 deviceType = pPayload->sas_identify.dev_type;
3163 phy->port = port;
3164 port->port_id = port_id;
3165 port->port_state = portstate;
3166 port->wide_port_phymap |= (1U << phy_id);
3167 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3168 pm8001_dbg(pm8001_ha, MSG,
3169 "portid:%d; phyid:%d; linkrate:%d; portstate:%x; devicetype:%x\n",
3170 port_id, phy_id, link_rate, portstate, deviceType);
3171
3172 switch (deviceType) {
3173 case SAS_PHY_UNUSED:
3174 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n");
3175 break;
3176 case SAS_END_DEVICE:
3177 pm8001_dbg(pm8001_ha, MSG, "end device.\n");
3178 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3179 PHY_NOTIFY_ENABLE_SPINUP);
3180 port->port_attached = 1;
3181 pm8001_get_lrate_mode(phy, link_rate);
3182 break;
3183 case SAS_EDGE_EXPANDER_DEVICE:
3184 pm8001_dbg(pm8001_ha, MSG, "expander device.\n");
3185 port->port_attached = 1;
3186 pm8001_get_lrate_mode(phy, link_rate);
3187 break;
3188 case SAS_FANOUT_EXPANDER_DEVICE:
3189 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n");
3190 port->port_attached = 1;
3191 pm8001_get_lrate_mode(phy, link_rate);
3192 break;
3193 default:
3194 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n",
3195 deviceType);
3196 break;
3197 }
3198 phy->phy_type |= PORT_TYPE_SAS;
3199 phy->identify.device_type = deviceType;
3200 phy->phy_attached = 1;
3201 if (phy->identify.device_type == SAS_END_DEVICE)
3202 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3203 else if (phy->identify.device_type != SAS_PHY_UNUSED)
3204 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3205 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3206 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3207 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3208 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3209 sizeof(struct sas_identify_frame)-4);
3210 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3211 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3212 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3213 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3214 mdelay(200); /* delay a moment to wait for disk to spin up */
3215 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3216 }
3217
3218 /**
3219 * hw_event_sata_phy_up - FW tells me a SATA phy up event.
3220 * @pm8001_ha: our hba card information
3221 * @piomb: IO message buffer
3222 */
3223 static void
hw_event_sata_phy_up(struct pm8001_hba_info * pm8001_ha,void * piomb)3224 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3225 {
3226 struct hw_event_resp *pPayload =
3227 (struct hw_event_resp *)(piomb + 4);
3228 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3229 u32 lr_status_evt_portid =
3230 le32_to_cpu(pPayload->lr_status_evt_portid);
3231 u8 link_rate =
3232 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3233 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3234 u8 phy_id =
3235 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3236
3237 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3238
3239 struct pm8001_port *port = &pm8001_ha->port[port_id];
3240 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3241 unsigned long flags;
3242 pm8001_dbg(pm8001_ha, EVENT,
3243 "HW_EVENT_SATA_PHY_UP phyid:%#x port_id:%#x link_rate:%d portstate:%#x\n",
3244 phy_id, port_id, link_rate, portstate);
3245
3246 phy->port = port;
3247 port->port_id = port_id;
3248 port->port_state = portstate;
3249 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3250 port->port_attached = 1;
3251 pm8001_get_lrate_mode(phy, link_rate);
3252 phy->phy_type |= PORT_TYPE_SATA;
3253 phy->phy_attached = 1;
3254 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3255 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3256 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3257 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3258 sizeof(struct dev_to_host_fis));
3259 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3260 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3261 phy->identify.device_type = SAS_SATA_DEV;
3262 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3263 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3264 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3265 }
3266
3267 /**
3268 * hw_event_phy_down - we should notify the libsas the phy is down.
3269 * @pm8001_ha: our hba card information
3270 * @piomb: IO message buffer
3271 */
3272 static void
hw_event_phy_down(struct pm8001_hba_info * pm8001_ha,void * piomb)3273 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3274 {
3275 struct hw_event_resp *pPayload =
3276 (struct hw_event_resp *)(piomb + 4);
3277
3278 u32 lr_status_evt_portid =
3279 le32_to_cpu(pPayload->lr_status_evt_portid);
3280 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3281 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3282 u8 phy_id =
3283 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3284 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3285
3286 struct pm8001_port *port = &pm8001_ha->port[port_id];
3287 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3288 u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);
3289 port->port_state = portstate;
3290 phy->identify.device_type = 0;
3291 phy->phy_attached = 0;
3292 switch (portstate) {
3293 case PORT_VALID:
3294 pm8001_dbg(pm8001_ha, EVENT,
3295 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_VALID\n",
3296 phy_id, port_id);
3297 break;
3298 case PORT_INVALID:
3299 pm8001_dbg(pm8001_ha, EVENT,
3300 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_INVALID\n",
3301 phy_id, port_id);
3302 pm8001_dbg(pm8001_ha, MSG,
3303 " Last phy Down and port invalid\n");
3304 if (port_sata) {
3305 phy->phy_type = 0;
3306 port->port_attached = 0;
3307 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3308 port_id, phy_id, 0, 0);
3309 }
3310 sas_phy_disconnected(&phy->sas_phy);
3311 break;
3312 case PORT_IN_RESET:
3313 pm8001_dbg(pm8001_ha, EVENT,
3314 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_IN_RESET\n",
3315 phy_id, port_id);
3316 break;
3317 case PORT_NOT_ESTABLISHED:
3318 pm8001_dbg(pm8001_ha, EVENT,
3319 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_NOT_ESTABLISHED\n",
3320 phy_id, port_id);
3321 port->port_attached = 0;
3322 break;
3323 case PORT_LOSTCOMM:
3324 pm8001_dbg(pm8001_ha, EVENT,
3325 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_LOSTCOMM\n",
3326 phy_id, port_id);
3327 pm8001_dbg(pm8001_ha, MSG, " Last phy Down and port invalid\n");
3328 if (port_sata) {
3329 port->port_attached = 0;
3330 phy->phy_type = 0;
3331 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3332 port_id, phy_id, 0, 0);
3333 }
3334 sas_phy_disconnected(&phy->sas_phy);
3335 break;
3336 default:
3337 port->port_attached = 0;
3338 pm8001_dbg(pm8001_ha, EVENT,
3339 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate:%#x\n",
3340 phy_id, port_id, portstate);
3341 break;
3342
3343 }
3344 if (port_sata && (portstate != PORT_IN_RESET))
3345 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL,
3346 GFP_ATOMIC);
3347 }
3348
mpi_phy_start_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3349 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3350 {
3351 struct phy_start_resp *pPayload =
3352 (struct phy_start_resp *)(piomb + 4);
3353 u32 status =
3354 le32_to_cpu(pPayload->status);
3355 u32 phy_id =
3356 le32_to_cpu(pPayload->phyid) & 0xFF;
3357 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3358
3359 pm8001_dbg(pm8001_ha, INIT,
3360 "phy start resp status:0x%x, phyid:0x%x\n",
3361 status, phy_id);
3362 if (status == 0)
3363 phy->phy_state = PHY_LINK_DOWN;
3364
3365 if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3366 phy->enable_completion != NULL) {
3367 complete(phy->enable_completion);
3368 phy->enable_completion = NULL;
3369 }
3370 return 0;
3371
3372 }
3373
3374 /**
3375 * mpi_thermal_hw_event - a thermal hw event has come.
3376 * @pm8001_ha: our hba card information
3377 * @piomb: IO message buffer
3378 */
mpi_thermal_hw_event(struct pm8001_hba_info * pm8001_ha,void * piomb)3379 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3380 {
3381 struct thermal_hw_event *pPayload =
3382 (struct thermal_hw_event *)(piomb + 4);
3383
3384 u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3385 u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3386
3387 if (thermal_event & 0x40) {
3388 pm8001_dbg(pm8001_ha, IO,
3389 "Thermal Event: Local high temperature violated!\n");
3390 pm8001_dbg(pm8001_ha, IO,
3391 "Thermal Event: Measured local high temperature %d\n",
3392 ((rht_lht & 0xFF00) >> 8));
3393 }
3394 if (thermal_event & 0x10) {
3395 pm8001_dbg(pm8001_ha, IO,
3396 "Thermal Event: Remote high temperature violated!\n");
3397 pm8001_dbg(pm8001_ha, IO,
3398 "Thermal Event: Measured remote high temperature %d\n",
3399 ((rht_lht & 0xFF000000) >> 24));
3400 }
3401 return 0;
3402 }
3403
3404 /**
3405 * mpi_hw_event - The hw event has come.
3406 * @pm8001_ha: our hba card information
3407 * @piomb: IO message buffer
3408 */
mpi_hw_event(struct pm8001_hba_info * pm8001_ha,void * piomb)3409 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3410 {
3411 unsigned long flags, i;
3412 struct hw_event_resp *pPayload =
3413 (struct hw_event_resp *)(piomb + 4);
3414 u32 lr_status_evt_portid =
3415 le32_to_cpu(pPayload->lr_status_evt_portid);
3416 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3417 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3418 u8 phy_id =
3419 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3420 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3421 u16 eventType =
3422 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3423 u8 status =
3424 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3425 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3426 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3427 struct pm8001_port *port = &pm8001_ha->port[port_id];
3428 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3429 pm8001_dbg(pm8001_ha, DEV,
3430 "portid:%d phyid:%d event:0x%x status:0x%x\n",
3431 port_id, phy_id, eventType, status);
3432
3433 switch (eventType) {
3434
3435 case HW_EVENT_SAS_PHY_UP:
3436 pm8001_dbg(pm8001_ha, EVENT,
3437 "HW_EVENT_SAS_PHY_UP phyid:%#x port_id:%#x\n",
3438 phy_id, port_id);
3439 hw_event_sas_phy_up(pm8001_ha, piomb);
3440 break;
3441 case HW_EVENT_SATA_PHY_UP:
3442 hw_event_sata_phy_up(pm8001_ha, piomb);
3443 break;
3444 case HW_EVENT_SATA_SPINUP_HOLD:
3445 pm8001_dbg(pm8001_ha, EVENT,
3446 "HW_EVENT_SATA_SPINUP_HOLD phyid:%#x port_id:%#x\n",
3447 phy_id, port_id);
3448 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD,
3449 GFP_ATOMIC);
3450 break;
3451 case HW_EVENT_PHY_DOWN:
3452 hw_event_phy_down(pm8001_ha, piomb);
3453 phy->phy_state = PHY_LINK_DISABLE;
3454 break;
3455 case HW_EVENT_PORT_INVALID:
3456 pm8001_dbg(pm8001_ha, EVENT,
3457 "HW_EVENT_PORT_INVALID phyid:%#x port_id:%#x\n",
3458 phy_id, port_id);
3459 sas_phy_disconnected(sas_phy);
3460 phy->phy_attached = 0;
3461 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3462 GFP_ATOMIC);
3463 break;
3464 /* the broadcast change primitive received, tell the LIBSAS this event
3465 to revalidate the sas domain*/
3466 case HW_EVENT_BROADCAST_CHANGE:
3467 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n");
3468 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3469 port_id, phy_id, 1, 0);
3470 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3471 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3472 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3473 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3474 GFP_ATOMIC);
3475 break;
3476 case HW_EVENT_PHY_ERROR:
3477 pm8001_dbg(pm8001_ha, EVENT,
3478 "HW_EVENT_PHY_ERROR phyid:%#x port_id:%#x\n",
3479 phy_id, port_id);
3480 sas_phy_disconnected(&phy->sas_phy);
3481 phy->phy_attached = 0;
3482 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC);
3483 break;
3484 case HW_EVENT_BROADCAST_EXP:
3485 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n");
3486 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3487 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3488 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3489 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3490 GFP_ATOMIC);
3491 break;
3492 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3493 pm8001_dbg(pm8001_ha, EVENT,
3494 "HW_EVENT_LINK_ERR_INVALID_DWORD phyid:%#x port_id:%#x\n",
3495 phy_id, port_id);
3496 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3497 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3498 break;
3499 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3500 pm8001_dbg(pm8001_ha, EVENT,
3501 "HW_EVENT_LINK_ERR_DISPARITY_ERROR phyid:%#x port_id:%#x\n",
3502 phy_id, port_id);
3503 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3504 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3505 port_id, phy_id, 0, 0);
3506 break;
3507 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3508 pm8001_dbg(pm8001_ha, EVENT,
3509 "HW_EVENT_LINK_ERR_CODE_VIOLATION phyid:%#x port_id:%#x\n",
3510 phy_id, port_id);
3511 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3512 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3513 port_id, phy_id, 0, 0);
3514 break;
3515 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3516 pm8001_dbg(pm8001_ha, EVENT,
3517 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH phyid:%#x port_id:%#x\n",
3518 phy_id, port_id);
3519 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3520 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3521 port_id, phy_id, 0, 0);
3522 break;
3523 case HW_EVENT_MALFUNCTION:
3524 pm8001_dbg(pm8001_ha, EVENT,
3525 "HW_EVENT_MALFUNCTION phyid:%#x\n", phy_id);
3526 break;
3527 case HW_EVENT_BROADCAST_SES:
3528 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n");
3529 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3530 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3531 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3532 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3533 GFP_ATOMIC);
3534 break;
3535 case HW_EVENT_INBOUND_CRC_ERROR:
3536 pm8001_dbg(pm8001_ha, EVENT,
3537 "HW_EVENT_INBOUND_CRC_ERROR phyid:%#x port_id:%#x\n",
3538 phy_id, port_id);
3539 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3540 HW_EVENT_INBOUND_CRC_ERROR,
3541 port_id, phy_id, 0, 0);
3542 break;
3543 case HW_EVENT_HARD_RESET_RECEIVED:
3544 pm8001_dbg(pm8001_ha, EVENT,
3545 "HW_EVENT_HARD_RESET_RECEIVED phyid:%#x\n", phy_id);
3546 sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC);
3547 break;
3548 case HW_EVENT_ID_FRAME_TIMEOUT:
3549 pm8001_dbg(pm8001_ha, EVENT,
3550 "HW_EVENT_ID_FRAME_TIMEOUT phyid:%#x\n", phy_id);
3551 sas_phy_disconnected(sas_phy);
3552 phy->phy_attached = 0;
3553 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3554 GFP_ATOMIC);
3555 break;
3556 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3557 pm8001_dbg(pm8001_ha, EVENT,
3558 "HW_EVENT_LINK_ERR_PHY_RESET_FAILED phyid:%#x port_id:%#x\n",
3559 phy_id, port_id);
3560 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3561 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3562 port_id, phy_id, 0, 0);
3563 sas_phy_disconnected(sas_phy);
3564 phy->phy_attached = 0;
3565 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3566 GFP_ATOMIC);
3567 break;
3568 case HW_EVENT_PORT_RESET_TIMER_TMO:
3569 pm8001_dbg(pm8001_ha, EVENT,
3570 "HW_EVENT_PORT_RESET_TIMER_TMO phyid:%#x port_id:%#x portstate:%#x\n",
3571 phy_id, port_id, portstate);
3572 if (!pm8001_ha->phy[phy_id].reset_completion) {
3573 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3574 port_id, phy_id, 0, 0);
3575 }
3576 sas_phy_disconnected(sas_phy);
3577 phy->phy_attached = 0;
3578 port->port_state = portstate;
3579 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3580 GFP_ATOMIC);
3581 if (pm8001_ha->phy[phy_id].reset_completion) {
3582 pm8001_ha->phy[phy_id].port_reset_status =
3583 PORT_RESET_TMO;
3584 complete(pm8001_ha->phy[phy_id].reset_completion);
3585 pm8001_ha->phy[phy_id].reset_completion = NULL;
3586 }
3587 break;
3588 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3589 pm8001_dbg(pm8001_ha, EVENT,
3590 "HW_EVENT_PORT_RECOVERY_TIMER_TMO phyid:%#x port_id:%#x\n",
3591 phy_id, port_id);
3592 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3593 HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3594 port_id, phy_id, 0, 0);
3595 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3596 if (port->wide_port_phymap & (1 << i)) {
3597 phy = &pm8001_ha->phy[i];
3598 sas_notify_phy_event(&phy->sas_phy,
3599 PHYE_LOSS_OF_SIGNAL, GFP_ATOMIC);
3600 port->wide_port_phymap &= ~(1 << i);
3601 }
3602 }
3603 break;
3604 case HW_EVENT_PORT_RECOVER:
3605 pm8001_dbg(pm8001_ha, EVENT,
3606 "HW_EVENT_PORT_RECOVER phyid:%#x port_id:%#x\n",
3607 phy_id, port_id);
3608 hw_event_port_recover(pm8001_ha, piomb);
3609 break;
3610 case HW_EVENT_PORT_RESET_COMPLETE:
3611 pm8001_dbg(pm8001_ha, EVENT,
3612 "HW_EVENT_PORT_RESET_COMPLETE phyid:%#x port_id:%#x portstate:%#x\n",
3613 phy_id, port_id, portstate);
3614 if (pm8001_ha->phy[phy_id].reset_completion) {
3615 pm8001_ha->phy[phy_id].port_reset_status =
3616 PORT_RESET_SUCCESS;
3617 complete(pm8001_ha->phy[phy_id].reset_completion);
3618 pm8001_ha->phy[phy_id].reset_completion = NULL;
3619 }
3620 phy->phy_attached = 1;
3621 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3622 port->port_state = portstate;
3623 break;
3624 case EVENT_BROADCAST_ASYNCH_EVENT:
3625 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n");
3626 break;
3627 default:
3628 pm8001_dbg(pm8001_ha, DEVIO,
3629 "Unknown event portid:%d phyid:%d event:0x%x status:0x%x\n",
3630 port_id, phy_id, eventType, status);
3631 break;
3632 }
3633 return 0;
3634 }
3635
3636 /**
3637 * mpi_phy_stop_resp - SPCv specific
3638 * @pm8001_ha: our hba card information
3639 * @piomb: IO message buffer
3640 */
mpi_phy_stop_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3641 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3642 {
3643 struct phy_stop_resp *pPayload =
3644 (struct phy_stop_resp *)(piomb + 4);
3645 u32 status =
3646 le32_to_cpu(pPayload->status);
3647 u32 phyid =
3648 le32_to_cpu(pPayload->phyid) & 0xFF;
3649 struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3650 pm8001_dbg(pm8001_ha, MSG, "phy:0x%x status:0x%x\n",
3651 phyid, status);
3652 if (status == PHY_STOP_SUCCESS ||
3653 status == PHY_STOP_ERR_DEVICE_ATTACHED) {
3654 phy->phy_state = PHY_LINK_DISABLE;
3655 phy->sas_phy.phy->negotiated_linkrate = SAS_PHY_DISABLED;
3656 phy->sas_phy.linkrate = SAS_PHY_DISABLED;
3657 }
3658
3659 return 0;
3660 }
3661
3662 /**
3663 * mpi_set_controller_config_resp - SPCv specific
3664 * @pm8001_ha: our hba card information
3665 * @piomb: IO message buffer
3666 */
mpi_set_controller_config_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3667 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3668 void *piomb)
3669 {
3670 struct set_ctrl_cfg_resp *pPayload =
3671 (struct set_ctrl_cfg_resp *)(piomb + 4);
3672 u32 status = le32_to_cpu(pPayload->status);
3673 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3674 u32 tag = le32_to_cpu(pPayload->tag);
3675
3676 pm8001_dbg(pm8001_ha, MSG,
3677 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3678 status, err_qlfr_pgcd);
3679 pm8001_tag_free(pm8001_ha, tag);
3680
3681 return 0;
3682 }
3683
3684 /**
3685 * mpi_get_controller_config_resp - SPCv specific
3686 * @pm8001_ha: our hba card information
3687 * @piomb: IO message buffer
3688 */
mpi_get_controller_config_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3689 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3690 void *piomb)
3691 {
3692 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3693
3694 return 0;
3695 }
3696
3697 /**
3698 * mpi_get_phy_profile_resp - SPCv specific
3699 * @pm8001_ha: our hba card information
3700 * @piomb: IO message buffer
3701 */
mpi_get_phy_profile_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3702 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3703 void *piomb)
3704 {
3705 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3706
3707 return 0;
3708 }
3709
3710 /**
3711 * mpi_flash_op_ext_resp - SPCv specific
3712 * @pm8001_ha: our hba card information
3713 * @piomb: IO message buffer
3714 */
mpi_flash_op_ext_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3715 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3716 {
3717 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3718
3719 return 0;
3720 }
3721
3722 /**
3723 * mpi_set_phy_profile_resp - SPCv specific
3724 * @pm8001_ha: our hba card information
3725 * @piomb: IO message buffer
3726 */
mpi_set_phy_profile_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3727 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3728 void *piomb)
3729 {
3730 u32 tag;
3731 u8 page_code;
3732 int rc = 0;
3733 struct set_phy_profile_resp *pPayload =
3734 (struct set_phy_profile_resp *)(piomb + 4);
3735 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3736 u32 status = le32_to_cpu(pPayload->status);
3737
3738 tag = le32_to_cpu(pPayload->tag);
3739 page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3740 if (status) {
3741 /* status is FAILED */
3742 pm8001_dbg(pm8001_ha, FAIL,
3743 "PhyProfile command failed with status 0x%08X\n",
3744 status);
3745 rc = -1;
3746 } else {
3747 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3748 pm8001_dbg(pm8001_ha, FAIL, "Invalid page code 0x%X\n",
3749 page_code);
3750 rc = -1;
3751 }
3752 }
3753 pm8001_tag_free(pm8001_ha, tag);
3754 return rc;
3755 }
3756
3757 /**
3758 * mpi_kek_management_resp - SPCv specific
3759 * @pm8001_ha: our hba card information
3760 * @piomb: IO message buffer
3761 */
mpi_kek_management_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3762 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3763 void *piomb)
3764 {
3765 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3766
3767 u32 status = le32_to_cpu(pPayload->status);
3768 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3769 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3770
3771 pm8001_dbg(pm8001_ha, MSG,
3772 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3773 status, kidx_new_curr_ksop, err_qlfr);
3774
3775 return 0;
3776 }
3777
3778 /**
3779 * mpi_dek_management_resp - SPCv specific
3780 * @pm8001_ha: our hba card information
3781 * @piomb: IO message buffer
3782 */
mpi_dek_management_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3783 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3784 void *piomb)
3785 {
3786 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3787
3788 return 0;
3789 }
3790
3791 /**
3792 * ssp_coalesced_comp_resp - SPCv specific
3793 * @pm8001_ha: our hba card information
3794 * @piomb: IO message buffer
3795 */
ssp_coalesced_comp_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3796 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3797 void *piomb)
3798 {
3799 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3800
3801 return 0;
3802 }
3803
3804 /**
3805 * process_one_iomb - process one outbound Queue memory block
3806 * @pm8001_ha: our hba card information
3807 * @circularQ: outbound circular queue
3808 * @piomb: IO message buffer
3809 */
process_one_iomb(struct pm8001_hba_info * pm8001_ha,struct outbound_queue_table * circularQ,void * piomb)3810 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha,
3811 struct outbound_queue_table *circularQ, void *piomb)
3812 {
3813 __le32 pHeader = *(__le32 *)piomb;
3814 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3815
3816 switch (opc) {
3817 case OPC_OUB_ECHO:
3818 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n");
3819 break;
3820 case OPC_OUB_HW_EVENT:
3821 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n");
3822 mpi_hw_event(pm8001_ha, piomb);
3823 break;
3824 case OPC_OUB_THERM_HW_EVENT:
3825 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_THERMAL_EVENT\n");
3826 mpi_thermal_hw_event(pm8001_ha, piomb);
3827 break;
3828 case OPC_OUB_SSP_COMP:
3829 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n");
3830 mpi_ssp_completion(pm8001_ha, piomb);
3831 break;
3832 case OPC_OUB_SMP_COMP:
3833 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n");
3834 mpi_smp_completion(pm8001_ha, piomb);
3835 break;
3836 case OPC_OUB_LOCAL_PHY_CNTRL:
3837 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n");
3838 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3839 break;
3840 case OPC_OUB_DEV_REGIST:
3841 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n");
3842 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3843 break;
3844 case OPC_OUB_DEREG_DEV:
3845 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n");
3846 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3847 break;
3848 case OPC_OUB_GET_DEV_HANDLE:
3849 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n");
3850 break;
3851 case OPC_OUB_SATA_COMP:
3852 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n");
3853 mpi_sata_completion(pm8001_ha, circularQ, piomb);
3854 break;
3855 case OPC_OUB_SATA_EVENT:
3856 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n");
3857 mpi_sata_event(pm8001_ha, circularQ, piomb);
3858 break;
3859 case OPC_OUB_SSP_EVENT:
3860 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n");
3861 mpi_ssp_event(pm8001_ha, piomb);
3862 break;
3863 case OPC_OUB_DEV_HANDLE_ARRIV:
3864 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n");
3865 /*This is for target*/
3866 break;
3867 case OPC_OUB_SSP_RECV_EVENT:
3868 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n");
3869 /*This is for target*/
3870 break;
3871 case OPC_OUB_FW_FLASH_UPDATE:
3872 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n");
3873 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3874 break;
3875 case OPC_OUB_GPIO_RESPONSE:
3876 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n");
3877 break;
3878 case OPC_OUB_GPIO_EVENT:
3879 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n");
3880 break;
3881 case OPC_OUB_GENERAL_EVENT:
3882 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n");
3883 pm8001_mpi_general_event(pm8001_ha, piomb);
3884 break;
3885 case OPC_OUB_SSP_ABORT_RSP:
3886 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n");
3887 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3888 break;
3889 case OPC_OUB_SATA_ABORT_RSP:
3890 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n");
3891 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3892 break;
3893 case OPC_OUB_SAS_DIAG_MODE_START_END:
3894 pm8001_dbg(pm8001_ha, MSG,
3895 "OPC_OUB_SAS_DIAG_MODE_START_END\n");
3896 break;
3897 case OPC_OUB_SAS_DIAG_EXECUTE:
3898 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n");
3899 break;
3900 case OPC_OUB_GET_TIME_STAMP:
3901 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n");
3902 break;
3903 case OPC_OUB_SAS_HW_EVENT_ACK:
3904 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n");
3905 break;
3906 case OPC_OUB_PORT_CONTROL:
3907 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n");
3908 break;
3909 case OPC_OUB_SMP_ABORT_RSP:
3910 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n");
3911 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3912 break;
3913 case OPC_OUB_GET_NVMD_DATA:
3914 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n");
3915 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3916 break;
3917 case OPC_OUB_SET_NVMD_DATA:
3918 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n");
3919 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3920 break;
3921 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3922 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n");
3923 break;
3924 case OPC_OUB_SET_DEVICE_STATE:
3925 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n");
3926 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3927 break;
3928 case OPC_OUB_GET_DEVICE_STATE:
3929 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n");
3930 break;
3931 case OPC_OUB_SET_DEV_INFO:
3932 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n");
3933 break;
3934 /* spcv specific commands */
3935 case OPC_OUB_PHY_START_RESP:
3936 pm8001_dbg(pm8001_ha, MSG,
3937 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc);
3938 mpi_phy_start_resp(pm8001_ha, piomb);
3939 break;
3940 case OPC_OUB_PHY_STOP_RESP:
3941 pm8001_dbg(pm8001_ha, MSG,
3942 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc);
3943 mpi_phy_stop_resp(pm8001_ha, piomb);
3944 break;
3945 case OPC_OUB_SET_CONTROLLER_CONFIG:
3946 pm8001_dbg(pm8001_ha, MSG,
3947 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc);
3948 mpi_set_controller_config_resp(pm8001_ha, piomb);
3949 break;
3950 case OPC_OUB_GET_CONTROLLER_CONFIG:
3951 pm8001_dbg(pm8001_ha, MSG,
3952 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc);
3953 mpi_get_controller_config_resp(pm8001_ha, piomb);
3954 break;
3955 case OPC_OUB_GET_PHY_PROFILE:
3956 pm8001_dbg(pm8001_ha, MSG,
3957 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc);
3958 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3959 break;
3960 case OPC_OUB_FLASH_OP_EXT:
3961 pm8001_dbg(pm8001_ha, MSG,
3962 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc);
3963 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3964 break;
3965 case OPC_OUB_SET_PHY_PROFILE:
3966 pm8001_dbg(pm8001_ha, MSG,
3967 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc);
3968 mpi_set_phy_profile_resp(pm8001_ha, piomb);
3969 break;
3970 case OPC_OUB_KEK_MANAGEMENT_RESP:
3971 pm8001_dbg(pm8001_ha, MSG,
3972 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc);
3973 mpi_kek_management_resp(pm8001_ha, piomb);
3974 break;
3975 case OPC_OUB_DEK_MANAGEMENT_RESP:
3976 pm8001_dbg(pm8001_ha, MSG,
3977 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc);
3978 mpi_dek_management_resp(pm8001_ha, piomb);
3979 break;
3980 case OPC_OUB_SSP_COALESCED_COMP_RESP:
3981 pm8001_dbg(pm8001_ha, MSG,
3982 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc);
3983 ssp_coalesced_comp_resp(pm8001_ha, piomb);
3984 break;
3985 default:
3986 pm8001_dbg(pm8001_ha, DEVIO,
3987 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc);
3988 break;
3989 }
3990 }
3991
print_scratchpad_registers(struct pm8001_hba_info * pm8001_ha)3992 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
3993 {
3994 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_0: 0x%x\n",
3995 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));
3996 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_1:0x%x\n",
3997 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1));
3998 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_2: 0x%x\n",
3999 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2));
4000 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_3: 0x%x\n",
4001 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));
4002 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
4003 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0));
4004 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
4005 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1));
4006 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
4007 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2));
4008 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
4009 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3));
4010 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
4011 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4));
4012 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
4013 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5));
4014 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
4015 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_0));
4016 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
4017 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_1));
4018 }
4019
process_oq(struct pm8001_hba_info * pm8001_ha,u8 vec)4020 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4021 {
4022 struct outbound_queue_table *circularQ;
4023 void *pMsg1 = NULL;
4024 u8 bc;
4025 u32 ret = MPI_IO_STATUS_FAIL;
4026 u32 regval;
4027
4028 /*
4029 * Fatal errors are programmed to be signalled in irq vector
4030 * pm8001_ha->max_q_num - 1 through pm8001_ha->main_cfg_tbl.pm80xx_tbl.
4031 * fatal_err_interrupt
4032 */
4033 if (vec == (pm8001_ha->max_q_num - 1)) {
4034 u32 mipsall_ready;
4035
4036 if (pm8001_ha->chip_id == chip_8008 ||
4037 pm8001_ha->chip_id == chip_8009)
4038 mipsall_ready = SCRATCH_PAD_MIPSALL_READY_8PORT;
4039 else
4040 mipsall_ready = SCRATCH_PAD_MIPSALL_READY_16PORT;
4041
4042 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
4043 if ((regval & mipsall_ready) != mipsall_ready) {
4044 pm8001_ha->controller_fatal_error = true;
4045 pm8001_dbg(pm8001_ha, FAIL,
4046 "Firmware Fatal error! Regval:0x%x\n",
4047 regval);
4048 pm8001_handle_event(pm8001_ha, NULL, IO_FATAL_ERROR);
4049 print_scratchpad_registers(pm8001_ha);
4050 return ret;
4051 } else {
4052 /*read scratchpad rsvd 0 register*/
4053 regval = pm8001_cr32(pm8001_ha, 0,
4054 MSGU_SCRATCH_PAD_RSVD_0);
4055 switch (regval) {
4056 case NON_FATAL_SPBC_LBUS_ECC_ERR:
4057 case NON_FATAL_BDMA_ERR:
4058 case NON_FATAL_THERM_OVERTEMP_ERR:
4059 /*Clear the register*/
4060 pm8001_cw32(pm8001_ha, 0,
4061 MSGU_SCRATCH_PAD_RSVD_0,
4062 0x00000000);
4063 break;
4064 default:
4065 break;
4066 }
4067 }
4068 }
4069 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4070 spin_lock_irqsave(&circularQ->oq_lock, circularQ->lock_flags);
4071 do {
4072 /* spurious interrupt during setup if kexec-ing and
4073 * driver doing a doorbell access w/ the pre-kexec oq
4074 * interrupt setup.
4075 */
4076 if (!circularQ->pi_virt)
4077 break;
4078 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4079 if (MPI_IO_STATUS_SUCCESS == ret) {
4080 /* process the outbound message */
4081 process_one_iomb(pm8001_ha, circularQ,
4082 (void *)(pMsg1 - 4));
4083 /* free the message from the outbound circular buffer */
4084 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4085 circularQ, bc);
4086 }
4087 if (MPI_IO_STATUS_BUSY == ret) {
4088 /* Update the producer index from SPC */
4089 circularQ->producer_index =
4090 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4091 if (le32_to_cpu(circularQ->producer_index) ==
4092 circularQ->consumer_idx)
4093 /* OQ is empty */
4094 break;
4095 }
4096 } while (1);
4097 spin_unlock_irqrestore(&circularQ->oq_lock, circularQ->lock_flags);
4098 return ret;
4099 }
4100
4101 /* DMA_... to our direction translation. */
4102 static const u8 data_dir_flags[] = {
4103 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
4104 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */
4105 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */
4106 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */
4107 };
4108
build_smp_cmd(u32 deviceID,__le32 hTag,struct smp_req * psmp_cmd,int mode,int length)4109 static void build_smp_cmd(u32 deviceID, __le32 hTag,
4110 struct smp_req *psmp_cmd, int mode, int length)
4111 {
4112 psmp_cmd->tag = hTag;
4113 psmp_cmd->device_id = cpu_to_le32(deviceID);
4114 if (mode == SMP_DIRECT) {
4115 length = length - 4; /* subtract crc */
4116 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
4117 } else {
4118 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4119 }
4120 }
4121
4122 /**
4123 * pm80xx_chip_smp_req - send an SMP task to FW
4124 * @pm8001_ha: our hba card information.
4125 * @ccb: the ccb information this request used.
4126 */
pm80xx_chip_smp_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)4127 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4128 struct pm8001_ccb_info *ccb)
4129 {
4130 int elem, rc;
4131 struct sas_task *task = ccb->task;
4132 struct domain_device *dev = task->dev;
4133 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4134 struct scatterlist *sg_req, *sg_resp, *smp_req;
4135 u32 req_len, resp_len;
4136 struct smp_req smp_cmd;
4137 u32 opc;
4138 u32 i, length;
4139 u8 *payload;
4140 u8 *to;
4141
4142 memset(&smp_cmd, 0, sizeof(smp_cmd));
4143 /*
4144 * DMA-map SMP request, response buffers
4145 */
4146 sg_req = &task->smp_task.smp_req;
4147 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4148 if (!elem)
4149 return -ENOMEM;
4150 req_len = sg_dma_len(sg_req);
4151
4152 sg_resp = &task->smp_task.smp_resp;
4153 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4154 if (!elem) {
4155 rc = -ENOMEM;
4156 goto err_out;
4157 }
4158 resp_len = sg_dma_len(sg_resp);
4159 /* must be in dwords */
4160 if ((req_len & 0x3) || (resp_len & 0x3)) {
4161 rc = -EINVAL;
4162 goto err_out_2;
4163 }
4164
4165 opc = OPC_INB_SMP_REQUEST;
4166 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4167
4168 length = sg_req->length;
4169 pm8001_dbg(pm8001_ha, IO, "SMP Frame Length %d\n", sg_req->length);
4170 if (!(length - 8))
4171 pm8001_ha->smp_exp_mode = SMP_DIRECT;
4172 else
4173 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
4174
4175
4176 smp_req = &task->smp_task.smp_req;
4177 to = kmap_atomic(sg_page(smp_req));
4178 payload = to + smp_req->offset;
4179
4180 /* INDIRECT MODE command settings. Use DMA */
4181 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
4182 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST INDIRECT MODE\n");
4183 /* for SPCv indirect mode. Place the top 4 bytes of
4184 * SMP Request header here. */
4185 for (i = 0; i < 4; i++)
4186 smp_cmd.smp_req16[i] = *(payload + i);
4187 /* exclude top 4 bytes for SMP req header */
4188 smp_cmd.long_smp_req.long_req_addr =
4189 cpu_to_le64((u64)sg_dma_address
4190 (&task->smp_task.smp_req) + 4);
4191 /* exclude 4 bytes for SMP req header and CRC */
4192 smp_cmd.long_smp_req.long_req_size =
4193 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
4194 smp_cmd.long_smp_req.long_resp_addr =
4195 cpu_to_le64((u64)sg_dma_address
4196 (&task->smp_task.smp_resp));
4197 smp_cmd.long_smp_req.long_resp_size =
4198 cpu_to_le32((u32)sg_dma_len
4199 (&task->smp_task.smp_resp)-4);
4200 } else { /* DIRECT MODE */
4201 smp_cmd.long_smp_req.long_req_addr =
4202 cpu_to_le64((u64)sg_dma_address
4203 (&task->smp_task.smp_req));
4204 smp_cmd.long_smp_req.long_req_size =
4205 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4206 smp_cmd.long_smp_req.long_resp_addr =
4207 cpu_to_le64((u64)sg_dma_address
4208 (&task->smp_task.smp_resp));
4209 smp_cmd.long_smp_req.long_resp_size =
4210 cpu_to_le32
4211 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4212 }
4213 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
4214 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST DIRECT MODE\n");
4215 for (i = 0; i < length; i++)
4216 if (i < 16) {
4217 smp_cmd.smp_req16[i] = *(payload + i);
4218 pm8001_dbg(pm8001_ha, IO,
4219 "Byte[%d]:%x (DMA data:%x)\n",
4220 i, smp_cmd.smp_req16[i],
4221 *(payload));
4222 } else {
4223 smp_cmd.smp_req[i] = *(payload + i);
4224 pm8001_dbg(pm8001_ha, IO,
4225 "Byte[%d]:%x (DMA data:%x)\n",
4226 i, smp_cmd.smp_req[i],
4227 *(payload));
4228 }
4229 }
4230 kunmap_atomic(to);
4231 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
4232 &smp_cmd, pm8001_ha->smp_exp_mode, length);
4233 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &smp_cmd,
4234 sizeof(smp_cmd), 0);
4235 if (rc)
4236 goto err_out_2;
4237 return 0;
4238
4239 err_out_2:
4240 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4241 DMA_FROM_DEVICE);
4242 err_out:
4243 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4244 DMA_TO_DEVICE);
4245 return rc;
4246 }
4247
check_enc_sas_cmd(struct sas_task * task)4248 static int check_enc_sas_cmd(struct sas_task *task)
4249 {
4250 u8 cmd = task->ssp_task.cmd->cmnd[0];
4251
4252 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
4253 return 1;
4254 else
4255 return 0;
4256 }
4257
check_enc_sat_cmd(struct sas_task * task)4258 static int check_enc_sat_cmd(struct sas_task *task)
4259 {
4260 int ret = 0;
4261 switch (task->ata_task.fis.command) {
4262 case ATA_CMD_FPDMA_READ:
4263 case ATA_CMD_READ_EXT:
4264 case ATA_CMD_READ:
4265 case ATA_CMD_FPDMA_WRITE:
4266 case ATA_CMD_WRITE_EXT:
4267 case ATA_CMD_WRITE:
4268 case ATA_CMD_PIO_READ:
4269 case ATA_CMD_PIO_READ_EXT:
4270 case ATA_CMD_PIO_WRITE:
4271 case ATA_CMD_PIO_WRITE_EXT:
4272 ret = 1;
4273 break;
4274 default:
4275 ret = 0;
4276 break;
4277 }
4278 return ret;
4279 }
4280
pm80xx_chip_get_q_index(struct sas_task * task)4281 static u32 pm80xx_chip_get_q_index(struct sas_task *task)
4282 {
4283 struct request *rq = sas_task_find_rq(task);
4284
4285 if (!rq)
4286 return 0;
4287
4288 return blk_mq_unique_tag_to_hwq(blk_mq_unique_tag(rq));
4289 }
4290
4291 /**
4292 * pm80xx_chip_ssp_io_req - send an SSP task to FW
4293 * @pm8001_ha: our hba card information.
4294 * @ccb: the ccb information this request used.
4295 */
pm80xx_chip_ssp_io_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)4296 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4297 struct pm8001_ccb_info *ccb)
4298 {
4299 struct sas_task *task = ccb->task;
4300 struct domain_device *dev = task->dev;
4301 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4302 struct ssp_ini_io_start_req ssp_cmd;
4303 u32 tag = ccb->ccb_tag;
4304 u64 phys_addr, end_addr;
4305 u32 end_addr_high, end_addr_low;
4306 u32 q_index;
4307 u32 opc = OPC_INB_SSPINIIOSTART;
4308
4309 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4310 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4311
4312 /* data address domain added for spcv; set to 0 by host,
4313 * used internally by controller
4314 * 0 for SAS 1.1 and SAS 2.0 compatible TLR
4315 */
4316 ssp_cmd.dad_dir_m_tlr =
4317 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
4318 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4319 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4320 ssp_cmd.tag = cpu_to_le32(tag);
4321 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4322 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4323 task->ssp_task.cmd->cmd_len);
4324 q_index = pm80xx_chip_get_q_index(task);
4325
4326 /* Check if encryption is set */
4327 if (pm8001_ha->chip->encrypt &&
4328 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
4329 pm8001_dbg(pm8001_ha, IO,
4330 "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
4331 task->ssp_task.cmd->cmnd[0]);
4332 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
4333 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
4334 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
4335 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
4336
4337 /* fill in PRD (scatter/gather) table, if any */
4338 if (task->num_scatter > 1) {
4339 pm8001_chip_make_sg(task->scatter,
4340 ccb->n_elem, ccb->buf_prd);
4341 phys_addr = ccb->ccb_dma_handle;
4342 ssp_cmd.enc_addr_low =
4343 cpu_to_le32(lower_32_bits(phys_addr));
4344 ssp_cmd.enc_addr_high =
4345 cpu_to_le32(upper_32_bits(phys_addr));
4346 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4347 } else if (task->num_scatter == 1) {
4348 u64 dma_addr = sg_dma_address(task->scatter);
4349
4350 ssp_cmd.enc_addr_low =
4351 cpu_to_le32(lower_32_bits(dma_addr));
4352 ssp_cmd.enc_addr_high =
4353 cpu_to_le32(upper_32_bits(dma_addr));
4354 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4355 ssp_cmd.enc_esgl = 0;
4356
4357 /* Check 4G Boundary */
4358 end_addr = dma_addr + le32_to_cpu(ssp_cmd.enc_len) - 1;
4359 end_addr_low = lower_32_bits(end_addr);
4360 end_addr_high = upper_32_bits(end_addr);
4361
4362 if (end_addr_high != le32_to_cpu(ssp_cmd.enc_addr_high)) {
4363 pm8001_dbg(pm8001_ha, FAIL,
4364 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4365 dma_addr,
4366 le32_to_cpu(ssp_cmd.enc_len),
4367 end_addr_high, end_addr_low);
4368 pm8001_chip_make_sg(task->scatter, 1,
4369 ccb->buf_prd);
4370 phys_addr = ccb->ccb_dma_handle;
4371 ssp_cmd.enc_addr_low =
4372 cpu_to_le32(lower_32_bits(phys_addr));
4373 ssp_cmd.enc_addr_high =
4374 cpu_to_le32(upper_32_bits(phys_addr));
4375 ssp_cmd.enc_esgl = cpu_to_le32(1U<<31);
4376 }
4377 } else if (task->num_scatter == 0) {
4378 ssp_cmd.enc_addr_low = 0;
4379 ssp_cmd.enc_addr_high = 0;
4380 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4381 ssp_cmd.enc_esgl = 0;
4382 }
4383
4384 /* XTS mode. All other fields are 0 */
4385 ssp_cmd.key_cmode = cpu_to_le32(0x6 << 4);
4386
4387 /* set tweak values. Should be the start lba */
4388 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4389 (task->ssp_task.cmd->cmnd[3] << 16) |
4390 (task->ssp_task.cmd->cmnd[4] << 8) |
4391 (task->ssp_task.cmd->cmnd[5]));
4392 } else {
4393 pm8001_dbg(pm8001_ha, IO,
4394 "Sending Normal SAS command 0x%x inb q %x\n",
4395 task->ssp_task.cmd->cmnd[0], q_index);
4396 /* fill in PRD (scatter/gather) table, if any */
4397 if (task->num_scatter > 1) {
4398 pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4399 ccb->buf_prd);
4400 phys_addr = ccb->ccb_dma_handle;
4401 ssp_cmd.addr_low =
4402 cpu_to_le32(lower_32_bits(phys_addr));
4403 ssp_cmd.addr_high =
4404 cpu_to_le32(upper_32_bits(phys_addr));
4405 ssp_cmd.esgl = cpu_to_le32(1<<31);
4406 } else if (task->num_scatter == 1) {
4407 u64 dma_addr = sg_dma_address(task->scatter);
4408
4409 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4410 ssp_cmd.addr_high =
4411 cpu_to_le32(upper_32_bits(dma_addr));
4412 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4413 ssp_cmd.esgl = 0;
4414
4415 /* Check 4G Boundary */
4416 end_addr = dma_addr + le32_to_cpu(ssp_cmd.len) - 1;
4417 end_addr_low = lower_32_bits(end_addr);
4418 end_addr_high = upper_32_bits(end_addr);
4419 if (end_addr_high != le32_to_cpu(ssp_cmd.addr_high)) {
4420 pm8001_dbg(pm8001_ha, FAIL,
4421 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4422 dma_addr,
4423 le32_to_cpu(ssp_cmd.len),
4424 end_addr_high, end_addr_low);
4425 pm8001_chip_make_sg(task->scatter, 1,
4426 ccb->buf_prd);
4427 phys_addr = ccb->ccb_dma_handle;
4428 ssp_cmd.addr_low =
4429 cpu_to_le32(lower_32_bits(phys_addr));
4430 ssp_cmd.addr_high =
4431 cpu_to_le32(upper_32_bits(phys_addr));
4432 ssp_cmd.esgl = cpu_to_le32(1<<31);
4433 }
4434 } else if (task->num_scatter == 0) {
4435 ssp_cmd.addr_low = 0;
4436 ssp_cmd.addr_high = 0;
4437 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4438 ssp_cmd.esgl = 0;
4439 }
4440 }
4441
4442 return pm8001_mpi_build_cmd(pm8001_ha, q_index, opc, &ssp_cmd,
4443 sizeof(ssp_cmd), q_index);
4444 }
4445
pm80xx_chip_sata_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)4446 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4447 struct pm8001_ccb_info *ccb)
4448 {
4449 struct sas_task *task = ccb->task;
4450 struct domain_device *dev = task->dev;
4451 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4452 struct ata_queued_cmd *qc = task->uldd_task;
4453 u32 tag = ccb->ccb_tag, q_index;
4454 struct sata_start_req sata_cmd;
4455 u32 hdr_tag, ncg_tag = 0;
4456 u64 phys_addr, end_addr;
4457 u32 end_addr_high, end_addr_low;
4458 u32 ATAP = 0x0;
4459 u32 dir, retfis = 0;
4460 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4461 memset(&sata_cmd, 0, sizeof(sata_cmd));
4462
4463 q_index = pm80xx_chip_get_q_index(task);
4464
4465 if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) {
4466 ATAP = 0x04; /* no data*/
4467 pm8001_dbg(pm8001_ha, IO, "no data\n");
4468 } else if (likely(!task->ata_task.device_control_reg_update)) {
4469 if (task->ata_task.use_ncq &&
4470 dev->sata_dev.class != ATA_DEV_ATAPI) {
4471 ATAP = 0x07; /* FPDMA */
4472 pm8001_dbg(pm8001_ha, IO, "FPDMA\n");
4473 } else if (task->ata_task.dma_xfer) {
4474 ATAP = 0x06; /* DMA */
4475 pm8001_dbg(pm8001_ha, IO, "DMA\n");
4476 } else {
4477 ATAP = 0x05; /* PIO*/
4478 pm8001_dbg(pm8001_ha, IO, "PIO\n");
4479 }
4480 }
4481 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4482 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4483 ncg_tag = hdr_tag;
4484 }
4485 dir = data_dir_flags[task->data_dir] << 8;
4486 sata_cmd.tag = cpu_to_le32(tag);
4487 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4488 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4489 if (task->ata_task.return_fis_on_success)
4490 retfis = 1;
4491 sata_cmd.sata_fis = task->ata_task.fis;
4492 if (likely(!task->ata_task.device_control_reg_update))
4493 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4494 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4495
4496 /* Check if encryption is set */
4497 if (pm8001_ha->chip->encrypt &&
4498 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4499 pm8001_dbg(pm8001_ha, IO,
4500 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4501 sata_cmd.sata_fis.command);
4502 opc = OPC_INB_SATA_DIF_ENC_IO;
4503 /* set encryption bit; dad (bits 0-1) is 0 */
4504 sata_cmd.retfis_ncqtag_atap_dir_m_dad =
4505 cpu_to_le32((retfis << 24) | ((ncg_tag & 0xff) << 16) |
4506 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4507 /* fill in PRD (scatter/gather) table, if any */
4508 if (task->num_scatter > 1) {
4509 pm8001_chip_make_sg(task->scatter,
4510 ccb->n_elem, ccb->buf_prd);
4511 phys_addr = ccb->ccb_dma_handle;
4512 sata_cmd.enc_addr_low =
4513 cpu_to_le32(lower_32_bits(phys_addr));
4514 sata_cmd.enc_addr_high =
4515 cpu_to_le32(upper_32_bits(phys_addr));
4516 sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4517 } else if (task->num_scatter == 1) {
4518 u64 dma_addr = sg_dma_address(task->scatter);
4519
4520 sata_cmd.enc_addr_low =
4521 cpu_to_le32(lower_32_bits(dma_addr));
4522 sata_cmd.enc_addr_high =
4523 cpu_to_le32(upper_32_bits(dma_addr));
4524 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4525 sata_cmd.enc_esgl = 0;
4526
4527 /* Check 4G Boundary */
4528 end_addr = dma_addr + le32_to_cpu(sata_cmd.enc_len) - 1;
4529 end_addr_low = lower_32_bits(end_addr);
4530 end_addr_high = upper_32_bits(end_addr);
4531 if (end_addr_high != le32_to_cpu(sata_cmd.enc_addr_high)) {
4532 pm8001_dbg(pm8001_ha, FAIL,
4533 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4534 dma_addr,
4535 le32_to_cpu(sata_cmd.enc_len),
4536 end_addr_high, end_addr_low);
4537 pm8001_chip_make_sg(task->scatter, 1,
4538 ccb->buf_prd);
4539 phys_addr = ccb->ccb_dma_handle;
4540 sata_cmd.enc_addr_low =
4541 cpu_to_le32(lower_32_bits(phys_addr));
4542 sata_cmd.enc_addr_high =
4543 cpu_to_le32(upper_32_bits(phys_addr));
4544 sata_cmd.enc_esgl =
4545 cpu_to_le32(1 << 31);
4546 }
4547 } else if (task->num_scatter == 0) {
4548 sata_cmd.enc_addr_low = 0;
4549 sata_cmd.enc_addr_high = 0;
4550 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4551 sata_cmd.enc_esgl = 0;
4552 }
4553 /* XTS mode. All other fields are 0 */
4554 sata_cmd.key_index_mode = cpu_to_le32(0x6 << 4);
4555
4556 /* set tweak values. Should be the start lba */
4557 sata_cmd.twk_val0 =
4558 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4559 (sata_cmd.sata_fis.lbah << 16) |
4560 (sata_cmd.sata_fis.lbam << 8) |
4561 (sata_cmd.sata_fis.lbal));
4562 sata_cmd.twk_val1 =
4563 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4564 (sata_cmd.sata_fis.lbam_exp));
4565 } else {
4566 pm8001_dbg(pm8001_ha, IO,
4567 "Sending Normal SATA command 0x%x inb %x\n",
4568 sata_cmd.sata_fis.command, q_index);
4569 /* dad (bits 0-1) is 0 */
4570 sata_cmd.retfis_ncqtag_atap_dir_m_dad =
4571 cpu_to_le32((retfis << 24) | ((ncg_tag & 0xff) << 16) |
4572 ((ATAP & 0x3f) << 10) | dir);
4573 /* fill in PRD (scatter/gather) table, if any */
4574 if (task->num_scatter > 1) {
4575 pm8001_chip_make_sg(task->scatter,
4576 ccb->n_elem, ccb->buf_prd);
4577 phys_addr = ccb->ccb_dma_handle;
4578 sata_cmd.addr_low = lower_32_bits(phys_addr);
4579 sata_cmd.addr_high = upper_32_bits(phys_addr);
4580 sata_cmd.esgl = cpu_to_le32(1U << 31);
4581 } else if (task->num_scatter == 1) {
4582 u64 dma_addr = sg_dma_address(task->scatter);
4583
4584 sata_cmd.addr_low = lower_32_bits(dma_addr);
4585 sata_cmd.addr_high = upper_32_bits(dma_addr);
4586 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4587 sata_cmd.esgl = 0;
4588
4589 /* Check 4G Boundary */
4590 end_addr = dma_addr + le32_to_cpu(sata_cmd.len) - 1;
4591 end_addr_low = lower_32_bits(end_addr);
4592 end_addr_high = upper_32_bits(end_addr);
4593 if (end_addr_high != sata_cmd.addr_high) {
4594 pm8001_dbg(pm8001_ha, FAIL,
4595 "The sg list address start_addr=0x%016llx data_len=0x%xend_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4596 dma_addr,
4597 le32_to_cpu(sata_cmd.len),
4598 end_addr_high, end_addr_low);
4599 pm8001_chip_make_sg(task->scatter, 1,
4600 ccb->buf_prd);
4601 phys_addr = ccb->ccb_dma_handle;
4602 sata_cmd.addr_low = lower_32_bits(phys_addr);
4603 sata_cmd.addr_high = upper_32_bits(phys_addr);
4604 sata_cmd.esgl = cpu_to_le32(1U << 31);
4605 }
4606 } else if (task->num_scatter == 0) {
4607 sata_cmd.addr_low = 0;
4608 sata_cmd.addr_high = 0;
4609 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4610 sata_cmd.esgl = 0;
4611 }
4612
4613 /* scsi cdb */
4614 sata_cmd.atapi_scsi_cdb[0] =
4615 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4616 (task->ata_task.atapi_packet[1] << 8) |
4617 (task->ata_task.atapi_packet[2] << 16) |
4618 (task->ata_task.atapi_packet[3] << 24)));
4619 sata_cmd.atapi_scsi_cdb[1] =
4620 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4621 (task->ata_task.atapi_packet[5] << 8) |
4622 (task->ata_task.atapi_packet[6] << 16) |
4623 (task->ata_task.atapi_packet[7] << 24)));
4624 sata_cmd.atapi_scsi_cdb[2] =
4625 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4626 (task->ata_task.atapi_packet[9] << 8) |
4627 (task->ata_task.atapi_packet[10] << 16) |
4628 (task->ata_task.atapi_packet[11] << 24)));
4629 sata_cmd.atapi_scsi_cdb[3] =
4630 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4631 (task->ata_task.atapi_packet[13] << 8) |
4632 (task->ata_task.atapi_packet[14] << 16) |
4633 (task->ata_task.atapi_packet[15] << 24)));
4634 }
4635
4636 trace_pm80xx_request_issue(pm8001_ha->id,
4637 ccb->device ? ccb->device->attached_phy : PM8001_MAX_PHYS,
4638 ccb->ccb_tag, opc,
4639 qc ? qc->tf.command : 0, // ata opcode
4640 ccb->device ? atomic_read(&ccb->device->running_req) : 0);
4641 return pm8001_mpi_build_cmd(pm8001_ha, q_index, opc, &sata_cmd,
4642 sizeof(sata_cmd), q_index);
4643 }
4644
4645 /**
4646 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4647 * @pm8001_ha: our hba card information.
4648 * @phy_id: the phy id which we wanted to start up.
4649 */
4650 static int
pm80xx_chip_phy_start_req(struct pm8001_hba_info * pm8001_ha,u8 phy_id)4651 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4652 {
4653 struct phy_start_req payload;
4654 u32 tag = 0x01;
4655 u32 opcode = OPC_INB_PHYSTART;
4656
4657 memset(&payload, 0, sizeof(payload));
4658 payload.tag = cpu_to_le32(tag);
4659
4660 pm8001_dbg(pm8001_ha, INIT, "PHY START REQ for phy_id %d\n", phy_id);
4661
4662 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4663 LINKMODE_AUTO | pm8001_ha->link_rate | phy_id);
4664 /* SSC Disable and SAS Analog ST configuration */
4665 /*
4666 payload.ase_sh_lm_slr_phyid =
4667 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4668 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4669 phy_id);
4670 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4671 */
4672
4673 payload.sas_identify.dev_type = SAS_END_DEVICE;
4674 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4675 memcpy(payload.sas_identify.sas_addr,
4676 &pm8001_ha->phy[phy_id].dev_sas_addr, SAS_ADDR_SIZE);
4677 payload.sas_identify.phy_id = phy_id;
4678
4679 return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload,
4680 sizeof(payload), 0);
4681 }
4682
4683 /**
4684 * pm80xx_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4685 * @pm8001_ha: our hba card information.
4686 * @phy_id: the phy id which we wanted to start up.
4687 */
pm80xx_chip_phy_stop_req(struct pm8001_hba_info * pm8001_ha,u8 phy_id)4688 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4689 u8 phy_id)
4690 {
4691 struct phy_stop_req payload;
4692 u32 tag = 0x01;
4693 u32 opcode = OPC_INB_PHYSTOP;
4694
4695 memset(&payload, 0, sizeof(payload));
4696 payload.tag = cpu_to_le32(tag);
4697 payload.phy_id = cpu_to_le32(phy_id);
4698
4699 return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload,
4700 sizeof(payload), 0);
4701 }
4702
4703 /*
4704 * see comments on pm8001_mpi_reg_resp.
4705 */
pm80xx_chip_reg_dev_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_device * pm8001_dev,u32 flag)4706 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4707 struct pm8001_device *pm8001_dev, u32 flag)
4708 {
4709 struct reg_dev_req payload;
4710 u32 opc;
4711 u32 stp_sspsmp_sata = 0x4;
4712 u32 linkrate, phy_id;
4713 int rc;
4714 struct pm8001_ccb_info *ccb;
4715 u8 retryFlag = 0x1;
4716 u16 firstBurstSize = 0;
4717 u16 ITNT = 2000;
4718 struct domain_device *dev = pm8001_dev->sas_device;
4719 struct domain_device *parent_dev = dev->parent;
4720 struct pm8001_port *port = dev->port->lldd_port;
4721
4722 memset(&payload, 0, sizeof(payload));
4723 ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_dev, NULL);
4724 if (!ccb)
4725 return -SAS_QUEUE_FULL;
4726
4727 payload.tag = cpu_to_le32(ccb->ccb_tag);
4728
4729 if (flag == 1) {
4730 stp_sspsmp_sata = 0x02; /*direct attached sata */
4731 } else {
4732 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4733 stp_sspsmp_sata = 0x00; /* stp*/
4734 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4735 dev_is_expander(pm8001_dev->dev_type))
4736 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4737 }
4738 if (parent_dev && dev_is_expander(parent_dev->dev_type))
4739 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4740 else
4741 phy_id = pm8001_dev->attached_phy;
4742
4743 opc = OPC_INB_REG_DEV;
4744
4745 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4746 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4747
4748 payload.phyid_portid =
4749 cpu_to_le32(((port->port_id) & 0xFF) |
4750 ((phy_id & 0xFF) << 8));
4751
4752 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4753 ((linkrate & 0x0F) << 24) |
4754 ((stp_sspsmp_sata & 0x03) << 28));
4755 payload.firstburstsize_ITNexustimeout =
4756 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4757
4758 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4759 SAS_ADDR_SIZE);
4760
4761 pm8001_dbg(pm8001_ha, INIT,
4762 "register device req phy_id 0x%x port_id 0x%x\n", phy_id,
4763 (port->port_id & 0xFF));
4764 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4765 sizeof(payload), 0);
4766 if (rc)
4767 pm8001_ccb_free(pm8001_ha, ccb);
4768
4769 return rc;
4770 }
4771
4772 /**
4773 * pm80xx_chip_phy_ctl_req - support the local phy operation
4774 * @pm8001_ha: our hba card information.
4775 * @phyId: the phy id which we wanted to operate
4776 * @phy_op: phy operation to request
4777 */
pm80xx_chip_phy_ctl_req(struct pm8001_hba_info * pm8001_ha,u32 phyId,u32 phy_op)4778 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4779 u32 phyId, u32 phy_op)
4780 {
4781 u32 tag;
4782 int rc;
4783 struct local_phy_ctl_req payload;
4784 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4785
4786 memset(&payload, 0, sizeof(payload));
4787 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4788 if (rc)
4789 return rc;
4790
4791 payload.tag = cpu_to_le32(tag);
4792 payload.phyop_phyid =
4793 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4794
4795 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4796 sizeof(payload), 0);
4797 if (rc)
4798 pm8001_tag_free(pm8001_ha, tag);
4799
4800 return rc;
4801 }
4802
pm80xx_chip_is_our_interrupt(struct pm8001_hba_info * pm8001_ha)4803 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4804 {
4805 #ifdef PM8001_USE_MSIX
4806 return 1;
4807 #else
4808 u32 value;
4809
4810 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4811 if (value)
4812 return 1;
4813 return 0;
4814 #endif
4815 }
4816
4817 /**
4818 * pm80xx_chip_isr - PM8001 isr handler.
4819 * @pm8001_ha: our hba card information.
4820 * @vec: irq number.
4821 */
4822 static irqreturn_t
pm80xx_chip_isr(struct pm8001_hba_info * pm8001_ha,u8 vec)4823 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4824 {
4825 pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4826 pm8001_dbg(pm8001_ha, DEVIO,
4827 "irq vec %d, ODMR:0x%x\n",
4828 vec, pm8001_cr32(pm8001_ha, 0, 0x30));
4829 process_oq(pm8001_ha, vec);
4830 pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4831 return IRQ_HANDLED;
4832 }
4833
mpi_set_phy_profile_req(struct pm8001_hba_info * pm8001_ha,u32 operation,u32 phyid,u32 length,u32 * buf)4834 static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4835 u32 operation, u32 phyid,
4836 u32 length, u32 *buf)
4837 {
4838 u32 tag, i, j = 0;
4839 int rc;
4840 struct set_phy_profile_req payload;
4841 u32 opc = OPC_INB_SET_PHY_PROFILE;
4842
4843 memset(&payload, 0, sizeof(payload));
4844 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4845 if (rc) {
4846 pm8001_dbg(pm8001_ha, FAIL, "Invalid tag\n");
4847 return;
4848 }
4849
4850 payload.tag = cpu_to_le32(tag);
4851 payload.ppc_phyid =
4852 cpu_to_le32(((operation & 0xF) << 8) | (phyid & 0xFF));
4853 pm8001_dbg(pm8001_ha, DISC,
4854 " phy profile command for phy %x ,length is %d\n",
4855 le32_to_cpu(payload.ppc_phyid), length);
4856 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4857 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i));
4858 j++;
4859 }
4860 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4861 sizeof(payload), 0);
4862 if (rc)
4863 pm8001_tag_free(pm8001_ha, tag);
4864 }
4865
pm8001_set_phy_profile(struct pm8001_hba_info * pm8001_ha,u32 length,u8 * buf)4866 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4867 u32 length, u8 *buf)
4868 {
4869 u32 i;
4870
4871 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4872 mpi_set_phy_profile_req(pm8001_ha,
4873 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4874 length = length + PHY_DWORD_LENGTH;
4875 }
4876 pm8001_dbg(pm8001_ha, INIT, "phy settings completed\n");
4877 }
4878
pm8001_set_phy_profile_single(struct pm8001_hba_info * pm8001_ha,u32 phy,u32 length,u32 * buf)4879 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
4880 u32 phy, u32 length, u32 *buf)
4881 {
4882 u32 tag, opc;
4883 int rc, i;
4884 struct set_phy_profile_req payload;
4885
4886 memset(&payload, 0, sizeof(payload));
4887
4888 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4889 if (rc) {
4890 pm8001_dbg(pm8001_ha, INIT, "Invalid tag\n");
4891 return;
4892 }
4893
4894 opc = OPC_INB_SET_PHY_PROFILE;
4895
4896 payload.tag = cpu_to_le32(tag);
4897 payload.ppc_phyid =
4898 cpu_to_le32(((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
4899 | (phy & 0xFF));
4900
4901 for (i = 0; i < length; i++)
4902 payload.reserved[i] = cpu_to_le32(*(buf + i));
4903
4904 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4905 sizeof(payload), 0);
4906 if (rc)
4907 pm8001_tag_free(pm8001_ha, tag);
4908
4909 pm8001_dbg(pm8001_ha, INIT, "PHY %d settings applied\n", phy);
4910 }
4911 const struct pm8001_dispatch pm8001_80xx_dispatch = {
4912 .name = "pmc80xx",
4913 .chip_init = pm80xx_chip_init,
4914 .chip_post_init = pm80xx_chip_post_init,
4915 .chip_soft_rst = pm80xx_chip_soft_rst,
4916 .chip_rst = pm80xx_hw_chip_rst,
4917 .chip_iounmap = pm8001_chip_iounmap,
4918 .isr = pm80xx_chip_isr,
4919 .is_our_interrupt = pm80xx_chip_is_our_interrupt,
4920 .isr_process_oq = process_oq,
4921 .interrupt_enable = pm80xx_chip_interrupt_enable,
4922 .interrupt_disable = pm80xx_chip_interrupt_disable,
4923 .make_prd = pm8001_chip_make_sg,
4924 .smp_req = pm80xx_chip_smp_req,
4925 .ssp_io_req = pm80xx_chip_ssp_io_req,
4926 .sata_req = pm80xx_chip_sata_req,
4927 .phy_start_req = pm80xx_chip_phy_start_req,
4928 .phy_stop_req = pm80xx_chip_phy_stop_req,
4929 .reg_dev_req = pm80xx_chip_reg_dev_req,
4930 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4931 .phy_ctl_req = pm80xx_chip_phy_ctl_req,
4932 .task_abort = pm8001_chip_abort_task,
4933 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4934 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4935 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4936 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4937 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4938 .fatal_errors = pm80xx_fatal_errors,
4939 .hw_event_ack_req = pm80xx_hw_event_ack_req,
4940 };
4941
