1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/platform_device.h>
34 #include <linux/acpi.h>
35 #include <linux/etherdevice.h>
36 #include <linux/interrupt.h>
37 #include <linux/of.h>
38 #include <linux/of_platform.h>
39 #include <rdma/ib_umem.h>
40 #include "hns_roce_common.h"
41 #include "hns_roce_device.h"
42 #include "hns_roce_cmd.h"
43 #include "hns_roce_hem.h"
44 #include "hns_roce_hw_v1.h"
45
set_data_seg(struct hns_roce_wqe_data_seg * dseg,struct ib_sge * sg)46 static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
47 {
48 dseg->lkey = cpu_to_le32(sg->lkey);
49 dseg->addr = cpu_to_le64(sg->addr);
50 dseg->len = cpu_to_le32(sg->length);
51 }
52
set_raddr_seg(struct hns_roce_wqe_raddr_seg * rseg,u64 remote_addr,u32 rkey)53 static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
54 u32 rkey)
55 {
56 rseg->raddr = cpu_to_le64(remote_addr);
57 rseg->rkey = cpu_to_le32(rkey);
58 rseg->len = 0;
59 }
60
hns_roce_v1_post_send(struct ib_qp * ibqp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)61 static int hns_roce_v1_post_send(struct ib_qp *ibqp,
62 const struct ib_send_wr *wr,
63 const struct ib_send_wr **bad_wr)
64 {
65 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
66 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
67 struct hns_roce_ud_send_wqe *ud_sq_wqe = NULL;
68 struct hns_roce_wqe_ctrl_seg *ctrl = NULL;
69 struct hns_roce_wqe_data_seg *dseg = NULL;
70 struct hns_roce_qp *qp = to_hr_qp(ibqp);
71 struct device *dev = &hr_dev->pdev->dev;
72 struct hns_roce_sq_db sq_db;
73 int ps_opcode = 0, i = 0;
74 unsigned long flags = 0;
75 void *wqe = NULL;
76 u32 doorbell[2];
77 int nreq = 0;
78 u32 ind = 0;
79 int ret = 0;
80 u8 *smac;
81 int loopback;
82
83 if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
84 ibqp->qp_type != IB_QPT_RC)) {
85 dev_err(dev, "un-supported QP type\n");
86 *bad_wr = NULL;
87 return -EOPNOTSUPP;
88 }
89
90 spin_lock_irqsave(&qp->sq.lock, flags);
91 ind = qp->sq_next_wqe;
92 for (nreq = 0; wr; ++nreq, wr = wr->next) {
93 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
94 ret = -ENOMEM;
95 *bad_wr = wr;
96 goto out;
97 }
98
99 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
100 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
101 wr->num_sge, qp->sq.max_gs);
102 ret = -EINVAL;
103 *bad_wr = wr;
104 goto out;
105 }
106
107 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
108 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
109 wr->wr_id;
110
111 /* Corresponding to the RC and RD type wqe process separately */
112 if (ibqp->qp_type == IB_QPT_GSI) {
113 ud_sq_wqe = wqe;
114 roce_set_field(ud_sq_wqe->dmac_h,
115 UD_SEND_WQE_U32_4_DMAC_0_M,
116 UD_SEND_WQE_U32_4_DMAC_0_S,
117 ah->av.mac[0]);
118 roce_set_field(ud_sq_wqe->dmac_h,
119 UD_SEND_WQE_U32_4_DMAC_1_M,
120 UD_SEND_WQE_U32_4_DMAC_1_S,
121 ah->av.mac[1]);
122 roce_set_field(ud_sq_wqe->dmac_h,
123 UD_SEND_WQE_U32_4_DMAC_2_M,
124 UD_SEND_WQE_U32_4_DMAC_2_S,
125 ah->av.mac[2]);
126 roce_set_field(ud_sq_wqe->dmac_h,
127 UD_SEND_WQE_U32_4_DMAC_3_M,
128 UD_SEND_WQE_U32_4_DMAC_3_S,
129 ah->av.mac[3]);
130
131 roce_set_field(ud_sq_wqe->u32_8,
132 UD_SEND_WQE_U32_8_DMAC_4_M,
133 UD_SEND_WQE_U32_8_DMAC_4_S,
134 ah->av.mac[4]);
135 roce_set_field(ud_sq_wqe->u32_8,
136 UD_SEND_WQE_U32_8_DMAC_5_M,
137 UD_SEND_WQE_U32_8_DMAC_5_S,
138 ah->av.mac[5]);
139
140 smac = (u8 *)hr_dev->dev_addr[qp->port];
141 loopback = ether_addr_equal_unaligned(ah->av.mac,
142 smac) ? 1 : 0;
143 roce_set_bit(ud_sq_wqe->u32_8,
144 UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S,
145 loopback);
146
147 roce_set_field(ud_sq_wqe->u32_8,
148 UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
149 UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
150 HNS_ROCE_WQE_OPCODE_SEND);
151 roce_set_field(ud_sq_wqe->u32_8,
152 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M,
153 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S,
154 2);
155 roce_set_bit(ud_sq_wqe->u32_8,
156 UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S,
157 1);
158
159 ud_sq_wqe->u32_8 |= (wr->send_flags & IB_SEND_SIGNALED ?
160 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
161 (wr->send_flags & IB_SEND_SOLICITED ?
162 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
163 ((wr->opcode == IB_WR_SEND_WITH_IMM) ?
164 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0);
165
166 roce_set_field(ud_sq_wqe->u32_16,
167 UD_SEND_WQE_U32_16_DEST_QP_M,
168 UD_SEND_WQE_U32_16_DEST_QP_S,
169 ud_wr(wr)->remote_qpn);
170 roce_set_field(ud_sq_wqe->u32_16,
171 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M,
172 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S,
173 ah->av.stat_rate);
174
175 roce_set_field(ud_sq_wqe->u32_36,
176 UD_SEND_WQE_U32_36_FLOW_LABEL_M,
177 UD_SEND_WQE_U32_36_FLOW_LABEL_S,
178 ah->av.sl_tclass_flowlabel &
179 HNS_ROCE_FLOW_LABEL_MASK);
180 roce_set_field(ud_sq_wqe->u32_36,
181 UD_SEND_WQE_U32_36_PRIORITY_M,
182 UD_SEND_WQE_U32_36_PRIORITY_S,
183 le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
184 HNS_ROCE_SL_SHIFT);
185 roce_set_field(ud_sq_wqe->u32_36,
186 UD_SEND_WQE_U32_36_SGID_INDEX_M,
187 UD_SEND_WQE_U32_36_SGID_INDEX_S,
188 hns_get_gid_index(hr_dev, qp->phy_port,
189 ah->av.gid_index));
190
191 roce_set_field(ud_sq_wqe->u32_40,
192 UD_SEND_WQE_U32_40_HOP_LIMIT_M,
193 UD_SEND_WQE_U32_40_HOP_LIMIT_S,
194 ah->av.hop_limit);
195 roce_set_field(ud_sq_wqe->u32_40,
196 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
197 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S,
198 ah->av.sl_tclass_flowlabel >>
199 HNS_ROCE_TCLASS_SHIFT);
200
201 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
202
203 ud_sq_wqe->va0_l =
204 cpu_to_le32((u32)wr->sg_list[0].addr);
205 ud_sq_wqe->va0_h =
206 cpu_to_le32((wr->sg_list[0].addr) >> 32);
207 ud_sq_wqe->l_key0 =
208 cpu_to_le32(wr->sg_list[0].lkey);
209
210 ud_sq_wqe->va1_l =
211 cpu_to_le32((u32)wr->sg_list[1].addr);
212 ud_sq_wqe->va1_h =
213 cpu_to_le32((wr->sg_list[1].addr) >> 32);
214 ud_sq_wqe->l_key1 =
215 cpu_to_le32(wr->sg_list[1].lkey);
216 ind++;
217 } else if (ibqp->qp_type == IB_QPT_RC) {
218 u32 tmp_len = 0;
219
220 ctrl = wqe;
221 memset(ctrl, 0, sizeof(struct hns_roce_wqe_ctrl_seg));
222 for (i = 0; i < wr->num_sge; i++)
223 tmp_len += wr->sg_list[i].length;
224
225 ctrl->msg_length =
226 cpu_to_le32(le32_to_cpu(ctrl->msg_length) + tmp_len);
227
228 ctrl->sgl_pa_h = 0;
229 ctrl->flag = 0;
230
231 switch (wr->opcode) {
232 case IB_WR_SEND_WITH_IMM:
233 case IB_WR_RDMA_WRITE_WITH_IMM:
234 ctrl->imm_data = wr->ex.imm_data;
235 break;
236 case IB_WR_SEND_WITH_INV:
237 ctrl->inv_key =
238 cpu_to_le32(wr->ex.invalidate_rkey);
239 break;
240 default:
241 ctrl->imm_data = 0;
242 break;
243 }
244
245 /*Ctrl field, ctrl set type: sig, solic, imm, fence */
246 /* SO wait for conforming application scenarios */
247 ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
248 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
249 (wr->send_flags & IB_SEND_SOLICITED ?
250 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
251 ((wr->opcode == IB_WR_SEND_WITH_IMM ||
252 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) ?
253 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0) |
254 (wr->send_flags & IB_SEND_FENCE ?
255 (cpu_to_le32(HNS_ROCE_WQE_FENCE)) : 0);
256
257 wqe += sizeof(struct hns_roce_wqe_ctrl_seg);
258
259 switch (wr->opcode) {
260 case IB_WR_RDMA_READ:
261 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_READ;
262 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
263 rdma_wr(wr)->rkey);
264 break;
265 case IB_WR_RDMA_WRITE:
266 case IB_WR_RDMA_WRITE_WITH_IMM:
267 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_WRITE;
268 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
269 rdma_wr(wr)->rkey);
270 break;
271 case IB_WR_SEND:
272 case IB_WR_SEND_WITH_INV:
273 case IB_WR_SEND_WITH_IMM:
274 ps_opcode = HNS_ROCE_WQE_OPCODE_SEND;
275 break;
276 case IB_WR_LOCAL_INV:
277 break;
278 case IB_WR_ATOMIC_CMP_AND_SWP:
279 case IB_WR_ATOMIC_FETCH_AND_ADD:
280 case IB_WR_LSO:
281 default:
282 ps_opcode = HNS_ROCE_WQE_OPCODE_MASK;
283 break;
284 }
285 ctrl->flag |= cpu_to_le32(ps_opcode);
286 wqe += sizeof(struct hns_roce_wqe_raddr_seg);
287
288 dseg = wqe;
289 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
290 if (le32_to_cpu(ctrl->msg_length) >
291 hr_dev->caps.max_sq_inline) {
292 ret = -EINVAL;
293 *bad_wr = wr;
294 dev_err(dev, "inline len(1-%d)=%d, illegal",
295 ctrl->msg_length,
296 hr_dev->caps.max_sq_inline);
297 goto out;
298 }
299 for (i = 0; i < wr->num_sge; i++) {
300 memcpy(wqe, ((void *) (uintptr_t)
301 wr->sg_list[i].addr),
302 wr->sg_list[i].length);
303 wqe += wr->sg_list[i].length;
304 }
305 ctrl->flag |= cpu_to_le32(HNS_ROCE_WQE_INLINE);
306 } else {
307 /*sqe num is two */
308 for (i = 0; i < wr->num_sge; i++)
309 set_data_seg(dseg + i, wr->sg_list + i);
310
311 ctrl->flag |= cpu_to_le32(wr->num_sge <<
312 HNS_ROCE_WQE_SGE_NUM_BIT);
313 }
314 ind++;
315 }
316 }
317
318 out:
319 /* Set DB return */
320 if (likely(nreq)) {
321 qp->sq.head += nreq;
322 /* Memory barrier */
323 wmb();
324
325 sq_db.u32_4 = 0;
326 sq_db.u32_8 = 0;
327 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
328 SQ_DOORBELL_U32_4_SQ_HEAD_S,
329 (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
330 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SL_M,
331 SQ_DOORBELL_U32_4_SL_S, qp->sl);
332 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
333 SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
334 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
335 SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
336 roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
337
338 doorbell[0] = le32_to_cpu(sq_db.u32_4);
339 doorbell[1] = le32_to_cpu(sq_db.u32_8);
340
341 hns_roce_write64_k((__le32 *)doorbell, qp->sq.db_reg_l);
342 qp->sq_next_wqe = ind;
343 }
344
345 spin_unlock_irqrestore(&qp->sq.lock, flags);
346
347 return ret;
348 }
349
hns_roce_v1_post_recv(struct ib_qp * ibqp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)350 static int hns_roce_v1_post_recv(struct ib_qp *ibqp,
351 const struct ib_recv_wr *wr,
352 const struct ib_recv_wr **bad_wr)
353 {
354 int ret = 0;
355 int nreq = 0;
356 int ind = 0;
357 int i = 0;
358 u32 reg_val;
359 unsigned long flags = 0;
360 struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
361 struct hns_roce_wqe_data_seg *scat = NULL;
362 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
363 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
364 struct device *dev = &hr_dev->pdev->dev;
365 struct hns_roce_rq_db rq_db;
366 uint32_t doorbell[2] = {0};
367
368 spin_lock_irqsave(&hr_qp->rq.lock, flags);
369 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
370
371 for (nreq = 0; wr; ++nreq, wr = wr->next) {
372 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
373 hr_qp->ibqp.recv_cq)) {
374 ret = -ENOMEM;
375 *bad_wr = wr;
376 goto out;
377 }
378
379 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
380 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
381 wr->num_sge, hr_qp->rq.max_gs);
382 ret = -EINVAL;
383 *bad_wr = wr;
384 goto out;
385 }
386
387 ctrl = get_recv_wqe(hr_qp, ind);
388
389 roce_set_field(ctrl->rwqe_byte_12,
390 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
391 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S,
392 wr->num_sge);
393
394 scat = (struct hns_roce_wqe_data_seg *)(ctrl + 1);
395
396 for (i = 0; i < wr->num_sge; i++)
397 set_data_seg(scat + i, wr->sg_list + i);
398
399 hr_qp->rq.wrid[ind] = wr->wr_id;
400
401 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
402 }
403
404 out:
405 if (likely(nreq)) {
406 hr_qp->rq.head += nreq;
407 /* Memory barrier */
408 wmb();
409
410 if (ibqp->qp_type == IB_QPT_GSI) {
411 __le32 tmp;
412
413 /* SW update GSI rq header */
414 reg_val = roce_read(to_hr_dev(ibqp->device),
415 ROCEE_QP1C_CFG3_0_REG +
416 QP1C_CFGN_OFFSET * hr_qp->phy_port);
417 tmp = cpu_to_le32(reg_val);
418 roce_set_field(tmp,
419 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M,
420 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S,
421 hr_qp->rq.head);
422 reg_val = le32_to_cpu(tmp);
423 roce_write(to_hr_dev(ibqp->device),
424 ROCEE_QP1C_CFG3_0_REG +
425 QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
426 } else {
427 rq_db.u32_4 = 0;
428 rq_db.u32_8 = 0;
429
430 roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
431 RQ_DOORBELL_U32_4_RQ_HEAD_S,
432 hr_qp->rq.head);
433 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_QPN_M,
434 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
435 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_CMD_M,
436 RQ_DOORBELL_U32_8_CMD_S, 1);
437 roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
438 1);
439
440 doorbell[0] = le32_to_cpu(rq_db.u32_4);
441 doorbell[1] = le32_to_cpu(rq_db.u32_8);
442
443 hns_roce_write64_k((__le32 *)doorbell,
444 hr_qp->rq.db_reg_l);
445 }
446 }
447 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
448
449 return ret;
450 }
451
hns_roce_set_db_event_mode(struct hns_roce_dev * hr_dev,int sdb_mode,int odb_mode)452 static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
453 int sdb_mode, int odb_mode)
454 {
455 __le32 tmp;
456 u32 val;
457
458 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
459 tmp = cpu_to_le32(val);
460 roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode);
461 roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
462 val = le32_to_cpu(tmp);
463 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
464 }
465
hns_roce_set_db_ext_mode(struct hns_roce_dev * hr_dev,u32 sdb_mode,u32 odb_mode)466 static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
467 u32 odb_mode)
468 {
469 __le32 tmp;
470 u32 val;
471
472 /* Configure SDB/ODB extend mode */
473 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
474 tmp = cpu_to_le32(val);
475 roce_set_bit(tmp, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode);
476 roce_set_bit(tmp, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode);
477 val = le32_to_cpu(tmp);
478 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
479 }
480
hns_roce_set_sdb(struct hns_roce_dev * hr_dev,u32 sdb_alept,u32 sdb_alful)481 static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept,
482 u32 sdb_alful)
483 {
484 __le32 tmp;
485 u32 val;
486
487 /* Configure SDB */
488 val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG);
489 tmp = cpu_to_le32(val);
490 roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M,
491 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful);
492 roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M,
493 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept);
494 val = le32_to_cpu(tmp);
495 roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val);
496 }
497
hns_roce_set_odb(struct hns_roce_dev * hr_dev,u32 odb_alept,u32 odb_alful)498 static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept,
499 u32 odb_alful)
500 {
501 __le32 tmp;
502 u32 val;
503
504 /* Configure ODB */
505 val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG);
506 tmp = cpu_to_le32(val);
507 roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M,
508 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful);
509 roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M,
510 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept);
511 val = le32_to_cpu(tmp);
512 roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val);
513 }
514
hns_roce_set_sdb_ext(struct hns_roce_dev * hr_dev,u32 ext_sdb_alept,u32 ext_sdb_alful)515 static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
516 u32 ext_sdb_alful)
517 {
518 struct device *dev = &hr_dev->pdev->dev;
519 struct hns_roce_v1_priv *priv;
520 struct hns_roce_db_table *db;
521 dma_addr_t sdb_dma_addr;
522 __le32 tmp;
523 u32 val;
524
525 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
526 db = &priv->db_table;
527
528 /* Configure extend SDB threshold */
529 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
530 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful);
531
532 /* Configure extend SDB base addr */
533 sdb_dma_addr = db->ext_db->sdb_buf_list->map;
534 roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12));
535
536 /* Configure extend SDB depth */
537 val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG);
538 tmp = cpu_to_le32(val);
539 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M,
540 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S,
541 db->ext_db->esdb_dep);
542 /*
543 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
544 * using 4K page, and shift more 32 because of
545 * caculating the high 32 bit value evaluated to hardware.
546 */
547 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M,
548 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44);
549 val = le32_to_cpu(tmp);
550 roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
551
552 dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
553 dev_dbg(dev, "ext SDB threshold: epmty: 0x%x, ful: 0x%x\n",
554 ext_sdb_alept, ext_sdb_alful);
555 }
556
hns_roce_set_odb_ext(struct hns_roce_dev * hr_dev,u32 ext_odb_alept,u32 ext_odb_alful)557 static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
558 u32 ext_odb_alful)
559 {
560 struct device *dev = &hr_dev->pdev->dev;
561 struct hns_roce_v1_priv *priv;
562 struct hns_roce_db_table *db;
563 dma_addr_t odb_dma_addr;
564 __le32 tmp;
565 u32 val;
566
567 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
568 db = &priv->db_table;
569
570 /* Configure extend ODB threshold */
571 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
572 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_REG, ext_odb_alful);
573
574 /* Configure extend ODB base addr */
575 odb_dma_addr = db->ext_db->odb_buf_list->map;
576 roce_write(hr_dev, ROCEE_EXT_DB_OTH_REG, (u32)(odb_dma_addr >> 12));
577
578 /* Configure extend ODB depth */
579 val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG);
580 tmp = cpu_to_le32(val);
581 roce_set_field(tmp, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M,
582 ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S,
583 db->ext_db->eodb_dep);
584 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M,
585 ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S,
586 db->ext_db->eodb_dep);
587 val = le32_to_cpu(tmp);
588 roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val);
589
590 dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
591 dev_dbg(dev, "ext ODB threshold: empty: 0x%x, ful: 0x%x\n",
592 ext_odb_alept, ext_odb_alful);
593 }
594
hns_roce_db_ext_init(struct hns_roce_dev * hr_dev,u32 sdb_ext_mod,u32 odb_ext_mod)595 static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
596 u32 odb_ext_mod)
597 {
598 struct device *dev = &hr_dev->pdev->dev;
599 struct hns_roce_v1_priv *priv;
600 struct hns_roce_db_table *db;
601 dma_addr_t sdb_dma_addr;
602 dma_addr_t odb_dma_addr;
603 int ret = 0;
604
605 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
606 db = &priv->db_table;
607
608 db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
609 if (!db->ext_db)
610 return -ENOMEM;
611
612 if (sdb_ext_mod) {
613 db->ext_db->sdb_buf_list = kmalloc(
614 sizeof(*db->ext_db->sdb_buf_list), GFP_KERNEL);
615 if (!db->ext_db->sdb_buf_list) {
616 ret = -ENOMEM;
617 goto ext_sdb_buf_fail_out;
618 }
619
620 db->ext_db->sdb_buf_list->buf = dma_alloc_coherent(dev,
621 HNS_ROCE_V1_EXT_SDB_SIZE,
622 &sdb_dma_addr, GFP_KERNEL);
623 if (!db->ext_db->sdb_buf_list->buf) {
624 ret = -ENOMEM;
625 goto alloc_sq_db_buf_fail;
626 }
627 db->ext_db->sdb_buf_list->map = sdb_dma_addr;
628
629 db->ext_db->esdb_dep = ilog2(HNS_ROCE_V1_EXT_SDB_DEPTH);
630 hns_roce_set_sdb_ext(hr_dev, HNS_ROCE_V1_EXT_SDB_ALEPT,
631 HNS_ROCE_V1_EXT_SDB_ALFUL);
632 } else
633 hns_roce_set_sdb(hr_dev, HNS_ROCE_V1_SDB_ALEPT,
634 HNS_ROCE_V1_SDB_ALFUL);
635
636 if (odb_ext_mod) {
637 db->ext_db->odb_buf_list = kmalloc(
638 sizeof(*db->ext_db->odb_buf_list), GFP_KERNEL);
639 if (!db->ext_db->odb_buf_list) {
640 ret = -ENOMEM;
641 goto ext_odb_buf_fail_out;
642 }
643
644 db->ext_db->odb_buf_list->buf = dma_alloc_coherent(dev,
645 HNS_ROCE_V1_EXT_ODB_SIZE,
646 &odb_dma_addr, GFP_KERNEL);
647 if (!db->ext_db->odb_buf_list->buf) {
648 ret = -ENOMEM;
649 goto alloc_otr_db_buf_fail;
650 }
651 db->ext_db->odb_buf_list->map = odb_dma_addr;
652
653 db->ext_db->eodb_dep = ilog2(HNS_ROCE_V1_EXT_ODB_DEPTH);
654 hns_roce_set_odb_ext(hr_dev, HNS_ROCE_V1_EXT_ODB_ALEPT,
655 HNS_ROCE_V1_EXT_ODB_ALFUL);
656 } else
657 hns_roce_set_odb(hr_dev, HNS_ROCE_V1_ODB_ALEPT,
658 HNS_ROCE_V1_ODB_ALFUL);
659
660 hns_roce_set_db_ext_mode(hr_dev, sdb_ext_mod, odb_ext_mod);
661
662 return 0;
663
664 alloc_otr_db_buf_fail:
665 kfree(db->ext_db->odb_buf_list);
666
667 ext_odb_buf_fail_out:
668 if (sdb_ext_mod) {
669 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
670 db->ext_db->sdb_buf_list->buf,
671 db->ext_db->sdb_buf_list->map);
672 }
673
674 alloc_sq_db_buf_fail:
675 if (sdb_ext_mod)
676 kfree(db->ext_db->sdb_buf_list);
677
678 ext_sdb_buf_fail_out:
679 kfree(db->ext_db);
680 return ret;
681 }
682
hns_roce_v1_create_lp_qp(struct hns_roce_dev * hr_dev,struct ib_pd * pd)683 static struct hns_roce_qp *hns_roce_v1_create_lp_qp(struct hns_roce_dev *hr_dev,
684 struct ib_pd *pd)
685 {
686 struct device *dev = &hr_dev->pdev->dev;
687 struct ib_qp_init_attr init_attr;
688 struct ib_qp *qp;
689
690 memset(&init_attr, 0, sizeof(struct ib_qp_init_attr));
691 init_attr.qp_type = IB_QPT_RC;
692 init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
693 init_attr.cap.max_recv_wr = HNS_ROCE_MIN_WQE_NUM;
694 init_attr.cap.max_send_wr = HNS_ROCE_MIN_WQE_NUM;
695
696 qp = hns_roce_create_qp(pd, &init_attr, NULL);
697 if (IS_ERR(qp)) {
698 dev_err(dev, "Create loop qp for mr free failed!");
699 return NULL;
700 }
701
702 return to_hr_qp(qp);
703 }
704
hns_roce_v1_rsv_lp_qp(struct hns_roce_dev * hr_dev)705 static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
706 {
707 struct hns_roce_caps *caps = &hr_dev->caps;
708 struct device *dev = &hr_dev->pdev->dev;
709 struct ib_cq_init_attr cq_init_attr;
710 struct hns_roce_free_mr *free_mr;
711 struct ib_qp_attr attr = { 0 };
712 struct hns_roce_v1_priv *priv;
713 struct hns_roce_qp *hr_qp;
714 struct ib_cq *cq;
715 struct ib_pd *pd;
716 union ib_gid dgid;
717 u64 subnet_prefix;
718 int attr_mask = 0;
719 int i, j;
720 int ret;
721 u8 queue_en[HNS_ROCE_V1_RESV_QP] = { 0 };
722 u8 phy_port;
723 u8 port = 0;
724 u8 sl;
725
726 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
727 free_mr = &priv->free_mr;
728
729 /* Reserved cq for loop qp */
730 cq_init_attr.cqe = HNS_ROCE_MIN_WQE_NUM * 2;
731 cq_init_attr.comp_vector = 0;
732 cq = hns_roce_ib_create_cq(&hr_dev->ib_dev, &cq_init_attr, NULL, NULL);
733 if (IS_ERR(cq)) {
734 dev_err(dev, "Create cq for reseved loop qp failed!");
735 return -ENOMEM;
736 }
737 free_mr->mr_free_cq = to_hr_cq(cq);
738 free_mr->mr_free_cq->ib_cq.device = &hr_dev->ib_dev;
739 free_mr->mr_free_cq->ib_cq.uobject = NULL;
740 free_mr->mr_free_cq->ib_cq.comp_handler = NULL;
741 free_mr->mr_free_cq->ib_cq.event_handler = NULL;
742 free_mr->mr_free_cq->ib_cq.cq_context = NULL;
743 atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
744
745 pd = hns_roce_alloc_pd(&hr_dev->ib_dev, NULL, NULL);
746 if (IS_ERR(pd)) {
747 dev_err(dev, "Create pd for reseved loop qp failed!");
748 ret = -ENOMEM;
749 goto alloc_pd_failed;
750 }
751 free_mr->mr_free_pd = to_hr_pd(pd);
752 free_mr->mr_free_pd->ibpd.device = &hr_dev->ib_dev;
753 free_mr->mr_free_pd->ibpd.uobject = NULL;
754 free_mr->mr_free_pd->ibpd.__internal_mr = NULL;
755 atomic_set(&free_mr->mr_free_pd->ibpd.usecnt, 0);
756
757 attr.qp_access_flags = IB_ACCESS_REMOTE_WRITE;
758 attr.pkey_index = 0;
759 attr.min_rnr_timer = 0;
760 /* Disable read ability */
761 attr.max_dest_rd_atomic = 0;
762 attr.max_rd_atomic = 0;
763 /* Use arbitrary values as rq_psn and sq_psn */
764 attr.rq_psn = 0x0808;
765 attr.sq_psn = 0x0808;
766 attr.retry_cnt = 7;
767 attr.rnr_retry = 7;
768 attr.timeout = 0x12;
769 attr.path_mtu = IB_MTU_256;
770 attr.ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
771 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
772 rdma_ah_set_static_rate(&attr.ah_attr, 3);
773
774 subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
775 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
776 phy_port = (i >= HNS_ROCE_MAX_PORTS) ? (i - 2) :
777 (i % HNS_ROCE_MAX_PORTS);
778 sl = i / HNS_ROCE_MAX_PORTS;
779
780 for (j = 0; j < caps->num_ports; j++) {
781 if (hr_dev->iboe.phy_port[j] == phy_port) {
782 queue_en[i] = 1;
783 port = j;
784 break;
785 }
786 }
787
788 if (!queue_en[i])
789 continue;
790
791 free_mr->mr_free_qp[i] = hns_roce_v1_create_lp_qp(hr_dev, pd);
792 if (!free_mr->mr_free_qp[i]) {
793 dev_err(dev, "Create loop qp failed!\n");
794 ret = -ENOMEM;
795 goto create_lp_qp_failed;
796 }
797 hr_qp = free_mr->mr_free_qp[i];
798
799 hr_qp->port = port;
800 hr_qp->phy_port = phy_port;
801 hr_qp->ibqp.qp_type = IB_QPT_RC;
802 hr_qp->ibqp.device = &hr_dev->ib_dev;
803 hr_qp->ibqp.uobject = NULL;
804 atomic_set(&hr_qp->ibqp.usecnt, 0);
805 hr_qp->ibqp.pd = pd;
806 hr_qp->ibqp.recv_cq = cq;
807 hr_qp->ibqp.send_cq = cq;
808
809 rdma_ah_set_port_num(&attr.ah_attr, port + 1);
810 rdma_ah_set_sl(&attr.ah_attr, sl);
811 attr.port_num = port + 1;
812
813 attr.dest_qp_num = hr_qp->qpn;
814 memcpy(rdma_ah_retrieve_dmac(&attr.ah_attr),
815 hr_dev->dev_addr[port],
816 MAC_ADDR_OCTET_NUM);
817
818 memcpy(&dgid.raw, &subnet_prefix, sizeof(u64));
819 memcpy(&dgid.raw[8], hr_dev->dev_addr[port], 3);
820 memcpy(&dgid.raw[13], hr_dev->dev_addr[port] + 3, 3);
821 dgid.raw[11] = 0xff;
822 dgid.raw[12] = 0xfe;
823 dgid.raw[8] ^= 2;
824 rdma_ah_set_dgid_raw(&attr.ah_attr, dgid.raw);
825
826 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
827 IB_QPS_RESET, IB_QPS_INIT);
828 if (ret) {
829 dev_err(dev, "modify qp failed(%d)!\n", ret);
830 goto create_lp_qp_failed;
831 }
832
833 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, IB_QP_DEST_QPN,
834 IB_QPS_INIT, IB_QPS_RTR);
835 if (ret) {
836 dev_err(dev, "modify qp failed(%d)!\n", ret);
837 goto create_lp_qp_failed;
838 }
839
840 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
841 IB_QPS_RTR, IB_QPS_RTS);
842 if (ret) {
843 dev_err(dev, "modify qp failed(%d)!\n", ret);
844 goto create_lp_qp_failed;
845 }
846 }
847
848 return 0;
849
850 create_lp_qp_failed:
851 for (i -= 1; i >= 0; i--) {
852 hr_qp = free_mr->mr_free_qp[i];
853 if (hns_roce_v1_destroy_qp(&hr_qp->ibqp))
854 dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
855 }
856
857 if (hns_roce_dealloc_pd(pd))
858 dev_err(dev, "Destroy pd for create_lp_qp failed!\n");
859
860 alloc_pd_failed:
861 if (hns_roce_ib_destroy_cq(cq))
862 dev_err(dev, "Destroy cq for create_lp_qp failed!\n");
863
864 return ret;
865 }
866
hns_roce_v1_release_lp_qp(struct hns_roce_dev * hr_dev)867 static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
868 {
869 struct device *dev = &hr_dev->pdev->dev;
870 struct hns_roce_free_mr *free_mr;
871 struct hns_roce_v1_priv *priv;
872 struct hns_roce_qp *hr_qp;
873 int ret;
874 int i;
875
876 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
877 free_mr = &priv->free_mr;
878
879 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
880 hr_qp = free_mr->mr_free_qp[i];
881 if (!hr_qp)
882 continue;
883
884 ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp);
885 if (ret)
886 dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
887 i, ret);
888 }
889
890 ret = hns_roce_ib_destroy_cq(&free_mr->mr_free_cq->ib_cq);
891 if (ret)
892 dev_err(dev, "Destroy cq for mr_free failed(%d)!\n", ret);
893
894 ret = hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd);
895 if (ret)
896 dev_err(dev, "Destroy pd for mr_free failed(%d)!\n", ret);
897 }
898
hns_roce_db_init(struct hns_roce_dev * hr_dev)899 static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
900 {
901 struct device *dev = &hr_dev->pdev->dev;
902 struct hns_roce_v1_priv *priv;
903 struct hns_roce_db_table *db;
904 u32 sdb_ext_mod;
905 u32 odb_ext_mod;
906 u32 sdb_evt_mod;
907 u32 odb_evt_mod;
908 int ret = 0;
909
910 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
911 db = &priv->db_table;
912
913 memset(db, 0, sizeof(*db));
914
915 /* Default DB mode */
916 sdb_ext_mod = HNS_ROCE_SDB_EXTEND_MODE;
917 odb_ext_mod = HNS_ROCE_ODB_EXTEND_MODE;
918 sdb_evt_mod = HNS_ROCE_SDB_NORMAL_MODE;
919 odb_evt_mod = HNS_ROCE_ODB_POLL_MODE;
920
921 db->sdb_ext_mod = sdb_ext_mod;
922 db->odb_ext_mod = odb_ext_mod;
923
924 /* Init extend DB */
925 ret = hns_roce_db_ext_init(hr_dev, sdb_ext_mod, odb_ext_mod);
926 if (ret) {
927 dev_err(dev, "Failed in extend DB configuration.\n");
928 return ret;
929 }
930
931 hns_roce_set_db_event_mode(hr_dev, sdb_evt_mod, odb_evt_mod);
932
933 return 0;
934 }
935
hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct * work)936 static void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
937 {
938 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
939 struct hns_roce_dev *hr_dev;
940
941 lp_qp_work = container_of(work, struct hns_roce_recreate_lp_qp_work,
942 work);
943 hr_dev = to_hr_dev(lp_qp_work->ib_dev);
944
945 hns_roce_v1_release_lp_qp(hr_dev);
946
947 if (hns_roce_v1_rsv_lp_qp(hr_dev))
948 dev_err(&hr_dev->pdev->dev, "create reserver qp failed\n");
949
950 if (lp_qp_work->comp_flag)
951 complete(lp_qp_work->comp);
952
953 kfree(lp_qp_work);
954 }
955
hns_roce_v1_recreate_lp_qp(struct hns_roce_dev * hr_dev)956 static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
957 {
958 struct device *dev = &hr_dev->pdev->dev;
959 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
960 struct hns_roce_free_mr *free_mr;
961 struct hns_roce_v1_priv *priv;
962 struct completion comp;
963 unsigned long end =
964 msecs_to_jiffies(HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS) + jiffies;
965
966 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
967 free_mr = &priv->free_mr;
968
969 lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
970 GFP_KERNEL);
971 if (!lp_qp_work)
972 return -ENOMEM;
973
974 INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
975
976 lp_qp_work->ib_dev = &(hr_dev->ib_dev);
977 lp_qp_work->comp = ∁
978 lp_qp_work->comp_flag = 1;
979
980 init_completion(lp_qp_work->comp);
981
982 queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
983
984 while (time_before_eq(jiffies, end)) {
985 if (try_wait_for_completion(&comp))
986 return 0;
987 msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
988 }
989
990 lp_qp_work->comp_flag = 0;
991 if (try_wait_for_completion(&comp))
992 return 0;
993
994 dev_warn(dev, "recreate lp qp failed 20s timeout and return failed!\n");
995 return -ETIMEDOUT;
996 }
997
hns_roce_v1_send_lp_wqe(struct hns_roce_qp * hr_qp)998 static int hns_roce_v1_send_lp_wqe(struct hns_roce_qp *hr_qp)
999 {
1000 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
1001 struct device *dev = &hr_dev->pdev->dev;
1002 struct ib_send_wr send_wr;
1003 const struct ib_send_wr *bad_wr;
1004 int ret;
1005
1006 memset(&send_wr, 0, sizeof(send_wr));
1007 send_wr.next = NULL;
1008 send_wr.num_sge = 0;
1009 send_wr.send_flags = 0;
1010 send_wr.sg_list = NULL;
1011 send_wr.wr_id = (unsigned long long)&send_wr;
1012 send_wr.opcode = IB_WR_RDMA_WRITE;
1013
1014 ret = hns_roce_v1_post_send(&hr_qp->ibqp, &send_wr, &bad_wr);
1015 if (ret) {
1016 dev_err(dev, "Post write wqe for mr free failed(%d)!", ret);
1017 return ret;
1018 }
1019
1020 return 0;
1021 }
1022
hns_roce_v1_mr_free_work_fn(struct work_struct * work)1023 static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
1024 {
1025 struct hns_roce_mr_free_work *mr_work;
1026 struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
1027 struct hns_roce_free_mr *free_mr;
1028 struct hns_roce_cq *mr_free_cq;
1029 struct hns_roce_v1_priv *priv;
1030 struct hns_roce_dev *hr_dev;
1031 struct hns_roce_mr *hr_mr;
1032 struct hns_roce_qp *hr_qp;
1033 struct device *dev;
1034 unsigned long end =
1035 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1036 int i;
1037 int ret;
1038 int ne = 0;
1039
1040 mr_work = container_of(work, struct hns_roce_mr_free_work, work);
1041 hr_mr = (struct hns_roce_mr *)mr_work->mr;
1042 hr_dev = to_hr_dev(mr_work->ib_dev);
1043 dev = &hr_dev->pdev->dev;
1044
1045 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1046 free_mr = &priv->free_mr;
1047 mr_free_cq = free_mr->mr_free_cq;
1048
1049 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
1050 hr_qp = free_mr->mr_free_qp[i];
1051 if (!hr_qp)
1052 continue;
1053 ne++;
1054
1055 ret = hns_roce_v1_send_lp_wqe(hr_qp);
1056 if (ret) {
1057 dev_err(dev,
1058 "Send wqe (qp:0x%lx) for mr free failed(%d)!\n",
1059 hr_qp->qpn, ret);
1060 goto free_work;
1061 }
1062 }
1063
1064 if (!ne) {
1065 dev_err(dev, "Reserved loop qp is absent!\n");
1066 goto free_work;
1067 }
1068
1069 do {
1070 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
1071 if (ret < 0 && hr_qp) {
1072 dev_err(dev,
1073 "(qp:0x%lx) starts, Poll cqe failed(%d) for mr 0x%x free! Remain %d cqe\n",
1074 hr_qp->qpn, ret, hr_mr->key, ne);
1075 goto free_work;
1076 }
1077 ne -= ret;
1078 usleep_range(HNS_ROCE_V1_FREE_MR_WAIT_VALUE * 1000,
1079 (1 + HNS_ROCE_V1_FREE_MR_WAIT_VALUE) * 1000);
1080 } while (ne && time_before_eq(jiffies, end));
1081
1082 if (ne != 0)
1083 dev_err(dev,
1084 "Poll cqe for mr 0x%x free timeout! Remain %d cqe\n",
1085 hr_mr->key, ne);
1086
1087 free_work:
1088 if (mr_work->comp_flag)
1089 complete(mr_work->comp);
1090 kfree(mr_work);
1091 }
1092
hns_roce_v1_dereg_mr(struct hns_roce_dev * hr_dev,struct hns_roce_mr * mr)1093 static int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev,
1094 struct hns_roce_mr *mr)
1095 {
1096 struct device *dev = &hr_dev->pdev->dev;
1097 struct hns_roce_mr_free_work *mr_work;
1098 struct hns_roce_free_mr *free_mr;
1099 struct hns_roce_v1_priv *priv;
1100 struct completion comp;
1101 unsigned long end =
1102 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1103 unsigned long start = jiffies;
1104 int npages;
1105 int ret = 0;
1106
1107 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1108 free_mr = &priv->free_mr;
1109
1110 if (mr->enabled) {
1111 if (hns_roce_hw2sw_mpt(hr_dev, NULL, key_to_hw_index(mr->key)
1112 & (hr_dev->caps.num_mtpts - 1)))
1113 dev_warn(dev, "HW2SW_MPT failed!\n");
1114 }
1115
1116 mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
1117 if (!mr_work) {
1118 ret = -ENOMEM;
1119 goto free_mr;
1120 }
1121
1122 INIT_WORK(&(mr_work->work), hns_roce_v1_mr_free_work_fn);
1123
1124 mr_work->ib_dev = &(hr_dev->ib_dev);
1125 mr_work->comp = ∁
1126 mr_work->comp_flag = 1;
1127 mr_work->mr = (void *)mr;
1128 init_completion(mr_work->comp);
1129
1130 queue_work(free_mr->free_mr_wq, &(mr_work->work));
1131
1132 while (time_before_eq(jiffies, end)) {
1133 if (try_wait_for_completion(&comp))
1134 goto free_mr;
1135 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1136 }
1137
1138 mr_work->comp_flag = 0;
1139 if (try_wait_for_completion(&comp))
1140 goto free_mr;
1141
1142 dev_warn(dev, "Free mr work 0x%x over 50s and failed!\n", mr->key);
1143 ret = -ETIMEDOUT;
1144
1145 free_mr:
1146 dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1147 mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1148
1149 if (mr->size != ~0ULL) {
1150 npages = ib_umem_page_count(mr->umem);
1151 dma_free_coherent(dev, npages * 8, mr->pbl_buf,
1152 mr->pbl_dma_addr);
1153 }
1154
1155 hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1156 key_to_hw_index(mr->key), 0);
1157
1158 if (mr->umem)
1159 ib_umem_release(mr->umem);
1160
1161 kfree(mr);
1162
1163 return ret;
1164 }
1165
hns_roce_db_free(struct hns_roce_dev * hr_dev)1166 static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1167 {
1168 struct device *dev = &hr_dev->pdev->dev;
1169 struct hns_roce_v1_priv *priv;
1170 struct hns_roce_db_table *db;
1171
1172 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1173 db = &priv->db_table;
1174
1175 if (db->sdb_ext_mod) {
1176 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
1177 db->ext_db->sdb_buf_list->buf,
1178 db->ext_db->sdb_buf_list->map);
1179 kfree(db->ext_db->sdb_buf_list);
1180 }
1181
1182 if (db->odb_ext_mod) {
1183 dma_free_coherent(dev, HNS_ROCE_V1_EXT_ODB_SIZE,
1184 db->ext_db->odb_buf_list->buf,
1185 db->ext_db->odb_buf_list->map);
1186 kfree(db->ext_db->odb_buf_list);
1187 }
1188
1189 kfree(db->ext_db);
1190 }
1191
hns_roce_raq_init(struct hns_roce_dev * hr_dev)1192 static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1193 {
1194 int ret;
1195 u32 val;
1196 __le32 tmp;
1197 int raq_shift = 0;
1198 dma_addr_t addr;
1199 struct hns_roce_v1_priv *priv;
1200 struct hns_roce_raq_table *raq;
1201 struct device *dev = &hr_dev->pdev->dev;
1202
1203 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1204 raq = &priv->raq_table;
1205
1206 raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1207 if (!raq->e_raq_buf)
1208 return -ENOMEM;
1209
1210 raq->e_raq_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_RAQ_SIZE,
1211 &addr, GFP_KERNEL);
1212 if (!raq->e_raq_buf->buf) {
1213 ret = -ENOMEM;
1214 goto err_dma_alloc_raq;
1215 }
1216 raq->e_raq_buf->map = addr;
1217
1218 /* Configure raq extended address. 48bit 4K align*/
1219 roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
1220
1221 /* Configure raq_shift */
1222 raq_shift = ilog2(HNS_ROCE_V1_RAQ_SIZE / HNS_ROCE_V1_RAQ_ENTRY);
1223 val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG);
1224 tmp = cpu_to_le32(val);
1225 roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M,
1226 ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S, raq_shift);
1227 /*
1228 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1229 * using 4K page, and shift more 32 because of
1230 * caculating the high 32 bit value evaluated to hardware.
1231 */
1232 roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M,
1233 ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S,
1234 raq->e_raq_buf->map >> 44);
1235 val = le32_to_cpu(tmp);
1236 roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val);
1237 dev_dbg(dev, "Configure raq_shift 0x%x.\n", val);
1238
1239 /* Configure raq threshold */
1240 val = roce_read(hr_dev, ROCEE_RAQ_WL_REG);
1241 tmp = cpu_to_le32(val);
1242 roce_set_field(tmp, ROCEE_RAQ_WL_ROCEE_RAQ_WL_M,
1243 ROCEE_RAQ_WL_ROCEE_RAQ_WL_S,
1244 HNS_ROCE_V1_EXT_RAQ_WF);
1245 val = le32_to_cpu(tmp);
1246 roce_write(hr_dev, ROCEE_RAQ_WL_REG, val);
1247 dev_dbg(dev, "Configure raq_wl 0x%x.\n", val);
1248
1249 /* Enable extend raq */
1250 val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG);
1251 tmp = cpu_to_le32(val);
1252 roce_set_field(tmp,
1253 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M,
1254 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S,
1255 POL_TIME_INTERVAL_VAL);
1256 roce_set_bit(tmp, ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE, 1);
1257 roce_set_field(tmp,
1258 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M,
1259 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S,
1260 2);
1261 roce_set_bit(tmp,
1262 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S, 1);
1263 val = le32_to_cpu(tmp);
1264 roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val);
1265 dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val);
1266
1267 /* Enable raq drop */
1268 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1269 tmp = cpu_to_le32(val);
1270 roce_set_bit(tmp, ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S, 1);
1271 val = le32_to_cpu(tmp);
1272 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1273 dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val);
1274
1275 return 0;
1276
1277 err_dma_alloc_raq:
1278 kfree(raq->e_raq_buf);
1279 return ret;
1280 }
1281
hns_roce_raq_free(struct hns_roce_dev * hr_dev)1282 static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1283 {
1284 struct device *dev = &hr_dev->pdev->dev;
1285 struct hns_roce_v1_priv *priv;
1286 struct hns_roce_raq_table *raq;
1287
1288 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1289 raq = &priv->raq_table;
1290
1291 dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1292 raq->e_raq_buf->map);
1293 kfree(raq->e_raq_buf);
1294 }
1295
hns_roce_port_enable(struct hns_roce_dev * hr_dev,int enable_flag)1296 static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
1297 {
1298 __le32 tmp;
1299 u32 val;
1300
1301 if (enable_flag) {
1302 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1303 /* Open all ports */
1304 tmp = cpu_to_le32(val);
1305 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1306 ROCEE_GLB_CFG_ROCEE_PORT_ST_S,
1307 ALL_PORT_VAL_OPEN);
1308 val = le32_to_cpu(tmp);
1309 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1310 } else {
1311 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1312 /* Close all ports */
1313 tmp = cpu_to_le32(val);
1314 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1315 ROCEE_GLB_CFG_ROCEE_PORT_ST_S, 0x0);
1316 val = le32_to_cpu(tmp);
1317 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1318 }
1319 }
1320
hns_roce_bt_init(struct hns_roce_dev * hr_dev)1321 static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1322 {
1323 struct device *dev = &hr_dev->pdev->dev;
1324 struct hns_roce_v1_priv *priv;
1325 int ret;
1326
1327 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1328
1329 priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1330 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
1331 GFP_KERNEL);
1332 if (!priv->bt_table.qpc_buf.buf)
1333 return -ENOMEM;
1334
1335 priv->bt_table.mtpt_buf.buf = dma_alloc_coherent(dev,
1336 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.mtpt_buf.map,
1337 GFP_KERNEL);
1338 if (!priv->bt_table.mtpt_buf.buf) {
1339 ret = -ENOMEM;
1340 goto err_failed_alloc_mtpt_buf;
1341 }
1342
1343 priv->bt_table.cqc_buf.buf = dma_alloc_coherent(dev,
1344 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.cqc_buf.map,
1345 GFP_KERNEL);
1346 if (!priv->bt_table.cqc_buf.buf) {
1347 ret = -ENOMEM;
1348 goto err_failed_alloc_cqc_buf;
1349 }
1350
1351 return 0;
1352
1353 err_failed_alloc_cqc_buf:
1354 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1355 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1356
1357 err_failed_alloc_mtpt_buf:
1358 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1359 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1360
1361 return ret;
1362 }
1363
hns_roce_bt_free(struct hns_roce_dev * hr_dev)1364 static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1365 {
1366 struct device *dev = &hr_dev->pdev->dev;
1367 struct hns_roce_v1_priv *priv;
1368
1369 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1370
1371 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1372 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
1373
1374 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1375 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1376
1377 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1378 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1379 }
1380
hns_roce_tptr_init(struct hns_roce_dev * hr_dev)1381 static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1382 {
1383 struct device *dev = &hr_dev->pdev->dev;
1384 struct hns_roce_buf_list *tptr_buf;
1385 struct hns_roce_v1_priv *priv;
1386
1387 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1388 tptr_buf = &priv->tptr_table.tptr_buf;
1389
1390 /*
1391 * This buffer will be used for CQ's tptr(tail pointer), also
1392 * named ci(customer index). Every CQ will use 2 bytes to save
1393 * cqe ci in hip06. Hardware will read this area to get new ci
1394 * when the queue is almost full.
1395 */
1396 tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1397 &tptr_buf->map, GFP_KERNEL);
1398 if (!tptr_buf->buf)
1399 return -ENOMEM;
1400
1401 hr_dev->tptr_dma_addr = tptr_buf->map;
1402 hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
1403
1404 return 0;
1405 }
1406
hns_roce_tptr_free(struct hns_roce_dev * hr_dev)1407 static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1408 {
1409 struct device *dev = &hr_dev->pdev->dev;
1410 struct hns_roce_buf_list *tptr_buf;
1411 struct hns_roce_v1_priv *priv;
1412
1413 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1414 tptr_buf = &priv->tptr_table.tptr_buf;
1415
1416 dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1417 tptr_buf->buf, tptr_buf->map);
1418 }
1419
hns_roce_free_mr_init(struct hns_roce_dev * hr_dev)1420 static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1421 {
1422 struct device *dev = &hr_dev->pdev->dev;
1423 struct hns_roce_free_mr *free_mr;
1424 struct hns_roce_v1_priv *priv;
1425 int ret = 0;
1426
1427 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1428 free_mr = &priv->free_mr;
1429
1430 free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1431 if (!free_mr->free_mr_wq) {
1432 dev_err(dev, "Create free mr workqueue failed!\n");
1433 return -ENOMEM;
1434 }
1435
1436 ret = hns_roce_v1_rsv_lp_qp(hr_dev);
1437 if (ret) {
1438 dev_err(dev, "Reserved loop qp failed(%d)!\n", ret);
1439 flush_workqueue(free_mr->free_mr_wq);
1440 destroy_workqueue(free_mr->free_mr_wq);
1441 }
1442
1443 return ret;
1444 }
1445
hns_roce_free_mr_free(struct hns_roce_dev * hr_dev)1446 static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1447 {
1448 struct hns_roce_free_mr *free_mr;
1449 struct hns_roce_v1_priv *priv;
1450
1451 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1452 free_mr = &priv->free_mr;
1453
1454 flush_workqueue(free_mr->free_mr_wq);
1455 destroy_workqueue(free_mr->free_mr_wq);
1456
1457 hns_roce_v1_release_lp_qp(hr_dev);
1458 }
1459
1460 /**
1461 * hns_roce_v1_reset - reset RoCE
1462 * @hr_dev: RoCE device struct pointer
1463 * @enable: true -- drop reset, false -- reset
1464 * return 0 - success , negative --fail
1465 */
hns_roce_v1_reset(struct hns_roce_dev * hr_dev,bool dereset)1466 static int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
1467 {
1468 struct device_node *dsaf_node;
1469 struct device *dev = &hr_dev->pdev->dev;
1470 struct device_node *np = dev->of_node;
1471 struct fwnode_handle *fwnode;
1472 int ret;
1473
1474 /* check if this is DT/ACPI case */
1475 if (dev_of_node(dev)) {
1476 dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
1477 if (!dsaf_node) {
1478 dev_err(dev, "could not find dsaf-handle\n");
1479 return -EINVAL;
1480 }
1481 fwnode = &dsaf_node->fwnode;
1482 } else if (is_acpi_device_node(dev->fwnode)) {
1483 struct fwnode_reference_args args;
1484
1485 ret = acpi_node_get_property_reference(dev->fwnode,
1486 "dsaf-handle", 0, &args);
1487 if (ret) {
1488 dev_err(dev, "could not find dsaf-handle\n");
1489 return ret;
1490 }
1491 fwnode = args.fwnode;
1492 } else {
1493 dev_err(dev, "cannot read data from DT or ACPI\n");
1494 return -ENXIO;
1495 }
1496
1497 ret = hns_dsaf_roce_reset(fwnode, false);
1498 if (ret)
1499 return ret;
1500
1501 if (dereset) {
1502 msleep(SLEEP_TIME_INTERVAL);
1503 ret = hns_dsaf_roce_reset(fwnode, true);
1504 }
1505
1506 return ret;
1507 }
1508
hns_roce_des_qp_init(struct hns_roce_dev * hr_dev)1509 static int hns_roce_des_qp_init(struct hns_roce_dev *hr_dev)
1510 {
1511 struct device *dev = &hr_dev->pdev->dev;
1512 struct hns_roce_v1_priv *priv;
1513 struct hns_roce_des_qp *des_qp;
1514
1515 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1516 des_qp = &priv->des_qp;
1517
1518 des_qp->requeue_flag = 1;
1519 des_qp->qp_wq = create_singlethread_workqueue("hns_roce_destroy_qp");
1520 if (!des_qp->qp_wq) {
1521 dev_err(dev, "Create destroy qp workqueue failed!\n");
1522 return -ENOMEM;
1523 }
1524
1525 return 0;
1526 }
1527
hns_roce_des_qp_free(struct hns_roce_dev * hr_dev)1528 static void hns_roce_des_qp_free(struct hns_roce_dev *hr_dev)
1529 {
1530 struct hns_roce_v1_priv *priv;
1531 struct hns_roce_des_qp *des_qp;
1532
1533 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
1534 des_qp = &priv->des_qp;
1535
1536 des_qp->requeue_flag = 0;
1537 flush_workqueue(des_qp->qp_wq);
1538 destroy_workqueue(des_qp->qp_wq);
1539 }
1540
hns_roce_v1_profile(struct hns_roce_dev * hr_dev)1541 static int hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1542 {
1543 int i = 0;
1544 struct hns_roce_caps *caps = &hr_dev->caps;
1545
1546 hr_dev->vendor_id = roce_read(hr_dev, ROCEE_VENDOR_ID_REG);
1547 hr_dev->vendor_part_id = roce_read(hr_dev, ROCEE_VENDOR_PART_ID_REG);
1548 hr_dev->sys_image_guid = roce_read(hr_dev, ROCEE_SYS_IMAGE_GUID_L_REG) |
1549 ((u64)roce_read(hr_dev,
1550 ROCEE_SYS_IMAGE_GUID_H_REG) << 32);
1551 hr_dev->hw_rev = HNS_ROCE_HW_VER1;
1552
1553 caps->num_qps = HNS_ROCE_V1_MAX_QP_NUM;
1554 caps->max_wqes = HNS_ROCE_V1_MAX_WQE_NUM;
1555 caps->min_wqes = HNS_ROCE_MIN_WQE_NUM;
1556 caps->num_cqs = HNS_ROCE_V1_MAX_CQ_NUM;
1557 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM;
1558 caps->max_cqes = HNS_ROCE_V1_MAX_CQE_NUM;
1559 caps->max_sq_sg = HNS_ROCE_V1_SG_NUM;
1560 caps->max_rq_sg = HNS_ROCE_V1_SG_NUM;
1561 caps->max_sq_inline = HNS_ROCE_V1_INLINE_SIZE;
1562 caps->num_uars = HNS_ROCE_V1_UAR_NUM;
1563 caps->phy_num_uars = HNS_ROCE_V1_PHY_UAR_NUM;
1564 caps->num_aeq_vectors = HNS_ROCE_V1_AEQE_VEC_NUM;
1565 caps->num_comp_vectors = HNS_ROCE_V1_COMP_VEC_NUM;
1566 caps->num_other_vectors = HNS_ROCE_V1_ABNORMAL_VEC_NUM;
1567 caps->num_mtpts = HNS_ROCE_V1_MAX_MTPT_NUM;
1568 caps->num_mtt_segs = HNS_ROCE_V1_MAX_MTT_SEGS;
1569 caps->num_pds = HNS_ROCE_V1_MAX_PD_NUM;
1570 caps->max_qp_init_rdma = HNS_ROCE_V1_MAX_QP_INIT_RDMA;
1571 caps->max_qp_dest_rdma = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1572 caps->max_sq_desc_sz = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1573 caps->max_rq_desc_sz = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1574 caps->qpc_entry_sz = HNS_ROCE_V1_QPC_ENTRY_SIZE;
1575 caps->irrl_entry_sz = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1576 caps->cqc_entry_sz = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1577 caps->mtpt_entry_sz = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1578 caps->mtt_entry_sz = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1579 caps->cq_entry_sz = HNS_ROCE_V1_CQE_ENTRY_SIZE;
1580 caps->page_size_cap = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
1581 caps->reserved_lkey = 0;
1582 caps->reserved_pds = 0;
1583 caps->reserved_mrws = 1;
1584 caps->reserved_uars = 0;
1585 caps->reserved_cqs = 0;
1586 caps->chunk_sz = HNS_ROCE_V1_TABLE_CHUNK_SIZE;
1587
1588 for (i = 0; i < caps->num_ports; i++)
1589 caps->pkey_table_len[i] = 1;
1590
1591 for (i = 0; i < caps->num_ports; i++) {
1592 /* Six ports shared 16 GID in v1 engine */
1593 if (i >= (HNS_ROCE_V1_GID_NUM % caps->num_ports))
1594 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1595 caps->num_ports;
1596 else
1597 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1598 caps->num_ports + 1;
1599 }
1600
1601 caps->ceqe_depth = HNS_ROCE_V1_COMP_EQE_NUM;
1602 caps->aeqe_depth = HNS_ROCE_V1_ASYNC_EQE_NUM;
1603 caps->local_ca_ack_delay = roce_read(hr_dev, ROCEE_ACK_DELAY_REG);
1604 caps->max_mtu = IB_MTU_2048;
1605
1606 return 0;
1607 }
1608
hns_roce_v1_init(struct hns_roce_dev * hr_dev)1609 static int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1610 {
1611 int ret;
1612 u32 val;
1613 __le32 tmp;
1614 struct device *dev = &hr_dev->pdev->dev;
1615
1616 /* DMAE user config */
1617 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG);
1618 tmp = cpu_to_le32(val);
1619 roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M,
1620 ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf);
1621 roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M,
1622 ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S,
1623 1 << PAGES_SHIFT_16);
1624 val = le32_to_cpu(tmp);
1625 roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val);
1626
1627 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG);
1628 tmp = cpu_to_le32(val);
1629 roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M,
1630 ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf);
1631 roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M,
1632 ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S,
1633 1 << PAGES_SHIFT_16);
1634
1635 ret = hns_roce_db_init(hr_dev);
1636 if (ret) {
1637 dev_err(dev, "doorbell init failed!\n");
1638 return ret;
1639 }
1640
1641 ret = hns_roce_raq_init(hr_dev);
1642 if (ret) {
1643 dev_err(dev, "raq init failed!\n");
1644 goto error_failed_raq_init;
1645 }
1646
1647 ret = hns_roce_bt_init(hr_dev);
1648 if (ret) {
1649 dev_err(dev, "bt init failed!\n");
1650 goto error_failed_bt_init;
1651 }
1652
1653 ret = hns_roce_tptr_init(hr_dev);
1654 if (ret) {
1655 dev_err(dev, "tptr init failed!\n");
1656 goto error_failed_tptr_init;
1657 }
1658
1659 ret = hns_roce_des_qp_init(hr_dev);
1660 if (ret) {
1661 dev_err(dev, "des qp init failed!\n");
1662 goto error_failed_des_qp_init;
1663 }
1664
1665 ret = hns_roce_free_mr_init(hr_dev);
1666 if (ret) {
1667 dev_err(dev, "free mr init failed!\n");
1668 goto error_failed_free_mr_init;
1669 }
1670
1671 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1672
1673 return 0;
1674
1675 error_failed_free_mr_init:
1676 hns_roce_des_qp_free(hr_dev);
1677
1678 error_failed_des_qp_init:
1679 hns_roce_tptr_free(hr_dev);
1680
1681 error_failed_tptr_init:
1682 hns_roce_bt_free(hr_dev);
1683
1684 error_failed_bt_init:
1685 hns_roce_raq_free(hr_dev);
1686
1687 error_failed_raq_init:
1688 hns_roce_db_free(hr_dev);
1689 return ret;
1690 }
1691
hns_roce_v1_exit(struct hns_roce_dev * hr_dev)1692 static void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1693 {
1694 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1695 hns_roce_free_mr_free(hr_dev);
1696 hns_roce_des_qp_free(hr_dev);
1697 hns_roce_tptr_free(hr_dev);
1698 hns_roce_bt_free(hr_dev);
1699 hns_roce_raq_free(hr_dev);
1700 hns_roce_db_free(hr_dev);
1701 }
1702
hns_roce_v1_cmd_pending(struct hns_roce_dev * hr_dev)1703 static int hns_roce_v1_cmd_pending(struct hns_roce_dev *hr_dev)
1704 {
1705 u32 status = readl(hr_dev->reg_base + ROCEE_MB6_REG);
1706
1707 return (!!(status & (1 << HCR_GO_BIT)));
1708 }
1709
hns_roce_v1_post_mbox(struct hns_roce_dev * hr_dev,u64 in_param,u64 out_param,u32 in_modifier,u8 op_modifier,u16 op,u16 token,int event)1710 static int hns_roce_v1_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1711 u64 out_param, u32 in_modifier, u8 op_modifier,
1712 u16 op, u16 token, int event)
1713 {
1714 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + ROCEE_MB1_REG);
1715 unsigned long end;
1716 u32 val = 0;
1717 __le32 tmp;
1718
1719 end = msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS) + jiffies;
1720 while (hns_roce_v1_cmd_pending(hr_dev)) {
1721 if (time_after(jiffies, end)) {
1722 dev_err(hr_dev->dev, "jiffies=%d end=%d\n",
1723 (int)jiffies, (int)end);
1724 return -EAGAIN;
1725 }
1726 cond_resched();
1727 }
1728
1729 tmp = cpu_to_le32(val);
1730 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_M, ROCEE_MB6_ROCEE_MB_CMD_S,
1731 op);
1732 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_MDF_M,
1733 ROCEE_MB6_ROCEE_MB_CMD_MDF_S, op_modifier);
1734 roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_EVENT_S, event);
1735 roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_HW_RUN_S, 1);
1736 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_TOKEN_M,
1737 ROCEE_MB6_ROCEE_MB_TOKEN_S, token);
1738
1739 val = le32_to_cpu(tmp);
1740 writeq(in_param, hcr + 0);
1741 writeq(out_param, hcr + 2);
1742 writel(in_modifier, hcr + 4);
1743 /* Memory barrier */
1744 wmb();
1745
1746 writel(val, hcr + 5);
1747
1748 mmiowb();
1749
1750 return 0;
1751 }
1752
hns_roce_v1_chk_mbox(struct hns_roce_dev * hr_dev,unsigned long timeout)1753 static int hns_roce_v1_chk_mbox(struct hns_roce_dev *hr_dev,
1754 unsigned long timeout)
1755 {
1756 u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG;
1757 unsigned long end = 0;
1758 u32 status = 0;
1759
1760 end = msecs_to_jiffies(timeout) + jiffies;
1761 while (hns_roce_v1_cmd_pending(hr_dev) && time_before(jiffies, end))
1762 cond_resched();
1763
1764 if (hns_roce_v1_cmd_pending(hr_dev)) {
1765 dev_err(hr_dev->dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1766 return -ETIMEDOUT;
1767 }
1768
1769 status = le32_to_cpu((__force __le32)
1770 __raw_readl(hcr + HCR_STATUS_OFFSET));
1771 if ((status & STATUS_MASK) != 0x1) {
1772 dev_err(hr_dev->dev, "mailbox status 0x%x!\n", status);
1773 return -EBUSY;
1774 }
1775
1776 return 0;
1777 }
1778
hns_roce_v1_set_gid(struct hns_roce_dev * hr_dev,u8 port,int gid_index,const union ib_gid * gid,const struct ib_gid_attr * attr)1779 static int hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u8 port,
1780 int gid_index, const union ib_gid *gid,
1781 const struct ib_gid_attr *attr)
1782 {
1783 u32 *p = NULL;
1784 u8 gid_idx = 0;
1785
1786 gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
1787
1788 p = (u32 *)&gid->raw[0];
1789 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
1790 (HNS_ROCE_V1_GID_NUM * gid_idx));
1791
1792 p = (u32 *)&gid->raw[4];
1793 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG +
1794 (HNS_ROCE_V1_GID_NUM * gid_idx));
1795
1796 p = (u32 *)&gid->raw[8];
1797 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG +
1798 (HNS_ROCE_V1_GID_NUM * gid_idx));
1799
1800 p = (u32 *)&gid->raw[0xc];
1801 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1802 (HNS_ROCE_V1_GID_NUM * gid_idx));
1803
1804 return 0;
1805 }
1806
hns_roce_v1_set_mac(struct hns_roce_dev * hr_dev,u8 phy_port,u8 * addr)1807 static int hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1808 u8 *addr)
1809 {
1810 u32 reg_smac_l;
1811 u16 reg_smac_h;
1812 __le32 tmp;
1813 u16 *p_h;
1814 u32 *p;
1815 u32 val;
1816
1817 /*
1818 * When mac changed, loopback may fail
1819 * because of smac not equal to dmac.
1820 * We Need to release and create reserved qp again.
1821 */
1822 if (hr_dev->hw->dereg_mr) {
1823 int ret;
1824
1825 ret = hns_roce_v1_recreate_lp_qp(hr_dev);
1826 if (ret && ret != -ETIMEDOUT)
1827 return ret;
1828 }
1829
1830 p = (u32 *)(&addr[0]);
1831 reg_smac_l = *p;
1832 roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
1833 PHY_PORT_OFFSET * phy_port);
1834
1835 val = roce_read(hr_dev,
1836 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1837 tmp = cpu_to_le32(val);
1838 p_h = (u16 *)(&addr[4]);
1839 reg_smac_h = *p_h;
1840 roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_SMAC_H_M,
1841 ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
1842 val = le32_to_cpu(tmp);
1843 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1844 val);
1845
1846 return 0;
1847 }
1848
hns_roce_v1_set_mtu(struct hns_roce_dev * hr_dev,u8 phy_port,enum ib_mtu mtu)1849 static void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1850 enum ib_mtu mtu)
1851 {
1852 __le32 tmp;
1853 u32 val;
1854
1855 val = roce_read(hr_dev,
1856 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1857 tmp = cpu_to_le32(val);
1858 roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_PORT_MTU_M,
1859 ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu);
1860 val = le32_to_cpu(tmp);
1861 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1862 val);
1863 }
1864
hns_roce_v1_write_mtpt(void * mb_buf,struct hns_roce_mr * mr,unsigned long mtpt_idx)1865 static int hns_roce_v1_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1866 unsigned long mtpt_idx)
1867 {
1868 struct hns_roce_v1_mpt_entry *mpt_entry;
1869 struct scatterlist *sg;
1870 u64 *pages;
1871 int entry;
1872 int i;
1873
1874 /* MPT filled into mailbox buf */
1875 mpt_entry = (struct hns_roce_v1_mpt_entry *)mb_buf;
1876 memset(mpt_entry, 0, sizeof(*mpt_entry));
1877
1878 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_STATE_M,
1879 MPT_BYTE_4_KEY_STATE_S, KEY_VALID);
1880 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_M,
1881 MPT_BYTE_4_KEY_S, mr->key);
1882 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_PAGE_SIZE_M,
1883 MPT_BYTE_4_PAGE_SIZE_S, MR_SIZE_4K);
1884 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_TYPE_S, 0);
1885 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_BIND_ENABLE_S,
1886 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1887 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_OWN_S, 0);
1888 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_MEMORY_LOCATION_TYPE_M,
1889 MPT_BYTE_4_MEMORY_LOCATION_TYPE_S, mr->type);
1890 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_ATOMIC_S, 0);
1891 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_LOCAL_WRITE_S,
1892 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1893 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_WRITE_S,
1894 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1895 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_READ_S,
1896 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1897 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_INVAL_ENABLE_S,
1898 0);
1899 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_ADDRESS_TYPE_S, 0);
1900
1901 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1902 MPT_BYTE_12_PBL_ADDR_H_S, 0);
1903 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M,
1904 MPT_BYTE_12_MW_BIND_COUNTER_S, 0);
1905
1906 mpt_entry->virt_addr_l = cpu_to_le32((u32)mr->iova);
1907 mpt_entry->virt_addr_h = cpu_to_le32((u32)(mr->iova >> 32));
1908 mpt_entry->length = cpu_to_le32((u32)mr->size);
1909
1910 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M,
1911 MPT_BYTE_28_PD_S, mr->pd);
1912 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_L_KEY_IDX_L_M,
1913 MPT_BYTE_28_L_KEY_IDX_L_S, mtpt_idx);
1914 roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_L_KEY_IDX_H_M,
1915 MPT_BYTE_64_L_KEY_IDX_H_S, mtpt_idx >> MTPT_IDX_SHIFT);
1916
1917 /* DMA memory register */
1918 if (mr->type == MR_TYPE_DMA)
1919 return 0;
1920
1921 pages = (u64 *) __get_free_page(GFP_KERNEL);
1922 if (!pages)
1923 return -ENOMEM;
1924
1925 i = 0;
1926 for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
1927 pages[i] = ((u64)sg_dma_address(sg)) >> 12;
1928
1929 /* Directly record to MTPT table firstly 7 entry */
1930 if (i >= HNS_ROCE_MAX_INNER_MTPT_NUM)
1931 break;
1932 i++;
1933 }
1934
1935 /* Register user mr */
1936 for (i = 0; i < HNS_ROCE_MAX_INNER_MTPT_NUM; i++) {
1937 switch (i) {
1938 case 0:
1939 mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
1940 roce_set_field(mpt_entry->mpt_byte_36,
1941 MPT_BYTE_36_PA0_H_M,
1942 MPT_BYTE_36_PA0_H_S,
1943 (u32)(pages[i] >> PAGES_SHIFT_32));
1944 break;
1945 case 1:
1946 roce_set_field(mpt_entry->mpt_byte_36,
1947 MPT_BYTE_36_PA1_L_M,
1948 MPT_BYTE_36_PA1_L_S, (u32)(pages[i]));
1949 roce_set_field(mpt_entry->mpt_byte_40,
1950 MPT_BYTE_40_PA1_H_M,
1951 MPT_BYTE_40_PA1_H_S,
1952 (u32)(pages[i] >> PAGES_SHIFT_24));
1953 break;
1954 case 2:
1955 roce_set_field(mpt_entry->mpt_byte_40,
1956 MPT_BYTE_40_PA2_L_M,
1957 MPT_BYTE_40_PA2_L_S, (u32)(pages[i]));
1958 roce_set_field(mpt_entry->mpt_byte_44,
1959 MPT_BYTE_44_PA2_H_M,
1960 MPT_BYTE_44_PA2_H_S,
1961 (u32)(pages[i] >> PAGES_SHIFT_16));
1962 break;
1963 case 3:
1964 roce_set_field(mpt_entry->mpt_byte_44,
1965 MPT_BYTE_44_PA3_L_M,
1966 MPT_BYTE_44_PA3_L_S, (u32)(pages[i]));
1967 roce_set_field(mpt_entry->mpt_byte_48,
1968 MPT_BYTE_48_PA3_H_M,
1969 MPT_BYTE_48_PA3_H_S,
1970 (u32)(pages[i] >> PAGES_SHIFT_8));
1971 break;
1972 case 4:
1973 mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i]));
1974 roce_set_field(mpt_entry->mpt_byte_56,
1975 MPT_BYTE_56_PA4_H_M,
1976 MPT_BYTE_56_PA4_H_S,
1977 (u32)(pages[i] >> PAGES_SHIFT_32));
1978 break;
1979 case 5:
1980 roce_set_field(mpt_entry->mpt_byte_56,
1981 MPT_BYTE_56_PA5_L_M,
1982 MPT_BYTE_56_PA5_L_S, (u32)(pages[i]));
1983 roce_set_field(mpt_entry->mpt_byte_60,
1984 MPT_BYTE_60_PA5_H_M,
1985 MPT_BYTE_60_PA5_H_S,
1986 (u32)(pages[i] >> PAGES_SHIFT_24));
1987 break;
1988 case 6:
1989 roce_set_field(mpt_entry->mpt_byte_60,
1990 MPT_BYTE_60_PA6_L_M,
1991 MPT_BYTE_60_PA6_L_S, (u32)(pages[i]));
1992 roce_set_field(mpt_entry->mpt_byte_64,
1993 MPT_BYTE_64_PA6_H_M,
1994 MPT_BYTE_64_PA6_H_S,
1995 (u32)(pages[i] >> PAGES_SHIFT_16));
1996 break;
1997 default:
1998 break;
1999 }
2000 }
2001
2002 free_page((unsigned long) pages);
2003
2004 mpt_entry->pbl_addr_l = cpu_to_le32((u32)(mr->pbl_dma_addr));
2005
2006 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
2007 MPT_BYTE_12_PBL_ADDR_H_S,
2008 ((u32)(mr->pbl_dma_addr >> 32)));
2009
2010 return 0;
2011 }
2012
get_cqe(struct hns_roce_cq * hr_cq,int n)2013 static void *get_cqe(struct hns_roce_cq *hr_cq, int n)
2014 {
2015 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
2016 n * HNS_ROCE_V1_CQE_ENTRY_SIZE);
2017 }
2018
get_sw_cqe(struct hns_roce_cq * hr_cq,int n)2019 static void *get_sw_cqe(struct hns_roce_cq *hr_cq, int n)
2020 {
2021 struct hns_roce_cqe *hr_cqe = get_cqe(hr_cq, n & hr_cq->ib_cq.cqe);
2022
2023 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
2024 return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
2025 !!(n & (hr_cq->ib_cq.cqe + 1))) ? hr_cqe : NULL;
2026 }
2027
next_cqe_sw(struct hns_roce_cq * hr_cq)2028 static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
2029 {
2030 return get_sw_cqe(hr_cq, hr_cq->cons_index);
2031 }
2032
hns_roce_v1_cq_set_ci(struct hns_roce_cq * hr_cq,u32 cons_index)2033 static void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
2034 {
2035 __le32 doorbell[2];
2036
2037 doorbell[0] = cpu_to_le32(cons_index & ((hr_cq->cq_depth << 1) - 1));
2038 doorbell[1] = 0;
2039 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2040 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2041 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2042 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2043 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
2044 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2045 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
2046
2047 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2048 }
2049
__hns_roce_v1_cq_clean(struct hns_roce_cq * hr_cq,u32 qpn,struct hns_roce_srq * srq)2050 static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2051 struct hns_roce_srq *srq)
2052 {
2053 struct hns_roce_cqe *cqe, *dest;
2054 u32 prod_index;
2055 int nfreed = 0;
2056 u8 owner_bit;
2057
2058 for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
2059 ++prod_index) {
2060 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
2061 break;
2062 }
2063
2064 /*
2065 * Now backwards through the CQ, removing CQ entries
2066 * that match our QP by overwriting them with next entries.
2067 */
2068 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
2069 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
2070 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2071 CQE_BYTE_16_LOCAL_QPN_S) &
2072 HNS_ROCE_CQE_QPN_MASK) == qpn) {
2073 /* In v1 engine, not support SRQ */
2074 ++nfreed;
2075 } else if (nfreed) {
2076 dest = get_cqe(hr_cq, (prod_index + nfreed) &
2077 hr_cq->ib_cq.cqe);
2078 owner_bit = roce_get_bit(dest->cqe_byte_4,
2079 CQE_BYTE_4_OWNER_S);
2080 memcpy(dest, cqe, sizeof(*cqe));
2081 roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
2082 owner_bit);
2083 }
2084 }
2085
2086 if (nfreed) {
2087 hr_cq->cons_index += nfreed;
2088 /*
2089 * Make sure update of buffer contents is done before
2090 * updating consumer index.
2091 */
2092 wmb();
2093
2094 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2095 }
2096 }
2097
hns_roce_v1_cq_clean(struct hns_roce_cq * hr_cq,u32 qpn,struct hns_roce_srq * srq)2098 static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2099 struct hns_roce_srq *srq)
2100 {
2101 spin_lock_irq(&hr_cq->lock);
2102 __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
2103 spin_unlock_irq(&hr_cq->lock);
2104 }
2105
hns_roce_v1_write_cqc(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq,void * mb_buf,u64 * mtts,dma_addr_t dma_handle,int nent,u32 vector)2106 static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
2107 struct hns_roce_cq *hr_cq, void *mb_buf,
2108 u64 *mtts, dma_addr_t dma_handle, int nent,
2109 u32 vector)
2110 {
2111 struct hns_roce_cq_context *cq_context = NULL;
2112 struct hns_roce_buf_list *tptr_buf;
2113 struct hns_roce_v1_priv *priv;
2114 dma_addr_t tptr_dma_addr;
2115 int offset;
2116
2117 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
2118 tptr_buf = &priv->tptr_table.tptr_buf;
2119
2120 cq_context = mb_buf;
2121 memset(cq_context, 0, sizeof(*cq_context));
2122
2123 /* Get the tptr for this CQ. */
2124 offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
2125 tptr_dma_addr = tptr_buf->map + offset;
2126 hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
2127
2128 /* Register cq_context members */
2129 roce_set_field(cq_context->cqc_byte_4,
2130 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
2131 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
2132 roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
2133 CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
2134
2135 cq_context->cq_bt_l = cpu_to_le32((u32)dma_handle);
2136
2137 roce_set_field(cq_context->cqc_byte_12,
2138 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
2139 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
2140 ((u64)dma_handle >> 32));
2141 roce_set_field(cq_context->cqc_byte_12,
2142 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
2143 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
2144 ilog2((unsigned int)nent));
2145 roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
2146 CQ_CONTEXT_CQC_BYTE_12_CEQN_S, vector);
2147
2148 cq_context->cur_cqe_ba0_l = cpu_to_le32((u32)(mtts[0]));
2149
2150 roce_set_field(cq_context->cqc_byte_20,
2151 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
2152 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S, (mtts[0]) >> 32);
2153 /* Dedicated hardware, directly set 0 */
2154 roce_set_field(cq_context->cqc_byte_20,
2155 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
2156 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
2157 /**
2158 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
2159 * using 4K page, and shift more 32 because of
2160 * caculating the high 32 bit value evaluated to hardware.
2161 */
2162 roce_set_field(cq_context->cqc_byte_20,
2163 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
2164 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
2165 tptr_dma_addr >> 44);
2166
2167 cq_context->cqe_tptr_addr_l = cpu_to_le32((u32)(tptr_dma_addr >> 12));
2168
2169 roce_set_field(cq_context->cqc_byte_32,
2170 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
2171 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
2172 roce_set_bit(cq_context->cqc_byte_32,
2173 CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
2174 roce_set_bit(cq_context->cqc_byte_32,
2175 CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
2176 roce_set_bit(cq_context->cqc_byte_32,
2177 CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
2178 roce_set_bit(cq_context->cqc_byte_32,
2179 CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
2180 0);
2181 /* The initial value of cq's ci is 0 */
2182 roce_set_field(cq_context->cqc_byte_32,
2183 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
2184 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
2185 }
2186
hns_roce_v1_modify_cq(struct ib_cq * cq,u16 cq_count,u16 cq_period)2187 static int hns_roce_v1_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
2188 {
2189 return -EOPNOTSUPP;
2190 }
2191
hns_roce_v1_req_notify_cq(struct ib_cq * ibcq,enum ib_cq_notify_flags flags)2192 static int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq,
2193 enum ib_cq_notify_flags flags)
2194 {
2195 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2196 u32 notification_flag;
2197 __le32 doorbell[2];
2198
2199 notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2200 IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
2201 /*
2202 * flags = 0; Notification Flag = 1, next
2203 * flags = 1; Notification Flag = 0, solocited
2204 */
2205 doorbell[0] =
2206 cpu_to_le32(hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2207 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2208 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2209 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2210 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2211 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 1);
2212 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2213 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S,
2214 hr_cq->cqn | notification_flag);
2215
2216 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2217
2218 return 0;
2219 }
2220
hns_roce_v1_poll_one(struct hns_roce_cq * hr_cq,struct hns_roce_qp ** cur_qp,struct ib_wc * wc)2221 static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
2222 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2223 {
2224 int qpn;
2225 int is_send;
2226 u16 wqe_ctr;
2227 u32 status;
2228 u32 opcode;
2229 struct hns_roce_cqe *cqe;
2230 struct hns_roce_qp *hr_qp;
2231 struct hns_roce_wq *wq;
2232 struct hns_roce_wqe_ctrl_seg *sq_wqe;
2233 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2234 struct device *dev = &hr_dev->pdev->dev;
2235
2236 /* Find cqe according consumer index */
2237 cqe = next_cqe_sw(hr_cq);
2238 if (!cqe)
2239 return -EAGAIN;
2240
2241 ++hr_cq->cons_index;
2242 /* Memory barrier */
2243 rmb();
2244 /* 0->SQ, 1->RQ */
2245 is_send = !(roce_get_bit(cqe->cqe_byte_4, CQE_BYTE_4_SQ_RQ_FLAG_S));
2246
2247 /* Local_qpn in UD cqe is always 1, so it needs to compute new qpn */
2248 if (roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2249 CQE_BYTE_16_LOCAL_QPN_S) <= 1) {
2250 qpn = roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_PORT_NUM_M,
2251 CQE_BYTE_20_PORT_NUM_S) +
2252 roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2253 CQE_BYTE_16_LOCAL_QPN_S) *
2254 HNS_ROCE_MAX_PORTS;
2255 } else {
2256 qpn = roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2257 CQE_BYTE_16_LOCAL_QPN_S);
2258 }
2259
2260 if (!*cur_qp || (qpn & HNS_ROCE_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2261 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2262 if (unlikely(!hr_qp)) {
2263 dev_err(dev, "CQ %06lx with entry for unknown QPN %06x\n",
2264 hr_cq->cqn, (qpn & HNS_ROCE_CQE_QPN_MASK));
2265 return -EINVAL;
2266 }
2267
2268 *cur_qp = hr_qp;
2269 }
2270
2271 wc->qp = &(*cur_qp)->ibqp;
2272 wc->vendor_err = 0;
2273
2274 status = roce_get_field(cqe->cqe_byte_4,
2275 CQE_BYTE_4_STATUS_OF_THE_OPERATION_M,
2276 CQE_BYTE_4_STATUS_OF_THE_OPERATION_S) &
2277 HNS_ROCE_CQE_STATUS_MASK;
2278 switch (status) {
2279 case HNS_ROCE_CQE_SUCCESS:
2280 wc->status = IB_WC_SUCCESS;
2281 break;
2282 case HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR:
2283 wc->status = IB_WC_LOC_LEN_ERR;
2284 break;
2285 case HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR:
2286 wc->status = IB_WC_LOC_QP_OP_ERR;
2287 break;
2288 case HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR:
2289 wc->status = IB_WC_LOC_PROT_ERR;
2290 break;
2291 case HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR:
2292 wc->status = IB_WC_WR_FLUSH_ERR;
2293 break;
2294 case HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR:
2295 wc->status = IB_WC_MW_BIND_ERR;
2296 break;
2297 case HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR:
2298 wc->status = IB_WC_BAD_RESP_ERR;
2299 break;
2300 case HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR:
2301 wc->status = IB_WC_LOC_ACCESS_ERR;
2302 break;
2303 case HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
2304 wc->status = IB_WC_REM_INV_REQ_ERR;
2305 break;
2306 case HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR:
2307 wc->status = IB_WC_REM_ACCESS_ERR;
2308 break;
2309 case HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR:
2310 wc->status = IB_WC_REM_OP_ERR;
2311 break;
2312 case HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
2313 wc->status = IB_WC_RETRY_EXC_ERR;
2314 break;
2315 case HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
2316 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2317 break;
2318 default:
2319 wc->status = IB_WC_GENERAL_ERR;
2320 break;
2321 }
2322
2323 /* CQE status error, directly return */
2324 if (wc->status != IB_WC_SUCCESS)
2325 return 0;
2326
2327 if (is_send) {
2328 /* SQ conrespond to CQE */
2329 sq_wqe = get_send_wqe(*cur_qp, roce_get_field(cqe->cqe_byte_4,
2330 CQE_BYTE_4_WQE_INDEX_M,
2331 CQE_BYTE_4_WQE_INDEX_S)&
2332 ((*cur_qp)->sq.wqe_cnt-1));
2333 switch (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_OPCODE_MASK) {
2334 case HNS_ROCE_WQE_OPCODE_SEND:
2335 wc->opcode = IB_WC_SEND;
2336 break;
2337 case HNS_ROCE_WQE_OPCODE_RDMA_READ:
2338 wc->opcode = IB_WC_RDMA_READ;
2339 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2340 break;
2341 case HNS_ROCE_WQE_OPCODE_RDMA_WRITE:
2342 wc->opcode = IB_WC_RDMA_WRITE;
2343 break;
2344 case HNS_ROCE_WQE_OPCODE_LOCAL_INV:
2345 wc->opcode = IB_WC_LOCAL_INV;
2346 break;
2347 case HNS_ROCE_WQE_OPCODE_UD_SEND:
2348 wc->opcode = IB_WC_SEND;
2349 break;
2350 default:
2351 wc->status = IB_WC_GENERAL_ERR;
2352 break;
2353 }
2354 wc->wc_flags = (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_IMM ?
2355 IB_WC_WITH_IMM : 0);
2356
2357 wq = &(*cur_qp)->sq;
2358 if ((*cur_qp)->sq_signal_bits) {
2359 /*
2360 * If sg_signal_bit is 1,
2361 * firstly tail pointer updated to wqe
2362 * which current cqe correspond to
2363 */
2364 wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
2365 CQE_BYTE_4_WQE_INDEX_M,
2366 CQE_BYTE_4_WQE_INDEX_S);
2367 wq->tail += (wqe_ctr - (u16)wq->tail) &
2368 (wq->wqe_cnt - 1);
2369 }
2370 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2371 ++wq->tail;
2372 } else {
2373 /* RQ conrespond to CQE */
2374 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2375 opcode = roce_get_field(cqe->cqe_byte_4,
2376 CQE_BYTE_4_OPERATION_TYPE_M,
2377 CQE_BYTE_4_OPERATION_TYPE_S) &
2378 HNS_ROCE_CQE_OPCODE_MASK;
2379 switch (opcode) {
2380 case HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE:
2381 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2382 wc->wc_flags = IB_WC_WITH_IMM;
2383 wc->ex.imm_data =
2384 cpu_to_be32(le32_to_cpu(cqe->immediate_data));
2385 break;
2386 case HNS_ROCE_OPCODE_SEND_DATA_RECEIVE:
2387 if (roce_get_bit(cqe->cqe_byte_4,
2388 CQE_BYTE_4_IMM_INDICATOR_S)) {
2389 wc->opcode = IB_WC_RECV;
2390 wc->wc_flags = IB_WC_WITH_IMM;
2391 wc->ex.imm_data = cpu_to_be32(
2392 le32_to_cpu(cqe->immediate_data));
2393 } else {
2394 wc->opcode = IB_WC_RECV;
2395 wc->wc_flags = 0;
2396 }
2397 break;
2398 default:
2399 wc->status = IB_WC_GENERAL_ERR;
2400 break;
2401 }
2402
2403 /* Update tail pointer, record wr_id */
2404 wq = &(*cur_qp)->rq;
2405 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2406 ++wq->tail;
2407 wc->sl = (u8)roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_SL_M,
2408 CQE_BYTE_20_SL_S);
2409 wc->src_qp = (u8)roce_get_field(cqe->cqe_byte_20,
2410 CQE_BYTE_20_REMOTE_QPN_M,
2411 CQE_BYTE_20_REMOTE_QPN_S);
2412 wc->wc_flags |= (roce_get_bit(cqe->cqe_byte_20,
2413 CQE_BYTE_20_GRH_PRESENT_S) ?
2414 IB_WC_GRH : 0);
2415 wc->pkey_index = (u16)roce_get_field(cqe->cqe_byte_28,
2416 CQE_BYTE_28_P_KEY_IDX_M,
2417 CQE_BYTE_28_P_KEY_IDX_S);
2418 }
2419
2420 return 0;
2421 }
2422
hns_roce_v1_poll_cq(struct ib_cq * ibcq,int num_entries,struct ib_wc * wc)2423 int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
2424 {
2425 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2426 struct hns_roce_qp *cur_qp = NULL;
2427 unsigned long flags;
2428 int npolled;
2429 int ret = 0;
2430
2431 spin_lock_irqsave(&hr_cq->lock, flags);
2432
2433 for (npolled = 0; npolled < num_entries; ++npolled) {
2434 ret = hns_roce_v1_poll_one(hr_cq, &cur_qp, wc + npolled);
2435 if (ret)
2436 break;
2437 }
2438
2439 if (npolled) {
2440 *hr_cq->tptr_addr = hr_cq->cons_index &
2441 ((hr_cq->cq_depth << 1) - 1);
2442
2443 /* Memroy barrier */
2444 wmb();
2445 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2446 }
2447
2448 spin_unlock_irqrestore(&hr_cq->lock, flags);
2449
2450 if (ret == 0 || ret == -EAGAIN)
2451 return npolled;
2452 else
2453 return ret;
2454 }
2455
hns_roce_v1_clear_hem(struct hns_roce_dev * hr_dev,struct hns_roce_hem_table * table,int obj,int step_idx)2456 static int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
2457 struct hns_roce_hem_table *table, int obj,
2458 int step_idx)
2459 {
2460 struct device *dev = &hr_dev->pdev->dev;
2461 struct hns_roce_v1_priv *priv;
2462 unsigned long end = 0, flags = 0;
2463 __le32 bt_cmd_val[2] = {0};
2464 void __iomem *bt_cmd;
2465 u64 bt_ba = 0;
2466
2467 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
2468
2469 switch (table->type) {
2470 case HEM_TYPE_QPC:
2471 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2472 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_QPC);
2473 bt_ba = priv->bt_table.qpc_buf.map >> 12;
2474 break;
2475 case HEM_TYPE_MTPT:
2476 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2477 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_MTPT);
2478 bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2479 break;
2480 case HEM_TYPE_CQC:
2481 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2482 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_CQC);
2483 bt_ba = priv->bt_table.cqc_buf.map >> 12;
2484 break;
2485 case HEM_TYPE_SRQC:
2486 dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
2487 return -EINVAL;
2488 default:
2489 return 0;
2490 }
2491 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2492 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2493 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
2494 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
2495
2496 spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags);
2497
2498 bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2499
2500 end = msecs_to_jiffies(HW_SYNC_TIMEOUT_MSECS) + jiffies;
2501 while (1) {
2502 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2503 if (!(time_before(jiffies, end))) {
2504 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2505 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2506 flags);
2507 return -EBUSY;
2508 }
2509 } else {
2510 break;
2511 }
2512 msleep(HW_SYNC_SLEEP_TIME_INTERVAL);
2513 }
2514
2515 bt_cmd_val[0] = (__le32)bt_ba;
2516 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2517 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2518 hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
2519
2520 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
2521
2522 return 0;
2523 }
2524
hns_roce_v1_qp_modify(struct hns_roce_dev * hr_dev,struct hns_roce_mtt * mtt,enum hns_roce_qp_state cur_state,enum hns_roce_qp_state new_state,struct hns_roce_qp_context * context,struct hns_roce_qp * hr_qp)2525 static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2526 struct hns_roce_mtt *mtt,
2527 enum hns_roce_qp_state cur_state,
2528 enum hns_roce_qp_state new_state,
2529 struct hns_roce_qp_context *context,
2530 struct hns_roce_qp *hr_qp)
2531 {
2532 static const u16
2533 op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = {
2534 [HNS_ROCE_QP_STATE_RST] = {
2535 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2536 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2537 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2538 },
2539 [HNS_ROCE_QP_STATE_INIT] = {
2540 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2541 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2542 /* Note: In v1 engine, HW doesn't support RST2INIT.
2543 * We use RST2INIT cmd instead of INIT2INIT.
2544 */
2545 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2546 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP,
2547 },
2548 [HNS_ROCE_QP_STATE_RTR] = {
2549 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2550 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2551 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP,
2552 },
2553 [HNS_ROCE_QP_STATE_RTS] = {
2554 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2555 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2556 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP,
2557 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP,
2558 },
2559 [HNS_ROCE_QP_STATE_SQD] = {
2560 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2561 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2562 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP,
2563 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP,
2564 },
2565 [HNS_ROCE_QP_STATE_ERR] = {
2566 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2567 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2568 }
2569 };
2570
2571 struct hns_roce_cmd_mailbox *mailbox;
2572 struct device *dev = &hr_dev->pdev->dev;
2573 int ret = 0;
2574
2575 if (cur_state >= HNS_ROCE_QP_NUM_STATE ||
2576 new_state >= HNS_ROCE_QP_NUM_STATE ||
2577 !op[cur_state][new_state]) {
2578 dev_err(dev, "[modify_qp]not support state %d to %d\n",
2579 cur_state, new_state);
2580 return -EINVAL;
2581 }
2582
2583 if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
2584 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2585 HNS_ROCE_CMD_2RST_QP,
2586 HNS_ROCE_CMD_TIMEOUT_MSECS);
2587
2588 if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
2589 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2590 HNS_ROCE_CMD_2ERR_QP,
2591 HNS_ROCE_CMD_TIMEOUT_MSECS);
2592
2593 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2594 if (IS_ERR(mailbox))
2595 return PTR_ERR(mailbox);
2596
2597 memcpy(mailbox->buf, context, sizeof(*context));
2598
2599 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2600 op[cur_state][new_state],
2601 HNS_ROCE_CMD_TIMEOUT_MSECS);
2602
2603 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2604 return ret;
2605 }
2606
hns_roce_v1_m_sqp(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state)2607 static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2608 int attr_mask, enum ib_qp_state cur_state,
2609 enum ib_qp_state new_state)
2610 {
2611 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2612 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2613 struct hns_roce_sqp_context *context;
2614 struct device *dev = &hr_dev->pdev->dev;
2615 dma_addr_t dma_handle = 0;
2616 u32 __iomem *addr;
2617 int rq_pa_start;
2618 __le32 tmp;
2619 u32 reg_val;
2620 u64 *mtts;
2621
2622 context = kzalloc(sizeof(*context), GFP_KERNEL);
2623 if (!context)
2624 return -ENOMEM;
2625
2626 /* Search QP buf's MTTs */
2627 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2628 hr_qp->mtt.first_seg, &dma_handle);
2629 if (!mtts) {
2630 dev_err(dev, "qp buf pa find failed\n");
2631 goto out;
2632 }
2633
2634 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2635 roce_set_field(context->qp1c_bytes_4,
2636 QP1C_BYTES_4_SQ_WQE_SHIFT_M,
2637 QP1C_BYTES_4_SQ_WQE_SHIFT_S,
2638 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2639 roce_set_field(context->qp1c_bytes_4,
2640 QP1C_BYTES_4_RQ_WQE_SHIFT_M,
2641 QP1C_BYTES_4_RQ_WQE_SHIFT_S,
2642 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2643 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2644 QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2645
2646 context->sq_rq_bt_l = cpu_to_le32((u32)(dma_handle));
2647 roce_set_field(context->qp1c_bytes_12,
2648 QP1C_BYTES_12_SQ_RQ_BT_H_M,
2649 QP1C_BYTES_12_SQ_RQ_BT_H_S,
2650 ((u32)(dma_handle >> 32)));
2651
2652 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2653 QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
2654 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M,
2655 QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
2656 roce_set_bit(context->qp1c_bytes_16,
2657 QP1C_BYTES_16_SIGNALING_TYPE_S,
2658 le32_to_cpu(hr_qp->sq_signal_bits));
2659 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2660 1);
2661 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
2662 1);
2663 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S,
2664 0);
2665
2666 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M,
2667 QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head);
2668 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2669 QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2670
2671 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
2672 context->cur_rq_wqe_ba_l =
2673 cpu_to_le32((u32)(mtts[rq_pa_start]));
2674
2675 roce_set_field(context->qp1c_bytes_28,
2676 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2677 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2678 (mtts[rq_pa_start]) >> 32);
2679 roce_set_field(context->qp1c_bytes_28,
2680 QP1C_BYTES_28_RQ_CUR_IDX_M,
2681 QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
2682
2683 roce_set_field(context->qp1c_bytes_32,
2684 QP1C_BYTES_32_RX_CQ_NUM_M,
2685 QP1C_BYTES_32_RX_CQ_NUM_S,
2686 to_hr_cq(ibqp->recv_cq)->cqn);
2687 roce_set_field(context->qp1c_bytes_32,
2688 QP1C_BYTES_32_TX_CQ_NUM_M,
2689 QP1C_BYTES_32_TX_CQ_NUM_S,
2690 to_hr_cq(ibqp->send_cq)->cqn);
2691
2692 context->cur_sq_wqe_ba_l = cpu_to_le32((u32)mtts[0]);
2693
2694 roce_set_field(context->qp1c_bytes_40,
2695 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2696 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2697 (mtts[0]) >> 32);
2698 roce_set_field(context->qp1c_bytes_40,
2699 QP1C_BYTES_40_SQ_CUR_IDX_M,
2700 QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
2701
2702 /* Copy context to QP1C register */
2703 addr = (u32 __iomem *)(hr_dev->reg_base +
2704 ROCEE_QP1C_CFG0_0_REG +
2705 hr_qp->phy_port * sizeof(*context));
2706
2707 writel(le32_to_cpu(context->qp1c_bytes_4), addr);
2708 writel(le32_to_cpu(context->sq_rq_bt_l), addr + 1);
2709 writel(le32_to_cpu(context->qp1c_bytes_12), addr + 2);
2710 writel(le32_to_cpu(context->qp1c_bytes_16), addr + 3);
2711 writel(le32_to_cpu(context->qp1c_bytes_20), addr + 4);
2712 writel(le32_to_cpu(context->cur_rq_wqe_ba_l), addr + 5);
2713 writel(le32_to_cpu(context->qp1c_bytes_28), addr + 6);
2714 writel(le32_to_cpu(context->qp1c_bytes_32), addr + 7);
2715 writel(le32_to_cpu(context->cur_sq_wqe_ba_l), addr + 8);
2716 writel(le32_to_cpu(context->qp1c_bytes_40), addr + 9);
2717 }
2718
2719 /* Modify QP1C status */
2720 reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2721 hr_qp->phy_port * sizeof(*context));
2722 tmp = cpu_to_le32(reg_val);
2723 roce_set_field(tmp, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M,
2724 ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state);
2725 reg_val = le32_to_cpu(tmp);
2726 roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2727 hr_qp->phy_port * sizeof(*context), reg_val);
2728
2729 hr_qp->state = new_state;
2730 if (new_state == IB_QPS_RESET) {
2731 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2732 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2733 if (ibqp->send_cq != ibqp->recv_cq)
2734 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2735 hr_qp->qpn, NULL);
2736
2737 hr_qp->rq.head = 0;
2738 hr_qp->rq.tail = 0;
2739 hr_qp->sq.head = 0;
2740 hr_qp->sq.tail = 0;
2741 hr_qp->sq_next_wqe = 0;
2742 }
2743
2744 kfree(context);
2745 return 0;
2746
2747 out:
2748 kfree(context);
2749 return -EINVAL;
2750 }
2751
hns_roce_v1_m_qp(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state)2752 static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2753 int attr_mask, enum ib_qp_state cur_state,
2754 enum ib_qp_state new_state)
2755 {
2756 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2757 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2758 struct device *dev = &hr_dev->pdev->dev;
2759 struct hns_roce_qp_context *context;
2760 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
2761 dma_addr_t dma_handle_2 = 0;
2762 dma_addr_t dma_handle = 0;
2763 __le32 doorbell[2] = {0};
2764 int rq_pa_start = 0;
2765 u64 *mtts_2 = NULL;
2766 int ret = -EINVAL;
2767 u64 *mtts = NULL;
2768 int port;
2769 u8 port_num;
2770 u8 *dmac;
2771 u8 *smac;
2772
2773 context = kzalloc(sizeof(*context), GFP_KERNEL);
2774 if (!context)
2775 return -ENOMEM;
2776
2777 /* Search qp buf's mtts */
2778 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2779 hr_qp->mtt.first_seg, &dma_handle);
2780 if (mtts == NULL) {
2781 dev_err(dev, "qp buf pa find failed\n");
2782 goto out;
2783 }
2784
2785 /* Search IRRL's mtts */
2786 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
2787 hr_qp->qpn, &dma_handle_2);
2788 if (mtts_2 == NULL) {
2789 dev_err(dev, "qp irrl_table find failed\n");
2790 goto out;
2791 }
2792
2793 /*
2794 * Reset to init
2795 * Mandatory param:
2796 * IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2797 * Optional param: NA
2798 */
2799 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2800 roce_set_field(context->qpc_bytes_4,
2801 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2802 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2803 to_hr_qp_type(hr_qp->ibqp.qp_type));
2804
2805 roce_set_bit(context->qpc_bytes_4,
2806 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2807 roce_set_bit(context->qpc_bytes_4,
2808 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2809 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2810 roce_set_bit(context->qpc_bytes_4,
2811 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2812 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
2813 );
2814 roce_set_bit(context->qpc_bytes_4,
2815 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S,
2816 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
2817 );
2818 roce_set_bit(context->qpc_bytes_4,
2819 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2820 roce_set_field(context->qpc_bytes_4,
2821 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2822 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2823 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2824 roce_set_field(context->qpc_bytes_4,
2825 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2826 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2827 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2828 roce_set_field(context->qpc_bytes_4,
2829 QP_CONTEXT_QPC_BYTES_4_PD_M,
2830 QP_CONTEXT_QPC_BYTES_4_PD_S,
2831 to_hr_pd(ibqp->pd)->pdn);
2832 hr_qp->access_flags = attr->qp_access_flags;
2833 roce_set_field(context->qpc_bytes_8,
2834 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2835 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2836 to_hr_cq(ibqp->send_cq)->cqn);
2837 roce_set_field(context->qpc_bytes_8,
2838 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2839 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2840 to_hr_cq(ibqp->recv_cq)->cqn);
2841
2842 if (ibqp->srq)
2843 roce_set_field(context->qpc_bytes_12,
2844 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2845 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2846 to_hr_srq(ibqp->srq)->srqn);
2847
2848 roce_set_field(context->qpc_bytes_12,
2849 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2850 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2851 attr->pkey_index);
2852 hr_qp->pkey_index = attr->pkey_index;
2853 roce_set_field(context->qpc_bytes_16,
2854 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2855 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2856
2857 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2858 roce_set_field(context->qpc_bytes_4,
2859 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2860 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2861 to_hr_qp_type(hr_qp->ibqp.qp_type));
2862 roce_set_bit(context->qpc_bytes_4,
2863 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2864 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2865 roce_set_bit(context->qpc_bytes_4,
2866 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2867 !!(attr->qp_access_flags &
2868 IB_ACCESS_REMOTE_READ));
2869 roce_set_bit(context->qpc_bytes_4,
2870 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2871 !!(attr->qp_access_flags &
2872 IB_ACCESS_REMOTE_WRITE));
2873 } else {
2874 roce_set_bit(context->qpc_bytes_4,
2875 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2876 !!(hr_qp->access_flags &
2877 IB_ACCESS_REMOTE_READ));
2878 roce_set_bit(context->qpc_bytes_4,
2879 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2880 !!(hr_qp->access_flags &
2881 IB_ACCESS_REMOTE_WRITE));
2882 }
2883
2884 roce_set_bit(context->qpc_bytes_4,
2885 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2886 roce_set_field(context->qpc_bytes_4,
2887 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2888 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2889 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2890 roce_set_field(context->qpc_bytes_4,
2891 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2892 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2893 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2894 roce_set_field(context->qpc_bytes_4,
2895 QP_CONTEXT_QPC_BYTES_4_PD_M,
2896 QP_CONTEXT_QPC_BYTES_4_PD_S,
2897 to_hr_pd(ibqp->pd)->pdn);
2898
2899 roce_set_field(context->qpc_bytes_8,
2900 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2901 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2902 to_hr_cq(ibqp->send_cq)->cqn);
2903 roce_set_field(context->qpc_bytes_8,
2904 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2905 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2906 to_hr_cq(ibqp->recv_cq)->cqn);
2907
2908 if (ibqp->srq)
2909 roce_set_field(context->qpc_bytes_12,
2910 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2911 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2912 to_hr_srq(ibqp->srq)->srqn);
2913 if (attr_mask & IB_QP_PKEY_INDEX)
2914 roce_set_field(context->qpc_bytes_12,
2915 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2916 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2917 attr->pkey_index);
2918 else
2919 roce_set_field(context->qpc_bytes_12,
2920 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2921 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2922 hr_qp->pkey_index);
2923
2924 roce_set_field(context->qpc_bytes_16,
2925 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2926 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2927 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2928 if ((attr_mask & IB_QP_ALT_PATH) ||
2929 (attr_mask & IB_QP_ACCESS_FLAGS) ||
2930 (attr_mask & IB_QP_PKEY_INDEX) ||
2931 (attr_mask & IB_QP_QKEY)) {
2932 dev_err(dev, "INIT2RTR attr_mask error\n");
2933 goto out;
2934 }
2935
2936 dmac = (u8 *)attr->ah_attr.roce.dmac;
2937
2938 context->sq_rq_bt_l = cpu_to_le32((u32)(dma_handle));
2939 roce_set_field(context->qpc_bytes_24,
2940 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2941 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2942 ((u32)(dma_handle >> 32)));
2943 roce_set_bit(context->qpc_bytes_24,
2944 QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2945 1);
2946 roce_set_field(context->qpc_bytes_24,
2947 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2948 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S,
2949 attr->min_rnr_timer);
2950 context->irrl_ba_l = cpu_to_le32((u32)(dma_handle_2));
2951 roce_set_field(context->qpc_bytes_32,
2952 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M,
2953 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S,
2954 ((u32)(dma_handle_2 >> 32)) &
2955 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M);
2956 roce_set_field(context->qpc_bytes_32,
2957 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M,
2958 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S, 0);
2959 roce_set_bit(context->qpc_bytes_32,
2960 QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S,
2961 1);
2962 roce_set_bit(context->qpc_bytes_32,
2963 QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2964 le32_to_cpu(hr_qp->sq_signal_bits));
2965
2966 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2967 hr_qp->port;
2968 smac = (u8 *)hr_dev->dev_addr[port];
2969 /* when dmac equals smac or loop_idc is 1, it should loopback */
2970 if (ether_addr_equal_unaligned(dmac, smac) ||
2971 hr_dev->loop_idc == 0x1)
2972 roce_set_bit(context->qpc_bytes_32,
2973 QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
2974
2975 roce_set_bit(context->qpc_bytes_32,
2976 QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
2977 rdma_ah_get_ah_flags(&attr->ah_attr));
2978 roce_set_field(context->qpc_bytes_32,
2979 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2980 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2981 ilog2((unsigned int)attr->max_dest_rd_atomic));
2982
2983 if (attr_mask & IB_QP_DEST_QPN)
2984 roce_set_field(context->qpc_bytes_36,
2985 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2986 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2987 attr->dest_qp_num);
2988
2989 /* Configure GID index */
2990 port_num = rdma_ah_get_port_num(&attr->ah_attr);
2991 roce_set_field(context->qpc_bytes_36,
2992 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2993 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S,
2994 hns_get_gid_index(hr_dev,
2995 port_num - 1,
2996 grh->sgid_index));
2997
2998 memcpy(&(context->dmac_l), dmac, 4);
2999
3000 roce_set_field(context->qpc_bytes_44,
3001 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
3002 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S,
3003 *((u16 *)(&dmac[4])));
3004 roce_set_field(context->qpc_bytes_44,
3005 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M,
3006 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S,
3007 rdma_ah_get_static_rate(&attr->ah_attr));
3008 roce_set_field(context->qpc_bytes_44,
3009 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3010 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S,
3011 grh->hop_limit);
3012
3013 roce_set_field(context->qpc_bytes_48,
3014 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3015 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S,
3016 grh->flow_label);
3017 roce_set_field(context->qpc_bytes_48,
3018 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3019 QP_CONTEXT_QPC_BYTES_48_TCLASS_S,
3020 grh->traffic_class);
3021 roce_set_field(context->qpc_bytes_48,
3022 QP_CONTEXT_QPC_BYTES_48_MTU_M,
3023 QP_CONTEXT_QPC_BYTES_48_MTU_S, attr->path_mtu);
3024
3025 memcpy(context->dgid, grh->dgid.raw,
3026 sizeof(grh->dgid.raw));
3027
3028 dev_dbg(dev, "dmac:%x :%lx\n", context->dmac_l,
3029 roce_get_field(context->qpc_bytes_44,
3030 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
3031 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S));
3032
3033 roce_set_field(context->qpc_bytes_68,
3034 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M,
3035 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S,
3036 hr_qp->rq.head);
3037 roce_set_field(context->qpc_bytes_68,
3038 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
3039 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
3040
3041 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
3042 context->cur_rq_wqe_ba_l =
3043 cpu_to_le32((u32)(mtts[rq_pa_start]));
3044
3045 roce_set_field(context->qpc_bytes_76,
3046 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
3047 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
3048 mtts[rq_pa_start] >> 32);
3049 roce_set_field(context->qpc_bytes_76,
3050 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
3051 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
3052
3053 context->rx_rnr_time = 0;
3054
3055 roce_set_field(context->qpc_bytes_84,
3056 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M,
3057 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S,
3058 attr->rq_psn - 1);
3059 roce_set_field(context->qpc_bytes_84,
3060 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M,
3061 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S, 0);
3062
3063 roce_set_field(context->qpc_bytes_88,
3064 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3065 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S,
3066 attr->rq_psn);
3067 roce_set_bit(context->qpc_bytes_88,
3068 QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S, 0);
3069 roce_set_bit(context->qpc_bytes_88,
3070 QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S, 0);
3071 roce_set_field(context->qpc_bytes_88,
3072 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M,
3073 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S,
3074 0);
3075 roce_set_field(context->qpc_bytes_88,
3076 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M,
3077 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S,
3078 0);
3079
3080 context->dma_length = 0;
3081 context->r_key = 0;
3082 context->va_l = 0;
3083 context->va_h = 0;
3084
3085 roce_set_field(context->qpc_bytes_108,
3086 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M,
3087 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S, 0);
3088 roce_set_bit(context->qpc_bytes_108,
3089 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S, 0);
3090 roce_set_bit(context->qpc_bytes_108,
3091 QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S, 0);
3092
3093 roce_set_field(context->qpc_bytes_112,
3094 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M,
3095 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S, 0);
3096 roce_set_field(context->qpc_bytes_112,
3097 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M,
3098 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S, 0);
3099
3100 /* For chip resp ack */
3101 roce_set_field(context->qpc_bytes_156,
3102 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3103 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3104 hr_qp->phy_port);
3105 roce_set_field(context->qpc_bytes_156,
3106 QP_CONTEXT_QPC_BYTES_156_SL_M,
3107 QP_CONTEXT_QPC_BYTES_156_SL_S,
3108 rdma_ah_get_sl(&attr->ah_attr));
3109 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3110 } else if (cur_state == IB_QPS_RTR &&
3111 new_state == IB_QPS_RTS) {
3112 /* If exist optional param, return error */
3113 if ((attr_mask & IB_QP_ALT_PATH) ||
3114 (attr_mask & IB_QP_ACCESS_FLAGS) ||
3115 (attr_mask & IB_QP_QKEY) ||
3116 (attr_mask & IB_QP_PATH_MIG_STATE) ||
3117 (attr_mask & IB_QP_CUR_STATE) ||
3118 (attr_mask & IB_QP_MIN_RNR_TIMER)) {
3119 dev_err(dev, "RTR2RTS attr_mask error\n");
3120 goto out;
3121 }
3122
3123 context->rx_cur_sq_wqe_ba_l = cpu_to_le32((u32)(mtts[0]));
3124
3125 roce_set_field(context->qpc_bytes_120,
3126 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
3127 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
3128 (mtts[0]) >> 32);
3129
3130 roce_set_field(context->qpc_bytes_124,
3131 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
3132 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S, 0);
3133 roce_set_field(context->qpc_bytes_124,
3134 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M,
3135 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S, 0);
3136
3137 roce_set_field(context->qpc_bytes_128,
3138 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M,
3139 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S,
3140 attr->sq_psn);
3141 roce_set_bit(context->qpc_bytes_128,
3142 QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S, 0);
3143 roce_set_field(context->qpc_bytes_128,
3144 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M,
3145 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S,
3146 0);
3147 roce_set_bit(context->qpc_bytes_128,
3148 QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S, 0);
3149
3150 roce_set_field(context->qpc_bytes_132,
3151 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M,
3152 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S, 0);
3153 roce_set_field(context->qpc_bytes_132,
3154 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M,
3155 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S, 0);
3156
3157 roce_set_field(context->qpc_bytes_136,
3158 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M,
3159 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S,
3160 attr->sq_psn);
3161 roce_set_field(context->qpc_bytes_136,
3162 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M,
3163 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S,
3164 attr->sq_psn);
3165
3166 roce_set_field(context->qpc_bytes_140,
3167 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M,
3168 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S,
3169 (attr->sq_psn >> SQ_PSN_SHIFT));
3170 roce_set_field(context->qpc_bytes_140,
3171 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M,
3172 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S, 0);
3173 roce_set_bit(context->qpc_bytes_140,
3174 QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S, 0);
3175
3176 roce_set_field(context->qpc_bytes_148,
3177 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M,
3178 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S, 0);
3179 roce_set_field(context->qpc_bytes_148,
3180 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3181 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S,
3182 attr->retry_cnt);
3183 roce_set_field(context->qpc_bytes_148,
3184 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M,
3185 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S,
3186 attr->rnr_retry);
3187 roce_set_field(context->qpc_bytes_148,
3188 QP_CONTEXT_QPC_BYTES_148_LSN_M,
3189 QP_CONTEXT_QPC_BYTES_148_LSN_S, 0x100);
3190
3191 context->rnr_retry = 0;
3192
3193 roce_set_field(context->qpc_bytes_156,
3194 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M,
3195 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S,
3196 attr->retry_cnt);
3197 if (attr->timeout < 0x12) {
3198 dev_info(dev, "ack timeout value(0x%x) must bigger than 0x12.\n",
3199 attr->timeout);
3200 roce_set_field(context->qpc_bytes_156,
3201 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3202 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3203 0x12);
3204 } else {
3205 roce_set_field(context->qpc_bytes_156,
3206 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3207 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3208 attr->timeout);
3209 }
3210 roce_set_field(context->qpc_bytes_156,
3211 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M,
3212 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S,
3213 attr->rnr_retry);
3214 roce_set_field(context->qpc_bytes_156,
3215 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3216 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3217 hr_qp->phy_port);
3218 roce_set_field(context->qpc_bytes_156,
3219 QP_CONTEXT_QPC_BYTES_156_SL_M,
3220 QP_CONTEXT_QPC_BYTES_156_SL_S,
3221 rdma_ah_get_sl(&attr->ah_attr));
3222 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3223 roce_set_field(context->qpc_bytes_156,
3224 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3225 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S,
3226 ilog2((unsigned int)attr->max_rd_atomic));
3227 roce_set_field(context->qpc_bytes_156,
3228 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M,
3229 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S, 0);
3230 context->pkt_use_len = 0;
3231
3232 roce_set_field(context->qpc_bytes_164,
3233 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3234 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S, attr->sq_psn);
3235 roce_set_field(context->qpc_bytes_164,
3236 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M,
3237 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S, 0);
3238
3239 roce_set_field(context->qpc_bytes_168,
3240 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M,
3241 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S,
3242 attr->sq_psn);
3243 roce_set_field(context->qpc_bytes_168,
3244 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M,
3245 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S, 0);
3246 roce_set_field(context->qpc_bytes_168,
3247 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M,
3248 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S, 0);
3249 roce_set_bit(context->qpc_bytes_168,
3250 QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S, 0);
3251 roce_set_bit(context->qpc_bytes_168,
3252 QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S, 0);
3253 roce_set_bit(context->qpc_bytes_168,
3254 QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S, 0);
3255 context->sge_use_len = 0;
3256
3257 roce_set_field(context->qpc_bytes_176,
3258 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M,
3259 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S, 0);
3260 roce_set_field(context->qpc_bytes_176,
3261 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M,
3262 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S,
3263 0);
3264 roce_set_field(context->qpc_bytes_180,
3265 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M,
3266 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S, 0);
3267 roce_set_field(context->qpc_bytes_180,
3268 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3269 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3270
3271 context->tx_cur_sq_wqe_ba_l = cpu_to_le32((u32)(mtts[0]));
3272
3273 roce_set_field(context->qpc_bytes_188,
3274 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3275 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3276 (mtts[0]) >> 32);
3277 roce_set_bit(context->qpc_bytes_188,
3278 QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3279 roce_set_field(context->qpc_bytes_188,
3280 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3281 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3282 0);
3283 } else if (!((cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
3284 (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
3285 (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
3286 (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
3287 (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
3288 (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
3289 (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
3290 (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR))) {
3291 dev_err(dev, "not support this status migration\n");
3292 goto out;
3293 }
3294
3295 /* Every status migrate must change state */
3296 roce_set_field(context->qpc_bytes_144,
3297 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3298 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
3299
3300 /* SW pass context to HW */
3301 ret = hns_roce_v1_qp_modify(hr_dev, &hr_qp->mtt,
3302 to_hns_roce_state(cur_state),
3303 to_hns_roce_state(new_state), context,
3304 hr_qp);
3305 if (ret) {
3306 dev_err(dev, "hns_roce_qp_modify failed\n");
3307 goto out;
3308 }
3309
3310 /*
3311 * Use rst2init to instead of init2init with drv,
3312 * need to hw to flash RQ HEAD by DB again
3313 */
3314 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3315 /* Memory barrier */
3316 wmb();
3317
3318 roce_set_field(doorbell[0], RQ_DOORBELL_U32_4_RQ_HEAD_M,
3319 RQ_DOORBELL_U32_4_RQ_HEAD_S, hr_qp->rq.head);
3320 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_QPN_M,
3321 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
3322 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_CMD_M,
3323 RQ_DOORBELL_U32_8_CMD_S, 1);
3324 roce_set_bit(doorbell[1], RQ_DOORBELL_U32_8_HW_SYNC_S, 1);
3325
3326 if (ibqp->uobject) {
3327 hr_qp->rq.db_reg_l = hr_dev->reg_base +
3328 hr_dev->odb_offset +
3329 DB_REG_OFFSET * hr_dev->priv_uar.index;
3330 }
3331
3332 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
3333 }
3334
3335 hr_qp->state = new_state;
3336
3337 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3338 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3339 if (attr_mask & IB_QP_PORT) {
3340 hr_qp->port = attr->port_num - 1;
3341 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3342 }
3343
3344 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3345 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3346 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3347 if (ibqp->send_cq != ibqp->recv_cq)
3348 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
3349 hr_qp->qpn, NULL);
3350
3351 hr_qp->rq.head = 0;
3352 hr_qp->rq.tail = 0;
3353 hr_qp->sq.head = 0;
3354 hr_qp->sq.tail = 0;
3355 hr_qp->sq_next_wqe = 0;
3356 }
3357 out:
3358 kfree(context);
3359 return ret;
3360 }
3361
hns_roce_v1_modify_qp(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state)3362 static int hns_roce_v1_modify_qp(struct ib_qp *ibqp,
3363 const struct ib_qp_attr *attr, int attr_mask,
3364 enum ib_qp_state cur_state,
3365 enum ib_qp_state new_state)
3366 {
3367
3368 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
3369 return hns_roce_v1_m_sqp(ibqp, attr, attr_mask, cur_state,
3370 new_state);
3371 else
3372 return hns_roce_v1_m_qp(ibqp, attr, attr_mask, cur_state,
3373 new_state);
3374 }
3375
to_ib_qp_state(enum hns_roce_qp_state state)3376 static enum ib_qp_state to_ib_qp_state(enum hns_roce_qp_state state)
3377 {
3378 switch (state) {
3379 case HNS_ROCE_QP_STATE_RST:
3380 return IB_QPS_RESET;
3381 case HNS_ROCE_QP_STATE_INIT:
3382 return IB_QPS_INIT;
3383 case HNS_ROCE_QP_STATE_RTR:
3384 return IB_QPS_RTR;
3385 case HNS_ROCE_QP_STATE_RTS:
3386 return IB_QPS_RTS;
3387 case HNS_ROCE_QP_STATE_SQD:
3388 return IB_QPS_SQD;
3389 case HNS_ROCE_QP_STATE_ERR:
3390 return IB_QPS_ERR;
3391 default:
3392 return IB_QPS_ERR;
3393 }
3394 }
3395
hns_roce_v1_query_qpc(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct hns_roce_qp_context * hr_context)3396 static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
3397 struct hns_roce_qp *hr_qp,
3398 struct hns_roce_qp_context *hr_context)
3399 {
3400 struct hns_roce_cmd_mailbox *mailbox;
3401 int ret;
3402
3403 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3404 if (IS_ERR(mailbox))
3405 return PTR_ERR(mailbox);
3406
3407 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3408 HNS_ROCE_CMD_QUERY_QP,
3409 HNS_ROCE_CMD_TIMEOUT_MSECS);
3410 if (!ret)
3411 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3412 else
3413 dev_err(&hr_dev->pdev->dev, "QUERY QP cmd process error\n");
3414
3415 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3416
3417 return ret;
3418 }
3419
hns_roce_v1_q_sqp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)3420 static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3421 int qp_attr_mask,
3422 struct ib_qp_init_attr *qp_init_attr)
3423 {
3424 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3425 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3426 struct hns_roce_sqp_context context;
3427 u32 addr;
3428
3429 mutex_lock(&hr_qp->mutex);
3430
3431 if (hr_qp->state == IB_QPS_RESET) {
3432 qp_attr->qp_state = IB_QPS_RESET;
3433 goto done;
3434 }
3435
3436 addr = ROCEE_QP1C_CFG0_0_REG +
3437 hr_qp->port * sizeof(struct hns_roce_sqp_context);
3438 context.qp1c_bytes_4 = cpu_to_le32(roce_read(hr_dev, addr));
3439 context.sq_rq_bt_l = cpu_to_le32(roce_read(hr_dev, addr + 1));
3440 context.qp1c_bytes_12 = cpu_to_le32(roce_read(hr_dev, addr + 2));
3441 context.qp1c_bytes_16 = cpu_to_le32(roce_read(hr_dev, addr + 3));
3442 context.qp1c_bytes_20 = cpu_to_le32(roce_read(hr_dev, addr + 4));
3443 context.cur_rq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 5));
3444 context.qp1c_bytes_28 = cpu_to_le32(roce_read(hr_dev, addr + 6));
3445 context.qp1c_bytes_32 = cpu_to_le32(roce_read(hr_dev, addr + 7));
3446 context.cur_sq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 8));
3447 context.qp1c_bytes_40 = cpu_to_le32(roce_read(hr_dev, addr + 9));
3448
3449 hr_qp->state = roce_get_field(context.qp1c_bytes_4,
3450 QP1C_BYTES_4_QP_STATE_M,
3451 QP1C_BYTES_4_QP_STATE_S);
3452 qp_attr->qp_state = hr_qp->state;
3453 qp_attr->path_mtu = IB_MTU_256;
3454 qp_attr->path_mig_state = IB_MIG_ARMED;
3455 qp_attr->qkey = QKEY_VAL;
3456 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
3457 qp_attr->rq_psn = 0;
3458 qp_attr->sq_psn = 0;
3459 qp_attr->dest_qp_num = 1;
3460 qp_attr->qp_access_flags = 6;
3461
3462 qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
3463 QP1C_BYTES_20_PKEY_IDX_M,
3464 QP1C_BYTES_20_PKEY_IDX_S);
3465 qp_attr->port_num = hr_qp->port + 1;
3466 qp_attr->sq_draining = 0;
3467 qp_attr->max_rd_atomic = 0;
3468 qp_attr->max_dest_rd_atomic = 0;
3469 qp_attr->min_rnr_timer = 0;
3470 qp_attr->timeout = 0;
3471 qp_attr->retry_cnt = 0;
3472 qp_attr->rnr_retry = 0;
3473 qp_attr->alt_timeout = 0;
3474
3475 done:
3476 qp_attr->cur_qp_state = qp_attr->qp_state;
3477 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3478 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3479 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3480 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3481 qp_attr->cap.max_inline_data = 0;
3482 qp_init_attr->cap = qp_attr->cap;
3483 qp_init_attr->create_flags = 0;
3484
3485 mutex_unlock(&hr_qp->mutex);
3486
3487 return 0;
3488 }
3489
hns_roce_v1_q_qp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)3490 static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3491 int qp_attr_mask,
3492 struct ib_qp_init_attr *qp_init_attr)
3493 {
3494 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3495 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3496 struct device *dev = &hr_dev->pdev->dev;
3497 struct hns_roce_qp_context *context;
3498 int tmp_qp_state = 0;
3499 int ret = 0;
3500 int state;
3501
3502 context = kzalloc(sizeof(*context), GFP_KERNEL);
3503 if (!context)
3504 return -ENOMEM;
3505
3506 memset(qp_attr, 0, sizeof(*qp_attr));
3507 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3508
3509 mutex_lock(&hr_qp->mutex);
3510
3511 if (hr_qp->state == IB_QPS_RESET) {
3512 qp_attr->qp_state = IB_QPS_RESET;
3513 goto done;
3514 }
3515
3516 ret = hns_roce_v1_query_qpc(hr_dev, hr_qp, context);
3517 if (ret) {
3518 dev_err(dev, "query qpc error\n");
3519 ret = -EINVAL;
3520 goto out;
3521 }
3522
3523 state = roce_get_field(context->qpc_bytes_144,
3524 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3525 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S);
3526 tmp_qp_state = (int)to_ib_qp_state((enum hns_roce_qp_state)state);
3527 if (tmp_qp_state == -1) {
3528 dev_err(dev, "to_ib_qp_state error\n");
3529 ret = -EINVAL;
3530 goto out;
3531 }
3532 hr_qp->state = (u8)tmp_qp_state;
3533 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3534 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->qpc_bytes_48,
3535 QP_CONTEXT_QPC_BYTES_48_MTU_M,
3536 QP_CONTEXT_QPC_BYTES_48_MTU_S);
3537 qp_attr->path_mig_state = IB_MIG_ARMED;
3538 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
3539 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3540 qp_attr->qkey = QKEY_VAL;
3541
3542 qp_attr->rq_psn = roce_get_field(context->qpc_bytes_88,
3543 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3544 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S);
3545 qp_attr->sq_psn = (u32)roce_get_field(context->qpc_bytes_164,
3546 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3547 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S);
3548 qp_attr->dest_qp_num = (u8)roce_get_field(context->qpc_bytes_36,
3549 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
3550 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S);
3551 qp_attr->qp_access_flags = ((roce_get_bit(context->qpc_bytes_4,
3552 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S)) << 2) |
3553 ((roce_get_bit(context->qpc_bytes_4,
3554 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S)) << 1) |
3555 ((roce_get_bit(context->qpc_bytes_4,
3556 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S)) << 3);
3557
3558 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3559 hr_qp->ibqp.qp_type == IB_QPT_UC) {
3560 struct ib_global_route *grh =
3561 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3562
3563 rdma_ah_set_sl(&qp_attr->ah_attr,
3564 roce_get_field(context->qpc_bytes_156,
3565 QP_CONTEXT_QPC_BYTES_156_SL_M,
3566 QP_CONTEXT_QPC_BYTES_156_SL_S));
3567 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
3568 grh->flow_label =
3569 roce_get_field(context->qpc_bytes_48,
3570 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3571 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S);
3572 grh->sgid_index =
3573 roce_get_field(context->qpc_bytes_36,
3574 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
3575 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S);
3576 grh->hop_limit =
3577 roce_get_field(context->qpc_bytes_44,
3578 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3579 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S);
3580 grh->traffic_class =
3581 roce_get_field(context->qpc_bytes_48,
3582 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3583 QP_CONTEXT_QPC_BYTES_48_TCLASS_S);
3584
3585 memcpy(grh->dgid.raw, context->dgid,
3586 sizeof(grh->dgid.raw));
3587 }
3588
3589 qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
3590 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
3591 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
3592 qp_attr->port_num = hr_qp->port + 1;
3593 qp_attr->sq_draining = 0;
3594 qp_attr->max_rd_atomic = 1 << roce_get_field(context->qpc_bytes_156,
3595 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3596 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
3597 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->qpc_bytes_32,
3598 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
3599 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
3600 qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
3601 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
3602 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S));
3603 qp_attr->timeout = (u8)(roce_get_field(context->qpc_bytes_156,
3604 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3605 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S));
3606 qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3607 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3608 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
3609 qp_attr->rnr_retry = (u8)context->rnr_retry;
3610
3611 done:
3612 qp_attr->cur_qp_state = qp_attr->qp_state;
3613 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3614 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3615
3616 if (!ibqp->uobject) {
3617 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3618 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3619 } else {
3620 qp_attr->cap.max_send_wr = 0;
3621 qp_attr->cap.max_send_sge = 0;
3622 }
3623
3624 qp_init_attr->cap = qp_attr->cap;
3625
3626 out:
3627 mutex_unlock(&hr_qp->mutex);
3628 kfree(context);
3629 return ret;
3630 }
3631
hns_roce_v1_query_qp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)3632 static int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3633 int qp_attr_mask,
3634 struct ib_qp_init_attr *qp_init_attr)
3635 {
3636 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3637
3638 return hr_qp->doorbell_qpn <= 1 ?
3639 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
3640 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3641 }
3642
hns_roce_check_sdb_status(struct hns_roce_dev * hr_dev,u32 * old_send,u32 * old_retry,u32 * tsp_st,u32 * success_flags)3643 static void hns_roce_check_sdb_status(struct hns_roce_dev *hr_dev,
3644 u32 *old_send, u32 *old_retry,
3645 u32 *tsp_st, u32 *success_flags)
3646 {
3647 __le32 *old_send_tmp, *old_retry_tmp;
3648 u32 sdb_retry_cnt;
3649 u32 sdb_send_ptr;
3650 u32 cur_cnt, old_cnt;
3651 __le32 tmp, tmp1;
3652 u32 send_ptr;
3653
3654 sdb_send_ptr = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3655 sdb_retry_cnt = roce_read(hr_dev, ROCEE_SDB_RETRY_CNT_REG);
3656 tmp = cpu_to_le32(sdb_send_ptr);
3657 tmp1 = cpu_to_le32(sdb_retry_cnt);
3658 cur_cnt = roce_get_field(tmp, ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3659 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3660 roce_get_field(tmp1, ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3661 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3662
3663 old_send_tmp = (__le32 *)old_send;
3664 old_retry_tmp = (__le32 *)old_retry;
3665 if (!roce_get_bit(*tsp_st, ROCEE_CNT_CLR_CE_CNT_CLR_CE_S)) {
3666 old_cnt = roce_get_field(*old_send_tmp,
3667 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3668 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3669 roce_get_field(*old_retry_tmp,
3670 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3671 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3672 if (cur_cnt - old_cnt > SDB_ST_CMP_VAL)
3673 *success_flags = 1;
3674 } else {
3675 old_cnt = roce_get_field(*old_send_tmp,
3676 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3677 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S);
3678 if (cur_cnt - old_cnt > SDB_ST_CMP_VAL) {
3679 *success_flags = 1;
3680 } else {
3681 send_ptr = roce_get_field(*old_send_tmp,
3682 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3683 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3684 roce_get_field(tmp1,
3685 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3686 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3687 roce_set_field(*old_send_tmp,
3688 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3689 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S,
3690 send_ptr);
3691 }
3692 }
3693 }
3694
check_qp_db_process_status(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,u32 sdb_issue_ptr,u32 * sdb_inv_cnt,u32 * wait_stage)3695 static int check_qp_db_process_status(struct hns_roce_dev *hr_dev,
3696 struct hns_roce_qp *hr_qp,
3697 u32 sdb_issue_ptr,
3698 u32 *sdb_inv_cnt,
3699 u32 *wait_stage)
3700 {
3701 struct device *dev = &hr_dev->pdev->dev;
3702 u32 sdb_send_ptr, old_send;
3703 __le32 sdb_issue_ptr_tmp;
3704 __le32 sdb_send_ptr_tmp;
3705 u32 success_flags = 0;
3706 unsigned long end;
3707 u32 old_retry;
3708 u32 inv_cnt;
3709 u32 tsp_st;
3710 __le32 tmp;
3711
3712 if (*wait_stage > HNS_ROCE_V1_DB_STAGE2 ||
3713 *wait_stage < HNS_ROCE_V1_DB_STAGE1) {
3714 dev_err(dev, "QP(0x%lx) db status wait stage(%d) error!\n",
3715 hr_qp->qpn, *wait_stage);
3716 return -EINVAL;
3717 }
3718
3719 /* Calculate the total timeout for the entire verification process */
3720 end = msecs_to_jiffies(HNS_ROCE_V1_CHECK_DB_TIMEOUT_MSECS) + jiffies;
3721
3722 if (*wait_stage == HNS_ROCE_V1_DB_STAGE1) {
3723 /* Query db process status, until hw process completely */
3724 sdb_send_ptr = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3725 while (roce_hw_index_cmp_lt(sdb_send_ptr, sdb_issue_ptr,
3726 ROCEE_SDB_PTR_CMP_BITS)) {
3727 if (!time_before(jiffies, end)) {
3728 dev_dbg(dev, "QP(0x%lx) db process stage1 timeout. issue 0x%x send 0x%x.\n",
3729 hr_qp->qpn, sdb_issue_ptr,
3730 sdb_send_ptr);
3731 return 0;
3732 }
3733
3734 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3735 sdb_send_ptr = roce_read(hr_dev,
3736 ROCEE_SDB_SEND_PTR_REG);
3737 }
3738
3739 sdb_send_ptr_tmp = cpu_to_le32(sdb_send_ptr);
3740 sdb_issue_ptr_tmp = cpu_to_le32(sdb_issue_ptr);
3741 if (roce_get_field(sdb_issue_ptr_tmp,
3742 ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M,
3743 ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S) ==
3744 roce_get_field(sdb_send_ptr_tmp,
3745 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3746 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S)) {
3747 old_send = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3748 old_retry = roce_read(hr_dev, ROCEE_SDB_RETRY_CNT_REG);
3749
3750 do {
3751 tsp_st = roce_read(hr_dev, ROCEE_TSP_BP_ST_REG);
3752 tmp = cpu_to_le32(tsp_st);
3753 if (roce_get_bit(tmp,
3754 ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S) == 1) {
3755 *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3756 return 0;
3757 }
3758
3759 if (!time_before(jiffies, end)) {
3760 dev_dbg(dev, "QP(0x%lx) db process stage1 timeout when send ptr equals issue ptr.\n"
3761 "issue 0x%x send 0x%x.\n",
3762 hr_qp->qpn,
3763 le32_to_cpu(sdb_issue_ptr_tmp),
3764 le32_to_cpu(sdb_send_ptr_tmp));
3765 return 0;
3766 }
3767
3768 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3769
3770 hns_roce_check_sdb_status(hr_dev, &old_send,
3771 &old_retry, &tsp_st,
3772 &success_flags);
3773 } while (!success_flags);
3774 }
3775
3776 *wait_stage = HNS_ROCE_V1_DB_STAGE2;
3777
3778 /* Get list pointer */
3779 *sdb_inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3780 dev_dbg(dev, "QP(0x%lx) db process stage2. inv cnt = 0x%x.\n",
3781 hr_qp->qpn, *sdb_inv_cnt);
3782 }
3783
3784 if (*wait_stage == HNS_ROCE_V1_DB_STAGE2) {
3785 /* Query db's list status, until hw reversal */
3786 inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3787 while (roce_hw_index_cmp_lt(inv_cnt,
3788 *sdb_inv_cnt + SDB_INV_CNT_OFFSET,
3789 ROCEE_SDB_CNT_CMP_BITS)) {
3790 if (!time_before(jiffies, end)) {
3791 dev_dbg(dev, "QP(0x%lx) db process stage2 timeout. inv cnt 0x%x.\n",
3792 hr_qp->qpn, inv_cnt);
3793 return 0;
3794 }
3795
3796 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3797 inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3798 }
3799
3800 *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3801 }
3802
3803 return 0;
3804 }
3805
check_qp_reset_state(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct hns_roce_qp_work * qp_work_entry,int * is_timeout)3806 static int check_qp_reset_state(struct hns_roce_dev *hr_dev,
3807 struct hns_roce_qp *hr_qp,
3808 struct hns_roce_qp_work *qp_work_entry,
3809 int *is_timeout)
3810 {
3811 struct device *dev = &hr_dev->pdev->dev;
3812 u32 sdb_issue_ptr;
3813 int ret;
3814
3815 if (hr_qp->state != IB_QPS_RESET) {
3816 /* Set qp to ERR, waiting for hw complete processing all dbs */
3817 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3818 IB_QPS_ERR);
3819 if (ret) {
3820 dev_err(dev, "Modify QP(0x%lx) to ERR failed!\n",
3821 hr_qp->qpn);
3822 return ret;
3823 }
3824
3825 /* Record issued doorbell */
3826 sdb_issue_ptr = roce_read(hr_dev, ROCEE_SDB_ISSUE_PTR_REG);
3827 qp_work_entry->sdb_issue_ptr = sdb_issue_ptr;
3828 qp_work_entry->db_wait_stage = HNS_ROCE_V1_DB_STAGE1;
3829
3830 /* Query db process status, until hw process completely */
3831 ret = check_qp_db_process_status(hr_dev, hr_qp, sdb_issue_ptr,
3832 &qp_work_entry->sdb_inv_cnt,
3833 &qp_work_entry->db_wait_stage);
3834 if (ret) {
3835 dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3836 hr_qp->qpn);
3837 return ret;
3838 }
3839
3840 if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK) {
3841 qp_work_entry->sche_cnt = 0;
3842 *is_timeout = 1;
3843 return 0;
3844 }
3845
3846 /* Modify qp to reset before destroying qp */
3847 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3848 IB_QPS_RESET);
3849 if (ret) {
3850 dev_err(dev, "Modify QP(0x%lx) to RST failed!\n",
3851 hr_qp->qpn);
3852 return ret;
3853 }
3854 }
3855
3856 return 0;
3857 }
3858
hns_roce_v1_destroy_qp_work_fn(struct work_struct * work)3859 static void hns_roce_v1_destroy_qp_work_fn(struct work_struct *work)
3860 {
3861 struct hns_roce_qp_work *qp_work_entry;
3862 struct hns_roce_v1_priv *priv;
3863 struct hns_roce_dev *hr_dev;
3864 struct hns_roce_qp *hr_qp;
3865 struct device *dev;
3866 unsigned long qpn;
3867 int ret;
3868
3869 qp_work_entry = container_of(work, struct hns_roce_qp_work, work);
3870 hr_dev = to_hr_dev(qp_work_entry->ib_dev);
3871 dev = &hr_dev->pdev->dev;
3872 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
3873 hr_qp = qp_work_entry->qp;
3874 qpn = hr_qp->qpn;
3875
3876 dev_dbg(dev, "Schedule destroy QP(0x%lx) work.\n", qpn);
3877
3878 qp_work_entry->sche_cnt++;
3879
3880 /* Query db process status, until hw process completely */
3881 ret = check_qp_db_process_status(hr_dev, hr_qp,
3882 qp_work_entry->sdb_issue_ptr,
3883 &qp_work_entry->sdb_inv_cnt,
3884 &qp_work_entry->db_wait_stage);
3885 if (ret) {
3886 dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3887 qpn);
3888 return;
3889 }
3890
3891 if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK &&
3892 priv->des_qp.requeue_flag) {
3893 queue_work(priv->des_qp.qp_wq, work);
3894 return;
3895 }
3896
3897 /* Modify qp to reset before destroying qp */
3898 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3899 IB_QPS_RESET);
3900 if (ret) {
3901 dev_err(dev, "Modify QP(0x%lx) to RST failed!\n", qpn);
3902 return;
3903 }
3904
3905 hns_roce_qp_remove(hr_dev, hr_qp);
3906 hns_roce_qp_free(hr_dev, hr_qp);
3907
3908 if (hr_qp->ibqp.qp_type == IB_QPT_RC) {
3909 /* RC QP, release QPN */
3910 hns_roce_release_range_qp(hr_dev, qpn, 1);
3911 kfree(hr_qp);
3912 } else
3913 kfree(hr_to_hr_sqp(hr_qp));
3914
3915 kfree(qp_work_entry);
3916
3917 dev_dbg(dev, "Accomplished destroy QP(0x%lx) work.\n", qpn);
3918 }
3919
hns_roce_v1_destroy_qp(struct ib_qp * ibqp)3920 int hns_roce_v1_destroy_qp(struct ib_qp *ibqp)
3921 {
3922 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3923 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3924 struct device *dev = &hr_dev->pdev->dev;
3925 struct hns_roce_qp_work qp_work_entry;
3926 struct hns_roce_qp_work *qp_work;
3927 struct hns_roce_v1_priv *priv;
3928 struct hns_roce_cq *send_cq, *recv_cq;
3929 int is_user = !!ibqp->pd->uobject;
3930 int is_timeout = 0;
3931 int ret;
3932
3933 ret = check_qp_reset_state(hr_dev, hr_qp, &qp_work_entry, &is_timeout);
3934 if (ret) {
3935 dev_err(dev, "QP reset state check failed(%d)!\n", ret);
3936 return ret;
3937 }
3938
3939 send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
3940 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
3941
3942 hns_roce_lock_cqs(send_cq, recv_cq);
3943 if (!is_user) {
3944 __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
3945 to_hr_srq(hr_qp->ibqp.srq) : NULL);
3946 if (send_cq != recv_cq)
3947 __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3948 }
3949 hns_roce_unlock_cqs(send_cq, recv_cq);
3950
3951 if (!is_timeout) {
3952 hns_roce_qp_remove(hr_dev, hr_qp);
3953 hns_roce_qp_free(hr_dev, hr_qp);
3954
3955 /* RC QP, release QPN */
3956 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3957 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3958 }
3959
3960 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3961
3962 if (is_user)
3963 ib_umem_release(hr_qp->umem);
3964 else {
3965 kfree(hr_qp->sq.wrid);
3966 kfree(hr_qp->rq.wrid);
3967
3968 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
3969 }
3970
3971 if (!is_timeout) {
3972 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3973 kfree(hr_qp);
3974 else
3975 kfree(hr_to_hr_sqp(hr_qp));
3976 } else {
3977 qp_work = kzalloc(sizeof(*qp_work), GFP_KERNEL);
3978 if (!qp_work)
3979 return -ENOMEM;
3980
3981 INIT_WORK(&qp_work->work, hns_roce_v1_destroy_qp_work_fn);
3982 qp_work->ib_dev = &hr_dev->ib_dev;
3983 qp_work->qp = hr_qp;
3984 qp_work->db_wait_stage = qp_work_entry.db_wait_stage;
3985 qp_work->sdb_issue_ptr = qp_work_entry.sdb_issue_ptr;
3986 qp_work->sdb_inv_cnt = qp_work_entry.sdb_inv_cnt;
3987 qp_work->sche_cnt = qp_work_entry.sche_cnt;
3988
3989 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
3990 queue_work(priv->des_qp.qp_wq, &qp_work->work);
3991 dev_dbg(dev, "Begin destroy QP(0x%lx) work.\n", hr_qp->qpn);
3992 }
3993
3994 return 0;
3995 }
3996
hns_roce_v1_destroy_cq(struct ib_cq * ibcq)3997 static int hns_roce_v1_destroy_cq(struct ib_cq *ibcq)
3998 {
3999 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
4000 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
4001 struct device *dev = &hr_dev->pdev->dev;
4002 u32 cqe_cnt_ori;
4003 u32 cqe_cnt_cur;
4004 u32 cq_buf_size;
4005 int wait_time = 0;
4006 int ret = 0;
4007
4008 hns_roce_free_cq(hr_dev, hr_cq);
4009
4010 /*
4011 * Before freeing cq buffer, we need to ensure that the outstanding CQE
4012 * have been written by checking the CQE counter.
4013 */
4014 cqe_cnt_ori = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
4015 while (1) {
4016 if (roce_read(hr_dev, ROCEE_CAEP_CQE_WCMD_EMPTY) &
4017 HNS_ROCE_CQE_WCMD_EMPTY_BIT)
4018 break;
4019
4020 cqe_cnt_cur = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
4021 if ((cqe_cnt_cur - cqe_cnt_ori) >= HNS_ROCE_MIN_CQE_CNT)
4022 break;
4023
4024 msleep(HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS);
4025 if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
4026 dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
4027 hr_cq->cqn);
4028 ret = -ETIMEDOUT;
4029 break;
4030 }
4031 wait_time++;
4032 }
4033
4034 hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
4035
4036 if (ibcq->uobject)
4037 ib_umem_release(hr_cq->umem);
4038 else {
4039 /* Free the buff of stored cq */
4040 cq_buf_size = (ibcq->cqe + 1) * hr_dev->caps.cq_entry_sz;
4041 hns_roce_buf_free(hr_dev, cq_buf_size, &hr_cq->hr_buf.hr_buf);
4042 }
4043
4044 kfree(hr_cq);
4045
4046 return ret;
4047 }
4048
set_eq_cons_index_v1(struct hns_roce_eq * eq,int req_not)4049 static void set_eq_cons_index_v1(struct hns_roce_eq *eq, int req_not)
4050 {
4051 roce_raw_write((eq->cons_index & HNS_ROCE_V1_CONS_IDX_M) |
4052 (req_not << eq->log_entries), eq->doorbell);
4053 }
4054
hns_roce_v1_wq_catas_err_handle(struct hns_roce_dev * hr_dev,struct hns_roce_aeqe * aeqe,int qpn)4055 static void hns_roce_v1_wq_catas_err_handle(struct hns_roce_dev *hr_dev,
4056 struct hns_roce_aeqe *aeqe, int qpn)
4057 {
4058 struct device *dev = &hr_dev->pdev->dev;
4059
4060 dev_warn(dev, "Local Work Queue Catastrophic Error.\n");
4061 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
4062 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
4063 case HNS_ROCE_LWQCE_QPC_ERROR:
4064 dev_warn(dev, "QP %d, QPC error.\n", qpn);
4065 break;
4066 case HNS_ROCE_LWQCE_MTU_ERROR:
4067 dev_warn(dev, "QP %d, MTU error.\n", qpn);
4068 break;
4069 case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR:
4070 dev_warn(dev, "QP %d, WQE BA addr error.\n", qpn);
4071 break;
4072 case HNS_ROCE_LWQCE_WQE_ADDR_ERROR:
4073 dev_warn(dev, "QP %d, WQE addr error.\n", qpn);
4074 break;
4075 case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR:
4076 dev_warn(dev, "QP %d, WQE shift error\n", qpn);
4077 break;
4078 case HNS_ROCE_LWQCE_SL_ERROR:
4079 dev_warn(dev, "QP %d, SL error.\n", qpn);
4080 break;
4081 case HNS_ROCE_LWQCE_PORT_ERROR:
4082 dev_warn(dev, "QP %d, port error.\n", qpn);
4083 break;
4084 default:
4085 break;
4086 }
4087 }
4088
hns_roce_v1_local_wq_access_err_handle(struct hns_roce_dev * hr_dev,struct hns_roce_aeqe * aeqe,int qpn)4089 static void hns_roce_v1_local_wq_access_err_handle(struct hns_roce_dev *hr_dev,
4090 struct hns_roce_aeqe *aeqe,
4091 int qpn)
4092 {
4093 struct device *dev = &hr_dev->pdev->dev;
4094
4095 dev_warn(dev, "Local Access Violation Work Queue Error.\n");
4096 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
4097 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
4098 case HNS_ROCE_LAVWQE_R_KEY_VIOLATION:
4099 dev_warn(dev, "QP %d, R_key violation.\n", qpn);
4100 break;
4101 case HNS_ROCE_LAVWQE_LENGTH_ERROR:
4102 dev_warn(dev, "QP %d, length error.\n", qpn);
4103 break;
4104 case HNS_ROCE_LAVWQE_VA_ERROR:
4105 dev_warn(dev, "QP %d, VA error.\n", qpn);
4106 break;
4107 case HNS_ROCE_LAVWQE_PD_ERROR:
4108 dev_err(dev, "QP %d, PD error.\n", qpn);
4109 break;
4110 case HNS_ROCE_LAVWQE_RW_ACC_ERROR:
4111 dev_warn(dev, "QP %d, rw acc error.\n", qpn);
4112 break;
4113 case HNS_ROCE_LAVWQE_KEY_STATE_ERROR:
4114 dev_warn(dev, "QP %d, key state error.\n", qpn);
4115 break;
4116 case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR:
4117 dev_warn(dev, "QP %d, MR operation error.\n", qpn);
4118 break;
4119 default:
4120 break;
4121 }
4122 }
4123
hns_roce_v1_qp_err_handle(struct hns_roce_dev * hr_dev,struct hns_roce_aeqe * aeqe,int event_type)4124 static void hns_roce_v1_qp_err_handle(struct hns_roce_dev *hr_dev,
4125 struct hns_roce_aeqe *aeqe,
4126 int event_type)
4127 {
4128 struct device *dev = &hr_dev->pdev->dev;
4129 int phy_port;
4130 int qpn;
4131
4132 qpn = roce_get_field(aeqe->event.qp_event.qp,
4133 HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M,
4134 HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S);
4135 phy_port = roce_get_field(aeqe->event.qp_event.qp,
4136 HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M,
4137 HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S);
4138 if (qpn <= 1)
4139 qpn = HNS_ROCE_MAX_PORTS * qpn + phy_port;
4140
4141 switch (event_type) {
4142 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
4143 dev_warn(dev, "Invalid Req Local Work Queue Error.\n"
4144 "QP %d, phy_port %d.\n", qpn, phy_port);
4145 break;
4146 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
4147 hns_roce_v1_wq_catas_err_handle(hr_dev, aeqe, qpn);
4148 break;
4149 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
4150 hns_roce_v1_local_wq_access_err_handle(hr_dev, aeqe, qpn);
4151 break;
4152 default:
4153 break;
4154 }
4155
4156 hns_roce_qp_event(hr_dev, qpn, event_type);
4157 }
4158
hns_roce_v1_cq_err_handle(struct hns_roce_dev * hr_dev,struct hns_roce_aeqe * aeqe,int event_type)4159 static void hns_roce_v1_cq_err_handle(struct hns_roce_dev *hr_dev,
4160 struct hns_roce_aeqe *aeqe,
4161 int event_type)
4162 {
4163 struct device *dev = &hr_dev->pdev->dev;
4164 u32 cqn;
4165
4166 cqn = roce_get_field(aeqe->event.cq_event.cq,
4167 HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M,
4168 HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S);
4169
4170 switch (event_type) {
4171 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4172 dev_warn(dev, "CQ 0x%x access err.\n", cqn);
4173 break;
4174 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
4175 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
4176 break;
4177 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
4178 dev_warn(dev, "CQ 0x%x ID invalid.\n", cqn);
4179 break;
4180 default:
4181 break;
4182 }
4183
4184 hns_roce_cq_event(hr_dev, cqn, event_type);
4185 }
4186
hns_roce_v1_db_overflow_handle(struct hns_roce_dev * hr_dev,struct hns_roce_aeqe * aeqe)4187 static void hns_roce_v1_db_overflow_handle(struct hns_roce_dev *hr_dev,
4188 struct hns_roce_aeqe *aeqe)
4189 {
4190 struct device *dev = &hr_dev->pdev->dev;
4191
4192 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
4193 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
4194 case HNS_ROCE_DB_SUBTYPE_SDB_OVF:
4195 dev_warn(dev, "SDB overflow.\n");
4196 break;
4197 case HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF:
4198 dev_warn(dev, "SDB almost overflow.\n");
4199 break;
4200 case HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP:
4201 dev_warn(dev, "SDB almost empty.\n");
4202 break;
4203 case HNS_ROCE_DB_SUBTYPE_ODB_OVF:
4204 dev_warn(dev, "ODB overflow.\n");
4205 break;
4206 case HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF:
4207 dev_warn(dev, "ODB almost overflow.\n");
4208 break;
4209 case HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP:
4210 dev_warn(dev, "SDB almost empty.\n");
4211 break;
4212 default:
4213 break;
4214 }
4215 }
4216
get_aeqe_v1(struct hns_roce_eq * eq,u32 entry)4217 static struct hns_roce_aeqe *get_aeqe_v1(struct hns_roce_eq *eq, u32 entry)
4218 {
4219 unsigned long off = (entry & (eq->entries - 1)) *
4220 HNS_ROCE_AEQ_ENTRY_SIZE;
4221
4222 return (struct hns_roce_aeqe *)((u8 *)
4223 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
4224 off % HNS_ROCE_BA_SIZE);
4225 }
4226
next_aeqe_sw_v1(struct hns_roce_eq * eq)4227 static struct hns_roce_aeqe *next_aeqe_sw_v1(struct hns_roce_eq *eq)
4228 {
4229 struct hns_roce_aeqe *aeqe = get_aeqe_v1(eq, eq->cons_index);
4230
4231 return (roce_get_bit(aeqe->asyn, HNS_ROCE_AEQE_U32_4_OWNER_S) ^
4232 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
4233 }
4234
hns_roce_v1_aeq_int(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)4235 static int hns_roce_v1_aeq_int(struct hns_roce_dev *hr_dev,
4236 struct hns_roce_eq *eq)
4237 {
4238 struct device *dev = &hr_dev->pdev->dev;
4239 struct hns_roce_aeqe *aeqe;
4240 int aeqes_found = 0;
4241 int event_type;
4242
4243 while ((aeqe = next_aeqe_sw_v1(eq))) {
4244
4245 /* Make sure we read the AEQ entry after we have checked the
4246 * ownership bit
4247 */
4248 dma_rmb();
4249
4250 dev_dbg(dev, "aeqe = %p, aeqe->asyn.event_type = 0x%lx\n", aeqe,
4251 roce_get_field(aeqe->asyn,
4252 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
4253 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S));
4254 event_type = roce_get_field(aeqe->asyn,
4255 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
4256 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S);
4257 switch (event_type) {
4258 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
4259 dev_warn(dev, "PATH MIG not supported\n");
4260 break;
4261 case HNS_ROCE_EVENT_TYPE_COMM_EST:
4262 dev_warn(dev, "COMMUNICATION established\n");
4263 break;
4264 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
4265 dev_warn(dev, "SQ DRAINED not supported\n");
4266 break;
4267 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
4268 dev_warn(dev, "PATH MIG failed\n");
4269 break;
4270 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
4271 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
4272 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
4273 hns_roce_v1_qp_err_handle(hr_dev, aeqe, event_type);
4274 break;
4275 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
4276 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
4277 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
4278 dev_warn(dev, "SRQ not support!\n");
4279 break;
4280 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4281 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
4282 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
4283 hns_roce_v1_cq_err_handle(hr_dev, aeqe, event_type);
4284 break;
4285 case HNS_ROCE_EVENT_TYPE_PORT_CHANGE:
4286 dev_warn(dev, "port change.\n");
4287 break;
4288 case HNS_ROCE_EVENT_TYPE_MB:
4289 hns_roce_cmd_event(hr_dev,
4290 le16_to_cpu(aeqe->event.cmd.token),
4291 aeqe->event.cmd.status,
4292 le64_to_cpu(aeqe->event.cmd.out_param
4293 ));
4294 break;
4295 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
4296 hns_roce_v1_db_overflow_handle(hr_dev, aeqe);
4297 break;
4298 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
4299 dev_warn(dev, "CEQ 0x%lx overflow.\n",
4300 roce_get_field(aeqe->event.ce_event.ceqe,
4301 HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_M,
4302 HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S));
4303 break;
4304 default:
4305 dev_warn(dev, "Unhandled event %d on EQ %d at idx %u.\n",
4306 event_type, eq->eqn, eq->cons_index);
4307 break;
4308 }
4309
4310 eq->cons_index++;
4311 aeqes_found = 1;
4312
4313 if (eq->cons_index > 2 * hr_dev->caps.aeqe_depth - 1) {
4314 dev_warn(dev, "cons_index overflow, set back to 0.\n");
4315 eq->cons_index = 0;
4316 }
4317 }
4318
4319 set_eq_cons_index_v1(eq, 0);
4320
4321 return aeqes_found;
4322 }
4323
get_ceqe_v1(struct hns_roce_eq * eq,u32 entry)4324 static struct hns_roce_ceqe *get_ceqe_v1(struct hns_roce_eq *eq, u32 entry)
4325 {
4326 unsigned long off = (entry & (eq->entries - 1)) *
4327 HNS_ROCE_CEQ_ENTRY_SIZE;
4328
4329 return (struct hns_roce_ceqe *)((u8 *)
4330 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
4331 off % HNS_ROCE_BA_SIZE);
4332 }
4333
next_ceqe_sw_v1(struct hns_roce_eq * eq)4334 static struct hns_roce_ceqe *next_ceqe_sw_v1(struct hns_roce_eq *eq)
4335 {
4336 struct hns_roce_ceqe *ceqe = get_ceqe_v1(eq, eq->cons_index);
4337
4338 return (!!(roce_get_bit(ceqe->comp,
4339 HNS_ROCE_CEQE_CEQE_COMP_OWNER_S))) ^
4340 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
4341 }
4342
hns_roce_v1_ceq_int(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)4343 static int hns_roce_v1_ceq_int(struct hns_roce_dev *hr_dev,
4344 struct hns_roce_eq *eq)
4345 {
4346 struct hns_roce_ceqe *ceqe;
4347 int ceqes_found = 0;
4348 u32 cqn;
4349
4350 while ((ceqe = next_ceqe_sw_v1(eq))) {
4351
4352 /* Make sure we read CEQ entry after we have checked the
4353 * ownership bit
4354 */
4355 dma_rmb();
4356
4357 cqn = roce_get_field(ceqe->comp,
4358 HNS_ROCE_CEQE_CEQE_COMP_CQN_M,
4359 HNS_ROCE_CEQE_CEQE_COMP_CQN_S);
4360 hns_roce_cq_completion(hr_dev, cqn);
4361
4362 ++eq->cons_index;
4363 ceqes_found = 1;
4364
4365 if (eq->cons_index > 2 * hr_dev->caps.ceqe_depth - 1) {
4366 dev_warn(&eq->hr_dev->pdev->dev,
4367 "cons_index overflow, set back to 0.\n");
4368 eq->cons_index = 0;
4369 }
4370 }
4371
4372 set_eq_cons_index_v1(eq, 0);
4373
4374 return ceqes_found;
4375 }
4376
hns_roce_v1_msix_interrupt_eq(int irq,void * eq_ptr)4377 static irqreturn_t hns_roce_v1_msix_interrupt_eq(int irq, void *eq_ptr)
4378 {
4379 struct hns_roce_eq *eq = eq_ptr;
4380 struct hns_roce_dev *hr_dev = eq->hr_dev;
4381 int int_work = 0;
4382
4383 if (eq->type_flag == HNS_ROCE_CEQ)
4384 /* CEQ irq routine, CEQ is pulse irq, not clear */
4385 int_work = hns_roce_v1_ceq_int(hr_dev, eq);
4386 else
4387 /* AEQ irq routine, AEQ is pulse irq, not clear */
4388 int_work = hns_roce_v1_aeq_int(hr_dev, eq);
4389
4390 return IRQ_RETVAL(int_work);
4391 }
4392
hns_roce_v1_msix_interrupt_abn(int irq,void * dev_id)4393 static irqreturn_t hns_roce_v1_msix_interrupt_abn(int irq, void *dev_id)
4394 {
4395 struct hns_roce_dev *hr_dev = dev_id;
4396 struct device *dev = &hr_dev->pdev->dev;
4397 int int_work = 0;
4398 u32 caepaemask_val;
4399 u32 cealmovf_val;
4400 u32 caepaest_val;
4401 u32 aeshift_val;
4402 u32 ceshift_val;
4403 u32 cemask_val;
4404 __le32 tmp;
4405 int i;
4406
4407 /*
4408 * Abnormal interrupt:
4409 * AEQ overflow, ECC multi-bit err, CEQ overflow must clear
4410 * interrupt, mask irq, clear irq, cancel mask operation
4411 */
4412 aeshift_val = roce_read(hr_dev, ROCEE_CAEP_AEQC_AEQE_SHIFT_REG);
4413 tmp = cpu_to_le32(aeshift_val);
4414
4415 /* AEQE overflow */
4416 if (roce_get_bit(tmp,
4417 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S) == 1) {
4418 dev_warn(dev, "AEQ overflow!\n");
4419
4420 /* Set mask */
4421 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4422 tmp = cpu_to_le32(caepaemask_val);
4423 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4424 HNS_ROCE_INT_MASK_ENABLE);
4425 caepaemask_val = le32_to_cpu(tmp);
4426 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4427
4428 /* Clear int state(INT_WC : write 1 clear) */
4429 caepaest_val = roce_read(hr_dev, ROCEE_CAEP_AE_ST_REG);
4430 tmp = cpu_to_le32(caepaest_val);
4431 roce_set_bit(tmp, ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S, 1);
4432 caepaest_val = le32_to_cpu(tmp);
4433 roce_write(hr_dev, ROCEE_CAEP_AE_ST_REG, caepaest_val);
4434
4435 /* Clear mask */
4436 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4437 tmp = cpu_to_le32(caepaemask_val);
4438 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4439 HNS_ROCE_INT_MASK_DISABLE);
4440 caepaemask_val = le32_to_cpu(tmp);
4441 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4442 }
4443
4444 /* CEQ almost overflow */
4445 for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4446 ceshift_val = roce_read(hr_dev, ROCEE_CAEP_CEQC_SHIFT_0_REG +
4447 i * CEQ_REG_OFFSET);
4448 tmp = cpu_to_le32(ceshift_val);
4449
4450 if (roce_get_bit(tmp,
4451 ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S) == 1) {
4452 dev_warn(dev, "CEQ[%d] almost overflow!\n", i);
4453 int_work++;
4454
4455 /* Set mask */
4456 cemask_val = roce_read(hr_dev,
4457 ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4458 i * CEQ_REG_OFFSET);
4459 tmp = cpu_to_le32(cemask_val);
4460 roce_set_bit(tmp,
4461 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4462 HNS_ROCE_INT_MASK_ENABLE);
4463 cemask_val = le32_to_cpu(tmp);
4464 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4465 i * CEQ_REG_OFFSET, cemask_val);
4466
4467 /* Clear int state(INT_WC : write 1 clear) */
4468 cealmovf_val = roce_read(hr_dev,
4469 ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4470 i * CEQ_REG_OFFSET);
4471 tmp = cpu_to_le32(cealmovf_val);
4472 roce_set_bit(tmp,
4473 ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S,
4474 1);
4475 cealmovf_val = le32_to_cpu(tmp);
4476 roce_write(hr_dev, ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4477 i * CEQ_REG_OFFSET, cealmovf_val);
4478
4479 /* Clear mask */
4480 cemask_val = roce_read(hr_dev,
4481 ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4482 i * CEQ_REG_OFFSET);
4483 tmp = cpu_to_le32(cemask_val);
4484 roce_set_bit(tmp,
4485 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4486 HNS_ROCE_INT_MASK_DISABLE);
4487 cemask_val = le32_to_cpu(tmp);
4488 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4489 i * CEQ_REG_OFFSET, cemask_val);
4490 }
4491 }
4492
4493 /* ECC multi-bit error alarm */
4494 dev_warn(dev, "ECC UCERR ALARM: 0x%x, 0x%x, 0x%x\n",
4495 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM0_REG),
4496 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM1_REG),
4497 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM2_REG));
4498
4499 dev_warn(dev, "ECC CERR ALARM: 0x%x, 0x%x, 0x%x\n",
4500 roce_read(hr_dev, ROCEE_ECC_CERR_ALM0_REG),
4501 roce_read(hr_dev, ROCEE_ECC_CERR_ALM1_REG),
4502 roce_read(hr_dev, ROCEE_ECC_CERR_ALM2_REG));
4503
4504 return IRQ_RETVAL(int_work);
4505 }
4506
hns_roce_v1_int_mask_enable(struct hns_roce_dev * hr_dev)4507 static void hns_roce_v1_int_mask_enable(struct hns_roce_dev *hr_dev)
4508 {
4509 u32 aemask_val;
4510 int masken = 0;
4511 __le32 tmp;
4512 int i;
4513
4514 /* AEQ INT */
4515 aemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4516 tmp = cpu_to_le32(aemask_val);
4517 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4518 masken);
4519 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S, masken);
4520 aemask_val = le32_to_cpu(tmp);
4521 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, aemask_val);
4522
4523 /* CEQ INT */
4524 for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4525 /* IRQ mask */
4526 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4527 i * CEQ_REG_OFFSET, masken);
4528 }
4529 }
4530
hns_roce_v1_free_eq(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)4531 static void hns_roce_v1_free_eq(struct hns_roce_dev *hr_dev,
4532 struct hns_roce_eq *eq)
4533 {
4534 int npages = (PAGE_ALIGN(eq->eqe_size * eq->entries) +
4535 HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4536 int i;
4537
4538 if (!eq->buf_list)
4539 return;
4540
4541 for (i = 0; i < npages; ++i)
4542 dma_free_coherent(&hr_dev->pdev->dev, HNS_ROCE_BA_SIZE,
4543 eq->buf_list[i].buf, eq->buf_list[i].map);
4544
4545 kfree(eq->buf_list);
4546 }
4547
hns_roce_v1_enable_eq(struct hns_roce_dev * hr_dev,int eq_num,int enable_flag)4548 static void hns_roce_v1_enable_eq(struct hns_roce_dev *hr_dev, int eq_num,
4549 int enable_flag)
4550 {
4551 void __iomem *eqc = hr_dev->eq_table.eqc_base[eq_num];
4552 __le32 tmp;
4553 u32 val;
4554
4555 val = readl(eqc);
4556 tmp = cpu_to_le32(val);
4557
4558 if (enable_flag)
4559 roce_set_field(tmp,
4560 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4561 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4562 HNS_ROCE_EQ_STAT_VALID);
4563 else
4564 roce_set_field(tmp,
4565 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4566 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4567 HNS_ROCE_EQ_STAT_INVALID);
4568
4569 val = le32_to_cpu(tmp);
4570 writel(val, eqc);
4571 }
4572
hns_roce_v1_create_eq(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)4573 static int hns_roce_v1_create_eq(struct hns_roce_dev *hr_dev,
4574 struct hns_roce_eq *eq)
4575 {
4576 void __iomem *eqc = hr_dev->eq_table.eqc_base[eq->eqn];
4577 struct device *dev = &hr_dev->pdev->dev;
4578 dma_addr_t tmp_dma_addr;
4579 u32 eqconsindx_val = 0;
4580 u32 eqcuridx_val = 0;
4581 u32 eqshift_val = 0;
4582 __le32 tmp2 = 0;
4583 __le32 tmp1 = 0;
4584 __le32 tmp = 0;
4585 int num_bas;
4586 int ret;
4587 int i;
4588
4589 num_bas = (PAGE_ALIGN(eq->entries * eq->eqe_size) +
4590 HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4591
4592 if ((eq->entries * eq->eqe_size) > HNS_ROCE_BA_SIZE) {
4593 dev_err(dev, "[error]eq buf %d gt ba size(%d) need bas=%d\n",
4594 (eq->entries * eq->eqe_size), HNS_ROCE_BA_SIZE,
4595 num_bas);
4596 return -EINVAL;
4597 }
4598
4599 eq->buf_list = kcalloc(num_bas, sizeof(*eq->buf_list), GFP_KERNEL);
4600 if (!eq->buf_list)
4601 return -ENOMEM;
4602
4603 for (i = 0; i < num_bas; ++i) {
4604 eq->buf_list[i].buf = dma_alloc_coherent(dev, HNS_ROCE_BA_SIZE,
4605 &tmp_dma_addr,
4606 GFP_KERNEL);
4607 if (!eq->buf_list[i].buf) {
4608 ret = -ENOMEM;
4609 goto err_out_free_pages;
4610 }
4611
4612 eq->buf_list[i].map = tmp_dma_addr;
4613 memset(eq->buf_list[i].buf, 0, HNS_ROCE_BA_SIZE);
4614 }
4615 eq->cons_index = 0;
4616 roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4617 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4618 HNS_ROCE_EQ_STAT_INVALID);
4619 roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M,
4620 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S,
4621 eq->log_entries);
4622 eqshift_val = le32_to_cpu(tmp);
4623 writel(eqshift_val, eqc);
4624
4625 /* Configure eq extended address 12~44bit */
4626 writel((u32)(eq->buf_list[0].map >> 12), eqc + 4);
4627
4628 /*
4629 * Configure eq extended address 45~49 bit.
4630 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
4631 * using 4K page, and shift more 32 because of
4632 * caculating the high 32 bit value evaluated to hardware.
4633 */
4634 roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M,
4635 ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S,
4636 eq->buf_list[0].map >> 44);
4637 roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M,
4638 ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S, 0);
4639 eqcuridx_val = le32_to_cpu(tmp1);
4640 writel(eqcuridx_val, eqc + 8);
4641
4642 /* Configure eq consumer index */
4643 roce_set_field(tmp2, ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M,
4644 ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S, 0);
4645 eqconsindx_val = le32_to_cpu(tmp2);
4646 writel(eqconsindx_val, eqc + 0xc);
4647
4648 return 0;
4649
4650 err_out_free_pages:
4651 for (i -= 1; i >= 0; i--)
4652 dma_free_coherent(dev, HNS_ROCE_BA_SIZE, eq->buf_list[i].buf,
4653 eq->buf_list[i].map);
4654
4655 kfree(eq->buf_list);
4656 return ret;
4657 }
4658
hns_roce_v1_init_eq_table(struct hns_roce_dev * hr_dev)4659 static int hns_roce_v1_init_eq_table(struct hns_roce_dev *hr_dev)
4660 {
4661 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4662 struct device *dev = &hr_dev->pdev->dev;
4663 struct hns_roce_eq *eq;
4664 int irq_num;
4665 int eq_num;
4666 int ret;
4667 int i, j;
4668
4669 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4670 irq_num = eq_num + hr_dev->caps.num_other_vectors;
4671
4672 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
4673 if (!eq_table->eq)
4674 return -ENOMEM;
4675
4676 eq_table->eqc_base = kcalloc(eq_num, sizeof(*eq_table->eqc_base),
4677 GFP_KERNEL);
4678 if (!eq_table->eqc_base) {
4679 ret = -ENOMEM;
4680 goto err_eqc_base_alloc_fail;
4681 }
4682
4683 for (i = 0; i < eq_num; i++) {
4684 eq = &eq_table->eq[i];
4685 eq->hr_dev = hr_dev;
4686 eq->eqn = i;
4687 eq->irq = hr_dev->irq[i];
4688 eq->log_page_size = PAGE_SHIFT;
4689
4690 if (i < hr_dev->caps.num_comp_vectors) {
4691 /* CEQ */
4692 eq_table->eqc_base[i] = hr_dev->reg_base +
4693 ROCEE_CAEP_CEQC_SHIFT_0_REG +
4694 CEQ_REG_OFFSET * i;
4695 eq->type_flag = HNS_ROCE_CEQ;
4696 eq->doorbell = hr_dev->reg_base +
4697 ROCEE_CAEP_CEQC_CONS_IDX_0_REG +
4698 CEQ_REG_OFFSET * i;
4699 eq->entries = hr_dev->caps.ceqe_depth;
4700 eq->log_entries = ilog2(eq->entries);
4701 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
4702 } else {
4703 /* AEQ */
4704 eq_table->eqc_base[i] = hr_dev->reg_base +
4705 ROCEE_CAEP_AEQC_AEQE_SHIFT_REG;
4706 eq->type_flag = HNS_ROCE_AEQ;
4707 eq->doorbell = hr_dev->reg_base +
4708 ROCEE_CAEP_AEQE_CONS_IDX_REG;
4709 eq->entries = hr_dev->caps.aeqe_depth;
4710 eq->log_entries = ilog2(eq->entries);
4711 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
4712 }
4713 }
4714
4715 /* Disable irq */
4716 hns_roce_v1_int_mask_enable(hr_dev);
4717
4718 /* Configure ce int interval */
4719 roce_write(hr_dev, ROCEE_CAEP_CE_INTERVAL_CFG_REG,
4720 HNS_ROCE_CEQ_DEFAULT_INTERVAL);
4721
4722 /* Configure ce int burst num */
4723 roce_write(hr_dev, ROCEE_CAEP_CE_BURST_NUM_CFG_REG,
4724 HNS_ROCE_CEQ_DEFAULT_BURST_NUM);
4725
4726 for (i = 0; i < eq_num; i++) {
4727 ret = hns_roce_v1_create_eq(hr_dev, &eq_table->eq[i]);
4728 if (ret) {
4729 dev_err(dev, "eq create failed\n");
4730 goto err_create_eq_fail;
4731 }
4732 }
4733
4734 for (j = 0; j < irq_num; j++) {
4735 if (j < eq_num)
4736 ret = request_irq(hr_dev->irq[j],
4737 hns_roce_v1_msix_interrupt_eq, 0,
4738 hr_dev->irq_names[j],
4739 &eq_table->eq[j]);
4740 else
4741 ret = request_irq(hr_dev->irq[j],
4742 hns_roce_v1_msix_interrupt_abn, 0,
4743 hr_dev->irq_names[j], hr_dev);
4744
4745 if (ret) {
4746 dev_err(dev, "request irq error!\n");
4747 goto err_request_irq_fail;
4748 }
4749 }
4750
4751 for (i = 0; i < eq_num; i++)
4752 hns_roce_v1_enable_eq(hr_dev, i, EQ_ENABLE);
4753
4754 return 0;
4755
4756 err_request_irq_fail:
4757 for (j -= 1; j >= 0; j--)
4758 free_irq(hr_dev->irq[j], &eq_table->eq[j]);
4759
4760 err_create_eq_fail:
4761 for (i -= 1; i >= 0; i--)
4762 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4763
4764 kfree(eq_table->eqc_base);
4765
4766 err_eqc_base_alloc_fail:
4767 kfree(eq_table->eq);
4768
4769 return ret;
4770 }
4771
hns_roce_v1_cleanup_eq_table(struct hns_roce_dev * hr_dev)4772 static void hns_roce_v1_cleanup_eq_table(struct hns_roce_dev *hr_dev)
4773 {
4774 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4775 int irq_num;
4776 int eq_num;
4777 int i;
4778
4779 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4780 irq_num = eq_num + hr_dev->caps.num_other_vectors;
4781 for (i = 0; i < eq_num; i++) {
4782 /* Disable EQ */
4783 hns_roce_v1_enable_eq(hr_dev, i, EQ_DISABLE);
4784
4785 free_irq(hr_dev->irq[i], &eq_table->eq[i]);
4786
4787 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4788 }
4789 for (i = eq_num; i < irq_num; i++)
4790 free_irq(hr_dev->irq[i], hr_dev);
4791
4792 kfree(eq_table->eqc_base);
4793 kfree(eq_table->eq);
4794 }
4795
4796 static const struct hns_roce_hw hns_roce_hw_v1 = {
4797 .reset = hns_roce_v1_reset,
4798 .hw_profile = hns_roce_v1_profile,
4799 .hw_init = hns_roce_v1_init,
4800 .hw_exit = hns_roce_v1_exit,
4801 .post_mbox = hns_roce_v1_post_mbox,
4802 .chk_mbox = hns_roce_v1_chk_mbox,
4803 .set_gid = hns_roce_v1_set_gid,
4804 .set_mac = hns_roce_v1_set_mac,
4805 .set_mtu = hns_roce_v1_set_mtu,
4806 .write_mtpt = hns_roce_v1_write_mtpt,
4807 .write_cqc = hns_roce_v1_write_cqc,
4808 .modify_cq = hns_roce_v1_modify_cq,
4809 .clear_hem = hns_roce_v1_clear_hem,
4810 .modify_qp = hns_roce_v1_modify_qp,
4811 .query_qp = hns_roce_v1_query_qp,
4812 .destroy_qp = hns_roce_v1_destroy_qp,
4813 .post_send = hns_roce_v1_post_send,
4814 .post_recv = hns_roce_v1_post_recv,
4815 .req_notify_cq = hns_roce_v1_req_notify_cq,
4816 .poll_cq = hns_roce_v1_poll_cq,
4817 .dereg_mr = hns_roce_v1_dereg_mr,
4818 .destroy_cq = hns_roce_v1_destroy_cq,
4819 .init_eq = hns_roce_v1_init_eq_table,
4820 .cleanup_eq = hns_roce_v1_cleanup_eq_table,
4821 };
4822
4823 static const struct of_device_id hns_roce_of_match[] = {
4824 { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
4825 {},
4826 };
4827 MODULE_DEVICE_TABLE(of, hns_roce_of_match);
4828
4829 static const struct acpi_device_id hns_roce_acpi_match[] = {
4830 { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
4831 {},
4832 };
4833 MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
4834
hns_roce_node_match(struct device * dev,void * fwnode)4835 static int hns_roce_node_match(struct device *dev, void *fwnode)
4836 {
4837 return dev->fwnode == fwnode;
4838 }
4839
4840 static struct
hns_roce_find_pdev(struct fwnode_handle * fwnode)4841 platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
4842 {
4843 struct device *dev;
4844
4845 /* get the 'device' corresponding to the matching 'fwnode' */
4846 dev = bus_find_device(&platform_bus_type, NULL,
4847 fwnode, hns_roce_node_match);
4848 /* get the platform device */
4849 return dev ? to_platform_device(dev) : NULL;
4850 }
4851
hns_roce_get_cfg(struct hns_roce_dev * hr_dev)4852 static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
4853 {
4854 struct device *dev = &hr_dev->pdev->dev;
4855 struct platform_device *pdev = NULL;
4856 struct net_device *netdev = NULL;
4857 struct device_node *net_node;
4858 struct resource *res;
4859 int port_cnt = 0;
4860 u8 phy_port;
4861 int ret;
4862 int i;
4863
4864 /* check if we are compatible with the underlying SoC */
4865 if (dev_of_node(dev)) {
4866 const struct of_device_id *of_id;
4867
4868 of_id = of_match_node(hns_roce_of_match, dev->of_node);
4869 if (!of_id) {
4870 dev_err(dev, "device is not compatible!\n");
4871 return -ENXIO;
4872 }
4873 hr_dev->hw = (const struct hns_roce_hw *)of_id->data;
4874 if (!hr_dev->hw) {
4875 dev_err(dev, "couldn't get H/W specific DT data!\n");
4876 return -ENXIO;
4877 }
4878 } else if (is_acpi_device_node(dev->fwnode)) {
4879 const struct acpi_device_id *acpi_id;
4880
4881 acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
4882 if (!acpi_id) {
4883 dev_err(dev, "device is not compatible!\n");
4884 return -ENXIO;
4885 }
4886 hr_dev->hw = (const struct hns_roce_hw *) acpi_id->driver_data;
4887 if (!hr_dev->hw) {
4888 dev_err(dev, "couldn't get H/W specific ACPI data!\n");
4889 return -ENXIO;
4890 }
4891 } else {
4892 dev_err(dev, "can't read compatibility data from DT or ACPI\n");
4893 return -ENXIO;
4894 }
4895
4896 /* get the mapped register base address */
4897 res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0);
4898 hr_dev->reg_base = devm_ioremap_resource(dev, res);
4899 if (IS_ERR(hr_dev->reg_base))
4900 return PTR_ERR(hr_dev->reg_base);
4901
4902 /* read the node_guid of IB device from the DT or ACPI */
4903 ret = device_property_read_u8_array(dev, "node-guid",
4904 (u8 *)&hr_dev->ib_dev.node_guid,
4905 GUID_LEN);
4906 if (ret) {
4907 dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
4908 return ret;
4909 }
4910
4911 /* get the RoCE associated ethernet ports or netdevices */
4912 for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
4913 if (dev_of_node(dev)) {
4914 net_node = of_parse_phandle(dev->of_node, "eth-handle",
4915 i);
4916 if (!net_node)
4917 continue;
4918 pdev = of_find_device_by_node(net_node);
4919 } else if (is_acpi_device_node(dev->fwnode)) {
4920 struct fwnode_reference_args args;
4921
4922 ret = acpi_node_get_property_reference(dev->fwnode,
4923 "eth-handle",
4924 i, &args);
4925 if (ret)
4926 continue;
4927 pdev = hns_roce_find_pdev(args.fwnode);
4928 } else {
4929 dev_err(dev, "cannot read data from DT or ACPI\n");
4930 return -ENXIO;
4931 }
4932
4933 if (pdev) {
4934 netdev = platform_get_drvdata(pdev);
4935 phy_port = (u8)i;
4936 if (netdev) {
4937 hr_dev->iboe.netdevs[port_cnt] = netdev;
4938 hr_dev->iboe.phy_port[port_cnt] = phy_port;
4939 } else {
4940 dev_err(dev, "no netdev found with pdev %s\n",
4941 pdev->name);
4942 return -ENODEV;
4943 }
4944 port_cnt++;
4945 }
4946 }
4947
4948 if (port_cnt == 0) {
4949 dev_err(dev, "unable to get eth-handle for available ports!\n");
4950 return -EINVAL;
4951 }
4952
4953 hr_dev->caps.num_ports = port_cnt;
4954
4955 /* cmd issue mode: 0 is poll, 1 is event */
4956 hr_dev->cmd_mod = 1;
4957 hr_dev->loop_idc = 0;
4958 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
4959 hr_dev->odb_offset = ROCEE_DB_OTHERS_L_0_REG;
4960
4961 /* read the interrupt names from the DT or ACPI */
4962 ret = device_property_read_string_array(dev, "interrupt-names",
4963 hr_dev->irq_names,
4964 HNS_ROCE_V1_MAX_IRQ_NUM);
4965 if (ret < 0) {
4966 dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
4967 return ret;
4968 }
4969
4970 /* fetch the interrupt numbers */
4971 for (i = 0; i < HNS_ROCE_V1_MAX_IRQ_NUM; i++) {
4972 hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
4973 if (hr_dev->irq[i] <= 0) {
4974 dev_err(dev, "platform get of irq[=%d] failed!\n", i);
4975 return -EINVAL;
4976 }
4977 }
4978
4979 return 0;
4980 }
4981
4982 /**
4983 * hns_roce_probe - RoCE driver entrance
4984 * @pdev: pointer to platform device
4985 * Return : int
4986 *
4987 */
hns_roce_probe(struct platform_device * pdev)4988 static int hns_roce_probe(struct platform_device *pdev)
4989 {
4990 int ret;
4991 struct hns_roce_dev *hr_dev;
4992 struct device *dev = &pdev->dev;
4993
4994 hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev));
4995 if (!hr_dev)
4996 return -ENOMEM;
4997
4998 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v1_priv), GFP_KERNEL);
4999 if (!hr_dev->priv) {
5000 ret = -ENOMEM;
5001 goto error_failed_kzalloc;
5002 }
5003
5004 hr_dev->pdev = pdev;
5005 hr_dev->dev = dev;
5006 platform_set_drvdata(pdev, hr_dev);
5007
5008 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
5009 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
5010 dev_err(dev, "Not usable DMA addressing mode\n");
5011 ret = -EIO;
5012 goto error_failed_get_cfg;
5013 }
5014
5015 ret = hns_roce_get_cfg(hr_dev);
5016 if (ret) {
5017 dev_err(dev, "Get Configuration failed!\n");
5018 goto error_failed_get_cfg;
5019 }
5020
5021 ret = hns_roce_init(hr_dev);
5022 if (ret) {
5023 dev_err(dev, "RoCE engine init failed!\n");
5024 goto error_failed_get_cfg;
5025 }
5026
5027 return 0;
5028
5029 error_failed_get_cfg:
5030 kfree(hr_dev->priv);
5031
5032 error_failed_kzalloc:
5033 ib_dealloc_device(&hr_dev->ib_dev);
5034
5035 return ret;
5036 }
5037
5038 /**
5039 * hns_roce_remove - remove RoCE device
5040 * @pdev: pointer to platform device
5041 */
hns_roce_remove(struct platform_device * pdev)5042 static int hns_roce_remove(struct platform_device *pdev)
5043 {
5044 struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
5045
5046 hns_roce_exit(hr_dev);
5047 kfree(hr_dev->priv);
5048 ib_dealloc_device(&hr_dev->ib_dev);
5049
5050 return 0;
5051 }
5052
5053 static struct platform_driver hns_roce_driver = {
5054 .probe = hns_roce_probe,
5055 .remove = hns_roce_remove,
5056 .driver = {
5057 .name = DRV_NAME,
5058 .of_match_table = hns_roce_of_match,
5059 .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
5060 },
5061 };
5062
5063 module_platform_driver(hns_roce_driver);
5064
5065 MODULE_LICENSE("Dual BSD/GPL");
5066 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
5067 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
5068 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
5069 MODULE_DESCRIPTION("Hisilicon Hip06 Family RoCE Driver");
5070
