1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
4 */
5 #include <linux/mm.h>
6 #include <linux/delay.h>
7 #include <linux/clk.h>
8 #include <linux/io.h>
9 #include <linux/clkdev.h>
10 #include <linux/of.h>
11 #include <linux/err.h>
12 #include <soc/imx/revision.h>
13 #include <asm/irq.h>
14
15 #include "clk.h"
16
17 #define MX35_CCM_BASE_ADDR 0x53f80000
18 #define MX35_GPT1_BASE_ADDR 0x53f90000
19 #define MX35_INT_GPT (NR_IRQS_LEGACY + 29)
20
21 #define MXC_CCM_PDR0 0x04
22 #define MX35_CCM_PDR2 0x0c
23 #define MX35_CCM_PDR3 0x10
24 #define MX35_CCM_PDR4 0x14
25 #define MX35_CCM_MPCTL 0x1c
26 #define MX35_CCM_PPCTL 0x20
27 #define MX35_CCM_CGR0 0x2c
28 #define MX35_CCM_CGR1 0x30
29 #define MX35_CCM_CGR2 0x34
30 #define MX35_CCM_CGR3 0x38
31
32 struct arm_ahb_div {
33 unsigned char arm, ahb, sel;
34 };
35
36 static struct arm_ahb_div clk_consumer[] = {
37 { .arm = 1, .ahb = 4, .sel = 0},
38 { .arm = 1, .ahb = 3, .sel = 1},
39 { .arm = 2, .ahb = 2, .sel = 0},
40 { .arm = 0, .ahb = 0, .sel = 0},
41 { .arm = 0, .ahb = 0, .sel = 0},
42 { .arm = 0, .ahb = 0, .sel = 0},
43 { .arm = 4, .ahb = 1, .sel = 0},
44 { .arm = 1, .ahb = 5, .sel = 0},
45 { .arm = 1, .ahb = 8, .sel = 0},
46 { .arm = 1, .ahb = 6, .sel = 1},
47 { .arm = 2, .ahb = 4, .sel = 0},
48 { .arm = 0, .ahb = 0, .sel = 0},
49 { .arm = 0, .ahb = 0, .sel = 0},
50 { .arm = 0, .ahb = 0, .sel = 0},
51 { .arm = 4, .ahb = 2, .sel = 0},
52 { .arm = 0, .ahb = 0, .sel = 0},
53 };
54
55 static char hsp_div_532[] = { 4, 8, 3, 0 };
56 static char hsp_div_400[] = { 3, 6, 3, 0 };
57
58 static struct clk_onecell_data clk_data;
59
60 static const char *std_sel[] = {"ppll", "arm"};
61 static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
62
63 enum mx35_clks {
64 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb,
65 /* 9 */ ipg, arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div,
66 /* 15 */ esdhc_sel, esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel,
67 /* 20 */ spdif_div_pre, spdif_div_post, ssi_sel, ssi1_div_pre,
68 /* 24 */ ssi1_div_post, ssi2_div_pre, ssi2_div_post, usb_sel, usb_div,
69 /* 29 */ nfc_div, asrc_gate, pata_gate, audmux_gate, can1_gate,
70 /* 34 */ can2_gate, cspi1_gate, cspi2_gate, ect_gate, edio_gate,
71 /* 39 */ emi_gate, epit1_gate, epit2_gate, esai_gate, esdhc1_gate,
72 /* 44 */ esdhc2_gate, esdhc3_gate, fec_gate, gpio1_gate, gpio2_gate,
73 /* 49 */ gpio3_gate, gpt_gate, i2c1_gate, i2c2_gate, i2c3_gate,
74 /* 54 */ iomuxc_gate, ipu_gate, kpp_gate, mlb_gate, mshc_gate,
75 /* 59 */ owire_gate, pwm_gate, rngc_gate, rtc_gate, rtic_gate, scc_gate,
76 /* 65 */ sdma_gate, spba_gate, spdif_gate, ssi1_gate, ssi2_gate,
77 /* 70 */ uart1_gate, uart2_gate, uart3_gate, usbotg_gate, wdog_gate,
78 /* 75 */ max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate,
79 /* 81 */ gpu2d_gate, ckil, clk_max
80 };
81
82 static struct clk *clk[clk_max];
83
_mx35_clocks_init(void)84 static void __init _mx35_clocks_init(void)
85 {
86 void __iomem *base;
87 u32 pdr0, consumer_sel, hsp_sel;
88 struct arm_ahb_div *aad;
89 unsigned char *hsp_div;
90
91 base = ioremap(MX35_CCM_BASE_ADDR, SZ_4K);
92 BUG_ON(!base);
93
94 pdr0 = __raw_readl(base + MXC_CCM_PDR0);
95 consumer_sel = (pdr0 >> 16) & 0xf;
96 aad = &clk_consumer[consumer_sel];
97 if (!aad->arm) {
98 pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel);
99 /*
100 * We are basically stuck. Continue with a default entry and hope we
101 * get far enough to actually show the above message
102 */
103 aad = &clk_consumer[0];
104 }
105
106 clk[ckih] = imx_clk_fixed("ckih", 24000000);
107 clk[ckil] = imx_clk_fixed("ckil", 32768);
108 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL);
109 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL);
110
111 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4);
112
113 if (aad->sel)
114 clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm);
115 else
116 clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm);
117
118 if (clk_get_rate(clk[arm]) > 400000000)
119 hsp_div = hsp_div_532;
120 else
121 hsp_div = hsp_div_400;
122
123 hsp_sel = (pdr0 >> 20) & 0x3;
124 if (!hsp_div[hsp_sel]) {
125 pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel);
126 hsp_sel = 0;
127 }
128
129 clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]);
130
131 clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb);
132 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
133
134 clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6);
135 clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3);
136 clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel));
137
138 clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel));
139 clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6);
140
141 clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
142 clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6);
143 clk[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + MX35_CCM_PDR3, 8, 6);
144 clk[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + MX35_CCM_PDR3, 16, 6);
145
146 clk[spdif_sel] = imx_clk_mux("spdif_sel", base + MX35_CCM_PDR3, 22, 1, std_sel, ARRAY_SIZE(std_sel));
147 clk[spdif_div_pre] = imx_clk_divider("spdif_div_pre", "spdif_sel", base + MX35_CCM_PDR3, 29, 3); /* divide by 1 not allowed */
148 clk[spdif_div_post] = imx_clk_divider("spdif_div_post", "spdif_div_pre", base + MX35_CCM_PDR3, 23, 6);
149
150 clk[ssi_sel] = imx_clk_mux("ssi_sel", base + MX35_CCM_PDR2, 6, 1, std_sel, ARRAY_SIZE(std_sel));
151 clk[ssi1_div_pre] = imx_clk_divider("ssi1_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 24, 3);
152 clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6);
153 clk[ssi2_div_pre] = imx_clk_divider("ssi2_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 27, 3);
154 clk[ssi2_div_post] = imx_clk_divider("ssi2_div_post", "ssi2_div_pre", base + MX35_CCM_PDR2, 8, 6);
155
156 clk[usb_sel] = imx_clk_mux("usb_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
157 clk[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + MX35_CCM_PDR4, 22, 6);
158
159 clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4);
160
161 clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel));
162 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6);
163
164 clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0);
165 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2);
166 clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4);
167 clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0, 6);
168 clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0, 8);
169 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10);
170 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12);
171 clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14);
172 clk[edio_gate] = imx_clk_gate2("edio_gate", "ipg", base + MX35_CCM_CGR0, 16);
173 clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18);
174 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20);
175 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22);
176 clk[esai_gate] = imx_clk_gate2("esai_gate", "ipg", base + MX35_CCM_CGR0, 24);
177 clk[esdhc1_gate] = imx_clk_gate2("esdhc1_gate", "esdhc1_div", base + MX35_CCM_CGR0, 26);
178 clk[esdhc2_gate] = imx_clk_gate2("esdhc2_gate", "esdhc2_div", base + MX35_CCM_CGR0, 28);
179 clk[esdhc3_gate] = imx_clk_gate2("esdhc3_gate", "esdhc3_div", base + MX35_CCM_CGR0, 30);
180
181 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1, 0);
182 clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1, 2);
183 clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1, 4);
184 clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1, 6);
185 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1, 8);
186 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "ipg_per", base + MX35_CCM_CGR1, 10);
187 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "ipg_per", base + MX35_CCM_CGR1, 12);
188 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "ipg_per", base + MX35_CCM_CGR1, 14);
189 clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16);
190 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18);
191 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20);
192 clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22);
193 clk[mshc_gate] = imx_clk_gate2("mshc_gate", "dummy", base + MX35_CCM_CGR1, 24);
194 clk[owire_gate] = imx_clk_gate2("owire_gate", "ipg_per", base + MX35_CCM_CGR1, 26);
195 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "ipg_per", base + MX35_CCM_CGR1, 28);
196 clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30);
197
198 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2, 0);
199 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2, 2);
200 clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2, 4);
201 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2, 6);
202 clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2, 8);
203 clk[spdif_gate] = imx_clk_gate2("spdif_gate", "spdif_div_post", base + MX35_CCM_CGR2, 10);
204 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "ssi1_div_post", base + MX35_CCM_CGR2, 12);
205 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "ssi2_div_post", base + MX35_CCM_CGR2, 14);
206 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16);
207 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18);
208 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20);
209 clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22);
210 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24);
211 clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26);
212 clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30);
213
214 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3, 0);
215 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2);
216 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4);
217
218 imx_check_clocks(clk, ARRAY_SIZE(clk));
219
220 clk_prepare_enable(clk[spba_gate]);
221 clk_prepare_enable(clk[gpio1_gate]);
222 clk_prepare_enable(clk[gpio2_gate]);
223 clk_prepare_enable(clk[gpio3_gate]);
224 clk_prepare_enable(clk[iim_gate]);
225 clk_prepare_enable(clk[emi_gate]);
226 clk_prepare_enable(clk[max_gate]);
227 clk_prepare_enable(clk[iomuxc_gate]);
228
229 /*
230 * SCC is needed to boot via mmc after a watchdog reset. The clock code
231 * before conversion to common clk also enabled UART1 (which isn't
232 * handled here and not needed for mmc) and IIM (which is enabled
233 * unconditionally above).
234 */
235 clk_prepare_enable(clk[scc_gate]);
236
237 imx_register_uart_clocks();
238
239 imx_print_silicon_rev("i.MX35", mx35_revision());
240 }
241
mx35_clocks_init_dt(struct device_node * ccm_node)242 static void __init mx35_clocks_init_dt(struct device_node *ccm_node)
243 {
244 _mx35_clocks_init();
245
246 clk_data.clks = clk;
247 clk_data.clk_num = ARRAY_SIZE(clk);
248 of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data);
249 }
250 CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt);
251
