1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for STMicroelectronics STM32F7 I2C controller
4 *
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
6 * reference manual.
7 * Please see below a link to the documentation:
8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
9 *
10 * Copyright (C) M'boumba Cedric Madianga 2017
11 * Copyright (C) STMicroelectronics 2017
12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
13 *
14 * This driver is based on i2c-stm32f4.c
15 *
16 */
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/i2c.h>
21 #include <linux/i2c-smbus.h>
22 #include <linux/interrupt.h>
23 #include <linux/io.h>
24 #include <linux/iopoll.h>
25 #include <linux/mfd/syscon.h>
26 #include <linux/module.h>
27 #include <linux/of.h>
28 #include <linux/of_address.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/pm_wakeirq.h>
34 #include <linux/regmap.h>
35 #include <linux/reset.h>
36 #include <linux/slab.h>
37
38 #include "i2c-stm32.h"
39
40 /* STM32F7 I2C registers */
41 #define STM32F7_I2C_CR1 0x00
42 #define STM32F7_I2C_CR2 0x04
43 #define STM32F7_I2C_OAR1 0x08
44 #define STM32F7_I2C_OAR2 0x0C
45 #define STM32F7_I2C_PECR 0x20
46 #define STM32F7_I2C_TIMINGR 0x10
47 #define STM32F7_I2C_ISR 0x18
48 #define STM32F7_I2C_ICR 0x1C
49 #define STM32F7_I2C_RXDR 0x24
50 #define STM32F7_I2C_TXDR 0x28
51
52 /* STM32F7 I2C control 1 */
53 #define STM32F7_I2C_CR1_PECEN BIT(23)
54 #define STM32F7_I2C_CR1_ALERTEN BIT(22)
55 #define STM32F7_I2C_CR1_SMBHEN BIT(20)
56 #define STM32F7_I2C_CR1_WUPEN BIT(18)
57 #define STM32F7_I2C_CR1_SBC BIT(16)
58 #define STM32F7_I2C_CR1_RXDMAEN BIT(15)
59 #define STM32F7_I2C_CR1_TXDMAEN BIT(14)
60 #define STM32F7_I2C_CR1_ANFOFF BIT(12)
61 #define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8)
62 #define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8)
63 #define STM32F7_I2C_CR1_ERRIE BIT(7)
64 #define STM32F7_I2C_CR1_TCIE BIT(6)
65 #define STM32F7_I2C_CR1_STOPIE BIT(5)
66 #define STM32F7_I2C_CR1_NACKIE BIT(4)
67 #define STM32F7_I2C_CR1_ADDRIE BIT(3)
68 #define STM32F7_I2C_CR1_RXIE BIT(2)
69 #define STM32F7_I2C_CR1_TXIE BIT(1)
70 #define STM32F7_I2C_CR1_PE BIT(0)
71 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
72 | STM32F7_I2C_CR1_TCIE \
73 | STM32F7_I2C_CR1_STOPIE \
74 | STM32F7_I2C_CR1_NACKIE \
75 | STM32F7_I2C_CR1_RXIE \
76 | STM32F7_I2C_CR1_TXIE)
77 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
78 | STM32F7_I2C_CR1_STOPIE \
79 | STM32F7_I2C_CR1_NACKIE \
80 | STM32F7_I2C_CR1_RXIE \
81 | STM32F7_I2C_CR1_TXIE)
82
83 /* STM32F7 I2C control 2 */
84 #define STM32F7_I2C_CR2_PECBYTE BIT(26)
85 #define STM32F7_I2C_CR2_RELOAD BIT(24)
86 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
87 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
88 #define STM32F7_I2C_CR2_NACK BIT(15)
89 #define STM32F7_I2C_CR2_STOP BIT(14)
90 #define STM32F7_I2C_CR2_START BIT(13)
91 #define STM32F7_I2C_CR2_HEAD10R BIT(12)
92 #define STM32F7_I2C_CR2_ADD10 BIT(11)
93 #define STM32F7_I2C_CR2_RD_WRN BIT(10)
94 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)
95 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \
96 STM32F7_I2C_CR2_SADD10_MASK))
97 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
98 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
99
100 /* STM32F7 I2C Own Address 1 */
101 #define STM32F7_I2C_OAR1_OA1EN BIT(15)
102 #define STM32F7_I2C_OAR1_OA1MODE BIT(10)
103 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
104 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
105 STM32F7_I2C_OAR1_OA1_10_MASK))
106 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
107 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
108 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
109 | STM32F7_I2C_OAR1_OA1_10_MASK \
110 | STM32F7_I2C_OAR1_OA1EN \
111 | STM32F7_I2C_OAR1_OA1MODE)
112
113 /* STM32F7 I2C Own Address 2 */
114 #define STM32F7_I2C_OAR2_OA2EN BIT(15)
115 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
116 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
117 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
118 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
119 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
120 | STM32F7_I2C_OAR2_OA2_7_MASK \
121 | STM32F7_I2C_OAR2_OA2EN)
122
123 /* STM32F7 I2C Interrupt Status */
124 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
125 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
126 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
127 #define STM32F7_I2C_ISR_DIR BIT(16)
128 #define STM32F7_I2C_ISR_BUSY BIT(15)
129 #define STM32F7_I2C_ISR_ALERT BIT(13)
130 #define STM32F7_I2C_ISR_PECERR BIT(11)
131 #define STM32F7_I2C_ISR_ARLO BIT(9)
132 #define STM32F7_I2C_ISR_BERR BIT(8)
133 #define STM32F7_I2C_ISR_TCR BIT(7)
134 #define STM32F7_I2C_ISR_TC BIT(6)
135 #define STM32F7_I2C_ISR_STOPF BIT(5)
136 #define STM32F7_I2C_ISR_NACKF BIT(4)
137 #define STM32F7_I2C_ISR_ADDR BIT(3)
138 #define STM32F7_I2C_ISR_RXNE BIT(2)
139 #define STM32F7_I2C_ISR_TXIS BIT(1)
140 #define STM32F7_I2C_ISR_TXE BIT(0)
141
142 /* STM32F7 I2C Interrupt Clear */
143 #define STM32F7_I2C_ICR_ALERTCF BIT(13)
144 #define STM32F7_I2C_ICR_PECCF BIT(11)
145 #define STM32F7_I2C_ICR_ARLOCF BIT(9)
146 #define STM32F7_I2C_ICR_BERRCF BIT(8)
147 #define STM32F7_I2C_ICR_STOPCF BIT(5)
148 #define STM32F7_I2C_ICR_NACKCF BIT(4)
149 #define STM32F7_I2C_ICR_ADDRCF BIT(3)
150
151 /* STM32F7 I2C Timing */
152 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
153 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
154 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
155 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
156 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
157
158 #define STM32F7_I2C_MAX_LEN 0xff
159 #define STM32F7_I2C_DMA_LEN_MIN 0x16
160 enum {
161 STM32F7_SLAVE_HOSTNOTIFY,
162 STM32F7_SLAVE_7_10_BITS_ADDR,
163 STM32F7_SLAVE_7_BITS_ADDR,
164 STM32F7_I2C_MAX_SLAVE
165 };
166
167 #define STM32F7_I2C_DNF_DEFAULT 0
168 #define STM32F7_I2C_DNF_MAX 15
169
170 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
171 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
172
173 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
174 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
175
176 #define STM32F7_PRESC_MAX BIT(4)
177 #define STM32F7_SCLDEL_MAX BIT(4)
178 #define STM32F7_SDADEL_MAX BIT(4)
179 #define STM32F7_SCLH_MAX BIT(8)
180 #define STM32F7_SCLL_MAX BIT(8)
181
182 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100)
183
184 /**
185 * struct stm32f7_i2c_regs - i2c f7 registers backup
186 * @cr1: Control register 1
187 * @cr2: Control register 2
188 * @oar1: Own address 1 register
189 * @oar2: Own address 2 register
190 * @tmgr: Timing register
191 */
192 struct stm32f7_i2c_regs {
193 u32 cr1;
194 u32 cr2;
195 u32 oar1;
196 u32 oar2;
197 u32 tmgr;
198 };
199
200 /**
201 * struct stm32f7_i2c_spec - private i2c specification timing
202 * @rate: I2C bus speed (Hz)
203 * @fall_max: Max fall time of both SDA and SCL signals (ns)
204 * @rise_max: Max rise time of both SDA and SCL signals (ns)
205 * @hddat_min: Min data hold time (ns)
206 * @vddat_max: Max data valid time (ns)
207 * @sudat_min: Min data setup time (ns)
208 * @l_min: Min low period of the SCL clock (ns)
209 * @h_min: Min high period of the SCL clock (ns)
210 */
211 struct stm32f7_i2c_spec {
212 u32 rate;
213 u32 fall_max;
214 u32 rise_max;
215 u32 hddat_min;
216 u32 vddat_max;
217 u32 sudat_min;
218 u32 l_min;
219 u32 h_min;
220 };
221
222 /**
223 * struct stm32f7_i2c_setup - private I2C timing setup parameters
224 * @speed_freq: I2C speed frequency (Hz)
225 * @clock_src: I2C clock source frequency (Hz)
226 * @rise_time: Rise time (ns)
227 * @fall_time: Fall time (ns)
228 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
229 */
230 struct stm32f7_i2c_setup {
231 u32 speed_freq;
232 u32 clock_src;
233 u32 rise_time;
234 u32 fall_time;
235 u32 fmp_clr_offset;
236 };
237
238 /**
239 * struct stm32f7_i2c_timings - private I2C output parameters
240 * @node: List entry
241 * @presc: Prescaler value
242 * @scldel: Data setup time
243 * @sdadel: Data hold time
244 * @sclh: SCL high period (master mode)
245 * @scll: SCL low period (master mode)
246 */
247 struct stm32f7_i2c_timings {
248 struct list_head node;
249 u8 presc;
250 u8 scldel;
251 u8 sdadel;
252 u8 sclh;
253 u8 scll;
254 };
255
256 /**
257 * struct stm32f7_i2c_msg - client specific data
258 * @addr: 8-bit or 10-bit slave addr, including r/w bit
259 * @count: number of bytes to be transferred
260 * @buf: data buffer
261 * @result: result of the transfer
262 * @stop: last I2C msg to be sent, i.e. STOP to be generated
263 * @smbus: boolean to know if the I2C IP is used in SMBus mode
264 * @size: type of SMBus protocol
265 * @read_write: direction of SMBus protocol
266 * SMBus block read and SMBus block write - block read process call protocols
267 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
268 * contain a maximum of 32 bytes of data + byte command + byte count + PEC
269 * This buffer has to be 32-bit aligned to be compliant with memory address
270 * register in DMA mode.
271 */
272 struct stm32f7_i2c_msg {
273 u16 addr;
274 u32 count;
275 u8 *buf;
276 int result;
277 bool stop;
278 bool smbus;
279 int size;
280 char read_write;
281 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
282 };
283
284 /**
285 * struct stm32f7_i2c_alert - SMBus alert specific data
286 * @setup: platform data for the smbus_alert i2c client
287 * @ara: I2C slave device used to respond to the SMBus Alert with Alert
288 * Response Address
289 */
290 struct stm32f7_i2c_alert {
291 struct i2c_smbus_alert_setup setup;
292 struct i2c_client *ara;
293 };
294
295 /**
296 * struct stm32f7_i2c_dev - private data of the controller
297 * @adap: I2C adapter for this controller
298 * @dev: device for this controller
299 * @base: virtual memory area
300 * @complete: completion of I2C message
301 * @clk: hw i2c clock
302 * @bus_rate: I2C clock frequency of the controller
303 * @msg: Pointer to data to be written
304 * @msg_num: number of I2C messages to be executed
305 * @msg_id: message identifiant
306 * @f7_msg: customized i2c msg for driver usage
307 * @setup: I2C timing input setup
308 * @timing: I2C computed timings
309 * @slave: list of slave devices registered on the I2C bus
310 * @slave_running: slave device currently used
311 * @backup_regs: backup of i2c controller registers (for suspend/resume)
312 * @slave_dir: transfer direction for the current slave device
313 * @master_mode: boolean to know in which mode the I2C is running (master or
314 * slave)
315 * @dma: dma data
316 * @use_dma: boolean to know if dma is used in the current transfer
317 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
318 * @fmp_sreg: register address for setting Fast Mode Plus bits
319 * @fmp_creg: register address for clearing Fast Mode Plus bits
320 * @fmp_mask: mask for Fast Mode Plus bits in set register
321 * @wakeup_src: boolean to know if the device is a wakeup source
322 * @smbus_mode: states that the controller is configured in SMBus mode
323 * @host_notify_client: SMBus host-notify client
324 * @analog_filter: boolean to indicate enabling of the analog filter
325 * @dnf_dt: value of digital filter requested via dt
326 * @dnf: value of digital filter to apply
327 * @alert: SMBus alert specific data
328 */
329 struct stm32f7_i2c_dev {
330 struct i2c_adapter adap;
331 struct device *dev;
332 void __iomem *base;
333 struct completion complete;
334 struct clk *clk;
335 unsigned int bus_rate;
336 struct i2c_msg *msg;
337 unsigned int msg_num;
338 unsigned int msg_id;
339 struct stm32f7_i2c_msg f7_msg;
340 struct stm32f7_i2c_setup setup;
341 struct stm32f7_i2c_timings timing;
342 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
343 struct i2c_client *slave_running;
344 struct stm32f7_i2c_regs backup_regs;
345 u32 slave_dir;
346 bool master_mode;
347 struct stm32_i2c_dma *dma;
348 bool use_dma;
349 struct regmap *regmap;
350 u32 fmp_sreg;
351 u32 fmp_creg;
352 u32 fmp_mask;
353 bool wakeup_src;
354 bool smbus_mode;
355 struct i2c_client *host_notify_client;
356 bool analog_filter;
357 u32 dnf_dt;
358 u32 dnf;
359 struct stm32f7_i2c_alert *alert;
360 };
361
362 /*
363 * All these values are coming from I2C Specification, Version 6.0, 4th of
364 * April 2014.
365 *
366 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
367 * and Fast-mode Plus I2C-bus devices
368 */
369 static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = {
370 {
371 .rate = I2C_MAX_STANDARD_MODE_FREQ,
372 .fall_max = 300,
373 .rise_max = 1000,
374 .hddat_min = 0,
375 .vddat_max = 3450,
376 .sudat_min = 250,
377 .l_min = 4700,
378 .h_min = 4000,
379 },
380 {
381 .rate = I2C_MAX_FAST_MODE_FREQ,
382 .fall_max = 300,
383 .rise_max = 300,
384 .hddat_min = 0,
385 .vddat_max = 900,
386 .sudat_min = 100,
387 .l_min = 1300,
388 .h_min = 600,
389 },
390 {
391 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ,
392 .fall_max = 100,
393 .rise_max = 120,
394 .hddat_min = 0,
395 .vddat_max = 450,
396 .sudat_min = 50,
397 .l_min = 500,
398 .h_min = 260,
399 },
400 };
401
402 static const struct stm32f7_i2c_setup stm32f7_setup = {
403 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
404 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
405 };
406
407 static const struct stm32f7_i2c_setup stm32mp15_setup = {
408 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
409 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
410 .fmp_clr_offset = 0x40,
411 };
412
413 static const struct stm32f7_i2c_setup stm32mp13_setup = {
414 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
415 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
416 .fmp_clr_offset = 0x4,
417 };
418
stm32f7_i2c_set_bits(void __iomem * reg,u32 mask)419 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
420 {
421 writel_relaxed(readl_relaxed(reg) | mask, reg);
422 }
423
stm32f7_i2c_clr_bits(void __iomem * reg,u32 mask)424 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
425 {
426 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
427 }
428
stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev * i2c_dev,u32 mask)429 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
430 {
431 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
432 }
433
stm32f7_get_specs(u32 rate)434 static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate)
435 {
436 int i;
437
438 for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++)
439 if (rate <= stm32f7_i2c_specs[i].rate)
440 return &stm32f7_i2c_specs[i];
441
442 return ERR_PTR(-EINVAL);
443 }
444
445 #define RATE_MIN(rate) ((rate) * 8 / 10)
stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev * i2c_dev,struct stm32f7_i2c_setup * setup,struct stm32f7_i2c_timings * output)446 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
447 struct stm32f7_i2c_setup *setup,
448 struct stm32f7_i2c_timings *output)
449 {
450 struct stm32f7_i2c_spec *specs;
451 u32 p_prev = STM32F7_PRESC_MAX;
452 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
453 setup->clock_src);
454 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
455 setup->speed_freq);
456 u32 clk_error_prev = i2cbus;
457 u32 tsync;
458 u32 af_delay_min, af_delay_max;
459 u32 dnf_delay;
460 u32 clk_min, clk_max;
461 int sdadel_min, sdadel_max;
462 int scldel_min;
463 struct stm32f7_i2c_timings *v, *_v, *s;
464 struct list_head solutions;
465 u16 p, l, a, h;
466 int ret = 0;
467
468 specs = stm32f7_get_specs(setup->speed_freq);
469 if (specs == ERR_PTR(-EINVAL)) {
470 dev_err(i2c_dev->dev, "speed out of bound {%d}\n",
471 setup->speed_freq);
472 return -EINVAL;
473 }
474
475 if ((setup->rise_time > specs->rise_max) ||
476 (setup->fall_time > specs->fall_max)) {
477 dev_err(i2c_dev->dev,
478 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
479 setup->rise_time, specs->rise_max,
480 setup->fall_time, specs->fall_max);
481 return -EINVAL;
482 }
483
484 i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk);
485 if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) {
486 dev_err(i2c_dev->dev,
487 "DNF out of bound %d/%d\n",
488 i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk);
489 return -EINVAL;
490 }
491
492 /* Analog and Digital Filters */
493 af_delay_min =
494 (i2c_dev->analog_filter ?
495 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
496 af_delay_max =
497 (i2c_dev->analog_filter ?
498 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
499 dnf_delay = i2c_dev->dnf * i2cclk;
500
501 sdadel_min = specs->hddat_min + setup->fall_time -
502 af_delay_min - (i2c_dev->dnf + 3) * i2cclk;
503
504 sdadel_max = specs->vddat_max - setup->rise_time -
505 af_delay_max - (i2c_dev->dnf + 4) * i2cclk;
506
507 scldel_min = setup->rise_time + specs->sudat_min;
508
509 if (sdadel_min < 0)
510 sdadel_min = 0;
511 if (sdadel_max < 0)
512 sdadel_max = 0;
513
514 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
515 sdadel_min, sdadel_max, scldel_min);
516
517 INIT_LIST_HEAD(&solutions);
518 /* Compute possible values for PRESC, SCLDEL and SDADEL */
519 for (p = 0; p < STM32F7_PRESC_MAX; p++) {
520 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
521 u32 scldel = (l + 1) * (p + 1) * i2cclk;
522
523 if (scldel < scldel_min)
524 continue;
525
526 for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
527 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
528
529 if (((sdadel >= sdadel_min) &&
530 (sdadel <= sdadel_max)) &&
531 (p != p_prev)) {
532 v = kmalloc(sizeof(*v), GFP_KERNEL);
533 if (!v) {
534 ret = -ENOMEM;
535 goto exit;
536 }
537
538 v->presc = p;
539 v->scldel = l;
540 v->sdadel = a;
541 p_prev = p;
542
543 list_add_tail(&v->node,
544 &solutions);
545 break;
546 }
547 }
548
549 if (p_prev == p)
550 break;
551 }
552 }
553
554 if (list_empty(&solutions)) {
555 dev_err(i2c_dev->dev, "no Prescaler solution\n");
556 ret = -EPERM;
557 goto exit;
558 }
559
560 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
561 s = NULL;
562 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq);
563 clk_min = NSEC_PER_SEC / setup->speed_freq;
564
565 /*
566 * Among Prescaler possibilities discovered above figures out SCL Low
567 * and High Period. Provided:
568 * - SCL Low Period has to be higher than SCL Clock Low Period
569 * defined by I2C Specification. I2C Clock has to be lower than
570 * (SCL Low Period - Analog/Digital filters) / 4.
571 * - SCL High Period has to be lower than SCL Clock High Period
572 * defined by I2C Specification
573 * - I2C Clock has to be lower than SCL High Period
574 */
575 list_for_each_entry(v, &solutions, node) {
576 u32 prescaler = (v->presc + 1) * i2cclk;
577
578 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
579 u32 tscl_l = (l + 1) * prescaler + tsync;
580
581 if ((tscl_l < specs->l_min) ||
582 (i2cclk >=
583 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
584 continue;
585 }
586
587 for (h = 0; h < STM32F7_SCLH_MAX; h++) {
588 u32 tscl_h = (h + 1) * prescaler + tsync;
589 u32 tscl = tscl_l + tscl_h +
590 setup->rise_time + setup->fall_time;
591
592 if ((tscl >= clk_min) && (tscl <= clk_max) &&
593 (tscl_h >= specs->h_min) &&
594 (i2cclk < tscl_h)) {
595 int clk_error = tscl - i2cbus;
596
597 if (clk_error < 0)
598 clk_error = -clk_error;
599
600 if (clk_error < clk_error_prev) {
601 clk_error_prev = clk_error;
602 v->scll = l;
603 v->sclh = h;
604 s = v;
605 }
606 }
607 }
608 }
609 }
610
611 if (!s) {
612 dev_err(i2c_dev->dev, "no solution at all\n");
613 ret = -EPERM;
614 goto exit;
615 }
616
617 output->presc = s->presc;
618 output->scldel = s->scldel;
619 output->sdadel = s->sdadel;
620 output->scll = s->scll;
621 output->sclh = s->sclh;
622
623 dev_dbg(i2c_dev->dev,
624 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
625 output->presc,
626 output->scldel, output->sdadel,
627 output->scll, output->sclh);
628
629 exit:
630 /* Release list and memory */
631 list_for_each_entry_safe(v, _v, &solutions, node) {
632 list_del(&v->node);
633 kfree(v);
634 }
635
636 return ret;
637 }
638
stm32f7_get_lower_rate(u32 rate)639 static u32 stm32f7_get_lower_rate(u32 rate)
640 {
641 int i = ARRAY_SIZE(stm32f7_i2c_specs);
642
643 while (--i)
644 if (stm32f7_i2c_specs[i].rate < rate)
645 break;
646
647 return stm32f7_i2c_specs[i].rate;
648 }
649
stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev * i2c_dev,struct stm32f7_i2c_setup * setup)650 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
651 struct stm32f7_i2c_setup *setup)
652 {
653 struct i2c_timings timings, *t = &timings;
654 int ret = 0;
655
656 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
657 t->scl_rise_ns = i2c_dev->setup.rise_time;
658 t->scl_fall_ns = i2c_dev->setup.fall_time;
659
660 i2c_parse_fw_timings(i2c_dev->dev, t, false);
661
662 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) {
663 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n",
664 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ);
665 return -EINVAL;
666 }
667
668 setup->speed_freq = t->bus_freq_hz;
669 i2c_dev->setup.rise_time = t->scl_rise_ns;
670 i2c_dev->setup.fall_time = t->scl_fall_ns;
671 i2c_dev->dnf_dt = t->digital_filter_width_ns;
672 setup->clock_src = clk_get_rate(i2c_dev->clk);
673
674 if (!setup->clock_src) {
675 dev_err(i2c_dev->dev, "clock rate is 0\n");
676 return -EINVAL;
677 }
678
679 if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter"))
680 i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT;
681
682 do {
683 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
684 &i2c_dev->timing);
685 if (ret) {
686 dev_err(i2c_dev->dev,
687 "failed to compute I2C timings.\n");
688 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ)
689 break;
690 setup->speed_freq =
691 stm32f7_get_lower_rate(setup->speed_freq);
692 dev_warn(i2c_dev->dev,
693 "downgrade I2C Speed Freq to (%i)\n",
694 setup->speed_freq);
695 }
696 } while (ret);
697
698 if (ret) {
699 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
700 return ret;
701 }
702
703 i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node,
704 "i2c-analog-filter");
705
706 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n",
707 setup->speed_freq, setup->clock_src);
708 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
709 setup->rise_time, setup->fall_time);
710 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
711 (i2c_dev->analog_filter ? "On" : "Off"), i2c_dev->dnf);
712
713 i2c_dev->bus_rate = setup->speed_freq;
714
715 return 0;
716 }
717
stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev * i2c_dev)718 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
719 {
720 void __iomem *base = i2c_dev->base;
721 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
722
723 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
724 }
725
stm32f7_i2c_dma_callback(void * arg)726 static void stm32f7_i2c_dma_callback(void *arg)
727 {
728 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
729 struct stm32_i2c_dma *dma = i2c_dev->dma;
730 struct device *dev = dma->chan_using->device->dev;
731
732 stm32f7_i2c_disable_dma_req(i2c_dev);
733 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
734 complete(&dma->dma_complete);
735 }
736
stm32f7_i2c_hw_config(struct stm32f7_i2c_dev * i2c_dev)737 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
738 {
739 struct stm32f7_i2c_timings *t = &i2c_dev->timing;
740 u32 timing = 0;
741
742 /* Timing settings */
743 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
744 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
745 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
746 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
747 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
748 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
749
750 /* Configure the Analog Filter */
751 if (i2c_dev->analog_filter)
752 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
753 STM32F7_I2C_CR1_ANFOFF);
754 else
755 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
756 STM32F7_I2C_CR1_ANFOFF);
757
758 /* Program the Digital Filter */
759 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
760 STM32F7_I2C_CR1_DNF_MASK);
761 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
762 STM32F7_I2C_CR1_DNF(i2c_dev->dnf));
763
764 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
765 STM32F7_I2C_CR1_PE);
766 }
767
stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev * i2c_dev)768 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
769 {
770 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
771 void __iomem *base = i2c_dev->base;
772
773 if (f7_msg->count) {
774 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
775 f7_msg->count--;
776 }
777 }
778
stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev * i2c_dev)779 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
780 {
781 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
782 void __iomem *base = i2c_dev->base;
783
784 if (f7_msg->count) {
785 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
786 f7_msg->count--;
787 } else {
788 /* Flush RX buffer has no data is expected */
789 readb_relaxed(base + STM32F7_I2C_RXDR);
790 }
791 }
792
stm32f7_i2c_reload(struct stm32f7_i2c_dev * i2c_dev)793 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
794 {
795 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
796 u32 cr2;
797
798 if (i2c_dev->use_dma)
799 f7_msg->count -= STM32F7_I2C_MAX_LEN;
800
801 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
802
803 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
804 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
805 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
806 } else {
807 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
808 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
809 }
810
811 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
812 }
813
stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev * i2c_dev)814 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
815 {
816 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
817 u32 cr2;
818 u8 *val;
819
820 /*
821 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
822 * data received inform us how many data will follow.
823 */
824 stm32f7_i2c_read_rx_data(i2c_dev);
825
826 /*
827 * Update NBYTES with the value read to continue the transfer
828 */
829 val = f7_msg->buf - sizeof(u8);
830 f7_msg->count = *val;
831 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
832 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
833 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
834 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
835 }
836
stm32f7_i2c_release_bus(struct i2c_adapter * i2c_adap)837 static void stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
838 {
839 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
840
841 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
842 STM32F7_I2C_CR1_PE);
843
844 stm32f7_i2c_hw_config(i2c_dev);
845 }
846
stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev * i2c_dev)847 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
848 {
849 u32 status;
850 int ret;
851
852 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
853 status,
854 !(status & STM32F7_I2C_ISR_BUSY),
855 10, 1000);
856 if (!ret)
857 return 0;
858
859 stm32f7_i2c_release_bus(&i2c_dev->adap);
860
861 return -EBUSY;
862 }
863
stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev * i2c_dev,struct i2c_msg * msg)864 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
865 struct i2c_msg *msg)
866 {
867 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
868 void __iomem *base = i2c_dev->base;
869 u32 cr1, cr2;
870 int ret;
871
872 f7_msg->addr = msg->addr;
873 f7_msg->buf = msg->buf;
874 f7_msg->count = msg->len;
875 f7_msg->result = 0;
876 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
877
878 reinit_completion(&i2c_dev->complete);
879
880 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
881 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
882
883 /* Set transfer direction */
884 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
885 if (msg->flags & I2C_M_RD)
886 cr2 |= STM32F7_I2C_CR2_RD_WRN;
887
888 /* Set slave address */
889 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
890 if (msg->flags & I2C_M_TEN) {
891 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
892 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
893 cr2 |= STM32F7_I2C_CR2_ADD10;
894 } else {
895 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
896 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
897 }
898
899 /* Set nb bytes to transfer and reload if needed */
900 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
901 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
902 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
903 cr2 |= STM32F7_I2C_CR2_RELOAD;
904 } else {
905 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
906 }
907
908 /* Enable NACK, STOP, error and transfer complete interrupts */
909 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
910 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
911
912 /* Clear DMA req and TX/RX interrupt */
913 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
914 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
915
916 /* Configure DMA or enable RX/TX interrupt */
917 i2c_dev->use_dma = false;
918 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
919 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
920 msg->flags & I2C_M_RD,
921 f7_msg->count, f7_msg->buf,
922 stm32f7_i2c_dma_callback,
923 i2c_dev);
924 if (!ret)
925 i2c_dev->use_dma = true;
926 else
927 dev_warn(i2c_dev->dev, "can't use DMA\n");
928 }
929
930 if (!i2c_dev->use_dma) {
931 if (msg->flags & I2C_M_RD)
932 cr1 |= STM32F7_I2C_CR1_RXIE;
933 else
934 cr1 |= STM32F7_I2C_CR1_TXIE;
935 } else {
936 if (msg->flags & I2C_M_RD)
937 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
938 else
939 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
940 }
941
942 /* Configure Start/Repeated Start */
943 cr2 |= STM32F7_I2C_CR2_START;
944
945 i2c_dev->master_mode = true;
946
947 /* Write configurations registers */
948 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
949 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
950 }
951
stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev * i2c_dev,unsigned short flags,u8 command,union i2c_smbus_data * data)952 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
953 unsigned short flags, u8 command,
954 union i2c_smbus_data *data)
955 {
956 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
957 struct device *dev = i2c_dev->dev;
958 void __iomem *base = i2c_dev->base;
959 u32 cr1, cr2;
960 int i, ret;
961
962 f7_msg->result = 0;
963 reinit_completion(&i2c_dev->complete);
964
965 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
966 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
967
968 /* Set transfer direction */
969 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
970 if (f7_msg->read_write)
971 cr2 |= STM32F7_I2C_CR2_RD_WRN;
972
973 /* Set slave address */
974 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
975 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
976
977 f7_msg->smbus_buf[0] = command;
978 switch (f7_msg->size) {
979 case I2C_SMBUS_QUICK:
980 f7_msg->stop = true;
981 f7_msg->count = 0;
982 break;
983 case I2C_SMBUS_BYTE:
984 f7_msg->stop = true;
985 f7_msg->count = 1;
986 break;
987 case I2C_SMBUS_BYTE_DATA:
988 if (f7_msg->read_write) {
989 f7_msg->stop = false;
990 f7_msg->count = 1;
991 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
992 } else {
993 f7_msg->stop = true;
994 f7_msg->count = 2;
995 f7_msg->smbus_buf[1] = data->byte;
996 }
997 break;
998 case I2C_SMBUS_WORD_DATA:
999 if (f7_msg->read_write) {
1000 f7_msg->stop = false;
1001 f7_msg->count = 1;
1002 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1003 } else {
1004 f7_msg->stop = true;
1005 f7_msg->count = 3;
1006 f7_msg->smbus_buf[1] = data->word & 0xff;
1007 f7_msg->smbus_buf[2] = data->word >> 8;
1008 }
1009 break;
1010 case I2C_SMBUS_BLOCK_DATA:
1011 if (f7_msg->read_write) {
1012 f7_msg->stop = false;
1013 f7_msg->count = 1;
1014 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1015 } else {
1016 f7_msg->stop = true;
1017 if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
1018 !data->block[0]) {
1019 dev_err(dev, "Invalid block write size %d\n",
1020 data->block[0]);
1021 return -EINVAL;
1022 }
1023 f7_msg->count = data->block[0] + 2;
1024 for (i = 1; i < f7_msg->count; i++)
1025 f7_msg->smbus_buf[i] = data->block[i - 1];
1026 }
1027 break;
1028 case I2C_SMBUS_PROC_CALL:
1029 f7_msg->stop = false;
1030 f7_msg->count = 3;
1031 f7_msg->smbus_buf[1] = data->word & 0xff;
1032 f7_msg->smbus_buf[2] = data->word >> 8;
1033 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1034 f7_msg->read_write = I2C_SMBUS_READ;
1035 break;
1036 case I2C_SMBUS_BLOCK_PROC_CALL:
1037 f7_msg->stop = false;
1038 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
1039 dev_err(dev, "Invalid block write size %d\n",
1040 data->block[0]);
1041 return -EINVAL;
1042 }
1043 f7_msg->count = data->block[0] + 2;
1044 for (i = 1; i < f7_msg->count; i++)
1045 f7_msg->smbus_buf[i] = data->block[i - 1];
1046 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1047 f7_msg->read_write = I2C_SMBUS_READ;
1048 break;
1049 case I2C_SMBUS_I2C_BLOCK_DATA:
1050 /* Rely on emulated i2c transfer (through master_xfer) */
1051 return -EOPNOTSUPP;
1052 default:
1053 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
1054 return -EOPNOTSUPP;
1055 }
1056
1057 f7_msg->buf = f7_msg->smbus_buf;
1058
1059 /* Configure PEC */
1060 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
1061 cr1 |= STM32F7_I2C_CR1_PECEN;
1062 if (!f7_msg->read_write) {
1063 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1064 f7_msg->count++;
1065 }
1066 } else {
1067 cr1 &= ~STM32F7_I2C_CR1_PECEN;
1068 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
1069 }
1070
1071 /* Set number of bytes to be transferred */
1072 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
1073 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1074
1075 /* Enable NACK, STOP, error and transfer complete interrupts */
1076 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1077 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
1078
1079 /* Clear DMA req and TX/RX interrupt */
1080 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1081 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1082
1083 /* Configure DMA or enable RX/TX interrupt */
1084 i2c_dev->use_dma = false;
1085 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1086 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1087 cr2 & STM32F7_I2C_CR2_RD_WRN,
1088 f7_msg->count, f7_msg->buf,
1089 stm32f7_i2c_dma_callback,
1090 i2c_dev);
1091 if (!ret)
1092 i2c_dev->use_dma = true;
1093 else
1094 dev_warn(i2c_dev->dev, "can't use DMA\n");
1095 }
1096
1097 if (!i2c_dev->use_dma) {
1098 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1099 cr1 |= STM32F7_I2C_CR1_RXIE;
1100 else
1101 cr1 |= STM32F7_I2C_CR1_TXIE;
1102 } else {
1103 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1104 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1105 else
1106 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1107 }
1108
1109 /* Set Start bit */
1110 cr2 |= STM32F7_I2C_CR2_START;
1111
1112 i2c_dev->master_mode = true;
1113
1114 /* Write configurations registers */
1115 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1116 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1117
1118 return 0;
1119 }
1120
stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev * i2c_dev)1121 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1122 {
1123 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1124 void __iomem *base = i2c_dev->base;
1125 u32 cr1, cr2;
1126 int ret;
1127
1128 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1129 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1130
1131 /* Set transfer direction */
1132 cr2 |= STM32F7_I2C_CR2_RD_WRN;
1133
1134 switch (f7_msg->size) {
1135 case I2C_SMBUS_BYTE_DATA:
1136 f7_msg->count = 1;
1137 break;
1138 case I2C_SMBUS_WORD_DATA:
1139 case I2C_SMBUS_PROC_CALL:
1140 f7_msg->count = 2;
1141 break;
1142 case I2C_SMBUS_BLOCK_DATA:
1143 case I2C_SMBUS_BLOCK_PROC_CALL:
1144 f7_msg->count = 1;
1145 cr2 |= STM32F7_I2C_CR2_RELOAD;
1146 break;
1147 }
1148
1149 f7_msg->buf = f7_msg->smbus_buf;
1150 f7_msg->stop = true;
1151
1152 /* Add one byte for PEC if needed */
1153 if (cr1 & STM32F7_I2C_CR1_PECEN) {
1154 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1155 f7_msg->count++;
1156 }
1157
1158 /* Set number of bytes to be transferred */
1159 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1160 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1161
1162 /*
1163 * Configure RX/TX interrupt:
1164 */
1165 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1166 cr1 |= STM32F7_I2C_CR1_RXIE;
1167
1168 /*
1169 * Configure DMA or enable RX/TX interrupt:
1170 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1171 * dma as we don't know in advance how many data will be received
1172 */
1173 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1174 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1175
1176 i2c_dev->use_dma = false;
1177 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1178 f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1179 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1180 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1181 cr2 & STM32F7_I2C_CR2_RD_WRN,
1182 f7_msg->count, f7_msg->buf,
1183 stm32f7_i2c_dma_callback,
1184 i2c_dev);
1185
1186 if (!ret)
1187 i2c_dev->use_dma = true;
1188 else
1189 dev_warn(i2c_dev->dev, "can't use DMA\n");
1190 }
1191
1192 if (!i2c_dev->use_dma)
1193 cr1 |= STM32F7_I2C_CR1_RXIE;
1194 else
1195 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1196
1197 /* Configure Repeated Start */
1198 cr2 |= STM32F7_I2C_CR2_START;
1199
1200 /* Write configurations registers */
1201 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1202 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1203 }
1204
stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev * i2c_dev)1205 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1206 {
1207 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1208 u8 count, internal_pec, received_pec;
1209
1210 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1211
1212 switch (f7_msg->size) {
1213 case I2C_SMBUS_BYTE:
1214 case I2C_SMBUS_BYTE_DATA:
1215 received_pec = f7_msg->smbus_buf[1];
1216 break;
1217 case I2C_SMBUS_WORD_DATA:
1218 case I2C_SMBUS_PROC_CALL:
1219 received_pec = f7_msg->smbus_buf[2];
1220 break;
1221 case I2C_SMBUS_BLOCK_DATA:
1222 case I2C_SMBUS_BLOCK_PROC_CALL:
1223 count = f7_msg->smbus_buf[0];
1224 received_pec = f7_msg->smbus_buf[count];
1225 break;
1226 default:
1227 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1228 return -EINVAL;
1229 }
1230
1231 if (internal_pec != received_pec) {
1232 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1233 internal_pec, received_pec);
1234 return -EBADMSG;
1235 }
1236
1237 return 0;
1238 }
1239
stm32f7_i2c_is_addr_match(struct i2c_client * slave,u32 addcode)1240 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1241 {
1242 u32 addr;
1243
1244 if (!slave)
1245 return false;
1246
1247 if (slave->flags & I2C_CLIENT_TEN) {
1248 /*
1249 * For 10-bit addr, addcode = 11110XY with
1250 * X = Bit 9 of slave address
1251 * Y = Bit 8 of slave address
1252 */
1253 addr = slave->addr >> 8;
1254 addr |= 0x78;
1255 if (addr == addcode)
1256 return true;
1257 } else {
1258 addr = slave->addr & 0x7f;
1259 if (addr == addcode)
1260 return true;
1261 }
1262
1263 return false;
1264 }
1265
stm32f7_i2c_slave_start(struct stm32f7_i2c_dev * i2c_dev)1266 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1267 {
1268 struct i2c_client *slave = i2c_dev->slave_running;
1269 void __iomem *base = i2c_dev->base;
1270 u32 mask;
1271 u8 value = 0;
1272
1273 if (i2c_dev->slave_dir) {
1274 /* Notify i2c slave that new read transfer is starting */
1275 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1276
1277 /*
1278 * Disable slave TX config in case of I2C combined message
1279 * (I2C Write followed by I2C Read)
1280 */
1281 mask = STM32F7_I2C_CR2_RELOAD;
1282 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1283 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1284 STM32F7_I2C_CR1_TCIE;
1285 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1286
1287 /* Enable TX empty, STOP, NACK interrupts */
1288 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1289 STM32F7_I2C_CR1_TXIE;
1290 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1291
1292 /* Write 1st data byte */
1293 writel_relaxed(value, base + STM32F7_I2C_TXDR);
1294 } else {
1295 /* Notify i2c slave that new write transfer is starting */
1296 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1297
1298 /* Set reload mode to be able to ACK/NACK each received byte */
1299 mask = STM32F7_I2C_CR2_RELOAD;
1300 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1301
1302 /*
1303 * Set STOP, NACK, RX empty and transfer complete interrupts.*
1304 * Set Slave Byte Control to be able to ACK/NACK each data
1305 * byte received
1306 */
1307 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1308 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1309 STM32F7_I2C_CR1_TCIE;
1310 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1311 }
1312 }
1313
stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev * i2c_dev)1314 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1315 {
1316 void __iomem *base = i2c_dev->base;
1317 u32 isr, addcode, dir, mask;
1318 int i;
1319
1320 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1321 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1322 dir = isr & STM32F7_I2C_ISR_DIR;
1323
1324 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1325 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1326 i2c_dev->slave_running = i2c_dev->slave[i];
1327 i2c_dev->slave_dir = dir;
1328
1329 /* Start I2C slave processing */
1330 stm32f7_i2c_slave_start(i2c_dev);
1331
1332 /* Clear ADDR flag */
1333 mask = STM32F7_I2C_ICR_ADDRCF;
1334 writel_relaxed(mask, base + STM32F7_I2C_ICR);
1335 break;
1336 }
1337 }
1338 }
1339
stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev * i2c_dev,struct i2c_client * slave,int * id)1340 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1341 struct i2c_client *slave, int *id)
1342 {
1343 int i;
1344
1345 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1346 if (i2c_dev->slave[i] == slave) {
1347 *id = i;
1348 return 0;
1349 }
1350 }
1351
1352 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1353
1354 return -ENODEV;
1355 }
1356
stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev * i2c_dev,struct i2c_client * slave,int * id)1357 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1358 struct i2c_client *slave, int *id)
1359 {
1360 struct device *dev = i2c_dev->dev;
1361 int i;
1362
1363 /*
1364 * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8)
1365 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address
1366 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only
1367 */
1368 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) {
1369 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY])
1370 goto fail;
1371 *id = STM32F7_SLAVE_HOSTNOTIFY;
1372 return 0;
1373 }
1374
1375 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) {
1376 if ((i == STM32F7_SLAVE_7_BITS_ADDR) &&
1377 (slave->flags & I2C_CLIENT_TEN))
1378 continue;
1379 if (!i2c_dev->slave[i]) {
1380 *id = i;
1381 return 0;
1382 }
1383 }
1384
1385 fail:
1386 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1387
1388 return -EINVAL;
1389 }
1390
stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev * i2c_dev)1391 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1392 {
1393 int i;
1394
1395 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1396 if (i2c_dev->slave[i])
1397 return true;
1398 }
1399
1400 return false;
1401 }
1402
stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev * i2c_dev)1403 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1404 {
1405 int i, busy;
1406
1407 busy = 0;
1408 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1409 if (i2c_dev->slave[i])
1410 busy++;
1411 }
1412
1413 return i == busy;
1414 }
1415
stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev * i2c_dev)1416 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1417 {
1418 void __iomem *base = i2c_dev->base;
1419 u32 cr2, status, mask;
1420 u8 val;
1421 int ret;
1422
1423 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1424
1425 /* Slave transmitter mode */
1426 if (status & STM32F7_I2C_ISR_TXIS) {
1427 i2c_slave_event(i2c_dev->slave_running,
1428 I2C_SLAVE_READ_PROCESSED,
1429 &val);
1430
1431 /* Write data byte */
1432 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1433 }
1434
1435 /* Transfer Complete Reload for Slave receiver mode */
1436 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1437 /*
1438 * Read data byte then set NBYTES to receive next byte or NACK
1439 * the current received byte
1440 */
1441 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1442 ret = i2c_slave_event(i2c_dev->slave_running,
1443 I2C_SLAVE_WRITE_RECEIVED,
1444 &val);
1445 if (!ret) {
1446 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1447 cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1448 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1449 } else {
1450 mask = STM32F7_I2C_CR2_NACK;
1451 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1452 }
1453 }
1454
1455 /* NACK received */
1456 if (status & STM32F7_I2C_ISR_NACKF) {
1457 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1458 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1459 }
1460
1461 /* STOP received */
1462 if (status & STM32F7_I2C_ISR_STOPF) {
1463 /* Disable interrupts */
1464 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1465
1466 if (i2c_dev->slave_dir) {
1467 /*
1468 * Flush TX buffer in order to not used the byte in
1469 * TXDR for the next transfer
1470 */
1471 mask = STM32F7_I2C_ISR_TXE;
1472 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1473 }
1474
1475 /* Clear STOP flag */
1476 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1477
1478 /* Notify i2c slave that a STOP flag has been detected */
1479 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1480
1481 i2c_dev->slave_running = NULL;
1482 }
1483
1484 /* Address match received */
1485 if (status & STM32F7_I2C_ISR_ADDR)
1486 stm32f7_i2c_slave_addr(i2c_dev);
1487
1488 return IRQ_HANDLED;
1489 }
1490
stm32f7_i2c_isr_event(int irq,void * data)1491 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1492 {
1493 struct stm32f7_i2c_dev *i2c_dev = data;
1494 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1495 struct stm32_i2c_dma *dma = i2c_dev->dma;
1496 void __iomem *base = i2c_dev->base;
1497 u32 status, mask;
1498 int ret = IRQ_HANDLED;
1499
1500 /* Check if the interrupt if for a slave device */
1501 if (!i2c_dev->master_mode) {
1502 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1503 return ret;
1504 }
1505
1506 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1507
1508 /* Tx empty */
1509 if (status & STM32F7_I2C_ISR_TXIS)
1510 stm32f7_i2c_write_tx_data(i2c_dev);
1511
1512 /* RX not empty */
1513 if (status & STM32F7_I2C_ISR_RXNE)
1514 stm32f7_i2c_read_rx_data(i2c_dev);
1515
1516 /* NACK received */
1517 if (status & STM32F7_I2C_ISR_NACKF) {
1518 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n",
1519 __func__, f7_msg->addr);
1520 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1521 if (i2c_dev->use_dma) {
1522 stm32f7_i2c_disable_dma_req(i2c_dev);
1523 dmaengine_terminate_async(dma->chan_using);
1524 }
1525 f7_msg->result = -ENXIO;
1526 }
1527
1528 /* STOP detection flag */
1529 if (status & STM32F7_I2C_ISR_STOPF) {
1530 /* Disable interrupts */
1531 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1532 mask = STM32F7_I2C_XFER_IRQ_MASK;
1533 else
1534 mask = STM32F7_I2C_ALL_IRQ_MASK;
1535 stm32f7_i2c_disable_irq(i2c_dev, mask);
1536
1537 /* Clear STOP flag */
1538 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1539
1540 if (i2c_dev->use_dma && !f7_msg->result) {
1541 ret = IRQ_WAKE_THREAD;
1542 } else {
1543 i2c_dev->master_mode = false;
1544 complete(&i2c_dev->complete);
1545 }
1546 }
1547
1548 /* Transfer complete */
1549 if (status & STM32F7_I2C_ISR_TC) {
1550 if (f7_msg->stop) {
1551 mask = STM32F7_I2C_CR2_STOP;
1552 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1553 } else if (i2c_dev->use_dma && !f7_msg->result) {
1554 ret = IRQ_WAKE_THREAD;
1555 } else if (f7_msg->smbus) {
1556 stm32f7_i2c_smbus_rep_start(i2c_dev);
1557 } else {
1558 i2c_dev->msg_id++;
1559 i2c_dev->msg++;
1560 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1561 }
1562 }
1563
1564 if (status & STM32F7_I2C_ISR_TCR) {
1565 if (f7_msg->smbus)
1566 stm32f7_i2c_smbus_reload(i2c_dev);
1567 else
1568 stm32f7_i2c_reload(i2c_dev);
1569 }
1570
1571 return ret;
1572 }
1573
stm32f7_i2c_isr_event_thread(int irq,void * data)1574 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1575 {
1576 struct stm32f7_i2c_dev *i2c_dev = data;
1577 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1578 struct stm32_i2c_dma *dma = i2c_dev->dma;
1579 u32 status;
1580 int ret;
1581
1582 /*
1583 * Wait for dma transfer completion before sending next message or
1584 * notity the end of xfer to the client
1585 */
1586 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1587 if (!ret) {
1588 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1589 stm32f7_i2c_disable_dma_req(i2c_dev);
1590 dmaengine_terminate_async(dma->chan_using);
1591 f7_msg->result = -ETIMEDOUT;
1592 }
1593
1594 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1595
1596 if (status & STM32F7_I2C_ISR_TC) {
1597 if (f7_msg->smbus) {
1598 stm32f7_i2c_smbus_rep_start(i2c_dev);
1599 } else {
1600 i2c_dev->msg_id++;
1601 i2c_dev->msg++;
1602 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1603 }
1604 } else {
1605 i2c_dev->master_mode = false;
1606 complete(&i2c_dev->complete);
1607 }
1608
1609 return IRQ_HANDLED;
1610 }
1611
stm32f7_i2c_isr_error(int irq,void * data)1612 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1613 {
1614 struct stm32f7_i2c_dev *i2c_dev = data;
1615 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1616 void __iomem *base = i2c_dev->base;
1617 struct device *dev = i2c_dev->dev;
1618 struct stm32_i2c_dma *dma = i2c_dev->dma;
1619 u32 status;
1620
1621 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1622
1623 /* Bus error */
1624 if (status & STM32F7_I2C_ISR_BERR) {
1625 dev_err(dev, "<%s>: Bus error accessing addr 0x%x\n",
1626 __func__, f7_msg->addr);
1627 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1628 stm32f7_i2c_release_bus(&i2c_dev->adap);
1629 f7_msg->result = -EIO;
1630 }
1631
1632 /* Arbitration loss */
1633 if (status & STM32F7_I2C_ISR_ARLO) {
1634 dev_dbg(dev, "<%s>: Arbitration loss accessing addr 0x%x\n",
1635 __func__, f7_msg->addr);
1636 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1637 f7_msg->result = -EAGAIN;
1638 }
1639
1640 if (status & STM32F7_I2C_ISR_PECERR) {
1641 dev_err(dev, "<%s>: PEC error in reception accessing addr 0x%x\n",
1642 __func__, f7_msg->addr);
1643 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1644 f7_msg->result = -EINVAL;
1645 }
1646
1647 if (status & STM32F7_I2C_ISR_ALERT) {
1648 dev_dbg(dev, "<%s>: SMBus alert received\n", __func__);
1649 writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR);
1650 i2c_handle_smbus_alert(i2c_dev->alert->ara);
1651 return IRQ_HANDLED;
1652 }
1653
1654 if (!i2c_dev->slave_running) {
1655 u32 mask;
1656 /* Disable interrupts */
1657 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1658 mask = STM32F7_I2C_XFER_IRQ_MASK;
1659 else
1660 mask = STM32F7_I2C_ALL_IRQ_MASK;
1661 stm32f7_i2c_disable_irq(i2c_dev, mask);
1662 }
1663
1664 /* Disable dma */
1665 if (i2c_dev->use_dma) {
1666 stm32f7_i2c_disable_dma_req(i2c_dev);
1667 dmaengine_terminate_async(dma->chan_using);
1668 }
1669
1670 i2c_dev->master_mode = false;
1671 complete(&i2c_dev->complete);
1672
1673 return IRQ_HANDLED;
1674 }
1675
stm32f7_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg msgs[],int num)1676 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1677 struct i2c_msg msgs[], int num)
1678 {
1679 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1680 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1681 struct stm32_i2c_dma *dma = i2c_dev->dma;
1682 unsigned long time_left;
1683 int ret;
1684
1685 i2c_dev->msg = msgs;
1686 i2c_dev->msg_num = num;
1687 i2c_dev->msg_id = 0;
1688 f7_msg->smbus = false;
1689
1690 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1691 if (ret < 0)
1692 return ret;
1693
1694 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1695 if (ret)
1696 goto pm_free;
1697
1698 stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1699
1700 time_left = wait_for_completion_timeout(&i2c_dev->complete,
1701 i2c_dev->adap.timeout);
1702 ret = f7_msg->result;
1703 if (ret) {
1704 if (i2c_dev->use_dma)
1705 dmaengine_synchronize(dma->chan_using);
1706
1707 /*
1708 * It is possible that some unsent data have already been
1709 * written into TXDR. To avoid sending old data in a
1710 * further transfer, flush TXDR in case of any error
1711 */
1712 writel_relaxed(STM32F7_I2C_ISR_TXE,
1713 i2c_dev->base + STM32F7_I2C_ISR);
1714 goto pm_free;
1715 }
1716
1717 if (!time_left) {
1718 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1719 i2c_dev->msg->addr);
1720 if (i2c_dev->use_dma)
1721 dmaengine_terminate_sync(dma->chan_using);
1722 stm32f7_i2c_wait_free_bus(i2c_dev);
1723 ret = -ETIMEDOUT;
1724 }
1725
1726 pm_free:
1727 pm_runtime_mark_last_busy(i2c_dev->dev);
1728 pm_runtime_put_autosuspend(i2c_dev->dev);
1729
1730 return (ret < 0) ? ret : num;
1731 }
1732
stm32f7_i2c_smbus_xfer(struct i2c_adapter * adapter,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)1733 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1734 unsigned short flags, char read_write,
1735 u8 command, int size,
1736 union i2c_smbus_data *data)
1737 {
1738 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1739 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1740 struct stm32_i2c_dma *dma = i2c_dev->dma;
1741 struct device *dev = i2c_dev->dev;
1742 unsigned long timeout;
1743 int i, ret;
1744
1745 f7_msg->addr = addr;
1746 f7_msg->size = size;
1747 f7_msg->read_write = read_write;
1748 f7_msg->smbus = true;
1749
1750 ret = pm_runtime_resume_and_get(dev);
1751 if (ret < 0)
1752 return ret;
1753
1754 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1755 if (ret)
1756 goto pm_free;
1757
1758 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1759 if (ret)
1760 goto pm_free;
1761
1762 timeout = wait_for_completion_timeout(&i2c_dev->complete,
1763 i2c_dev->adap.timeout);
1764 ret = f7_msg->result;
1765 if (ret) {
1766 if (i2c_dev->use_dma)
1767 dmaengine_synchronize(dma->chan_using);
1768
1769 /*
1770 * It is possible that some unsent data have already been
1771 * written into TXDR. To avoid sending old data in a
1772 * further transfer, flush TXDR in case of any error
1773 */
1774 writel_relaxed(STM32F7_I2C_ISR_TXE,
1775 i2c_dev->base + STM32F7_I2C_ISR);
1776 goto pm_free;
1777 }
1778
1779 if (!timeout) {
1780 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1781 if (i2c_dev->use_dma)
1782 dmaengine_terminate_sync(dma->chan_using);
1783 stm32f7_i2c_wait_free_bus(i2c_dev);
1784 ret = -ETIMEDOUT;
1785 goto pm_free;
1786 }
1787
1788 /* Check PEC */
1789 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1790 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1791 if (ret)
1792 goto pm_free;
1793 }
1794
1795 if (read_write && size != I2C_SMBUS_QUICK) {
1796 switch (size) {
1797 case I2C_SMBUS_BYTE:
1798 case I2C_SMBUS_BYTE_DATA:
1799 data->byte = f7_msg->smbus_buf[0];
1800 break;
1801 case I2C_SMBUS_WORD_DATA:
1802 case I2C_SMBUS_PROC_CALL:
1803 data->word = f7_msg->smbus_buf[0] |
1804 (f7_msg->smbus_buf[1] << 8);
1805 break;
1806 case I2C_SMBUS_BLOCK_DATA:
1807 case I2C_SMBUS_BLOCK_PROC_CALL:
1808 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1809 data->block[i] = f7_msg->smbus_buf[i];
1810 break;
1811 default:
1812 dev_err(dev, "Unsupported smbus transaction\n");
1813 ret = -EINVAL;
1814 }
1815 }
1816
1817 pm_free:
1818 pm_runtime_mark_last_busy(dev);
1819 pm_runtime_put_autosuspend(dev);
1820 return ret;
1821 }
1822
stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev * i2c_dev,bool enable)1823 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev,
1824 bool enable)
1825 {
1826 void __iomem *base = i2c_dev->base;
1827 u32 mask = STM32F7_I2C_CR1_WUPEN;
1828
1829 if (!i2c_dev->wakeup_src)
1830 return;
1831
1832 if (enable) {
1833 device_set_wakeup_enable(i2c_dev->dev, true);
1834 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1835 } else {
1836 device_set_wakeup_enable(i2c_dev->dev, false);
1837 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1838 }
1839 }
1840
stm32f7_i2c_reg_slave(struct i2c_client * slave)1841 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1842 {
1843 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1844 void __iomem *base = i2c_dev->base;
1845 struct device *dev = i2c_dev->dev;
1846 u32 oar1, oar2, mask;
1847 int id, ret;
1848
1849 if (slave->flags & I2C_CLIENT_PEC) {
1850 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1851 return -EINVAL;
1852 }
1853
1854 if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1855 dev_err(dev, "Too much slave registered\n");
1856 return -EBUSY;
1857 }
1858
1859 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1860 if (ret)
1861 return ret;
1862
1863 ret = pm_runtime_resume_and_get(dev);
1864 if (ret < 0)
1865 return ret;
1866
1867 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1868 stm32f7_i2c_enable_wakeup(i2c_dev, true);
1869
1870 switch (id) {
1871 case 0:
1872 /* Slave SMBus Host */
1873 i2c_dev->slave[id] = slave;
1874 break;
1875
1876 case 1:
1877 /* Configure Own Address 1 */
1878 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1879 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1880 if (slave->flags & I2C_CLIENT_TEN) {
1881 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1882 oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1883 } else {
1884 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1885 }
1886 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1887 i2c_dev->slave[id] = slave;
1888 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1889 break;
1890
1891 case 2:
1892 /* Configure Own Address 2 */
1893 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1894 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1895 if (slave->flags & I2C_CLIENT_TEN) {
1896 ret = -EOPNOTSUPP;
1897 goto pm_free;
1898 }
1899
1900 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1901 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1902 i2c_dev->slave[id] = slave;
1903 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1904 break;
1905
1906 default:
1907 dev_err(dev, "I2C slave id not supported\n");
1908 ret = -ENODEV;
1909 goto pm_free;
1910 }
1911
1912 /* Enable ACK */
1913 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1914
1915 /* Enable Address match interrupt, error interrupt and enable I2C */
1916 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1917 STM32F7_I2C_CR1_PE;
1918 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1919
1920 ret = 0;
1921 pm_free:
1922 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1923 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1924
1925 pm_runtime_mark_last_busy(dev);
1926 pm_runtime_put_autosuspend(dev);
1927
1928 return ret;
1929 }
1930
stm32f7_i2c_unreg_slave(struct i2c_client * slave)1931 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1932 {
1933 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1934 void __iomem *base = i2c_dev->base;
1935 u32 mask;
1936 int id, ret;
1937
1938 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1939 if (ret)
1940 return ret;
1941
1942 WARN_ON(!i2c_dev->slave[id]);
1943
1944 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1945 if (ret < 0)
1946 return ret;
1947
1948 if (id == 1) {
1949 mask = STM32F7_I2C_OAR1_OA1EN;
1950 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1951 } else if (id == 2) {
1952 mask = STM32F7_I2C_OAR2_OA2EN;
1953 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1954 }
1955
1956 i2c_dev->slave[id] = NULL;
1957
1958 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
1959 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1960 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1961 }
1962
1963 pm_runtime_mark_last_busy(i2c_dev->dev);
1964 pm_runtime_put_autosuspend(i2c_dev->dev);
1965
1966 return 0;
1967 }
1968
stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev * i2c_dev,bool enable)1969 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,
1970 bool enable)
1971 {
1972 int ret;
1973
1974 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ ||
1975 IS_ERR_OR_NULL(i2c_dev->regmap))
1976 /* Optional */
1977 return 0;
1978
1979 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg)
1980 ret = regmap_update_bits(i2c_dev->regmap,
1981 i2c_dev->fmp_sreg,
1982 i2c_dev->fmp_mask,
1983 enable ? i2c_dev->fmp_mask : 0);
1984 else
1985 ret = regmap_write(i2c_dev->regmap,
1986 enable ? i2c_dev->fmp_sreg :
1987 i2c_dev->fmp_creg,
1988 i2c_dev->fmp_mask);
1989
1990 return ret;
1991 }
1992
stm32f7_i2c_setup_fm_plus_bits(struct platform_device * pdev,struct stm32f7_i2c_dev * i2c_dev)1993 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
1994 struct stm32f7_i2c_dev *i2c_dev)
1995 {
1996 struct device_node *np = pdev->dev.of_node;
1997 int ret;
1998
1999 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
2000 if (IS_ERR(i2c_dev->regmap))
2001 /* Optional */
2002 return 0;
2003
2004 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1,
2005 &i2c_dev->fmp_sreg);
2006 if (ret)
2007 return ret;
2008
2009 i2c_dev->fmp_creg = i2c_dev->fmp_sreg +
2010 i2c_dev->setup.fmp_clr_offset;
2011
2012 return of_property_read_u32_index(np, "st,syscfg-fmp", 2,
2013 &i2c_dev->fmp_mask);
2014 }
2015
stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev * i2c_dev)2016 static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2017 {
2018 struct i2c_adapter *adap = &i2c_dev->adap;
2019 void __iomem *base = i2c_dev->base;
2020 struct i2c_client *client;
2021
2022 client = i2c_new_slave_host_notify_device(adap);
2023 if (IS_ERR(client))
2024 return PTR_ERR(client);
2025
2026 i2c_dev->host_notify_client = client;
2027
2028 /* Enable SMBus Host address */
2029 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);
2030
2031 return 0;
2032 }
2033
stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev * i2c_dev)2034 static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2035 {
2036 void __iomem *base = i2c_dev->base;
2037
2038 if (i2c_dev->host_notify_client) {
2039 /* Disable SMBus Host address */
2040 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2041 STM32F7_I2C_CR1_SMBHEN);
2042 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client);
2043 }
2044 }
2045
stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev * i2c_dev)2046 static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2047 {
2048 struct stm32f7_i2c_alert *alert;
2049 struct i2c_adapter *adap = &i2c_dev->adap;
2050 struct device *dev = i2c_dev->dev;
2051 void __iomem *base = i2c_dev->base;
2052
2053 alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL);
2054 if (!alert)
2055 return -ENOMEM;
2056
2057 alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup);
2058 if (IS_ERR(alert->ara))
2059 return PTR_ERR(alert->ara);
2060
2061 i2c_dev->alert = alert;
2062
2063 /* Enable SMBus Alert */
2064 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN);
2065
2066 return 0;
2067 }
2068
stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev * i2c_dev)2069 static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2070 {
2071 struct stm32f7_i2c_alert *alert = i2c_dev->alert;
2072 void __iomem *base = i2c_dev->base;
2073
2074 if (alert) {
2075 /* Disable SMBus Alert */
2076 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2077 STM32F7_I2C_CR1_ALERTEN);
2078 i2c_unregister_device(alert->ara);
2079 }
2080 }
2081
stm32f7_i2c_func(struct i2c_adapter * adap)2082 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
2083 {
2084 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
2085
2086 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
2087 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
2088 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
2089 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
2090 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
2091 I2C_FUNC_SMBUS_I2C_BLOCK;
2092
2093 if (i2c_dev->smbus_mode)
2094 func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
2095
2096 return func;
2097 }
2098
2099 static const struct i2c_algorithm stm32f7_i2c_algo = {
2100 .master_xfer = stm32f7_i2c_xfer,
2101 .smbus_xfer = stm32f7_i2c_smbus_xfer,
2102 .functionality = stm32f7_i2c_func,
2103 .reg_slave = stm32f7_i2c_reg_slave,
2104 .unreg_slave = stm32f7_i2c_unreg_slave,
2105 };
2106
stm32f7_i2c_probe(struct platform_device * pdev)2107 static int stm32f7_i2c_probe(struct platform_device *pdev)
2108 {
2109 struct stm32f7_i2c_dev *i2c_dev;
2110 const struct stm32f7_i2c_setup *setup;
2111 struct resource *res;
2112 struct i2c_adapter *adap;
2113 struct reset_control *rst;
2114 dma_addr_t phy_addr;
2115 int irq_error, irq_event, ret;
2116
2117 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
2118 if (!i2c_dev)
2119 return -ENOMEM;
2120
2121 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2122 if (IS_ERR(i2c_dev->base))
2123 return PTR_ERR(i2c_dev->base);
2124 phy_addr = (dma_addr_t)res->start;
2125
2126 irq_event = platform_get_irq(pdev, 0);
2127 if (irq_event < 0)
2128 return irq_event;
2129
2130 irq_error = platform_get_irq(pdev, 1);
2131 if (irq_error < 0)
2132 return irq_error;
2133
2134 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node,
2135 "wakeup-source");
2136
2137 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
2138 if (IS_ERR(i2c_dev->clk))
2139 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk),
2140 "Failed to get controller clock\n");
2141
2142 ret = clk_prepare_enable(i2c_dev->clk);
2143 if (ret) {
2144 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
2145 return ret;
2146 }
2147
2148 rst = devm_reset_control_get(&pdev->dev, NULL);
2149 if (IS_ERR(rst)) {
2150 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
2151 "Error: Missing reset ctrl\n");
2152 goto clk_free;
2153 }
2154 reset_control_assert(rst);
2155 udelay(2);
2156 reset_control_deassert(rst);
2157
2158 i2c_dev->dev = &pdev->dev;
2159
2160 ret = devm_request_threaded_irq(&pdev->dev, irq_event,
2161 stm32f7_i2c_isr_event,
2162 stm32f7_i2c_isr_event_thread,
2163 IRQF_ONESHOT,
2164 pdev->name, i2c_dev);
2165 if (ret) {
2166 dev_err(&pdev->dev, "Failed to request irq event %i\n",
2167 irq_event);
2168 goto clk_free;
2169 }
2170
2171 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
2172 pdev->name, i2c_dev);
2173 if (ret) {
2174 dev_err(&pdev->dev, "Failed to request irq error %i\n",
2175 irq_error);
2176 goto clk_free;
2177 }
2178
2179 setup = of_device_get_match_data(&pdev->dev);
2180 if (!setup) {
2181 dev_err(&pdev->dev, "Can't get device data\n");
2182 ret = -ENODEV;
2183 goto clk_free;
2184 }
2185 i2c_dev->setup = *setup;
2186
2187 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
2188 if (ret)
2189 goto clk_free;
2190
2191 /* Setup Fast mode plus if necessary */
2192 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) {
2193 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
2194 if (ret)
2195 goto clk_free;
2196 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2197 if (ret)
2198 goto clk_free;
2199 }
2200
2201 adap = &i2c_dev->adap;
2202 i2c_set_adapdata(adap, i2c_dev);
2203 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
2204 &res->start);
2205 adap->owner = THIS_MODULE;
2206 adap->timeout = 2 * HZ;
2207 adap->retries = 3;
2208 adap->algo = &stm32f7_i2c_algo;
2209 adap->dev.parent = &pdev->dev;
2210 adap->dev.of_node = pdev->dev.of_node;
2211
2212 init_completion(&i2c_dev->complete);
2213
2214 /* Init DMA config if supported */
2215 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
2216 STM32F7_I2C_TXDR,
2217 STM32F7_I2C_RXDR);
2218 if (IS_ERR(i2c_dev->dma)) {
2219 ret = PTR_ERR(i2c_dev->dma);
2220 /* DMA support is optional, only report other errors */
2221 if (ret != -ENODEV)
2222 goto fmp_clear;
2223 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n");
2224 i2c_dev->dma = NULL;
2225 }
2226
2227 if (i2c_dev->wakeup_src) {
2228 device_set_wakeup_capable(i2c_dev->dev, true);
2229
2230 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event);
2231 if (ret) {
2232 dev_err(i2c_dev->dev, "Failed to set wake up irq\n");
2233 goto clr_wakeup_capable;
2234 }
2235 }
2236
2237 platform_set_drvdata(pdev, i2c_dev);
2238
2239 pm_runtime_set_autosuspend_delay(i2c_dev->dev,
2240 STM32F7_AUTOSUSPEND_DELAY);
2241 pm_runtime_use_autosuspend(i2c_dev->dev);
2242 pm_runtime_set_active(i2c_dev->dev);
2243 pm_runtime_enable(i2c_dev->dev);
2244
2245 pm_runtime_get_noresume(&pdev->dev);
2246
2247 stm32f7_i2c_hw_config(i2c_dev);
2248
2249 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus");
2250
2251 ret = i2c_add_adapter(adap);
2252 if (ret)
2253 goto pm_disable;
2254
2255 if (i2c_dev->smbus_mode) {
2256 ret = stm32f7_i2c_enable_smbus_host(i2c_dev);
2257 if (ret) {
2258 dev_err(i2c_dev->dev,
2259 "failed to enable SMBus Host-Notify protocol (%d)\n",
2260 ret);
2261 goto i2c_adapter_remove;
2262 }
2263 }
2264
2265 if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) {
2266 ret = stm32f7_i2c_enable_smbus_alert(i2c_dev);
2267 if (ret) {
2268 dev_err(i2c_dev->dev,
2269 "failed to enable SMBus alert protocol (%d)\n",
2270 ret);
2271 goto i2c_disable_smbus_host;
2272 }
2273 }
2274
2275 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2276
2277 pm_runtime_mark_last_busy(i2c_dev->dev);
2278 pm_runtime_put_autosuspend(i2c_dev->dev);
2279
2280 return 0;
2281
2282 i2c_disable_smbus_host:
2283 stm32f7_i2c_disable_smbus_host(i2c_dev);
2284
2285 i2c_adapter_remove:
2286 i2c_del_adapter(adap);
2287
2288 pm_disable:
2289 pm_runtime_put_noidle(i2c_dev->dev);
2290 pm_runtime_disable(i2c_dev->dev);
2291 pm_runtime_set_suspended(i2c_dev->dev);
2292 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2293
2294 if (i2c_dev->wakeup_src)
2295 dev_pm_clear_wake_irq(i2c_dev->dev);
2296
2297 clr_wakeup_capable:
2298 if (i2c_dev->wakeup_src)
2299 device_set_wakeup_capable(i2c_dev->dev, false);
2300
2301 if (i2c_dev->dma) {
2302 stm32_i2c_dma_free(i2c_dev->dma);
2303 i2c_dev->dma = NULL;
2304 }
2305
2306 fmp_clear:
2307 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2308
2309 clk_free:
2310 clk_disable_unprepare(i2c_dev->clk);
2311
2312 return ret;
2313 }
2314
stm32f7_i2c_remove(struct platform_device * pdev)2315 static void stm32f7_i2c_remove(struct platform_device *pdev)
2316 {
2317 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2318
2319 stm32f7_i2c_disable_smbus_alert(i2c_dev);
2320 stm32f7_i2c_disable_smbus_host(i2c_dev);
2321
2322 i2c_del_adapter(&i2c_dev->adap);
2323 pm_runtime_get_sync(i2c_dev->dev);
2324
2325 if (i2c_dev->wakeup_src) {
2326 dev_pm_clear_wake_irq(i2c_dev->dev);
2327 /*
2328 * enforce that wakeup is disabled and that the device
2329 * is marked as non wakeup capable
2330 */
2331 device_init_wakeup(i2c_dev->dev, false);
2332 }
2333
2334 pm_runtime_put_noidle(i2c_dev->dev);
2335 pm_runtime_disable(i2c_dev->dev);
2336 pm_runtime_set_suspended(i2c_dev->dev);
2337 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2338
2339 if (i2c_dev->dma) {
2340 stm32_i2c_dma_free(i2c_dev->dma);
2341 i2c_dev->dma = NULL;
2342 }
2343
2344 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2345
2346 clk_disable_unprepare(i2c_dev->clk);
2347 }
2348
stm32f7_i2c_runtime_suspend(struct device * dev)2349 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
2350 {
2351 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2352
2353 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2354 clk_disable_unprepare(i2c_dev->clk);
2355
2356 return 0;
2357 }
2358
stm32f7_i2c_runtime_resume(struct device * dev)2359 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
2360 {
2361 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2362 int ret;
2363
2364 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2365 ret = clk_prepare_enable(i2c_dev->clk);
2366 if (ret) {
2367 dev_err(dev, "failed to prepare_enable clock\n");
2368 return ret;
2369 }
2370 }
2371
2372 return 0;
2373 }
2374
stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev * i2c_dev)2375 static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
2376 {
2377 int ret;
2378 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2379
2380 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2381 if (ret < 0)
2382 return ret;
2383
2384 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2385 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2386 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2387 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
2388 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
2389 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2390
2391 pm_runtime_put_sync(i2c_dev->dev);
2392
2393 return ret;
2394 }
2395
stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev * i2c_dev)2396 static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
2397 {
2398 u32 cr1;
2399 int ret;
2400 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2401
2402 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2403 if (ret < 0)
2404 return ret;
2405
2406 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2407 if (cr1 & STM32F7_I2C_CR1_PE)
2408 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
2409 STM32F7_I2C_CR1_PE);
2410
2411 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2412 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2413 i2c_dev->base + STM32F7_I2C_CR1);
2414 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
2415 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
2416 STM32F7_I2C_CR1_PE);
2417 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2418 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2419 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
2420 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2421
2422 pm_runtime_put_sync(i2c_dev->dev);
2423
2424 return ret;
2425 }
2426
stm32f7_i2c_suspend(struct device * dev)2427 static int __maybe_unused stm32f7_i2c_suspend(struct device *dev)
2428 {
2429 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2430 int ret;
2431
2432 i2c_mark_adapter_suspended(&i2c_dev->adap);
2433
2434 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2435 ret = stm32f7_i2c_regs_backup(i2c_dev);
2436 if (ret < 0) {
2437 i2c_mark_adapter_resumed(&i2c_dev->adap);
2438 return ret;
2439 }
2440
2441 pinctrl_pm_select_sleep_state(dev);
2442 pm_runtime_force_suspend(dev);
2443 }
2444
2445 return 0;
2446 }
2447
stm32f7_i2c_resume(struct device * dev)2448 static int __maybe_unused stm32f7_i2c_resume(struct device *dev)
2449 {
2450 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2451 int ret;
2452
2453 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2454 ret = pm_runtime_force_resume(dev);
2455 if (ret < 0)
2456 return ret;
2457 pinctrl_pm_select_default_state(dev);
2458
2459 ret = stm32f7_i2c_regs_restore(i2c_dev);
2460 if (ret < 0)
2461 return ret;
2462 }
2463
2464 i2c_mark_adapter_resumed(&i2c_dev->adap);
2465
2466 return 0;
2467 }
2468
2469 static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2470 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2471 stm32f7_i2c_runtime_resume, NULL)
2472 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
2473 };
2474
2475 static const struct of_device_id stm32f7_i2c_match[] = {
2476 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2477 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
2478 { .compatible = "st,stm32mp13-i2c", .data = &stm32mp13_setup},
2479 {},
2480 };
2481 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2482
2483 static struct platform_driver stm32f7_i2c_driver = {
2484 .driver = {
2485 .name = "stm32f7-i2c",
2486 .of_match_table = stm32f7_i2c_match,
2487 .pm = &stm32f7_i2c_pm_ops,
2488 },
2489 .probe = stm32f7_i2c_probe,
2490 .remove_new = stm32f7_i2c_remove,
2491 };
2492
2493 module_platform_driver(stm32f7_i2c_driver);
2494
2495 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2496 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2497 MODULE_LICENSE("GPL v2");
2498
