Searched defs:irq_source (Results 1 – 9 of 9) sorted by relevance
85 enum dc_irq_source irq_source; member140 enum dc_irq_source irq_source; in remove_irq_handler() local263 static bool validate_irq_unregistration_params(enum dc_irq_source irq_source, in validate_irq_unregistration_params()310 enum dc_irq_source irq_source; in amdgpu_dm_irq_register_interrupt() local370 enum dc_irq_source irq_source, in amdgpu_dm_irq_unregister_interrupt()570 enum dc_irq_source irq_source) in amdgpu_dm_irq_schedule_work()624 enum dc_irq_source irq_source) in amdgpu_dm_irq_immediate_work()713 enum dc_irq_source irq_source; in dm_irq_state() local783 enum dc_irq_source irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX; in amdgpu_dm_set_dmub_outbox_irq_state() local809 enum dc_irq_source irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX0; in amdgpu_dm_set_dmub_trace_irq_state() local
76 enum dc_irq_source irq_source; in amdgpu_dm_crtc_set_vupdate_irq() local
1058 enum dc_irq_source irq_source; in dm_helpers_dmub_outbox_interrupt_control() local
2535 enum dc_irq_source irq_source; in dm_gpureset_toggle_interrupts() local
146 struct irq_source { struct147 uint32_t ivpr; /* IRQ vector/priority register */148 uint32_t idr; /* IRQ destination register */149 uint32_t destmask; /* bitmap of CPU destinations */150 int last_cpu;151 int output; /* IRQ level, e.g. ILR_INTTGT_INT */152 int pending; /* TRUE if IRQ is pending */153 enum irq_type type;154 bool level:1; /* level-triggered */155 bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */
208 enum dc_irq_source irq_source; member
1249 enum dc_irq_source irq_source; member
197 enum irq_source { enum205 int irq_source; member
472 struct amdgpu_irq_src irq_source; member