1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 *
5 * Multi-channel Audio Serial Port Driver
6 *
7 * Author: Nirmal Pandey <n-pandey@ti.com>,
8 * Suresh Rajashekara <suresh.r@ti.com>
9 * Steve Chen <schen@.mvista.com>
10 *
11 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
12 * Copyright: (C) 2009 Texas Instruments, India
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/device.h>
18 #include <linux/slab.h>
19 #include <linux/delay.h>
20 #include <linux/io.h>
21 #include <linux/clk.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/of.h>
24 #include <linux/of_platform.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_data/davinci_asp.h>
27 #include <linux/math64.h>
28 #include <linux/bitmap.h>
29 #include <linux/gpio/driver.h>
30
31 #include <sound/asoundef.h>
32 #include <sound/core.h>
33 #include <sound/pcm.h>
34 #include <sound/pcm_params.h>
35 #include <sound/initval.h>
36 #include <sound/soc.h>
37 #include <sound/dmaengine_pcm.h>
38
39 #include "edma-pcm.h"
40 #include "sdma-pcm.h"
41 #include "udma-pcm.h"
42 #include "davinci-mcasp.h"
43
44 #define MCASP_MAX_AFIFO_DEPTH 64
45
46 #ifdef CONFIG_PM
47 static u32 context_regs[] = {
48 DAVINCI_MCASP_TXFMCTL_REG,
49 DAVINCI_MCASP_RXFMCTL_REG,
50 DAVINCI_MCASP_TXFMT_REG,
51 DAVINCI_MCASP_RXFMT_REG,
52 DAVINCI_MCASP_ACLKXCTL_REG,
53 DAVINCI_MCASP_ACLKRCTL_REG,
54 DAVINCI_MCASP_AHCLKXCTL_REG,
55 DAVINCI_MCASP_AHCLKRCTL_REG,
56 DAVINCI_MCASP_PDIR_REG,
57 DAVINCI_MCASP_PFUNC_REG,
58 DAVINCI_MCASP_RXMASK_REG,
59 DAVINCI_MCASP_TXMASK_REG,
60 DAVINCI_MCASP_RXTDM_REG,
61 DAVINCI_MCASP_TXTDM_REG,
62 };
63
64 struct davinci_mcasp_context {
65 u32 config_regs[ARRAY_SIZE(context_regs)];
66 u32 afifo_regs[2]; /* for read/write fifo control registers */
67 u32 *xrsr_regs; /* for serializer configuration */
68 bool pm_state;
69 };
70 #endif
71
72 struct davinci_mcasp_ruledata {
73 struct davinci_mcasp *mcasp;
74 int serializers;
75 };
76
77 struct davinci_mcasp {
78 struct snd_dmaengine_dai_dma_data dma_data[2];
79 struct davinci_mcasp_pdata *pdata;
80 void __iomem *base;
81 u32 fifo_base;
82 struct device *dev;
83 struct snd_pcm_substream *substreams[2];
84 unsigned int dai_fmt;
85
86 u32 iec958_status;
87
88 /* Audio can not be enabled due to missing parameter(s) */
89 bool missing_audio_param;
90
91 /* McASP specific data */
92 int tdm_slots;
93 u32 tdm_mask[2];
94 int slot_width;
95 u8 op_mode;
96 u8 dismod;
97 u8 num_serializer;
98 u8 *serial_dir;
99 u8 version;
100 u8 bclk_div;
101 int streams;
102 u32 irq_request[2];
103
104 int sysclk_freq;
105 bool bclk_master;
106 u32 auxclk_fs_ratio;
107
108 unsigned long pdir; /* Pin direction bitfield */
109
110 /* McASP FIFO related */
111 u8 txnumevt;
112 u8 rxnumevt;
113
114 bool dat_port;
115
116 /* Used for comstraint setting on the second stream */
117 u32 channels;
118 int max_format_width;
119 u8 active_serializers[2];
120
121 #ifdef CONFIG_GPIOLIB
122 struct gpio_chip gpio_chip;
123 #endif
124
125 #ifdef CONFIG_PM
126 struct davinci_mcasp_context context;
127 #endif
128
129 struct davinci_mcasp_ruledata ruledata[2];
130 struct snd_pcm_hw_constraint_list chconstr[2];
131 };
132
mcasp_set_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val)133 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
134 u32 val)
135 {
136 void __iomem *reg = mcasp->base + offset;
137 __raw_writel(__raw_readl(reg) | val, reg);
138 }
139
mcasp_clr_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val)140 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
141 u32 val)
142 {
143 void __iomem *reg = mcasp->base + offset;
144 __raw_writel((__raw_readl(reg) & ~(val)), reg);
145 }
146
mcasp_mod_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val,u32 mask)147 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
148 u32 val, u32 mask)
149 {
150 void __iomem *reg = mcasp->base + offset;
151 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
152 }
153
mcasp_set_reg(struct davinci_mcasp * mcasp,u32 offset,u32 val)154 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
155 u32 val)
156 {
157 __raw_writel(val, mcasp->base + offset);
158 }
159
mcasp_get_reg(struct davinci_mcasp * mcasp,u32 offset)160 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
161 {
162 return (u32)__raw_readl(mcasp->base + offset);
163 }
164
mcasp_set_ctl_reg(struct davinci_mcasp * mcasp,u32 ctl_reg,u32 val)165 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
166 {
167 int i = 0;
168
169 mcasp_set_bits(mcasp, ctl_reg, val);
170
171 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
172 /* loop count is to avoid the lock-up */
173 for (i = 0; i < 1000; i++) {
174 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
175 break;
176 }
177
178 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
179 printk(KERN_ERR "GBLCTL write error\n");
180 }
181
mcasp_is_synchronous(struct davinci_mcasp * mcasp)182 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
183 {
184 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
185 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
186
187 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
188 }
189
mcasp_set_clk_pdir(struct davinci_mcasp * mcasp,bool enable)190 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
191 {
192 u32 bit = PIN_BIT_AMUTE;
193
194 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {
195 if (enable)
196 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
197 else
198 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
199 }
200 }
201
mcasp_set_axr_pdir(struct davinci_mcasp * mcasp,bool enable)202 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
203 {
204 u32 bit;
205
206 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) {
207 if (enable)
208 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
209 else
210 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
211 }
212 }
213
mcasp_start_rx(struct davinci_mcasp * mcasp)214 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
215 {
216 if (mcasp->rxnumevt) { /* enable FIFO */
217 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
218
219 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
220 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
221 }
222
223 /* Start clocks */
224 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
225 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
226 /*
227 * When ASYNC == 0 the transmit and receive sections operate
228 * synchronously from the transmit clock and frame sync. We need to make
229 * sure that the TX signlas are enabled when starting reception.
230 */
231 if (mcasp_is_synchronous(mcasp)) {
232 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
233 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
234 mcasp_set_clk_pdir(mcasp, true);
235 }
236
237 /* Activate serializer(s) */
238 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
239 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
240 /* Release RX state machine */
241 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
242 /* Release Frame Sync generator */
243 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
244 if (mcasp_is_synchronous(mcasp))
245 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
246
247 /* enable receive IRQs */
248 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
249 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
250 }
251
mcasp_start_tx(struct davinci_mcasp * mcasp)252 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
253 {
254 u32 cnt;
255
256 if (mcasp->txnumevt) { /* enable FIFO */
257 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
258
259 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
260 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
261 }
262
263 /* Start clocks */
264 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
265 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
266 mcasp_set_clk_pdir(mcasp, true);
267
268 /* Activate serializer(s) */
269 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
270 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
271
272 /* wait for XDATA to be cleared */
273 cnt = 0;
274 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
275 (cnt < 100000))
276 cnt++;
277
278 mcasp_set_axr_pdir(mcasp, true);
279
280 /* Release TX state machine */
281 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
282 /* Release Frame Sync generator */
283 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
284
285 /* enable transmit IRQs */
286 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
287 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
288 }
289
davinci_mcasp_start(struct davinci_mcasp * mcasp,int stream)290 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
291 {
292 mcasp->streams++;
293
294 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
295 mcasp_start_tx(mcasp);
296 else
297 mcasp_start_rx(mcasp);
298 }
299
mcasp_stop_rx(struct davinci_mcasp * mcasp)300 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
301 {
302 /* disable IRQ sources */
303 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
304 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
305
306 /*
307 * In synchronous mode stop the TX clocks if no other stream is
308 * running
309 */
310 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {
311 mcasp_set_clk_pdir(mcasp, false);
312 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
313 }
314
315 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
316 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
317
318 if (mcasp->rxnumevt) { /* disable FIFO */
319 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
320
321 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
322 }
323 }
324
mcasp_stop_tx(struct davinci_mcasp * mcasp)325 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
326 {
327 u32 val = 0;
328
329 /* disable IRQ sources */
330 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
331 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
332
333 /*
334 * In synchronous mode keep TX clocks running if the capture stream is
335 * still running.
336 */
337 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
338 val = TXHCLKRST | TXCLKRST | TXFSRST;
339 else
340 mcasp_set_clk_pdir(mcasp, false);
341
342
343 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
344 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
345
346 if (mcasp->txnumevt) { /* disable FIFO */
347 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
348
349 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
350 }
351
352 mcasp_set_axr_pdir(mcasp, false);
353 }
354
davinci_mcasp_stop(struct davinci_mcasp * mcasp,int stream)355 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
356 {
357 mcasp->streams--;
358
359 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
360 mcasp_stop_tx(mcasp);
361 else
362 mcasp_stop_rx(mcasp);
363 }
364
davinci_mcasp_tx_irq_handler(int irq,void * data)365 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
366 {
367 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
368 struct snd_pcm_substream *substream;
369 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
370 u32 handled_mask = 0;
371 u32 stat;
372
373 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
374 if (stat & XUNDRN & irq_mask) {
375 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
376 handled_mask |= XUNDRN;
377
378 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
379 if (substream)
380 snd_pcm_stop_xrun(substream);
381 }
382
383 if (!handled_mask)
384 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
385 stat);
386
387 if (stat & XRERR)
388 handled_mask |= XRERR;
389
390 /* Ack the handled event only */
391 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
392
393 return IRQ_RETVAL(handled_mask);
394 }
395
davinci_mcasp_rx_irq_handler(int irq,void * data)396 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
397 {
398 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
399 struct snd_pcm_substream *substream;
400 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
401 u32 handled_mask = 0;
402 u32 stat;
403
404 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
405 if (stat & ROVRN & irq_mask) {
406 dev_warn(mcasp->dev, "Receive buffer overflow\n");
407 handled_mask |= ROVRN;
408
409 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
410 if (substream)
411 snd_pcm_stop_xrun(substream);
412 }
413
414 if (!handled_mask)
415 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
416 stat);
417
418 if (stat & XRERR)
419 handled_mask |= XRERR;
420
421 /* Ack the handled event only */
422 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
423
424 return IRQ_RETVAL(handled_mask);
425 }
426
davinci_mcasp_common_irq_handler(int irq,void * data)427 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
428 {
429 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
430 irqreturn_t ret = IRQ_NONE;
431
432 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
433 ret = davinci_mcasp_tx_irq_handler(irq, data);
434
435 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
436 ret |= davinci_mcasp_rx_irq_handler(irq, data);
437
438 return ret;
439 }
440
davinci_mcasp_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)441 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
442 unsigned int fmt)
443 {
444 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
445 int ret = 0;
446 u32 data_delay;
447 bool fs_pol_rising;
448 bool inv_fs = false;
449
450 if (!fmt)
451 return 0;
452
453 pm_runtime_get_sync(mcasp->dev);
454 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
455 case SND_SOC_DAIFMT_DSP_A:
456 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
457 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
458 /* 1st data bit occur one ACLK cycle after the frame sync */
459 data_delay = 1;
460 break;
461 case SND_SOC_DAIFMT_DSP_B:
462 case SND_SOC_DAIFMT_AC97:
463 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
464 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
465 /* No delay after FS */
466 data_delay = 0;
467 break;
468 case SND_SOC_DAIFMT_I2S:
469 /* configure a full-word SYNC pulse (LRCLK) */
470 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
471 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
472 /* 1st data bit occur one ACLK cycle after the frame sync */
473 data_delay = 1;
474 /* FS need to be inverted */
475 inv_fs = true;
476 break;
477 case SND_SOC_DAIFMT_RIGHT_J:
478 case SND_SOC_DAIFMT_LEFT_J:
479 /* configure a full-word SYNC pulse (LRCLK) */
480 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
481 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
482 /* No delay after FS */
483 data_delay = 0;
484 break;
485 default:
486 ret = -EINVAL;
487 goto out;
488 }
489
490 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
491 FSXDLY(3));
492 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
493 FSRDLY(3));
494
495 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
496 case SND_SOC_DAIFMT_BP_FP:
497 /* codec is clock and frame slave */
498 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
499 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
500
501 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
502 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
503
504 /* BCLK */
505 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
506 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
507 /* Frame Sync */
508 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
509 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
510
511 mcasp->bclk_master = 1;
512 break;
513 case SND_SOC_DAIFMT_BP_FC:
514 /* codec is clock slave and frame master */
515 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
516 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
517
518 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
519 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
520
521 /* BCLK */
522 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
523 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
524 /* Frame Sync */
525 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
526 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
527
528 mcasp->bclk_master = 1;
529 break;
530 case SND_SOC_DAIFMT_BC_FP:
531 /* codec is clock master and frame slave */
532 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
533 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
534
535 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
536 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
537
538 /* BCLK */
539 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
540 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
541 /* Frame Sync */
542 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
543 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
544
545 mcasp->bclk_master = 0;
546 break;
547 case SND_SOC_DAIFMT_BC_FC:
548 /* codec is clock and frame master */
549 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
550 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
551
552 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
553 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
554
555 /* BCLK */
556 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
557 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
558 /* Frame Sync */
559 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
560 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
561
562 mcasp->bclk_master = 0;
563 break;
564 default:
565 ret = -EINVAL;
566 goto out;
567 }
568
569 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
570 case SND_SOC_DAIFMT_IB_NF:
571 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
572 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
573 fs_pol_rising = true;
574 break;
575 case SND_SOC_DAIFMT_NB_IF:
576 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
577 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
578 fs_pol_rising = false;
579 break;
580 case SND_SOC_DAIFMT_IB_IF:
581 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
582 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
583 fs_pol_rising = false;
584 break;
585 case SND_SOC_DAIFMT_NB_NF:
586 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
587 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
588 fs_pol_rising = true;
589 break;
590 default:
591 ret = -EINVAL;
592 goto out;
593 }
594
595 if (inv_fs)
596 fs_pol_rising = !fs_pol_rising;
597
598 if (fs_pol_rising) {
599 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
600 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
601 } else {
602 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
603 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
604 }
605
606 mcasp->dai_fmt = fmt;
607 out:
608 pm_runtime_put(mcasp->dev);
609 return ret;
610 }
611
__davinci_mcasp_set_clkdiv(struct davinci_mcasp * mcasp,int div_id,int div,bool explicit)612 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
613 int div, bool explicit)
614 {
615 pm_runtime_get_sync(mcasp->dev);
616 switch (div_id) {
617 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
618 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
619 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
620 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
621 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
622 break;
623
624 case MCASP_CLKDIV_BCLK: /* BCLK divider */
625 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
626 ACLKXDIV(div - 1), ACLKXDIV_MASK);
627 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
628 ACLKRDIV(div - 1), ACLKRDIV_MASK);
629 if (explicit)
630 mcasp->bclk_div = div;
631 break;
632
633 case MCASP_CLKDIV_BCLK_FS_RATIO:
634 /*
635 * BCLK/LRCLK ratio descries how many bit-clock cycles
636 * fit into one frame. The clock ratio is given for a
637 * full period of data (for I2S format both left and
638 * right channels), so it has to be divided by number
639 * of tdm-slots (for I2S - divided by 2).
640 * Instead of storing this ratio, we calculate a new
641 * tdm_slot width by dividing the ratio by the
642 * number of configured tdm slots.
643 */
644 mcasp->slot_width = div / mcasp->tdm_slots;
645 if (div % mcasp->tdm_slots)
646 dev_warn(mcasp->dev,
647 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
648 __func__, div, mcasp->tdm_slots);
649 break;
650
651 default:
652 return -EINVAL;
653 }
654
655 pm_runtime_put(mcasp->dev);
656 return 0;
657 }
658
davinci_mcasp_set_clkdiv(struct snd_soc_dai * dai,int div_id,int div)659 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
660 int div)
661 {
662 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
663
664 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
665 }
666
davinci_mcasp_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)667 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
668 unsigned int freq, int dir)
669 {
670 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
671
672 pm_runtime_get_sync(mcasp->dev);
673
674 if (dir == SND_SOC_CLOCK_IN) {
675 switch (clk_id) {
676 case MCASP_CLK_HCLK_AHCLK:
677 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
678 AHCLKXE);
679 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
680 AHCLKRE);
681 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
682 break;
683 case MCASP_CLK_HCLK_AUXCLK:
684 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
685 AHCLKXE);
686 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
687 AHCLKRE);
688 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
689 break;
690 default:
691 dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id);
692 goto out;
693 }
694 } else {
695 /* Select AUXCLK as HCLK */
696 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
697 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
698 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
699 }
700 /*
701 * When AHCLK X/R is selected to be output it means that the HCLK is
702 * the same clock - coming via AUXCLK.
703 */
704 mcasp->sysclk_freq = freq;
705 out:
706 pm_runtime_put(mcasp->dev);
707 return 0;
708 }
709
710 /* All serializers must have equal number of channels */
davinci_mcasp_ch_constraint(struct davinci_mcasp * mcasp,int stream,int serializers)711 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
712 int serializers)
713 {
714 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
715 unsigned int *list = (unsigned int *) cl->list;
716 int slots = mcasp->tdm_slots;
717 int i, count = 0;
718
719 if (mcasp->tdm_mask[stream])
720 slots = hweight32(mcasp->tdm_mask[stream]);
721
722 for (i = 1; i <= slots; i++)
723 list[count++] = i;
724
725 for (i = 2; i <= serializers; i++)
726 list[count++] = i*slots;
727
728 cl->count = count;
729
730 return 0;
731 }
732
davinci_mcasp_set_ch_constraints(struct davinci_mcasp * mcasp)733 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
734 {
735 int rx_serializers = 0, tx_serializers = 0, ret, i;
736
737 for (i = 0; i < mcasp->num_serializer; i++)
738 if (mcasp->serial_dir[i] == TX_MODE)
739 tx_serializers++;
740 else if (mcasp->serial_dir[i] == RX_MODE)
741 rx_serializers++;
742
743 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
744 tx_serializers);
745 if (ret)
746 return ret;
747
748 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
749 rx_serializers);
750
751 return ret;
752 }
753
754
davinci_mcasp_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)755 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
756 unsigned int tx_mask,
757 unsigned int rx_mask,
758 int slots, int slot_width)
759 {
760 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
761
762 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
763 return 0;
764
765 dev_dbg(mcasp->dev,
766 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
767 __func__, tx_mask, rx_mask, slots, slot_width);
768
769 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
770 dev_err(mcasp->dev,
771 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
772 tx_mask, rx_mask, slots);
773 return -EINVAL;
774 }
775
776 if (slot_width &&
777 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
778 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
779 __func__, slot_width);
780 return -EINVAL;
781 }
782
783 mcasp->tdm_slots = slots;
784 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
785 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
786 mcasp->slot_width = slot_width;
787
788 return davinci_mcasp_set_ch_constraints(mcasp);
789 }
790
davinci_config_channel_size(struct davinci_mcasp * mcasp,int sample_width)791 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
792 int sample_width)
793 {
794 u32 fmt;
795 u32 tx_rotate, rx_rotate, slot_width;
796 u32 mask = (1ULL << sample_width) - 1;
797
798 if (mcasp->slot_width)
799 slot_width = mcasp->slot_width;
800 else if (mcasp->max_format_width)
801 slot_width = mcasp->max_format_width;
802 else
803 slot_width = sample_width;
804 /*
805 * TX rotation:
806 * right aligned formats: rotate w/ slot_width
807 * left aligned formats: rotate w/ sample_width
808 *
809 * RX rotation:
810 * right aligned formats: no rotation needed
811 * left aligned formats: rotate w/ (slot_width - sample_width)
812 */
813 if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
814 SND_SOC_DAIFMT_RIGHT_J) {
815 tx_rotate = (slot_width / 4) & 0x7;
816 rx_rotate = 0;
817 } else {
818 tx_rotate = (sample_width / 4) & 0x7;
819 rx_rotate = (slot_width - sample_width) / 4;
820 }
821
822 /* mapping of the XSSZ bit-field as described in the datasheet */
823 fmt = (slot_width >> 1) - 1;
824
825 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
826 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
827 RXSSZ(0x0F));
828 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
829 TXSSZ(0x0F));
830 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
831 TXROT(7));
832 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
833 RXROT(7));
834 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
835 } else {
836 /*
837 * according to the TRM it should be TXROT=0, this one works:
838 * 16 bit to 23-8 (TXROT=6, rotate 24 bits)
839 * 24 bit to 23-0 (TXROT=0, rotate 0 bits)
840 *
841 * TXROT = 0 only works with 24bit samples
842 */
843 tx_rotate = (sample_width / 4 + 2) & 0x7;
844
845 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
846 TXROT(7));
847 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(15),
848 TXSSZ(0x0F));
849 }
850
851 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
852
853 return 0;
854 }
855
mcasp_common_hw_param(struct davinci_mcasp * mcasp,int stream,int period_words,int channels)856 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
857 int period_words, int channels)
858 {
859 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
860 int i;
861 u8 tx_ser = 0;
862 u8 rx_ser = 0;
863 u8 slots = mcasp->tdm_slots;
864 u8 max_active_serializers, max_rx_serializers, max_tx_serializers;
865 int active_serializers, numevt;
866 u32 reg;
867
868 /* In DIT mode we only allow maximum of one serializers for now */
869 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
870 max_active_serializers = 1;
871 else
872 max_active_serializers = DIV_ROUND_UP(channels, slots);
873
874 /* Default configuration */
875 if (mcasp->version < MCASP_VERSION_3)
876 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
877
878 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
879 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
880 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
881 max_tx_serializers = max_active_serializers;
882 max_rx_serializers =
883 mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE];
884 } else {
885 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
886 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
887 max_tx_serializers =
888 mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK];
889 max_rx_serializers = max_active_serializers;
890 }
891
892 for (i = 0; i < mcasp->num_serializer; i++) {
893 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
894 mcasp->serial_dir[i]);
895 if (mcasp->serial_dir[i] == TX_MODE &&
896 tx_ser < max_tx_serializers) {
897 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
898 mcasp->dismod, DISMOD_MASK);
899 set_bit(PIN_BIT_AXR(i), &mcasp->pdir);
900 tx_ser++;
901 } else if (mcasp->serial_dir[i] == RX_MODE &&
902 rx_ser < max_rx_serializers) {
903 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
904 rx_ser++;
905 } else {
906 /* Inactive or unused pin, set it to inactive */
907 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
908 SRMOD_INACTIVE, SRMOD_MASK);
909 /* If unused, set DISMOD for the pin */
910 if (mcasp->serial_dir[i] != INACTIVE_MODE)
911 mcasp_mod_bits(mcasp,
912 DAVINCI_MCASP_XRSRCTL_REG(i),
913 mcasp->dismod, DISMOD_MASK);
914 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
915 }
916 }
917
918 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
919 active_serializers = tx_ser;
920 numevt = mcasp->txnumevt;
921 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
922 } else {
923 active_serializers = rx_ser;
924 numevt = mcasp->rxnumevt;
925 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
926 }
927
928 if (active_serializers < max_active_serializers) {
929 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
930 "enabled in mcasp (%d)\n", channels,
931 active_serializers * slots);
932 return -EINVAL;
933 }
934
935 /* AFIFO is not in use */
936 if (!numevt) {
937 /* Configure the burst size for platform drivers */
938 if (active_serializers > 1) {
939 /*
940 * If more than one serializers are in use we have one
941 * DMA request to provide data for all serializers.
942 * For example if three serializers are enabled the DMA
943 * need to transfer three words per DMA request.
944 */
945 dma_data->maxburst = active_serializers;
946 } else {
947 dma_data->maxburst = 0;
948 }
949
950 goto out;
951 }
952
953 if (period_words % active_serializers) {
954 dev_err(mcasp->dev, "Invalid combination of period words and "
955 "active serializers: %d, %d\n", period_words,
956 active_serializers);
957 return -EINVAL;
958 }
959
960 /*
961 * Calculate the optimal AFIFO depth for platform side:
962 * The number of words for numevt need to be in steps of active
963 * serializers.
964 */
965 numevt = (numevt / active_serializers) * active_serializers;
966
967 while (period_words % numevt && numevt > 0)
968 numevt -= active_serializers;
969 if (numevt <= 0)
970 numevt = active_serializers;
971
972 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
973 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
974
975 /* Configure the burst size for platform drivers */
976 if (numevt == 1)
977 numevt = 0;
978 dma_data->maxburst = numevt;
979
980 out:
981 mcasp->active_serializers[stream] = active_serializers;
982
983 return 0;
984 }
985
mcasp_i2s_hw_param(struct davinci_mcasp * mcasp,int stream,int channels)986 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
987 int channels)
988 {
989 int i, active_slots;
990 int total_slots;
991 int active_serializers;
992 u32 mask = 0;
993 u32 busel = 0;
994
995 total_slots = mcasp->tdm_slots;
996
997 /*
998 * If more than one serializer is needed, then use them with
999 * all the specified tdm_slots. Otherwise, one serializer can
1000 * cope with the transaction using just as many slots as there
1001 * are channels in the stream.
1002 */
1003 if (mcasp->tdm_mask[stream]) {
1004 active_slots = hweight32(mcasp->tdm_mask[stream]);
1005 active_serializers = DIV_ROUND_UP(channels, active_slots);
1006 if (active_serializers == 1)
1007 active_slots = channels;
1008 for (i = 0; i < total_slots; i++) {
1009 if ((1 << i) & mcasp->tdm_mask[stream]) {
1010 mask |= (1 << i);
1011 if (--active_slots <= 0)
1012 break;
1013 }
1014 }
1015 } else {
1016 active_serializers = DIV_ROUND_UP(channels, total_slots);
1017 if (active_serializers == 1)
1018 active_slots = channels;
1019 else
1020 active_slots = total_slots;
1021
1022 for (i = 0; i < active_slots; i++)
1023 mask |= (1 << i);
1024 }
1025
1026 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
1027
1028 if (!mcasp->dat_port)
1029 busel = TXSEL;
1030
1031 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1032 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
1033 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
1034 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
1035 FSXMOD(total_slots), FSXMOD(0x1FF));
1036 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
1037 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
1038 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
1039 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
1040 FSRMOD(total_slots), FSRMOD(0x1FF));
1041 /*
1042 * If McASP is set to be TX/RX synchronous and the playback is
1043 * not running already we need to configure the TX slots in
1044 * order to have correct FSX on the bus
1045 */
1046 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
1047 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
1048 FSXMOD(total_slots), FSXMOD(0x1FF));
1049 }
1050
1051 return 0;
1052 }
1053
1054 /* S/PDIF */
mcasp_dit_hw_param(struct davinci_mcasp * mcasp,unsigned int rate)1055 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
1056 unsigned int rate)
1057 {
1058 u8 *cs_bytes = (u8 *)&mcasp->iec958_status;
1059
1060 if (!mcasp->dat_port)
1061 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL);
1062 else
1063 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL);
1064
1065 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
1066 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
1067
1068 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, 0xFFFF);
1069
1070 /* Set the TX tdm : for all the slots */
1071 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
1072
1073 /* Set the TX clock controls : div = 1 and internal */
1074 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
1075
1076 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
1077
1078 /* Set S/PDIF channel status bits */
1079 cs_bytes[3] &= ~IEC958_AES3_CON_FS;
1080 switch (rate) {
1081 case 22050:
1082 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
1083 break;
1084 case 24000:
1085 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
1086 break;
1087 case 32000:
1088 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
1089 break;
1090 case 44100:
1091 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
1092 break;
1093 case 48000:
1094 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
1095 break;
1096 case 88200:
1097 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
1098 break;
1099 case 96000:
1100 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
1101 break;
1102 case 176400:
1103 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
1104 break;
1105 case 192000:
1106 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
1107 break;
1108 default:
1109 dev_err(mcasp->dev, "unsupported sampling rate: %d\n", rate);
1110 return -EINVAL;
1111 }
1112
1113 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, mcasp->iec958_status);
1114 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, mcasp->iec958_status);
1115
1116 /* Enable the DIT */
1117 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
1118
1119 return 0;
1120 }
1121
davinci_mcasp_calc_clk_div(struct davinci_mcasp * mcasp,unsigned int sysclk_freq,unsigned int bclk_freq,bool set)1122 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
1123 unsigned int sysclk_freq,
1124 unsigned int bclk_freq, bool set)
1125 {
1126 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1127 int div = sysclk_freq / bclk_freq;
1128 int rem = sysclk_freq % bclk_freq;
1129 int error_ppm;
1130 int aux_div = 1;
1131
1132 if (div > (ACLKXDIV_MASK + 1)) {
1133 if (reg & AHCLKXE) {
1134 aux_div = div / (ACLKXDIV_MASK + 1);
1135 if (div % (ACLKXDIV_MASK + 1))
1136 aux_div++;
1137
1138 sysclk_freq /= aux_div;
1139 div = sysclk_freq / bclk_freq;
1140 rem = sysclk_freq % bclk_freq;
1141 } else if (set) {
1142 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1143 sysclk_freq);
1144 }
1145 }
1146
1147 if (rem != 0) {
1148 if (div == 0 ||
1149 ((sysclk_freq / div) - bclk_freq) >
1150 (bclk_freq - (sysclk_freq / (div+1)))) {
1151 div++;
1152 rem = rem - bclk_freq;
1153 }
1154 }
1155 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1156 (int)bclk_freq)) / div - 1000000;
1157
1158 if (set) {
1159 if (error_ppm)
1160 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1161 error_ppm);
1162
1163 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1164 if (reg & AHCLKXE)
1165 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1166 aux_div, 0);
1167 }
1168
1169 return error_ppm;
1170 }
1171
davinci_mcasp_tx_delay(struct davinci_mcasp * mcasp)1172 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)
1173 {
1174 if (!mcasp->txnumevt)
1175 return 0;
1176
1177 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);
1178 }
1179
davinci_mcasp_rx_delay(struct davinci_mcasp * mcasp)1180 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)
1181 {
1182 if (!mcasp->rxnumevt)
1183 return 0;
1184
1185 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);
1186 }
1187
davinci_mcasp_delay(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)1188 static snd_pcm_sframes_t davinci_mcasp_delay(
1189 struct snd_pcm_substream *substream,
1190 struct snd_soc_dai *cpu_dai)
1191 {
1192 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1193 u32 fifo_use;
1194
1195 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1196 fifo_use = davinci_mcasp_tx_delay(mcasp);
1197 else
1198 fifo_use = davinci_mcasp_rx_delay(mcasp);
1199
1200 /*
1201 * Divide the used locations with the channel count to get the
1202 * FIFO usage in samples (don't care about partial samples in the
1203 * buffer).
1204 */
1205 return fifo_use / substream->runtime->channels;
1206 }
1207
davinci_mcasp_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)1208 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1209 struct snd_pcm_hw_params *params,
1210 struct snd_soc_dai *cpu_dai)
1211 {
1212 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1213 int word_length;
1214 int channels = params_channels(params);
1215 int period_size = params_period_size(params);
1216 int ret;
1217
1218 switch (params_format(params)) {
1219 case SNDRV_PCM_FORMAT_U8:
1220 case SNDRV_PCM_FORMAT_S8:
1221 word_length = 8;
1222 break;
1223
1224 case SNDRV_PCM_FORMAT_U16_LE:
1225 case SNDRV_PCM_FORMAT_S16_LE:
1226 word_length = 16;
1227 break;
1228
1229 case SNDRV_PCM_FORMAT_U24_3LE:
1230 case SNDRV_PCM_FORMAT_S24_3LE:
1231 word_length = 24;
1232 break;
1233
1234 case SNDRV_PCM_FORMAT_U24_LE:
1235 case SNDRV_PCM_FORMAT_S24_LE:
1236 word_length = 24;
1237 break;
1238
1239 case SNDRV_PCM_FORMAT_U32_LE:
1240 case SNDRV_PCM_FORMAT_S32_LE:
1241 word_length = 32;
1242 break;
1243
1244 default:
1245 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1246 return -EINVAL;
1247 }
1248
1249 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1250 if (ret)
1251 return ret;
1252
1253 /*
1254 * If mcasp is BCLK master, and a BCLK divider was not provided by
1255 * the machine driver, we need to calculate the ratio.
1256 */
1257 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1258 int slots = mcasp->tdm_slots;
1259 int rate = params_rate(params);
1260 int sbits = params_width(params);
1261 unsigned int bclk_target;
1262
1263 if (mcasp->slot_width)
1264 sbits = mcasp->slot_width;
1265
1266 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1267 bclk_target = rate * sbits * slots;
1268 else
1269 bclk_target = rate * 128;
1270
1271 davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq,
1272 bclk_target, true);
1273 }
1274
1275 ret = mcasp_common_hw_param(mcasp, substream->stream,
1276 period_size * channels, channels);
1277 if (ret)
1278 return ret;
1279
1280 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1281 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1282 else
1283 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1284 channels);
1285
1286 if (ret)
1287 return ret;
1288
1289 davinci_config_channel_size(mcasp, word_length);
1290
1291 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1292 mcasp->channels = channels;
1293 if (!mcasp->max_format_width)
1294 mcasp->max_format_width = word_length;
1295 }
1296
1297 return 0;
1298 }
1299
davinci_mcasp_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)1300 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1301 int cmd, struct snd_soc_dai *cpu_dai)
1302 {
1303 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1304 int ret = 0;
1305
1306 switch (cmd) {
1307 case SNDRV_PCM_TRIGGER_RESUME:
1308 case SNDRV_PCM_TRIGGER_START:
1309 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1310 davinci_mcasp_start(mcasp, substream->stream);
1311 break;
1312 case SNDRV_PCM_TRIGGER_SUSPEND:
1313 case SNDRV_PCM_TRIGGER_STOP:
1314 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1315 davinci_mcasp_stop(mcasp, substream->stream);
1316 break;
1317
1318 default:
1319 ret = -EINVAL;
1320 }
1321
1322 return ret;
1323 }
1324
davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1325 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
1326 struct snd_pcm_hw_rule *rule)
1327 {
1328 struct davinci_mcasp_ruledata *rd = rule->private;
1329 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1330 struct snd_mask nfmt;
1331 int slot_width;
1332 snd_pcm_format_t i;
1333
1334 snd_mask_none(&nfmt);
1335 slot_width = rd->mcasp->slot_width;
1336
1337 pcm_for_each_format(i) {
1338 if (snd_mask_test_format(fmt, i)) {
1339 if (snd_pcm_format_width(i) <= slot_width) {
1340 snd_mask_set_format(&nfmt, i);
1341 }
1342 }
1343 }
1344
1345 return snd_mask_refine(fmt, &nfmt);
1346 }
1347
davinci_mcasp_hw_rule_format_width(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1348 static int davinci_mcasp_hw_rule_format_width(struct snd_pcm_hw_params *params,
1349 struct snd_pcm_hw_rule *rule)
1350 {
1351 struct davinci_mcasp_ruledata *rd = rule->private;
1352 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1353 struct snd_mask nfmt;
1354 int format_width;
1355 snd_pcm_format_t i;
1356
1357 snd_mask_none(&nfmt);
1358 format_width = rd->mcasp->max_format_width;
1359
1360 pcm_for_each_format(i) {
1361 if (snd_mask_test_format(fmt, i)) {
1362 if (snd_pcm_format_width(i) == format_width) {
1363 snd_mask_set_format(&nfmt, i);
1364 }
1365 }
1366 }
1367
1368 return snd_mask_refine(fmt, &nfmt);
1369 }
1370
1371 static const unsigned int davinci_mcasp_dai_rates[] = {
1372 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1373 88200, 96000, 176400, 192000,
1374 };
1375
1376 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1377
davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1378 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1379 struct snd_pcm_hw_rule *rule)
1380 {
1381 struct davinci_mcasp_ruledata *rd = rule->private;
1382 struct snd_interval *ri =
1383 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1384 int sbits = params_width(params);
1385 int slots = rd->mcasp->tdm_slots;
1386 struct snd_interval range;
1387 int i;
1388
1389 if (rd->mcasp->slot_width)
1390 sbits = rd->mcasp->slot_width;
1391
1392 snd_interval_any(&range);
1393 range.empty = 1;
1394
1395 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1396 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1397 uint bclk_freq = sbits * slots *
1398 davinci_mcasp_dai_rates[i];
1399 unsigned int sysclk_freq;
1400 int ppm;
1401
1402 if (rd->mcasp->auxclk_fs_ratio)
1403 sysclk_freq = davinci_mcasp_dai_rates[i] *
1404 rd->mcasp->auxclk_fs_ratio;
1405 else
1406 sysclk_freq = rd->mcasp->sysclk_freq;
1407
1408 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1409 bclk_freq, false);
1410 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1411 if (range.empty) {
1412 range.min = davinci_mcasp_dai_rates[i];
1413 range.empty = 0;
1414 }
1415 range.max = davinci_mcasp_dai_rates[i];
1416 }
1417 }
1418 }
1419
1420 dev_dbg(rd->mcasp->dev,
1421 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1422 ri->min, ri->max, range.min, range.max, sbits, slots);
1423
1424 return snd_interval_refine(hw_param_interval(params, rule->var),
1425 &range);
1426 }
1427
davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1428 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1429 struct snd_pcm_hw_rule *rule)
1430 {
1431 struct davinci_mcasp_ruledata *rd = rule->private;
1432 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1433 struct snd_mask nfmt;
1434 int rate = params_rate(params);
1435 int slots = rd->mcasp->tdm_slots;
1436 int count = 0;
1437 snd_pcm_format_t i;
1438
1439 snd_mask_none(&nfmt);
1440
1441 pcm_for_each_format(i) {
1442 if (snd_mask_test_format(fmt, i)) {
1443 uint sbits = snd_pcm_format_width(i);
1444 unsigned int sysclk_freq;
1445 int ppm;
1446
1447 if (rd->mcasp->auxclk_fs_ratio)
1448 sysclk_freq = rate *
1449 rd->mcasp->auxclk_fs_ratio;
1450 else
1451 sysclk_freq = rd->mcasp->sysclk_freq;
1452
1453 if (rd->mcasp->slot_width)
1454 sbits = rd->mcasp->slot_width;
1455
1456 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1457 sbits * slots * rate,
1458 false);
1459 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1460 snd_mask_set_format(&nfmt, i);
1461 count++;
1462 }
1463 }
1464 }
1465 dev_dbg(rd->mcasp->dev,
1466 "%d possible sample format for %d Hz and %d tdm slots\n",
1467 count, rate, slots);
1468
1469 return snd_mask_refine(fmt, &nfmt);
1470 }
1471
davinci_mcasp_hw_rule_min_periodsize(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1472 static int davinci_mcasp_hw_rule_min_periodsize(
1473 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
1474 {
1475 struct snd_interval *period_size = hw_param_interval(params,
1476 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1477 struct snd_interval frames;
1478
1479 snd_interval_any(&frames);
1480 frames.min = 64;
1481 frames.integer = 1;
1482
1483 return snd_interval_refine(period_size, &frames);
1484 }
1485
davinci_mcasp_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)1486 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1487 struct snd_soc_dai *cpu_dai)
1488 {
1489 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1490 struct davinci_mcasp_ruledata *ruledata =
1491 &mcasp->ruledata[substream->stream];
1492 u32 max_channels = 0;
1493 int i, dir, ret;
1494 int tdm_slots = mcasp->tdm_slots;
1495
1496 /* Do not allow more then one stream per direction */
1497 if (mcasp->substreams[substream->stream])
1498 return -EBUSY;
1499
1500 mcasp->substreams[substream->stream] = substream;
1501
1502 if (mcasp->tdm_mask[substream->stream])
1503 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1504
1505 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1506 return 0;
1507
1508 /*
1509 * Limit the maximum allowed channels for the first stream:
1510 * number of serializers for the direction * tdm slots per serializer
1511 */
1512 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1513 dir = TX_MODE;
1514 else
1515 dir = RX_MODE;
1516
1517 for (i = 0; i < mcasp->num_serializer; i++) {
1518 if (mcasp->serial_dir[i] == dir)
1519 max_channels++;
1520 }
1521 ruledata->serializers = max_channels;
1522 ruledata->mcasp = mcasp;
1523 max_channels *= tdm_slots;
1524 /*
1525 * If the already active stream has less channels than the calculated
1526 * limit based on the seirializers * tdm_slots, and only one serializer
1527 * is in use we need to use that as a constraint for the second stream.
1528 * Otherwise (first stream or less allowed channels or more than one
1529 * serializer in use) we use the calculated constraint.
1530 */
1531 if (mcasp->channels && mcasp->channels < max_channels &&
1532 ruledata->serializers == 1)
1533 max_channels = mcasp->channels;
1534 /*
1535 * But we can always allow channels upto the amount of
1536 * the available tdm_slots.
1537 */
1538 if (max_channels < tdm_slots)
1539 max_channels = tdm_slots;
1540
1541 snd_pcm_hw_constraint_minmax(substream->runtime,
1542 SNDRV_PCM_HW_PARAM_CHANNELS,
1543 0, max_channels);
1544
1545 snd_pcm_hw_constraint_list(substream->runtime,
1546 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1547 &mcasp->chconstr[substream->stream]);
1548
1549 if (mcasp->max_format_width) {
1550 /*
1551 * Only allow formats which require same amount of bits on the
1552 * bus as the currently running stream
1553 */
1554 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1555 SNDRV_PCM_HW_PARAM_FORMAT,
1556 davinci_mcasp_hw_rule_format_width,
1557 ruledata,
1558 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1559 if (ret)
1560 return ret;
1561 }
1562 else if (mcasp->slot_width) {
1563 /* Only allow formats require <= slot_width bits on the bus */
1564 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1565 SNDRV_PCM_HW_PARAM_FORMAT,
1566 davinci_mcasp_hw_rule_slot_width,
1567 ruledata,
1568 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1569 if (ret)
1570 return ret;
1571 }
1572
1573 /*
1574 * If we rely on implicit BCLK divider setting we should
1575 * set constraints based on what we can provide.
1576 */
1577 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1578 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1579 SNDRV_PCM_HW_PARAM_RATE,
1580 davinci_mcasp_hw_rule_rate,
1581 ruledata,
1582 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1583 if (ret)
1584 return ret;
1585 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1586 SNDRV_PCM_HW_PARAM_FORMAT,
1587 davinci_mcasp_hw_rule_format,
1588 ruledata,
1589 SNDRV_PCM_HW_PARAM_RATE, -1);
1590 if (ret)
1591 return ret;
1592 }
1593
1594 snd_pcm_hw_rule_add(substream->runtime, 0,
1595 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1596 davinci_mcasp_hw_rule_min_periodsize, NULL,
1597 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
1598
1599 return 0;
1600 }
1601
davinci_mcasp_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)1602 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1603 struct snd_soc_dai *cpu_dai)
1604 {
1605 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1606
1607 mcasp->substreams[substream->stream] = NULL;
1608 mcasp->active_serializers[substream->stream] = 0;
1609
1610 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1611 return;
1612
1613 if (!snd_soc_dai_active(cpu_dai)) {
1614 mcasp->channels = 0;
1615 mcasp->max_format_width = 0;
1616 }
1617 }
1618
davinci_mcasp_iec958_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1619 static int davinci_mcasp_iec958_info(struct snd_kcontrol *kcontrol,
1620 struct snd_ctl_elem_info *uinfo)
1621 {
1622 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1623 uinfo->count = 1;
1624
1625 return 0;
1626 }
1627
davinci_mcasp_iec958_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uctl)1628 static int davinci_mcasp_iec958_get(struct snd_kcontrol *kcontrol,
1629 struct snd_ctl_elem_value *uctl)
1630 {
1631 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
1632 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1633
1634 memcpy(uctl->value.iec958.status, &mcasp->iec958_status,
1635 sizeof(mcasp->iec958_status));
1636
1637 return 0;
1638 }
1639
davinci_mcasp_iec958_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uctl)1640 static int davinci_mcasp_iec958_put(struct snd_kcontrol *kcontrol,
1641 struct snd_ctl_elem_value *uctl)
1642 {
1643 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
1644 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1645
1646 memcpy(&mcasp->iec958_status, uctl->value.iec958.status,
1647 sizeof(mcasp->iec958_status));
1648
1649 return 0;
1650 }
1651
davinci_mcasp_iec958_con_mask_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1652 static int davinci_mcasp_iec958_con_mask_get(struct snd_kcontrol *kcontrol,
1653 struct snd_ctl_elem_value *ucontrol)
1654 {
1655 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
1656 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1657
1658 memset(ucontrol->value.iec958.status, 0xff, sizeof(mcasp->iec958_status));
1659 return 0;
1660 }
1661
1662 static const struct snd_kcontrol_new davinci_mcasp_iec958_ctls[] = {
1663 {
1664 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1665 SNDRV_CTL_ELEM_ACCESS_VOLATILE),
1666 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1667 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1668 .info = davinci_mcasp_iec958_info,
1669 .get = davinci_mcasp_iec958_get,
1670 .put = davinci_mcasp_iec958_put,
1671 }, {
1672 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1673 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1674 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1675 .info = davinci_mcasp_iec958_info,
1676 .get = davinci_mcasp_iec958_con_mask_get,
1677 },
1678 };
1679
davinci_mcasp_init_iec958_status(struct davinci_mcasp * mcasp)1680 static void davinci_mcasp_init_iec958_status(struct davinci_mcasp *mcasp)
1681 {
1682 unsigned char *cs = (u8 *)&mcasp->iec958_status;
1683
1684 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;
1685 cs[1] = IEC958_AES1_CON_PCM_CODER;
1686 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC;
1687 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM;
1688 }
1689
davinci_mcasp_dai_probe(struct snd_soc_dai * dai)1690 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1691 {
1692 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1693 int stream;
1694
1695 for_each_pcm_streams(stream)
1696 snd_soc_dai_dma_data_set(dai, stream, &mcasp->dma_data[stream]);
1697
1698 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) {
1699 davinci_mcasp_init_iec958_status(mcasp);
1700 snd_soc_add_dai_controls(dai, davinci_mcasp_iec958_ctls,
1701 ARRAY_SIZE(davinci_mcasp_iec958_ctls));
1702 }
1703
1704 return 0;
1705 }
1706
1707 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1708 .probe = davinci_mcasp_dai_probe,
1709 .startup = davinci_mcasp_startup,
1710 .shutdown = davinci_mcasp_shutdown,
1711 .trigger = davinci_mcasp_trigger,
1712 .delay = davinci_mcasp_delay,
1713 .hw_params = davinci_mcasp_hw_params,
1714 .set_fmt = davinci_mcasp_set_dai_fmt,
1715 .set_clkdiv = davinci_mcasp_set_clkdiv,
1716 .set_sysclk = davinci_mcasp_set_sysclk,
1717 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
1718 };
1719
1720 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1721
1722 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1723 SNDRV_PCM_FMTBIT_U8 | \
1724 SNDRV_PCM_FMTBIT_S16_LE | \
1725 SNDRV_PCM_FMTBIT_U16_LE | \
1726 SNDRV_PCM_FMTBIT_S24_LE | \
1727 SNDRV_PCM_FMTBIT_U24_LE | \
1728 SNDRV_PCM_FMTBIT_S24_3LE | \
1729 SNDRV_PCM_FMTBIT_U24_3LE | \
1730 SNDRV_PCM_FMTBIT_S32_LE | \
1731 SNDRV_PCM_FMTBIT_U32_LE)
1732
1733 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1734 {
1735 .name = "davinci-mcasp.0",
1736 .playback = {
1737 .stream_name = "IIS Playback",
1738 .channels_min = 1,
1739 .channels_max = 32 * 16,
1740 .rates = DAVINCI_MCASP_RATES,
1741 .formats = DAVINCI_MCASP_PCM_FMTS,
1742 },
1743 .capture = {
1744 .stream_name = "IIS Capture",
1745 .channels_min = 1,
1746 .channels_max = 32 * 16,
1747 .rates = DAVINCI_MCASP_RATES,
1748 .formats = DAVINCI_MCASP_PCM_FMTS,
1749 },
1750 .ops = &davinci_mcasp_dai_ops,
1751
1752 .symmetric_rate = 1,
1753 },
1754 {
1755 .name = "davinci-mcasp.1",
1756 .playback = {
1757 .stream_name = "DIT Playback",
1758 .channels_min = 1,
1759 .channels_max = 384,
1760 .rates = DAVINCI_MCASP_RATES,
1761 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1762 SNDRV_PCM_FMTBIT_S24_LE,
1763 },
1764 .ops = &davinci_mcasp_dai_ops,
1765 },
1766
1767 };
1768
1769 static const struct snd_soc_component_driver davinci_mcasp_component = {
1770 .name = "davinci-mcasp",
1771 .legacy_dai_naming = 1,
1772 };
1773
1774 /* Some HW specific values and defaults. The rest is filled in from DT. */
1775 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1776 .tx_dma_offset = 0x400,
1777 .rx_dma_offset = 0x400,
1778 .version = MCASP_VERSION_1,
1779 };
1780
1781 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1782 .tx_dma_offset = 0x2000,
1783 .rx_dma_offset = 0x2000,
1784 .version = MCASP_VERSION_2,
1785 };
1786
1787 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1788 .tx_dma_offset = 0,
1789 .rx_dma_offset = 0,
1790 .version = MCASP_VERSION_3,
1791 };
1792
1793 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1794 /* The CFG port offset will be calculated if it is needed */
1795 .tx_dma_offset = 0,
1796 .rx_dma_offset = 0,
1797 .version = MCASP_VERSION_4,
1798 };
1799
1800 static struct davinci_mcasp_pdata omap_mcasp_pdata = {
1801 .tx_dma_offset = 0x200,
1802 .rx_dma_offset = 0,
1803 .version = MCASP_VERSION_OMAP,
1804 };
1805
1806 static const struct of_device_id mcasp_dt_ids[] = {
1807 {
1808 .compatible = "ti,dm646x-mcasp-audio",
1809 .data = &dm646x_mcasp_pdata,
1810 },
1811 {
1812 .compatible = "ti,da830-mcasp-audio",
1813 .data = &da830_mcasp_pdata,
1814 },
1815 {
1816 .compatible = "ti,am33xx-mcasp-audio",
1817 .data = &am33xx_mcasp_pdata,
1818 },
1819 {
1820 .compatible = "ti,dra7-mcasp-audio",
1821 .data = &dra7_mcasp_pdata,
1822 },
1823 {
1824 .compatible = "ti,omap4-mcasp-audio",
1825 .data = &omap_mcasp_pdata,
1826 },
1827 { /* sentinel */ }
1828 };
1829 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1830
mcasp_reparent_fck(struct platform_device * pdev)1831 static int mcasp_reparent_fck(struct platform_device *pdev)
1832 {
1833 struct device_node *node = pdev->dev.of_node;
1834 struct clk *gfclk, *parent_clk;
1835 const char *parent_name;
1836 int ret;
1837
1838 if (!node)
1839 return 0;
1840
1841 parent_name = of_get_property(node, "fck_parent", NULL);
1842 if (!parent_name)
1843 return 0;
1844
1845 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1846
1847 gfclk = clk_get(&pdev->dev, "fck");
1848 if (IS_ERR(gfclk)) {
1849 dev_err(&pdev->dev, "failed to get fck\n");
1850 return PTR_ERR(gfclk);
1851 }
1852
1853 parent_clk = clk_get(NULL, parent_name);
1854 if (IS_ERR(parent_clk)) {
1855 dev_err(&pdev->dev, "failed to get parent clock\n");
1856 ret = PTR_ERR(parent_clk);
1857 goto err1;
1858 }
1859
1860 ret = clk_set_parent(gfclk, parent_clk);
1861 if (ret) {
1862 dev_err(&pdev->dev, "failed to reparent fck\n");
1863 goto err2;
1864 }
1865
1866 err2:
1867 clk_put(parent_clk);
1868 err1:
1869 clk_put(gfclk);
1870 return ret;
1871 }
1872
davinci_mcasp_have_gpiochip(struct davinci_mcasp * mcasp)1873 static bool davinci_mcasp_have_gpiochip(struct davinci_mcasp *mcasp)
1874 {
1875 #ifdef CONFIG_OF_GPIO
1876 return of_property_read_bool(mcasp->dev->of_node, "gpio-controller");
1877 #else
1878 return false;
1879 #endif
1880 }
1881
davinci_mcasp_get_config(struct davinci_mcasp * mcasp,struct platform_device * pdev)1882 static int davinci_mcasp_get_config(struct davinci_mcasp *mcasp,
1883 struct platform_device *pdev)
1884 {
1885 const struct of_device_id *match = of_match_device(mcasp_dt_ids, &pdev->dev);
1886 struct device_node *np = pdev->dev.of_node;
1887 struct davinci_mcasp_pdata *pdata = NULL;
1888 const u32 *of_serial_dir32;
1889 u32 val;
1890 int i;
1891
1892 if (pdev->dev.platform_data) {
1893 pdata = pdev->dev.platform_data;
1894 pdata->dismod = DISMOD_LOW;
1895 goto out;
1896 } else if (match) {
1897 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1898 GFP_KERNEL);
1899 if (!pdata)
1900 return -ENOMEM;
1901 } else {
1902 dev_err(&pdev->dev, "No compatible match found\n");
1903 return -EINVAL;
1904 }
1905
1906 if (of_property_read_u32(np, "op-mode", &val) == 0) {
1907 pdata->op_mode = val;
1908 } else {
1909 mcasp->missing_audio_param = true;
1910 goto out;
1911 }
1912
1913 if (of_property_read_u32(np, "tdm-slots", &val) == 0) {
1914 if (val < 2 || val > 32) {
1915 dev_err(&pdev->dev, "tdm-slots must be in rage [2-32]\n");
1916 return -EINVAL;
1917 }
1918
1919 pdata->tdm_slots = val;
1920 } else if (pdata->op_mode == DAVINCI_MCASP_IIS_MODE) {
1921 mcasp->missing_audio_param = true;
1922 goto out;
1923 }
1924
1925 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1926 val /= sizeof(u32);
1927 if (of_serial_dir32) {
1928 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1929 (sizeof(*of_serial_dir) * val),
1930 GFP_KERNEL);
1931 if (!of_serial_dir)
1932 return -ENOMEM;
1933
1934 for (i = 0; i < val; i++)
1935 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1936
1937 pdata->num_serializer = val;
1938 pdata->serial_dir = of_serial_dir;
1939 } else {
1940 mcasp->missing_audio_param = true;
1941 goto out;
1942 }
1943
1944 if (of_property_read_u32(np, "tx-num-evt", &val) == 0)
1945 pdata->txnumevt = val;
1946
1947 if (of_property_read_u32(np, "rx-num-evt", &val) == 0)
1948 pdata->rxnumevt = val;
1949
1950 if (of_property_read_u32(np, "auxclk-fs-ratio", &val) == 0)
1951 mcasp->auxclk_fs_ratio = val;
1952
1953 if (of_property_read_u32(np, "dismod", &val) == 0) {
1954 if (val == 0 || val == 2 || val == 3) {
1955 pdata->dismod = DISMOD_VAL(val);
1956 } else {
1957 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val);
1958 pdata->dismod = DISMOD_LOW;
1959 }
1960 } else {
1961 pdata->dismod = DISMOD_LOW;
1962 }
1963
1964 out:
1965 mcasp->pdata = pdata;
1966
1967 if (mcasp->missing_audio_param) {
1968 if (davinci_mcasp_have_gpiochip(mcasp)) {
1969 dev_dbg(&pdev->dev, "Missing DT parameter(s) for audio\n");
1970 return 0;
1971 }
1972
1973 dev_err(&pdev->dev, "Insufficient DT parameter(s)\n");
1974 return -ENODEV;
1975 }
1976
1977 mcasp->op_mode = pdata->op_mode;
1978 /* sanity check for tdm slots parameter */
1979 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1980 if (pdata->tdm_slots < 2) {
1981 dev_warn(&pdev->dev, "invalid tdm slots: %d\n",
1982 pdata->tdm_slots);
1983 mcasp->tdm_slots = 2;
1984 } else if (pdata->tdm_slots > 32) {
1985 dev_warn(&pdev->dev, "invalid tdm slots: %d\n",
1986 pdata->tdm_slots);
1987 mcasp->tdm_slots = 32;
1988 } else {
1989 mcasp->tdm_slots = pdata->tdm_slots;
1990 }
1991 } else {
1992 mcasp->tdm_slots = 32;
1993 }
1994
1995 mcasp->num_serializer = pdata->num_serializer;
1996 #ifdef CONFIG_PM
1997 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
1998 mcasp->num_serializer, sizeof(u32),
1999 GFP_KERNEL);
2000 if (!mcasp->context.xrsr_regs)
2001 return -ENOMEM;
2002 #endif
2003 mcasp->serial_dir = pdata->serial_dir;
2004 mcasp->version = pdata->version;
2005 mcasp->txnumevt = pdata->txnumevt;
2006 mcasp->rxnumevt = pdata->rxnumevt;
2007 mcasp->dismod = pdata->dismod;
2008
2009 return 0;
2010 }
2011
2012 enum {
2013 PCM_EDMA,
2014 PCM_SDMA,
2015 PCM_UDMA,
2016 };
2017 static const char *sdma_prefix = "ti,omap";
2018
davinci_mcasp_get_dma_type(struct davinci_mcasp * mcasp)2019 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
2020 {
2021 struct dma_chan *chan;
2022 const char *tmp;
2023 int ret = PCM_EDMA;
2024
2025 if (!mcasp->dev->of_node)
2026 return PCM_EDMA;
2027
2028 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
2029 chan = dma_request_chan(mcasp->dev, tmp);
2030 if (IS_ERR(chan))
2031 return dev_err_probe(mcasp->dev, PTR_ERR(chan),
2032 "Can't verify DMA configuration\n");
2033 if (WARN_ON(!chan->device || !chan->device->dev)) {
2034 dma_release_channel(chan);
2035 return -EINVAL;
2036 }
2037
2038 if (chan->device->dev->of_node)
2039 ret = of_property_read_string(chan->device->dev->of_node,
2040 "compatible", &tmp);
2041 else
2042 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
2043
2044 dma_release_channel(chan);
2045 if (ret)
2046 return ret;
2047
2048 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
2049 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
2050 return PCM_SDMA;
2051 else if (strstr(tmp, "udmap"))
2052 return PCM_UDMA;
2053 else if (strstr(tmp, "bcdma"))
2054 return PCM_UDMA;
2055
2056 return PCM_EDMA;
2057 }
2058
davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata * pdata)2059 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
2060 {
2061 int i;
2062 u32 offset = 0;
2063
2064 if (pdata->version != MCASP_VERSION_4)
2065 return pdata->tx_dma_offset;
2066
2067 for (i = 0; i < pdata->num_serializer; i++) {
2068 if (pdata->serial_dir[i] == TX_MODE) {
2069 if (!offset) {
2070 offset = DAVINCI_MCASP_TXBUF_REG(i);
2071 } else {
2072 pr_err("%s: Only one serializer allowed!\n",
2073 __func__);
2074 break;
2075 }
2076 }
2077 }
2078
2079 return offset;
2080 }
2081
davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata * pdata)2082 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
2083 {
2084 int i;
2085 u32 offset = 0;
2086
2087 if (pdata->version != MCASP_VERSION_4)
2088 return pdata->rx_dma_offset;
2089
2090 for (i = 0; i < pdata->num_serializer; i++) {
2091 if (pdata->serial_dir[i] == RX_MODE) {
2092 if (!offset) {
2093 offset = DAVINCI_MCASP_RXBUF_REG(i);
2094 } else {
2095 pr_err("%s: Only one serializer allowed!\n",
2096 __func__);
2097 break;
2098 }
2099 }
2100 }
2101
2102 return offset;
2103 }
2104
2105 #ifdef CONFIG_GPIOLIB
davinci_mcasp_gpio_request(struct gpio_chip * chip,unsigned offset)2106 static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset)
2107 {
2108 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2109
2110 if (mcasp->num_serializer && offset < mcasp->num_serializer &&
2111 mcasp->serial_dir[offset] != INACTIVE_MODE) {
2112 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset);
2113 return -EBUSY;
2114 }
2115
2116 /* Do not change the PIN yet */
2117 return pm_runtime_resume_and_get(mcasp->dev);
2118 }
2119
davinci_mcasp_gpio_free(struct gpio_chip * chip,unsigned offset)2120 static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset)
2121 {
2122 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2123
2124 /* Set the direction to input */
2125 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2126
2127 /* Set the pin as McASP pin */
2128 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2129
2130 pm_runtime_put_sync(mcasp->dev);
2131 }
2132
davinci_mcasp_gpio_direction_out(struct gpio_chip * chip,unsigned offset,int value)2133 static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip,
2134 unsigned offset, int value)
2135 {
2136 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2137 u32 val;
2138
2139 if (value)
2140 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2141 else
2142 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2143
2144 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
2145 if (!(val & BIT(offset))) {
2146 /* Set the pin as GPIO pin */
2147 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2148
2149 /* Set the direction to output */
2150 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2151 }
2152
2153 return 0;
2154 }
2155
davinci_mcasp_gpio_set(struct gpio_chip * chip,unsigned offset,int value)2156 static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset,
2157 int value)
2158 {
2159 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2160
2161 if (value)
2162 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2163 else
2164 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2165 }
2166
davinci_mcasp_gpio_direction_in(struct gpio_chip * chip,unsigned offset)2167 static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip,
2168 unsigned offset)
2169 {
2170 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2171 u32 val;
2172
2173 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
2174 if (!(val & BIT(offset))) {
2175 /* Set the direction to input */
2176 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2177
2178 /* Set the pin as GPIO pin */
2179 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2180 }
2181
2182 return 0;
2183 }
2184
davinci_mcasp_gpio_get(struct gpio_chip * chip,unsigned offset)2185 static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset)
2186 {
2187 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2188 u32 val;
2189
2190 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG);
2191 if (val & BIT(offset))
2192 return 1;
2193
2194 return 0;
2195 }
2196
davinci_mcasp_gpio_get_direction(struct gpio_chip * chip,unsigned offset)2197 static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip,
2198 unsigned offset)
2199 {
2200 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2201 u32 val;
2202
2203 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
2204 if (val & BIT(offset))
2205 return 0;
2206
2207 return 1;
2208 }
2209
2210 static const struct gpio_chip davinci_mcasp_template_chip = {
2211 .owner = THIS_MODULE,
2212 .request = davinci_mcasp_gpio_request,
2213 .free = davinci_mcasp_gpio_free,
2214 .direction_output = davinci_mcasp_gpio_direction_out,
2215 .set = davinci_mcasp_gpio_set,
2216 .direction_input = davinci_mcasp_gpio_direction_in,
2217 .get = davinci_mcasp_gpio_get,
2218 .get_direction = davinci_mcasp_gpio_get_direction,
2219 .base = -1,
2220 .ngpio = 32,
2221 };
2222
davinci_mcasp_init_gpiochip(struct davinci_mcasp * mcasp)2223 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2224 {
2225 if (!davinci_mcasp_have_gpiochip(mcasp))
2226 return 0;
2227
2228 mcasp->gpio_chip = davinci_mcasp_template_chip;
2229 mcasp->gpio_chip.label = dev_name(mcasp->dev);
2230 mcasp->gpio_chip.parent = mcasp->dev;
2231
2232 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp);
2233 }
2234
2235 #else /* CONFIG_GPIOLIB */
davinci_mcasp_init_gpiochip(struct davinci_mcasp * mcasp)2236 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2237 {
2238 return 0;
2239 }
2240 #endif /* CONFIG_GPIOLIB */
2241
davinci_mcasp_probe(struct platform_device * pdev)2242 static int davinci_mcasp_probe(struct platform_device *pdev)
2243 {
2244 struct snd_dmaengine_dai_dma_data *dma_data;
2245 struct resource *mem, *dat;
2246 struct davinci_mcasp *mcasp;
2247 char *irq_name;
2248 int irq;
2249 int ret;
2250
2251 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
2252 dev_err(&pdev->dev, "No platform data supplied\n");
2253 return -EINVAL;
2254 }
2255
2256 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
2257 GFP_KERNEL);
2258 if (!mcasp)
2259 return -ENOMEM;
2260
2261 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
2262 if (!mem) {
2263 dev_warn(&pdev->dev,
2264 "\"mpu\" mem resource not found, using index 0\n");
2265 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2266 if (!mem) {
2267 dev_err(&pdev->dev, "no mem resource?\n");
2268 return -ENODEV;
2269 }
2270 }
2271
2272 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
2273 if (IS_ERR(mcasp->base))
2274 return PTR_ERR(mcasp->base);
2275
2276 dev_set_drvdata(&pdev->dev, mcasp);
2277 pm_runtime_enable(&pdev->dev);
2278
2279 mcasp->dev = &pdev->dev;
2280 ret = davinci_mcasp_get_config(mcasp, pdev);
2281 if (ret)
2282 goto err;
2283
2284 /* All PINS as McASP */
2285 pm_runtime_get_sync(mcasp->dev);
2286 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
2287 pm_runtime_put(mcasp->dev);
2288
2289 /* Skip audio related setup code if the configuration is not adequat */
2290 if (mcasp->missing_audio_param)
2291 goto no_audio;
2292
2293 irq = platform_get_irq_byname_optional(pdev, "common");
2294 if (irq > 0) {
2295 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
2296 dev_name(&pdev->dev));
2297 if (!irq_name) {
2298 ret = -ENOMEM;
2299 goto err;
2300 }
2301 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2302 davinci_mcasp_common_irq_handler,
2303 IRQF_ONESHOT | IRQF_SHARED,
2304 irq_name, mcasp);
2305 if (ret) {
2306 dev_err(&pdev->dev, "common IRQ request failed\n");
2307 goto err;
2308 }
2309
2310 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2311 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2312 }
2313
2314 irq = platform_get_irq_byname_optional(pdev, "rx");
2315 if (irq > 0) {
2316 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
2317 dev_name(&pdev->dev));
2318 if (!irq_name) {
2319 ret = -ENOMEM;
2320 goto err;
2321 }
2322 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2323 davinci_mcasp_rx_irq_handler,
2324 IRQF_ONESHOT, irq_name, mcasp);
2325 if (ret) {
2326 dev_err(&pdev->dev, "RX IRQ request failed\n");
2327 goto err;
2328 }
2329
2330 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2331 }
2332
2333 irq = platform_get_irq_byname_optional(pdev, "tx");
2334 if (irq > 0) {
2335 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
2336 dev_name(&pdev->dev));
2337 if (!irq_name) {
2338 ret = -ENOMEM;
2339 goto err;
2340 }
2341 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2342 davinci_mcasp_tx_irq_handler,
2343 IRQF_ONESHOT, irq_name, mcasp);
2344 if (ret) {
2345 dev_err(&pdev->dev, "TX IRQ request failed\n");
2346 goto err;
2347 }
2348
2349 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2350 }
2351
2352 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
2353 if (dat)
2354 mcasp->dat_port = true;
2355
2356 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
2357 dma_data->filter_data = "tx";
2358 if (dat) {
2359 dma_data->addr = dat->start;
2360 /*
2361 * According to the TRM there should be 0x200 offset added to
2362 * the DAT port address
2363 */
2364 if (mcasp->version == MCASP_VERSION_OMAP)
2365 dma_data->addr += davinci_mcasp_txdma_offset(mcasp->pdata);
2366 } else {
2367 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(mcasp->pdata);
2368 }
2369
2370
2371 /* RX is not valid in DIT mode */
2372 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
2373 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
2374 dma_data->filter_data = "rx";
2375 if (dat)
2376 dma_data->addr = dat->start;
2377 else
2378 dma_data->addr =
2379 mem->start + davinci_mcasp_rxdma_offset(mcasp->pdata);
2380 }
2381
2382 if (mcasp->version < MCASP_VERSION_3) {
2383 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
2384 /* dma_params->dma_addr is pointing to the data port address */
2385 mcasp->dat_port = true;
2386 } else {
2387 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2388 }
2389
2390 /* Allocate memory for long enough list for all possible
2391 * scenarios. Maximum number tdm slots is 32 and there cannot
2392 * be more serializers than given in the configuration. The
2393 * serializer directions could be taken into account, but it
2394 * would make code much more complex and save only couple of
2395 * bytes.
2396 */
2397 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
2398 devm_kcalloc(mcasp->dev,
2399 32 + mcasp->num_serializer - 1,
2400 sizeof(unsigned int),
2401 GFP_KERNEL);
2402
2403 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2404 devm_kcalloc(mcasp->dev,
2405 32 + mcasp->num_serializer - 1,
2406 sizeof(unsigned int),
2407 GFP_KERNEL);
2408
2409 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2410 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2411 ret = -ENOMEM;
2412 goto err;
2413 }
2414
2415 ret = davinci_mcasp_set_ch_constraints(mcasp);
2416 if (ret)
2417 goto err;
2418
2419 mcasp_reparent_fck(pdev);
2420
2421 ret = devm_snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
2422 &davinci_mcasp_dai[mcasp->op_mode], 1);
2423
2424 if (ret != 0)
2425 goto err;
2426
2427 ret = davinci_mcasp_get_dma_type(mcasp);
2428 switch (ret) {
2429 case PCM_EDMA:
2430 ret = edma_pcm_platform_register(&pdev->dev);
2431 break;
2432 case PCM_SDMA:
2433 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
2434 ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
2435 else
2436 ret = sdma_pcm_platform_register(&pdev->dev, "tx", NULL);
2437 break;
2438 case PCM_UDMA:
2439 ret = udma_pcm_platform_register(&pdev->dev);
2440 break;
2441 default:
2442 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2443 fallthrough;
2444 case -EPROBE_DEFER:
2445 goto err;
2446 }
2447
2448 if (ret) {
2449 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
2450 goto err;
2451 }
2452
2453 no_audio:
2454 ret = davinci_mcasp_init_gpiochip(mcasp);
2455 if (ret) {
2456 dev_err(&pdev->dev, "gpiochip registration failed: %d\n", ret);
2457 goto err;
2458 }
2459
2460 return 0;
2461 err:
2462 pm_runtime_disable(&pdev->dev);
2463 return ret;
2464 }
2465
davinci_mcasp_remove(struct platform_device * pdev)2466 static void davinci_mcasp_remove(struct platform_device *pdev)
2467 {
2468 pm_runtime_disable(&pdev->dev);
2469 }
2470
2471 #ifdef CONFIG_PM
davinci_mcasp_runtime_suspend(struct device * dev)2472 static int davinci_mcasp_runtime_suspend(struct device *dev)
2473 {
2474 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2475 struct davinci_mcasp_context *context = &mcasp->context;
2476 u32 reg;
2477 int i;
2478
2479 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2480 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
2481
2482 if (mcasp->txnumevt) {
2483 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2484 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
2485 }
2486 if (mcasp->rxnumevt) {
2487 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2488 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
2489 }
2490
2491 for (i = 0; i < mcasp->num_serializer; i++)
2492 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
2493 DAVINCI_MCASP_XRSRCTL_REG(i));
2494
2495 return 0;
2496 }
2497
davinci_mcasp_runtime_resume(struct device * dev)2498 static int davinci_mcasp_runtime_resume(struct device *dev)
2499 {
2500 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2501 struct davinci_mcasp_context *context = &mcasp->context;
2502 u32 reg;
2503 int i;
2504
2505 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2506 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
2507
2508 if (mcasp->txnumevt) {
2509 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2510 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
2511 }
2512 if (mcasp->rxnumevt) {
2513 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2514 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
2515 }
2516
2517 for (i = 0; i < mcasp->num_serializer; i++)
2518 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
2519 context->xrsr_regs[i]);
2520
2521 return 0;
2522 }
2523
2524 #endif
2525
2526 static const struct dev_pm_ops davinci_mcasp_pm_ops = {
2527 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend,
2528 davinci_mcasp_runtime_resume,
2529 NULL)
2530 };
2531
2532 static struct platform_driver davinci_mcasp_driver = {
2533 .probe = davinci_mcasp_probe,
2534 .remove_new = davinci_mcasp_remove,
2535 .driver = {
2536 .name = "davinci-mcasp",
2537 .pm = &davinci_mcasp_pm_ops,
2538 .of_match_table = mcasp_dt_ids,
2539 },
2540 };
2541
2542 module_platform_driver(davinci_mcasp_driver);
2543
2544 MODULE_AUTHOR("Steve Chen");
2545 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2546 MODULE_LICENSE("GPL");
2547
