1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/component.h>
25 #include <linux/kernel.h>
26
27 #include <drm/drm_edid.h>
28 #include <drm/i915_component.h>
29
30 #include "i915_drv.h"
31 #include "intel_atomic.h"
32 #include "intel_audio.h"
33 #include "intel_audio_regs.h"
34 #include "intel_cdclk.h"
35 #include "intel_crtc.h"
36 #include "intel_de.h"
37 #include "intel_display_types.h"
38 #include "intel_lpe_audio.h"
39
40 /**
41 * DOC: High Definition Audio over HDMI and Display Port
42 *
43 * The graphics and audio drivers together support High Definition Audio over
44 * HDMI and Display Port. The audio programming sequences are divided into audio
45 * codec and controller enable and disable sequences. The graphics driver
46 * handles the audio codec sequences, while the audio driver handles the audio
47 * controller sequences.
48 *
49 * The disable sequences must be performed before disabling the transcoder or
50 * port. The enable sequences may only be performed after enabling the
51 * transcoder and port, and after completed link training. Therefore the audio
52 * enable/disable sequences are part of the modeset sequence.
53 *
54 * The codec and controller sequences could be done either parallel or serial,
55 * but generally the ELDV/PD change in the codec sequence indicates to the audio
56 * driver that the controller sequence should start. Indeed, most of the
57 * co-operation between the graphics and audio drivers is handled via audio
58 * related registers. (The notable exception is the power management, not
59 * covered here.)
60 *
61 * The struct &i915_audio_component is used to interact between the graphics
62 * and audio drivers. The struct &i915_audio_component_ops @ops in it is
63 * defined in graphics driver and called in audio driver. The
64 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
65 */
66
67 struct intel_audio_funcs {
68 void (*audio_codec_enable)(struct intel_encoder *encoder,
69 const struct intel_crtc_state *crtc_state,
70 const struct drm_connector_state *conn_state);
71 void (*audio_codec_disable)(struct intel_encoder *encoder,
72 const struct intel_crtc_state *old_crtc_state,
73 const struct drm_connector_state *old_conn_state);
74 void (*audio_codec_get_config)(struct intel_encoder *encoder,
75 struct intel_crtc_state *crtc_state);
76 };
77
78 /* DP N/M table */
79 #define LC_810M 810000
80 #define LC_540M 540000
81 #define LC_270M 270000
82 #define LC_162M 162000
83
84 struct dp_aud_n_m {
85 int sample_rate;
86 int clock;
87 u16 m;
88 u16 n;
89 };
90
91 struct hdmi_aud_ncts {
92 int sample_rate;
93 int clock;
94 int n;
95 int cts;
96 };
97
98 /* Values according to DP 1.4 Table 2-104 */
99 static const struct dp_aud_n_m dp_aud_n_m[] = {
100 { 32000, LC_162M, 1024, 10125 },
101 { 44100, LC_162M, 784, 5625 },
102 { 48000, LC_162M, 512, 3375 },
103 { 64000, LC_162M, 2048, 10125 },
104 { 88200, LC_162M, 1568, 5625 },
105 { 96000, LC_162M, 1024, 3375 },
106 { 128000, LC_162M, 4096, 10125 },
107 { 176400, LC_162M, 3136, 5625 },
108 { 192000, LC_162M, 2048, 3375 },
109 { 32000, LC_270M, 1024, 16875 },
110 { 44100, LC_270M, 784, 9375 },
111 { 48000, LC_270M, 512, 5625 },
112 { 64000, LC_270M, 2048, 16875 },
113 { 88200, LC_270M, 1568, 9375 },
114 { 96000, LC_270M, 1024, 5625 },
115 { 128000, LC_270M, 4096, 16875 },
116 { 176400, LC_270M, 3136, 9375 },
117 { 192000, LC_270M, 2048, 5625 },
118 { 32000, LC_540M, 1024, 33750 },
119 { 44100, LC_540M, 784, 18750 },
120 { 48000, LC_540M, 512, 11250 },
121 { 64000, LC_540M, 2048, 33750 },
122 { 88200, LC_540M, 1568, 18750 },
123 { 96000, LC_540M, 1024, 11250 },
124 { 128000, LC_540M, 4096, 33750 },
125 { 176400, LC_540M, 3136, 18750 },
126 { 192000, LC_540M, 2048, 11250 },
127 { 32000, LC_810M, 1024, 50625 },
128 { 44100, LC_810M, 784, 28125 },
129 { 48000, LC_810M, 512, 16875 },
130 { 64000, LC_810M, 2048, 50625 },
131 { 88200, LC_810M, 1568, 28125 },
132 { 96000, LC_810M, 1024, 16875 },
133 { 128000, LC_810M, 4096, 50625 },
134 { 176400, LC_810M, 3136, 28125 },
135 { 192000, LC_810M, 2048, 16875 },
136 };
137
138 static const struct dp_aud_n_m *
audio_config_dp_get_n_m(const struct intel_crtc_state * crtc_state,int rate)139 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate)
140 {
141 int i;
142
143 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
144 if (rate == dp_aud_n_m[i].sample_rate &&
145 crtc_state->port_clock == dp_aud_n_m[i].clock)
146 return &dp_aud_n_m[i];
147 }
148
149 return NULL;
150 }
151
152 static const struct {
153 int clock;
154 u32 config;
155 } hdmi_audio_clock[] = {
156 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
157 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
158 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
159 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
160 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
161 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
162 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
163 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
164 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
165 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
166 { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 },
167 { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 },
168 { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 },
169 { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 },
170 };
171
172 /* HDMI N/CTS table */
173 #define TMDS_297M 297000
174 #define TMDS_296M 296703
175 #define TMDS_594M 594000
176 #define TMDS_593M 593407
177
178 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = {
179 { 32000, TMDS_296M, 5824, 421875 },
180 { 32000, TMDS_297M, 3072, 222750 },
181 { 32000, TMDS_593M, 5824, 843750 },
182 { 32000, TMDS_594M, 3072, 445500 },
183 { 44100, TMDS_296M, 4459, 234375 },
184 { 44100, TMDS_297M, 4704, 247500 },
185 { 44100, TMDS_593M, 8918, 937500 },
186 { 44100, TMDS_594M, 9408, 990000 },
187 { 88200, TMDS_296M, 8918, 234375 },
188 { 88200, TMDS_297M, 9408, 247500 },
189 { 88200, TMDS_593M, 17836, 937500 },
190 { 88200, TMDS_594M, 18816, 990000 },
191 { 176400, TMDS_296M, 17836, 234375 },
192 { 176400, TMDS_297M, 18816, 247500 },
193 { 176400, TMDS_593M, 35672, 937500 },
194 { 176400, TMDS_594M, 37632, 990000 },
195 { 48000, TMDS_296M, 5824, 281250 },
196 { 48000, TMDS_297M, 5120, 247500 },
197 { 48000, TMDS_593M, 5824, 562500 },
198 { 48000, TMDS_594M, 6144, 594000 },
199 { 96000, TMDS_296M, 11648, 281250 },
200 { 96000, TMDS_297M, 10240, 247500 },
201 { 96000, TMDS_593M, 11648, 562500 },
202 { 96000, TMDS_594M, 12288, 594000 },
203 { 192000, TMDS_296M, 23296, 281250 },
204 { 192000, TMDS_297M, 20480, 247500 },
205 { 192000, TMDS_593M, 23296, 562500 },
206 { 192000, TMDS_594M, 24576, 594000 },
207 };
208
209 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/
210 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/
211 #define TMDS_371M 371250
212 #define TMDS_370M 370878
213
214 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = {
215 { 32000, TMDS_370M, 5824, 527344 },
216 { 32000, TMDS_371M, 6144, 556875 },
217 { 44100, TMDS_370M, 8918, 585938 },
218 { 44100, TMDS_371M, 4704, 309375 },
219 { 88200, TMDS_370M, 17836, 585938 },
220 { 88200, TMDS_371M, 9408, 309375 },
221 { 176400, TMDS_370M, 35672, 585938 },
222 { 176400, TMDS_371M, 18816, 309375 },
223 { 48000, TMDS_370M, 11648, 703125 },
224 { 48000, TMDS_371M, 5120, 309375 },
225 { 96000, TMDS_370M, 23296, 703125 },
226 { 96000, TMDS_371M, 10240, 309375 },
227 { 192000, TMDS_370M, 46592, 703125 },
228 { 192000, TMDS_371M, 20480, 309375 },
229 };
230
231 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/
232 #define TMDS_445_5M 445500
233 #define TMDS_445M 445054
234
235 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
236 { 32000, TMDS_445M, 5824, 632813 },
237 { 32000, TMDS_445_5M, 4096, 445500 },
238 { 44100, TMDS_445M, 8918, 703125 },
239 { 44100, TMDS_445_5M, 4704, 371250 },
240 { 88200, TMDS_445M, 17836, 703125 },
241 { 88200, TMDS_445_5M, 9408, 371250 },
242 { 176400, TMDS_445M, 35672, 703125 },
243 { 176400, TMDS_445_5M, 18816, 371250 },
244 { 48000, TMDS_445M, 5824, 421875 },
245 { 48000, TMDS_445_5M, 5120, 371250 },
246 { 96000, TMDS_445M, 11648, 421875 },
247 { 96000, TMDS_445_5M, 10240, 371250 },
248 { 192000, TMDS_445M, 23296, 421875 },
249 { 192000, TMDS_445_5M, 20480, 371250 },
250 };
251
252 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
audio_config_hdmi_pixel_clock(const struct intel_crtc_state * crtc_state)253 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
254 {
255 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
256 const struct drm_display_mode *adjusted_mode =
257 &crtc_state->hw.adjusted_mode;
258 int i;
259
260 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
261 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
262 break;
263 }
264
265 if (DISPLAY_VER(i915) < 12 && adjusted_mode->crtc_clock > 148500)
266 i = ARRAY_SIZE(hdmi_audio_clock);
267
268 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
269 drm_dbg_kms(&i915->drm,
270 "HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
271 adjusted_mode->crtc_clock);
272 i = 1;
273 }
274
275 drm_dbg_kms(&i915->drm,
276 "Configuring HDMI audio for pixel clock %d (0x%08x)\n",
277 hdmi_audio_clock[i].clock,
278 hdmi_audio_clock[i].config);
279
280 return hdmi_audio_clock[i].config;
281 }
282
audio_config_hdmi_get_n(const struct intel_crtc_state * crtc_state,int rate)283 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
284 int rate)
285 {
286 const struct hdmi_aud_ncts *hdmi_ncts_table;
287 int i, size;
288
289 if (crtc_state->pipe_bpp == 36) {
290 hdmi_ncts_table = hdmi_aud_ncts_36bpp;
291 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp);
292 } else if (crtc_state->pipe_bpp == 30) {
293 hdmi_ncts_table = hdmi_aud_ncts_30bpp;
294 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp);
295 } else {
296 hdmi_ncts_table = hdmi_aud_ncts_24bpp;
297 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp);
298 }
299
300 for (i = 0; i < size; i++) {
301 if (rate == hdmi_ncts_table[i].sample_rate &&
302 crtc_state->port_clock == hdmi_ncts_table[i].clock) {
303 return hdmi_ncts_table[i].n;
304 }
305 }
306 return 0;
307 }
308
309 /* ELD buffer size in dwords */
g4x_eld_buffer_size(struct drm_i915_private * i915)310 static int g4x_eld_buffer_size(struct drm_i915_private *i915)
311 {
312 u32 tmp;
313
314 tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
315
316 return REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp);
317 }
318
g4x_audio_codec_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)319 static void g4x_audio_codec_get_config(struct intel_encoder *encoder,
320 struct intel_crtc_state *crtc_state)
321 {
322 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
323 u32 *eld = (u32 *)crtc_state->eld;
324 int eld_buffer_size, len, i;
325 u32 tmp;
326
327 tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
328 if ((tmp & G4X_ELD_VALID) == 0)
329 return;
330
331 intel_de_rmw(i915, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0);
332
333 eld_buffer_size = g4x_eld_buffer_size(i915);
334 len = min_t(int, sizeof(crtc_state->eld) / 4, eld_buffer_size);
335
336 for (i = 0; i < len; i++)
337 eld[i] = intel_de_read(i915, G4X_HDMIW_HDMIEDID);
338 }
339
g4x_audio_codec_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)340 static void g4x_audio_codec_disable(struct intel_encoder *encoder,
341 const struct intel_crtc_state *old_crtc_state,
342 const struct drm_connector_state *old_conn_state)
343 {
344 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
345 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
346
347 /* Invalidate ELD */
348 intel_de_rmw(i915, G4X_AUD_CNTL_ST,
349 G4X_ELD_VALID, 0);
350
351 intel_crtc_wait_for_next_vblank(crtc);
352 intel_crtc_wait_for_next_vblank(crtc);
353 }
354
g4x_audio_codec_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)355 static void g4x_audio_codec_enable(struct intel_encoder *encoder,
356 const struct intel_crtc_state *crtc_state,
357 const struct drm_connector_state *conn_state)
358 {
359 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
360 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
361 const u32 *eld = (const u32 *)crtc_state->eld;
362 int eld_buffer_size, len, i;
363
364 intel_crtc_wait_for_next_vblank(crtc);
365
366 intel_de_rmw(i915, G4X_AUD_CNTL_ST,
367 G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK, 0);
368
369 eld_buffer_size = g4x_eld_buffer_size(i915);
370 len = min(drm_eld_size(crtc_state->eld) / 4, eld_buffer_size);
371
372 for (i = 0; i < len; i++)
373 intel_de_write(i915, G4X_HDMIW_HDMIEDID, eld[i]);
374 for (; i < eld_buffer_size; i++)
375 intel_de_write(i915, G4X_HDMIW_HDMIEDID, 0);
376
377 drm_WARN_ON(&i915->drm,
378 (intel_de_read(i915, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0);
379
380 intel_de_rmw(i915, G4X_AUD_CNTL_ST,
381 0, G4X_ELD_VALID);
382 }
383
384 static void
hsw_dp_audio_config_update(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)385 hsw_dp_audio_config_update(struct intel_encoder *encoder,
386 const struct intel_crtc_state *crtc_state)
387 {
388 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
389 struct i915_audio_component *acomp = i915->display.audio.component;
390 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
391 enum port port = encoder->port;
392 const struct dp_aud_n_m *nm;
393 int rate;
394 u32 tmp;
395
396 rate = acomp ? acomp->aud_sample_rate[port] : 0;
397 nm = audio_config_dp_get_n_m(crtc_state, rate);
398 if (nm)
399 drm_dbg_kms(&i915->drm, "using Maud %u, Naud %u\n", nm->m,
400 nm->n);
401 else
402 drm_dbg_kms(&i915->drm, "using automatic Maud, Naud\n");
403
404 tmp = intel_de_read(i915, HSW_AUD_CFG(cpu_transcoder));
405 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
406 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
407 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
408 tmp |= AUD_CONFIG_N_VALUE_INDEX;
409
410 if (nm) {
411 tmp &= ~AUD_CONFIG_N_MASK;
412 tmp |= AUD_CONFIG_N(nm->n);
413 tmp |= AUD_CONFIG_N_PROG_ENABLE;
414 }
415
416 intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp);
417
418 tmp = intel_de_read(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
419 tmp &= ~AUD_CONFIG_M_MASK;
420 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
421 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
422
423 if (nm) {
424 tmp |= nm->m;
425 tmp |= AUD_M_CTS_M_VALUE_INDEX;
426 tmp |= AUD_M_CTS_M_PROG_ENABLE;
427 }
428
429 intel_de_write(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
430 }
431
432 static void
hsw_hdmi_audio_config_update(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)433 hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
434 const struct intel_crtc_state *crtc_state)
435 {
436 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
437 struct i915_audio_component *acomp = i915->display.audio.component;
438 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
439 enum port port = encoder->port;
440 int n, rate;
441 u32 tmp;
442
443 rate = acomp ? acomp->aud_sample_rate[port] : 0;
444
445 tmp = intel_de_read(i915, HSW_AUD_CFG(cpu_transcoder));
446 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
447 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
448 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
449 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
450
451 n = audio_config_hdmi_get_n(crtc_state, rate);
452 if (n != 0) {
453 drm_dbg_kms(&i915->drm, "using N %d\n", n);
454
455 tmp &= ~AUD_CONFIG_N_MASK;
456 tmp |= AUD_CONFIG_N(n);
457 tmp |= AUD_CONFIG_N_PROG_ENABLE;
458 } else {
459 drm_dbg_kms(&i915->drm, "using automatic N\n");
460 }
461
462 intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp);
463
464 /*
465 * Let's disable "Enable CTS or M Prog bit"
466 * and let HW calculate the value
467 */
468 tmp = intel_de_read(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
469 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
470 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
471 intel_de_write(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
472 }
473
474 static void
hsw_audio_config_update(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)475 hsw_audio_config_update(struct intel_encoder *encoder,
476 const struct intel_crtc_state *crtc_state)
477 {
478 if (intel_crtc_has_dp_encoder(crtc_state))
479 hsw_dp_audio_config_update(encoder, crtc_state);
480 else
481 hsw_hdmi_audio_config_update(encoder, crtc_state);
482 }
483
hsw_audio_codec_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)484 static void hsw_audio_codec_disable(struct intel_encoder *encoder,
485 const struct intel_crtc_state *old_crtc_state,
486 const struct drm_connector_state *old_conn_state)
487 {
488 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
489 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
490 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
491
492 mutex_lock(&i915->display.audio.mutex);
493
494 /* Disable timestamps */
495 intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder),
496 AUD_CONFIG_N_VALUE_INDEX |
497 AUD_CONFIG_UPPER_N_MASK |
498 AUD_CONFIG_LOWER_N_MASK,
499 AUD_CONFIG_N_PROG_ENABLE |
500 (intel_crtc_has_dp_encoder(old_crtc_state) ?
501 AUD_CONFIG_N_VALUE_INDEX : 0));
502
503 /* Invalidate ELD */
504 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
505 AUDIO_ELD_VALID(cpu_transcoder), 0);
506
507 intel_crtc_wait_for_next_vblank(crtc);
508 intel_crtc_wait_for_next_vblank(crtc);
509
510 /* Disable audio presence detect */
511 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
512 AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0);
513
514 mutex_unlock(&i915->display.audio.mutex);
515 }
516
calc_hblank_early_prog(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)517 static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
518 const struct intel_crtc_state *crtc_state)
519 {
520 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
521 unsigned int link_clks_available, link_clks_required;
522 unsigned int tu_data, tu_line, link_clks_active;
523 unsigned int h_active, h_total, hblank_delta, pixel_clk;
524 unsigned int fec_coeff, cdclk, vdsc_bpp;
525 unsigned int link_clk, lanes;
526 unsigned int hblank_rise;
527
528 h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
529 h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
530 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
531 vdsc_bpp = crtc_state->dsc.compressed_bpp;
532 cdclk = i915->display.cdclk.hw.cdclk;
533 /* fec= 0.972261, using rounding multiplier of 1000000 */
534 fec_coeff = 972261;
535 link_clk = crtc_state->port_clock;
536 lanes = crtc_state->lane_count;
537
538 drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
539 "lanes = %u vdsc_bpp = %u cdclk = %u\n",
540 h_active, link_clk, lanes, vdsc_bpp, cdclk);
541
542 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk))
543 return 0;
544
545 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28;
546 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2);
547
548 if (link_clks_available > link_clks_required)
549 hblank_delta = 32;
550 else
551 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk),
552 mul_u32_u32(link_clk, cdclk));
553
554 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000),
555 mul_u32_u32(link_clk * lanes, fec_coeff));
556 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
557 mul_u32_u32(64 * pixel_clk, 1000000));
558 link_clks_active = (tu_line - 1) * 64 + tu_data;
559
560 hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk;
561
562 return h_active - hblank_rise + hblank_delta;
563 }
564
calc_samples_room(const struct intel_crtc_state * crtc_state)565 static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state)
566 {
567 unsigned int h_active, h_total, pixel_clk;
568 unsigned int link_clk, lanes;
569
570 h_active = crtc_state->hw.adjusted_mode.hdisplay;
571 h_total = crtc_state->hw.adjusted_mode.htotal;
572 pixel_clk = crtc_state->hw.adjusted_mode.clock;
573 link_clk = crtc_state->port_clock;
574 lanes = crtc_state->lane_count;
575
576 return ((h_total - h_active) * link_clk - 12 * pixel_clk) /
577 (pixel_clk * (48 / lanes + 2));
578 }
579
enable_audio_dsc_wa(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)580 static void enable_audio_dsc_wa(struct intel_encoder *encoder,
581 const struct intel_crtc_state *crtc_state)
582 {
583 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
584 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
585 unsigned int hblank_early_prog, samples_room;
586 unsigned int val;
587
588 if (DISPLAY_VER(i915) < 11)
589 return;
590
591 val = intel_de_read(i915, AUD_CONFIG_BE);
592
593 if (DISPLAY_VER(i915) == 11)
594 val |= HBLANK_EARLY_ENABLE_ICL(cpu_transcoder);
595 else if (DISPLAY_VER(i915) >= 12)
596 val |= HBLANK_EARLY_ENABLE_TGL(cpu_transcoder);
597
598 if (crtc_state->dsc.compression_enable &&
599 crtc_state->hw.adjusted_mode.hdisplay >= 3840 &&
600 crtc_state->hw.adjusted_mode.vdisplay >= 2160) {
601 /* Get hblank early enable value required */
602 val &= ~HBLANK_START_COUNT_MASK(cpu_transcoder);
603 hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state);
604 if (hblank_early_prog < 32)
605 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_32);
606 else if (hblank_early_prog < 64)
607 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_64);
608 else if (hblank_early_prog < 96)
609 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_96);
610 else
611 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_128);
612
613 /* Get samples room value required */
614 val &= ~NUMBER_SAMPLES_PER_LINE_MASK(cpu_transcoder);
615 samples_room = calc_samples_room(crtc_state);
616 if (samples_room < 3)
617 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, samples_room);
618 else /* Program 0 i.e "All Samples available in buffer" */
619 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, 0x0);
620 }
621
622 intel_de_write(i915, AUD_CONFIG_BE, val);
623 }
624
hsw_audio_codec_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)625 static void hsw_audio_codec_enable(struct intel_encoder *encoder,
626 const struct intel_crtc_state *crtc_state,
627 const struct drm_connector_state *conn_state)
628 {
629 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
630 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
631 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
632
633 mutex_lock(&i915->display.audio.mutex);
634
635 /* Enable Audio WA for 4k DSC usecases */
636 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
637 enable_audio_dsc_wa(encoder, crtc_state);
638
639 /* Enable audio presence detect */
640 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
641 0, AUDIO_OUTPUT_ENABLE(cpu_transcoder));
642
643 intel_crtc_wait_for_next_vblank(crtc);
644
645 /* Invalidate ELD */
646 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
647 AUDIO_ELD_VALID(cpu_transcoder), 0);
648
649 /*
650 * The audio componenent is used to convey the ELD
651 * instead using of the hardware ELD buffer.
652 */
653
654 /* Enable timestamps */
655 hsw_audio_config_update(encoder, crtc_state);
656
657 mutex_unlock(&i915->display.audio.mutex);
658 }
659
660 struct ibx_audio_regs {
661 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
662 };
663
ibx_audio_regs_init(struct drm_i915_private * i915,enum pipe pipe,struct ibx_audio_regs * regs)664 static void ibx_audio_regs_init(struct drm_i915_private *i915,
665 enum pipe pipe,
666 struct ibx_audio_regs *regs)
667 {
668 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
669 regs->hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
670 regs->aud_config = VLV_AUD_CFG(pipe);
671 regs->aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
672 regs->aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
673 } else if (HAS_PCH_CPT(i915)) {
674 regs->hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
675 regs->aud_config = CPT_AUD_CFG(pipe);
676 regs->aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
677 regs->aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
678 } else if (HAS_PCH_IBX(i915)) {
679 regs->hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
680 regs->aud_config = IBX_AUD_CFG(pipe);
681 regs->aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
682 regs->aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
683 }
684 }
685
ibx_audio_codec_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)686 static void ibx_audio_codec_disable(struct intel_encoder *encoder,
687 const struct intel_crtc_state *old_crtc_state,
688 const struct drm_connector_state *old_conn_state)
689 {
690 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
691 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
692 enum port port = encoder->port;
693 enum pipe pipe = crtc->pipe;
694 struct ibx_audio_regs regs;
695
696 if (drm_WARN_ON(&i915->drm, port == PORT_A))
697 return;
698
699 ibx_audio_regs_init(i915, pipe, ®s);
700
701 mutex_lock(&i915->display.audio.mutex);
702
703 /* Disable timestamps */
704 intel_de_rmw(i915, regs.aud_config,
705 AUD_CONFIG_N_VALUE_INDEX |
706 AUD_CONFIG_UPPER_N_MASK |
707 AUD_CONFIG_LOWER_N_MASK,
708 AUD_CONFIG_N_PROG_ENABLE |
709 (intel_crtc_has_dp_encoder(old_crtc_state) ?
710 AUD_CONFIG_N_VALUE_INDEX : 0));
711
712 /* Invalidate ELD */
713 intel_de_rmw(i915, regs.aud_cntrl_st2,
714 IBX_ELD_VALID(port), 0);
715
716 mutex_unlock(&i915->display.audio.mutex);
717
718 intel_crtc_wait_for_next_vblank(crtc);
719 intel_crtc_wait_for_next_vblank(crtc);
720 }
721
ibx_audio_codec_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)722 static void ibx_audio_codec_enable(struct intel_encoder *encoder,
723 const struct intel_crtc_state *crtc_state,
724 const struct drm_connector_state *conn_state)
725 {
726 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
727 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
728 enum port port = encoder->port;
729 enum pipe pipe = crtc->pipe;
730 struct ibx_audio_regs regs;
731
732 if (drm_WARN_ON(&i915->drm, port == PORT_A))
733 return;
734
735 intel_crtc_wait_for_next_vblank(crtc);
736
737 ibx_audio_regs_init(i915, pipe, ®s);
738
739 mutex_lock(&i915->display.audio.mutex);
740
741 /* Invalidate ELD */
742 intel_de_rmw(i915, regs.aud_cntrl_st2,
743 IBX_ELD_VALID(port), 0);
744
745 /*
746 * The audio componenent is used to convey the ELD
747 * instead using of the hardware ELD buffer.
748 */
749
750 /* Enable timestamps */
751 intel_de_rmw(i915, regs.aud_config,
752 AUD_CONFIG_N_VALUE_INDEX |
753 AUD_CONFIG_N_PROG_ENABLE |
754 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK,
755 (intel_crtc_has_dp_encoder(crtc_state) ?
756 AUD_CONFIG_N_VALUE_INDEX :
757 audio_config_hdmi_pixel_clock(crtc_state)));
758
759 mutex_unlock(&i915->display.audio.mutex);
760 }
761
intel_audio_sdp_split_update(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)762 void intel_audio_sdp_split_update(struct intel_encoder *encoder,
763 const struct intel_crtc_state *crtc_state)
764 {
765 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
766 enum transcoder trans = crtc_state->cpu_transcoder;
767
768 if (HAS_DP20(i915))
769 intel_de_rmw(i915, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT,
770 crtc_state->sdp_split_enable ? AUD_ENABLE_SDP_SPLIT : 0);
771 }
772
intel_audio_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)773 bool intel_audio_compute_config(struct intel_encoder *encoder,
774 struct intel_crtc_state *crtc_state,
775 struct drm_connector_state *conn_state)
776 {
777 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
778 struct drm_connector *connector = conn_state->connector;
779 const struct drm_display_mode *adjusted_mode =
780 &crtc_state->hw.adjusted_mode;
781
782 if (!connector->eld[0]) {
783 drm_dbg_kms(&i915->drm,
784 "Bogus ELD on [CONNECTOR:%d:%s]\n",
785 connector->base.id, connector->name);
786 return false;
787 }
788
789 BUILD_BUG_ON(sizeof(crtc_state->eld) != sizeof(connector->eld));
790 memcpy(crtc_state->eld, connector->eld, sizeof(crtc_state->eld));
791
792 crtc_state->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
793
794 return true;
795 }
796
797 /**
798 * intel_audio_codec_enable - Enable the audio codec for HD audio
799 * @encoder: encoder on which to enable audio
800 * @crtc_state: pointer to the current crtc state.
801 * @conn_state: pointer to the current connector state.
802 *
803 * The enable sequences may only be performed after enabling the transcoder and
804 * port, and after completed link training.
805 */
intel_audio_codec_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)806 void intel_audio_codec_enable(struct intel_encoder *encoder,
807 const struct intel_crtc_state *crtc_state,
808 const struct drm_connector_state *conn_state)
809 {
810 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
811 struct i915_audio_component *acomp = i915->display.audio.component;
812 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
813 struct intel_connector *connector = to_intel_connector(conn_state->connector);
814 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
815 struct intel_audio_state *audio_state;
816 enum port port = encoder->port;
817
818 if (!crtc_state->has_audio)
819 return;
820
821 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on [CRTC:%d:%s], %u bytes ELD\n",
822 connector->base.base.id, connector->base.name,
823 encoder->base.base.id, encoder->base.name,
824 crtc->base.base.id, crtc->base.name,
825 drm_eld_size(crtc_state->eld));
826
827 if (i915->display.funcs.audio)
828 i915->display.funcs.audio->audio_codec_enable(encoder,
829 crtc_state,
830 conn_state);
831
832 mutex_lock(&i915->display.audio.mutex);
833
834 audio_state = &i915->display.audio.state[cpu_transcoder];
835
836 audio_state->encoder = encoder;
837 BUILD_BUG_ON(sizeof(audio_state->eld) != sizeof(crtc_state->eld));
838 memcpy(audio_state->eld, crtc_state->eld, sizeof(audio_state->eld));
839
840 mutex_unlock(&i915->display.audio.mutex);
841
842 if (acomp && acomp->base.audio_ops &&
843 acomp->base.audio_ops->pin_eld_notify) {
844 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */
845 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
846 cpu_transcoder = -1;
847 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
848 (int)port, (int)cpu_transcoder);
849 }
850
851 intel_lpe_audio_notify(i915, cpu_transcoder, port, crtc_state->eld,
852 crtc_state->port_clock,
853 intel_crtc_has_dp_encoder(crtc_state));
854 }
855
856 /**
857 * intel_audio_codec_disable - Disable the audio codec for HD audio
858 * @encoder: encoder on which to disable audio
859 * @old_crtc_state: pointer to the old crtc state.
860 * @old_conn_state: pointer to the old connector state.
861 *
862 * The disable sequences must be performed before disabling the transcoder or
863 * port.
864 */
intel_audio_codec_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)865 void intel_audio_codec_disable(struct intel_encoder *encoder,
866 const struct intel_crtc_state *old_crtc_state,
867 const struct drm_connector_state *old_conn_state)
868 {
869 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
870 struct i915_audio_component *acomp = i915->display.audio.component;
871 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
872 struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
873 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
874 struct intel_audio_state *audio_state;
875 enum port port = encoder->port;
876
877 if (!old_crtc_state->has_audio)
878 return;
879
880 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on [CRTC:%d:%s]\n",
881 connector->base.base.id, connector->base.name,
882 encoder->base.base.id, encoder->base.name,
883 crtc->base.base.id, crtc->base.name);
884
885 if (i915->display.funcs.audio)
886 i915->display.funcs.audio->audio_codec_disable(encoder,
887 old_crtc_state,
888 old_conn_state);
889
890 mutex_lock(&i915->display.audio.mutex);
891
892 audio_state = &i915->display.audio.state[cpu_transcoder];
893
894 audio_state->encoder = NULL;
895 memset(audio_state->eld, 0, sizeof(audio_state->eld));
896
897 mutex_unlock(&i915->display.audio.mutex);
898
899 if (acomp && acomp->base.audio_ops &&
900 acomp->base.audio_ops->pin_eld_notify) {
901 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */
902 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
903 cpu_transcoder = -1;
904 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
905 (int)port, (int)cpu_transcoder);
906 }
907
908 intel_lpe_audio_notify(i915, cpu_transcoder, port, NULL, 0, false);
909 }
910
intel_acomp_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)911 static void intel_acomp_get_config(struct intel_encoder *encoder,
912 struct intel_crtc_state *crtc_state)
913 {
914 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
915 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
916 struct intel_audio_state *audio_state;
917
918 mutex_lock(&i915->display.audio.mutex);
919
920 audio_state = &i915->display.audio.state[cpu_transcoder];
921
922 if (audio_state->encoder)
923 memcpy(crtc_state->eld, audio_state->eld, sizeof(audio_state->eld));
924
925 mutex_unlock(&i915->display.audio.mutex);
926 }
927
intel_audio_codec_get_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)928 void intel_audio_codec_get_config(struct intel_encoder *encoder,
929 struct intel_crtc_state *crtc_state)
930 {
931 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
932
933 if (!crtc_state->has_audio)
934 return;
935
936 if (i915->display.funcs.audio)
937 i915->display.funcs.audio->audio_codec_get_config(encoder, crtc_state);
938 }
939
940 static const struct intel_audio_funcs g4x_audio_funcs = {
941 .audio_codec_enable = g4x_audio_codec_enable,
942 .audio_codec_disable = g4x_audio_codec_disable,
943 .audio_codec_get_config = g4x_audio_codec_get_config,
944 };
945
946 static const struct intel_audio_funcs ibx_audio_funcs = {
947 .audio_codec_enable = ibx_audio_codec_enable,
948 .audio_codec_disable = ibx_audio_codec_disable,
949 .audio_codec_get_config = intel_acomp_get_config,
950 };
951
952 static const struct intel_audio_funcs hsw_audio_funcs = {
953 .audio_codec_enable = hsw_audio_codec_enable,
954 .audio_codec_disable = hsw_audio_codec_disable,
955 .audio_codec_get_config = intel_acomp_get_config,
956 };
957
958 /**
959 * intel_audio_hooks_init - Set up chip specific audio hooks
960 * @i915: device private
961 */
intel_audio_hooks_init(struct drm_i915_private * i915)962 void intel_audio_hooks_init(struct drm_i915_private *i915)
963 {
964 if (IS_G4X(i915))
965 i915->display.funcs.audio = &g4x_audio_funcs;
966 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915) ||
967 HAS_PCH_CPT(i915) || HAS_PCH_IBX(i915))
968 i915->display.funcs.audio = &ibx_audio_funcs;
969 else if (IS_HASWELL(i915) || DISPLAY_VER(i915) >= 8)
970 i915->display.funcs.audio = &hsw_audio_funcs;
971 }
972
973 struct aud_ts_cdclk_m_n {
974 u8 m;
975 u16 n;
976 };
977
intel_audio_cdclk_change_pre(struct drm_i915_private * i915)978 void intel_audio_cdclk_change_pre(struct drm_i915_private *i915)
979 {
980 if (DISPLAY_VER(i915) >= 13)
981 intel_de_rmw(i915, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0);
982 }
983
get_aud_ts_cdclk_m_n(int refclk,int cdclk,struct aud_ts_cdclk_m_n * aud_ts)984 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts)
985 {
986 aud_ts->m = 60;
987 aud_ts->n = cdclk * aud_ts->m / 24000;
988 }
989
intel_audio_cdclk_change_post(struct drm_i915_private * i915)990 void intel_audio_cdclk_change_post(struct drm_i915_private *i915)
991 {
992 struct aud_ts_cdclk_m_n aud_ts;
993
994 if (DISPLAY_VER(i915) >= 13) {
995 get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts);
996
997 intel_de_write(i915, AUD_TS_CDCLK_N, aud_ts.n);
998 intel_de_write(i915, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN);
999 drm_dbg_kms(&i915->drm, "aud_ts_cdclk set to M=%u, N=%u\n", aud_ts.m, aud_ts.n);
1000 }
1001 }
1002
glk_force_audio_cdclk_commit(struct intel_atomic_state * state,struct intel_crtc * crtc,bool enable)1003 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state,
1004 struct intel_crtc *crtc,
1005 bool enable)
1006 {
1007 struct intel_cdclk_state *cdclk_state;
1008 int ret;
1009
1010 /* need to hold at least one crtc lock for the global state */
1011 ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx);
1012 if (ret)
1013 return ret;
1014
1015 cdclk_state = intel_atomic_get_cdclk_state(state);
1016 if (IS_ERR(cdclk_state))
1017 return PTR_ERR(cdclk_state);
1018
1019 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0;
1020
1021 return drm_atomic_commit(&state->base);
1022 }
1023
glk_force_audio_cdclk(struct drm_i915_private * i915,bool enable)1024 static void glk_force_audio_cdclk(struct drm_i915_private *i915,
1025 bool enable)
1026 {
1027 struct drm_modeset_acquire_ctx ctx;
1028 struct drm_atomic_state *state;
1029 struct intel_crtc *crtc;
1030 int ret;
1031
1032 crtc = intel_first_crtc(i915);
1033 if (!crtc)
1034 return;
1035
1036 drm_modeset_acquire_init(&ctx, 0);
1037 state = drm_atomic_state_alloc(&i915->drm);
1038 if (drm_WARN_ON(&i915->drm, !state))
1039 return;
1040
1041 state->acquire_ctx = &ctx;
1042 to_intel_atomic_state(state)->internal = true;
1043
1044 retry:
1045 ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc,
1046 enable);
1047 if (ret == -EDEADLK) {
1048 drm_atomic_state_clear(state);
1049 drm_modeset_backoff(&ctx);
1050 goto retry;
1051 }
1052
1053 drm_WARN_ON(&i915->drm, ret);
1054
1055 drm_atomic_state_put(state);
1056
1057 drm_modeset_drop_locks(&ctx);
1058 drm_modeset_acquire_fini(&ctx);
1059 }
1060
i915_audio_component_get_power(struct device * kdev)1061 static unsigned long i915_audio_component_get_power(struct device *kdev)
1062 {
1063 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1064 intel_wakeref_t ret;
1065
1066 /* Catch potential impedance mismatches before they occur! */
1067 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
1068
1069 ret = intel_display_power_get(i915, POWER_DOMAIN_AUDIO_PLAYBACK);
1070
1071 if (i915->display.audio.power_refcount++ == 0) {
1072 if (DISPLAY_VER(i915) >= 9) {
1073 intel_de_write(i915, AUD_FREQ_CNTRL,
1074 i915->display.audio.freq_cntrl);
1075 drm_dbg_kms(&i915->drm,
1076 "restored AUD_FREQ_CNTRL to 0x%x\n",
1077 i915->display.audio.freq_cntrl);
1078 }
1079
1080 /* Force CDCLK to 2*BCLK as long as we need audio powered. */
1081 if (IS_GEMINILAKE(i915))
1082 glk_force_audio_cdclk(i915, true);
1083
1084 if (DISPLAY_VER(i915) >= 10)
1085 intel_de_rmw(i915, AUD_PIN_BUF_CTL,
1086 0, AUD_PIN_BUF_ENABLE);
1087 }
1088
1089 return ret;
1090 }
1091
i915_audio_component_put_power(struct device * kdev,unsigned long cookie)1092 static void i915_audio_component_put_power(struct device *kdev,
1093 unsigned long cookie)
1094 {
1095 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1096
1097 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
1098 if (--i915->display.audio.power_refcount == 0)
1099 if (IS_GEMINILAKE(i915))
1100 glk_force_audio_cdclk(i915, false);
1101
1102 intel_display_power_put(i915, POWER_DOMAIN_AUDIO_PLAYBACK, cookie);
1103 }
1104
i915_audio_component_codec_wake_override(struct device * kdev,bool enable)1105 static void i915_audio_component_codec_wake_override(struct device *kdev,
1106 bool enable)
1107 {
1108 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1109 unsigned long cookie;
1110
1111 if (DISPLAY_VER(i915) < 9)
1112 return;
1113
1114 cookie = i915_audio_component_get_power(kdev);
1115
1116 /*
1117 * Enable/disable generating the codec wake signal, overriding the
1118 * internal logic to generate the codec wake to controller.
1119 */
1120 intel_de_rmw(i915, HSW_AUD_CHICKENBIT,
1121 SKL_AUD_CODEC_WAKE_SIGNAL, 0);
1122 usleep_range(1000, 1500);
1123
1124 if (enable) {
1125 intel_de_rmw(i915, HSW_AUD_CHICKENBIT,
1126 0, SKL_AUD_CODEC_WAKE_SIGNAL);
1127 usleep_range(1000, 1500);
1128 }
1129
1130 i915_audio_component_put_power(kdev, cookie);
1131 }
1132
1133 /* Get CDCLK in kHz */
i915_audio_component_get_cdclk_freq(struct device * kdev)1134 static int i915_audio_component_get_cdclk_freq(struct device *kdev)
1135 {
1136 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1137
1138 if (drm_WARN_ON_ONCE(&i915->drm, !HAS_DDI(i915)))
1139 return -ENODEV;
1140
1141 return i915->display.cdclk.hw.cdclk;
1142 }
1143
1144 /*
1145 * get the intel audio state according to the parameter port and cpu_transcoder
1146 * MST & (cpu_transcoder >= 0): return the audio.state[cpu_transcoder].encoder],
1147 * when port is matched
1148 * MST & (cpu_transcoder < 0): this is invalid
1149 * Non-MST & (cpu_transcoder >= 0): only cpu_transcoder = 0 (the first device entry)
1150 * will get the right intel_encoder with port matched
1151 * Non-MST & (cpu_transcoder < 0): get the right intel_encoder with port matched
1152 */
find_audio_state(struct drm_i915_private * i915,int port,int cpu_transcoder)1153 static struct intel_audio_state *find_audio_state(struct drm_i915_private *i915,
1154 int port, int cpu_transcoder)
1155 {
1156 /* MST */
1157 if (cpu_transcoder >= 0) {
1158 struct intel_audio_state *audio_state;
1159 struct intel_encoder *encoder;
1160
1161 if (drm_WARN_ON(&i915->drm,
1162 cpu_transcoder >= ARRAY_SIZE(i915->display.audio.state)))
1163 return NULL;
1164
1165 audio_state = &i915->display.audio.state[cpu_transcoder];
1166 encoder = audio_state->encoder;
1167
1168 if (encoder && encoder->port == port &&
1169 encoder->type == INTEL_OUTPUT_DP_MST)
1170 return audio_state;
1171 }
1172
1173 /* Non-MST */
1174 if (cpu_transcoder > 0)
1175 return NULL;
1176
1177 for_each_cpu_transcoder(i915, cpu_transcoder) {
1178 struct intel_audio_state *audio_state;
1179 struct intel_encoder *encoder;
1180
1181 audio_state = &i915->display.audio.state[cpu_transcoder];
1182 encoder = audio_state->encoder;
1183
1184 if (encoder && encoder->port == port &&
1185 encoder->type != INTEL_OUTPUT_DP_MST)
1186 return audio_state;
1187 }
1188
1189 return NULL;
1190 }
1191
i915_audio_component_sync_audio_rate(struct device * kdev,int port,int cpu_transcoder,int rate)1192 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
1193 int cpu_transcoder, int rate)
1194 {
1195 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1196 struct i915_audio_component *acomp = i915->display.audio.component;
1197 const struct intel_audio_state *audio_state;
1198 struct intel_encoder *encoder;
1199 struct intel_crtc *crtc;
1200 unsigned long cookie;
1201 int err = 0;
1202
1203 if (!HAS_DDI(i915))
1204 return 0;
1205
1206 cookie = i915_audio_component_get_power(kdev);
1207 mutex_lock(&i915->display.audio.mutex);
1208
1209 audio_state = find_audio_state(i915, port, cpu_transcoder);
1210 if (!audio_state) {
1211 drm_dbg_kms(&i915->drm, "Not valid for port %c\n", port_name(port));
1212 err = -ENODEV;
1213 goto unlock;
1214 }
1215
1216 encoder = audio_state->encoder;
1217
1218 /* FIXME stop using the legacy crtc pointer */
1219 crtc = to_intel_crtc(encoder->base.crtc);
1220
1221 /* port must be valid now, otherwise the cpu_transcoder will be invalid */
1222 acomp->aud_sample_rate[port] = rate;
1223
1224 /* FIXME get rid of the crtc->config stuff */
1225 hsw_audio_config_update(encoder, crtc->config);
1226
1227 unlock:
1228 mutex_unlock(&i915->display.audio.mutex);
1229 i915_audio_component_put_power(kdev, cookie);
1230 return err;
1231 }
1232
i915_audio_component_get_eld(struct device * kdev,int port,int cpu_transcoder,bool * enabled,unsigned char * buf,int max_bytes)1233 static int i915_audio_component_get_eld(struct device *kdev, int port,
1234 int cpu_transcoder, bool *enabled,
1235 unsigned char *buf, int max_bytes)
1236 {
1237 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1238 const struct intel_audio_state *audio_state;
1239 int ret = 0;
1240
1241 mutex_lock(&i915->display.audio.mutex);
1242
1243 audio_state = find_audio_state(i915, port, cpu_transcoder);
1244 if (!audio_state) {
1245 drm_dbg_kms(&i915->drm, "Not valid for port %c\n", port_name(port));
1246 mutex_unlock(&i915->display.audio.mutex);
1247 return -EINVAL;
1248 }
1249
1250 *enabled = audio_state->encoder != NULL;
1251 if (*enabled) {
1252 const u8 *eld = audio_state->eld;
1253
1254 ret = drm_eld_size(eld);
1255 memcpy(buf, eld, min(max_bytes, ret));
1256 }
1257
1258 mutex_unlock(&i915->display.audio.mutex);
1259 return ret;
1260 }
1261
1262 static const struct drm_audio_component_ops i915_audio_component_ops = {
1263 .owner = THIS_MODULE,
1264 .get_power = i915_audio_component_get_power,
1265 .put_power = i915_audio_component_put_power,
1266 .codec_wake_override = i915_audio_component_codec_wake_override,
1267 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
1268 .sync_audio_rate = i915_audio_component_sync_audio_rate,
1269 .get_eld = i915_audio_component_get_eld,
1270 };
1271
i915_audio_component_bind(struct device * i915_kdev,struct device * hda_kdev,void * data)1272 static int i915_audio_component_bind(struct device *i915_kdev,
1273 struct device *hda_kdev, void *data)
1274 {
1275 struct i915_audio_component *acomp = data;
1276 struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
1277 int i;
1278
1279 if (drm_WARN_ON(&i915->drm, acomp->base.ops || acomp->base.dev))
1280 return -EEXIST;
1281
1282 if (drm_WARN_ON(&i915->drm,
1283 !device_link_add(hda_kdev, i915_kdev,
1284 DL_FLAG_STATELESS)))
1285 return -ENOMEM;
1286
1287 drm_modeset_lock_all(&i915->drm);
1288 acomp->base.ops = &i915_audio_component_ops;
1289 acomp->base.dev = i915_kdev;
1290 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
1291 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
1292 acomp->aud_sample_rate[i] = 0;
1293 i915->display.audio.component = acomp;
1294 drm_modeset_unlock_all(&i915->drm);
1295
1296 return 0;
1297 }
1298
i915_audio_component_unbind(struct device * i915_kdev,struct device * hda_kdev,void * data)1299 static void i915_audio_component_unbind(struct device *i915_kdev,
1300 struct device *hda_kdev, void *data)
1301 {
1302 struct i915_audio_component *acomp = data;
1303 struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
1304
1305 drm_modeset_lock_all(&i915->drm);
1306 acomp->base.ops = NULL;
1307 acomp->base.dev = NULL;
1308 i915->display.audio.component = NULL;
1309 drm_modeset_unlock_all(&i915->drm);
1310
1311 device_link_remove(hda_kdev, i915_kdev);
1312
1313 if (i915->display.audio.power_refcount)
1314 drm_err(&i915->drm, "audio power refcount %d after unbind\n",
1315 i915->display.audio.power_refcount);
1316 }
1317
1318 static const struct component_ops i915_audio_component_bind_ops = {
1319 .bind = i915_audio_component_bind,
1320 .unbind = i915_audio_component_unbind,
1321 };
1322
1323 #define AUD_FREQ_TMODE_SHIFT 14
1324 #define AUD_FREQ_4T 0
1325 #define AUD_FREQ_8T (2 << AUD_FREQ_TMODE_SHIFT)
1326 #define AUD_FREQ_PULLCLKS(x) (((x) & 0x3) << 11)
1327 #define AUD_FREQ_BCLK_96M BIT(4)
1328
1329 #define AUD_FREQ_GEN12 (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M)
1330 #define AUD_FREQ_TGL_BROKEN (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M)
1331
1332 /**
1333 * i915_audio_component_init - initialize and register the audio component
1334 * @i915: i915 device instance
1335 *
1336 * This will register with the component framework a child component which
1337 * will bind dynamically to the snd_hda_intel driver's corresponding master
1338 * component when the latter is registered. During binding the child
1339 * initializes an instance of struct i915_audio_component which it receives
1340 * from the master. The master can then start to use the interface defined by
1341 * this struct. Each side can break the binding at any point by deregistering
1342 * its own component after which each side's component unbind callback is
1343 * called.
1344 *
1345 * We ignore any error during registration and continue with reduced
1346 * functionality (i.e. without HDMI audio).
1347 */
i915_audio_component_init(struct drm_i915_private * i915)1348 static void i915_audio_component_init(struct drm_i915_private *i915)
1349 {
1350 u32 aud_freq, aud_freq_init;
1351 int ret;
1352
1353 ret = component_add_typed(i915->drm.dev,
1354 &i915_audio_component_bind_ops,
1355 I915_COMPONENT_AUDIO);
1356 if (ret < 0) {
1357 drm_err(&i915->drm,
1358 "failed to add audio component (%d)\n", ret);
1359 /* continue with reduced functionality */
1360 return;
1361 }
1362
1363 if (DISPLAY_VER(i915) >= 9) {
1364 aud_freq_init = intel_de_read(i915, AUD_FREQ_CNTRL);
1365
1366 if (DISPLAY_VER(i915) >= 12)
1367 aud_freq = AUD_FREQ_GEN12;
1368 else
1369 aud_freq = aud_freq_init;
1370
1371 /* use BIOS provided value for TGL and RKL unless it is a known bad value */
1372 if ((IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) &&
1373 aud_freq_init != AUD_FREQ_TGL_BROKEN)
1374 aud_freq = aud_freq_init;
1375
1376 drm_dbg_kms(&i915->drm, "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n",
1377 aud_freq, aud_freq_init);
1378
1379 i915->display.audio.freq_cntrl = aud_freq;
1380 }
1381
1382 /* init with current cdclk */
1383 intel_audio_cdclk_change_post(i915);
1384
1385 i915->display.audio.component_registered = true;
1386 }
1387
1388 /**
1389 * i915_audio_component_cleanup - deregister the audio component
1390 * @i915: i915 device instance
1391 *
1392 * Deregisters the audio component, breaking any existing binding to the
1393 * corresponding snd_hda_intel driver's master component.
1394 */
i915_audio_component_cleanup(struct drm_i915_private * i915)1395 static void i915_audio_component_cleanup(struct drm_i915_private *i915)
1396 {
1397 if (!i915->display.audio.component_registered)
1398 return;
1399
1400 component_del(i915->drm.dev, &i915_audio_component_bind_ops);
1401 i915->display.audio.component_registered = false;
1402 }
1403
1404 /**
1405 * intel_audio_init() - Initialize the audio driver either using
1406 * component framework or using lpe audio bridge
1407 * @i915: the i915 drm device private data
1408 *
1409 */
intel_audio_init(struct drm_i915_private * i915)1410 void intel_audio_init(struct drm_i915_private *i915)
1411 {
1412 if (intel_lpe_audio_init(i915) < 0)
1413 i915_audio_component_init(i915);
1414 }
1415
1416 /**
1417 * intel_audio_deinit() - deinitialize the audio driver
1418 * @i915: the i915 drm device private data
1419 *
1420 */
intel_audio_deinit(struct drm_i915_private * i915)1421 void intel_audio_deinit(struct drm_i915_private *i915)
1422 {
1423 if (i915->display.audio.lpe.platdev != NULL)
1424 intel_lpe_audio_teardown(i915);
1425 else
1426 i915_audio_component_cleanup(i915);
1427 }
1428
