1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2016 Broadcom Corporation
3 *
4 * This file contains the Northstar2 IOMUX driver that supports group
5 * based PINMUX configuration. The PWM is functional only when the
6 * corresponding mfio pin group is selected as gpio.
7 */
8
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/of.h>
12 #include <linux/pinctrl/pinconf.h>
13 #include <linux/pinctrl/pinconf-generic.h>
14 #include <linux/pinctrl/pinctrl.h>
15 #include <linux/pinctrl/pinmux.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
18
19 #include "../core.h"
20 #include "../pinctrl-utils.h"
21
22 #define NS2_NUM_IOMUX 19
23 #define NS2_NUM_PWM_MUX 4
24
25 #define NS2_PIN_MUX_BASE0 0x00
26 #define NS2_PIN_MUX_BASE1 0x01
27 #define NS2_PIN_CONF_BASE 0x02
28 #define NS2_MUX_PAD_FUNC1_OFFSET 0x04
29
30 #define NS2_PIN_SRC_MASK 0x01
31 #define NS2_PIN_PULL_MASK 0x03
32 #define NS2_PIN_DRIVE_STRENGTH_MASK 0x07
33
34 #define NS2_PIN_PULL_UP 0x01
35 #define NS2_PIN_PULL_DOWN 0x02
36
37 #define NS2_PIN_INPUT_EN_MASK 0x01
38
39 /*
40 * Northstar2 IOMUX register description
41 *
42 * @base: base address number
43 * @offset: register offset for mux configuration of a group
44 * @shift: bit shift for mux configuration of a group
45 * @mask: mask bits
46 * @alt: alternate function to set to
47 */
48 struct ns2_mux {
49 unsigned int base;
50 unsigned int offset;
51 unsigned int shift;
52 unsigned int mask;
53 unsigned int alt;
54 };
55
56 /*
57 * Keep track of Northstar2 IOMUX configuration and prevent double
58 * configuration
59 *
60 * @ns2_mux: Northstar2 IOMUX register description
61 * @is_configured: flag to indicate whether a mux setting has already
62 * been configured
63 */
64 struct ns2_mux_log {
65 struct ns2_mux mux;
66 bool is_configured;
67 };
68
69 /*
70 * Group based IOMUX configuration
71 *
72 * @name: name of the group
73 * @pins: array of pins used by this group
74 * @num_pins: total number of pins used by this group
75 * @mux: Northstar2 group based IOMUX configuration
76 */
77 struct ns2_pin_group {
78 const char *name;
79 const unsigned int *pins;
80 const unsigned int num_pins;
81 const struct ns2_mux mux;
82 };
83
84 /*
85 * Northstar2 mux function and supported pin groups
86 *
87 * @name: name of the function
88 * @groups: array of groups that can be supported by this function
89 * @num_groups: total number of groups that can be supported by function
90 */
91 struct ns2_pin_function {
92 const char *name;
93 const char * const *groups;
94 const unsigned int num_groups;
95 };
96
97 /*
98 * Northstar2 IOMUX pinctrl core
99 *
100 * @pctl: pointer to pinctrl_dev
101 * @dev: pointer to device
102 * @base0: first IOMUX register base
103 * @base1: second IOMUX register base
104 * @pinconf_base: configuration register base
105 * @groups: pointer to array of groups
106 * @num_groups: total number of groups
107 * @functions: pointer to array of functions
108 * @num_functions: total number of functions
109 * @mux_log: pointer to the array of mux logs
110 * @lock: lock to protect register access
111 */
112 struct ns2_pinctrl {
113 struct pinctrl_dev *pctl;
114 struct device *dev;
115 void __iomem *base0;
116 void __iomem *base1;
117 void __iomem *pinconf_base;
118
119 const struct ns2_pin_group *groups;
120 unsigned int num_groups;
121
122 const struct ns2_pin_function *functions;
123 unsigned int num_functions;
124
125 struct ns2_mux_log *mux_log;
126
127 spinlock_t lock;
128 };
129
130 /*
131 * Pin configuration info
132 *
133 * @base: base address number
134 * @offset: register offset from base
135 * @src_shift: slew rate control bit shift in the register
136 * @input_en: input enable control bit shift
137 * @pull_shift: pull-up/pull-down control bit shift in the register
138 * @drive_shift: drive strength control bit shift in the register
139 */
140 struct ns2_pinconf {
141 unsigned int base;
142 unsigned int offset;
143 unsigned int src_shift;
144 unsigned int input_en;
145 unsigned int pull_shift;
146 unsigned int drive_shift;
147 };
148
149 /*
150 * Description of a pin in Northstar2
151 *
152 * @pin: pin number
153 * @name: pin name
154 * @pin_conf: pin configuration structure
155 */
156 struct ns2_pin {
157 unsigned int pin;
158 char *name;
159 struct ns2_pinconf pin_conf;
160 };
161
162 #define NS2_PIN_DESC(p, n, b, o, s, i, pu, d) \
163 { \
164 .pin = p, \
165 .name = n, \
166 .pin_conf = { \
167 .base = b, \
168 .offset = o, \
169 .src_shift = s, \
170 .input_en = i, \
171 .pull_shift = pu, \
172 .drive_shift = d, \
173 } \
174 }
175
176 /*
177 * List of pins in Northstar2
178 */
179 static struct ns2_pin ns2_pins[] = {
180 NS2_PIN_DESC(0, "mfio_0", -1, 0, 0, 0, 0, 0),
181 NS2_PIN_DESC(1, "mfio_1", -1, 0, 0, 0, 0, 0),
182 NS2_PIN_DESC(2, "mfio_2", -1, 0, 0, 0, 0, 0),
183 NS2_PIN_DESC(3, "mfio_3", -1, 0, 0, 0, 0, 0),
184 NS2_PIN_DESC(4, "mfio_4", -1, 0, 0, 0, 0, 0),
185 NS2_PIN_DESC(5, "mfio_5", -1, 0, 0, 0, 0, 0),
186 NS2_PIN_DESC(6, "mfio_6", -1, 0, 0, 0, 0, 0),
187 NS2_PIN_DESC(7, "mfio_7", -1, 0, 0, 0, 0, 0),
188 NS2_PIN_DESC(8, "mfio_8", -1, 0, 0, 0, 0, 0),
189 NS2_PIN_DESC(9, "mfio_9", -1, 0, 0, 0, 0, 0),
190 NS2_PIN_DESC(10, "mfio_10", -1, 0, 0, 0, 0, 0),
191 NS2_PIN_DESC(11, "mfio_11", -1, 0, 0, 0, 0, 0),
192 NS2_PIN_DESC(12, "mfio_12", -1, 0, 0, 0, 0, 0),
193 NS2_PIN_DESC(13, "mfio_13", -1, 0, 0, 0, 0, 0),
194 NS2_PIN_DESC(14, "mfio_14", -1, 0, 0, 0, 0, 0),
195 NS2_PIN_DESC(15, "mfio_15", -1, 0, 0, 0, 0, 0),
196 NS2_PIN_DESC(16, "mfio_16", -1, 0, 0, 0, 0, 0),
197 NS2_PIN_DESC(17, "mfio_17", -1, 0, 0, 0, 0, 0),
198 NS2_PIN_DESC(18, "mfio_18", -1, 0, 0, 0, 0, 0),
199 NS2_PIN_DESC(19, "mfio_19", -1, 0, 0, 0, 0, 0),
200 NS2_PIN_DESC(20, "mfio_20", -1, 0, 0, 0, 0, 0),
201 NS2_PIN_DESC(21, "mfio_21", -1, 0, 0, 0, 0, 0),
202 NS2_PIN_DESC(22, "mfio_22", -1, 0, 0, 0, 0, 0),
203 NS2_PIN_DESC(23, "mfio_23", -1, 0, 0, 0, 0, 0),
204 NS2_PIN_DESC(24, "mfio_24", -1, 0, 0, 0, 0, 0),
205 NS2_PIN_DESC(25, "mfio_25", -1, 0, 0, 0, 0, 0),
206 NS2_PIN_DESC(26, "mfio_26", -1, 0, 0, 0, 0, 0),
207 NS2_PIN_DESC(27, "mfio_27", -1, 0, 0, 0, 0, 0),
208 NS2_PIN_DESC(28, "mfio_28", -1, 0, 0, 0, 0, 0),
209 NS2_PIN_DESC(29, "mfio_29", -1, 0, 0, 0, 0, 0),
210 NS2_PIN_DESC(30, "mfio_30", -1, 0, 0, 0, 0, 0),
211 NS2_PIN_DESC(31, "mfio_31", -1, 0, 0, 0, 0, 0),
212 NS2_PIN_DESC(32, "mfio_32", -1, 0, 0, 0, 0, 0),
213 NS2_PIN_DESC(33, "mfio_33", -1, 0, 0, 0, 0, 0),
214 NS2_PIN_DESC(34, "mfio_34", -1, 0, 0, 0, 0, 0),
215 NS2_PIN_DESC(35, "mfio_35", -1, 0, 0, 0, 0, 0),
216 NS2_PIN_DESC(36, "mfio_36", -1, 0, 0, 0, 0, 0),
217 NS2_PIN_DESC(37, "mfio_37", -1, 0, 0, 0, 0, 0),
218 NS2_PIN_DESC(38, "mfio_38", -1, 0, 0, 0, 0, 0),
219 NS2_PIN_DESC(39, "mfio_39", -1, 0, 0, 0, 0, 0),
220 NS2_PIN_DESC(40, "mfio_40", -1, 0, 0, 0, 0, 0),
221 NS2_PIN_DESC(41, "mfio_41", -1, 0, 0, 0, 0, 0),
222 NS2_PIN_DESC(42, "mfio_42", -1, 0, 0, 0, 0, 0),
223 NS2_PIN_DESC(43, "mfio_43", -1, 0, 0, 0, 0, 0),
224 NS2_PIN_DESC(44, "mfio_44", -1, 0, 0, 0, 0, 0),
225 NS2_PIN_DESC(45, "mfio_45", -1, 0, 0, 0, 0, 0),
226 NS2_PIN_DESC(46, "mfio_46", -1, 0, 0, 0, 0, 0),
227 NS2_PIN_DESC(47, "mfio_47", -1, 0, 0, 0, 0, 0),
228 NS2_PIN_DESC(48, "mfio_48", -1, 0, 0, 0, 0, 0),
229 NS2_PIN_DESC(49, "mfio_49", -1, 0, 0, 0, 0, 0),
230 NS2_PIN_DESC(50, "mfio_50", -1, 0, 0, 0, 0, 0),
231 NS2_PIN_DESC(51, "mfio_51", -1, 0, 0, 0, 0, 0),
232 NS2_PIN_DESC(52, "mfio_52", -1, 0, 0, 0, 0, 0),
233 NS2_PIN_DESC(53, "mfio_53", -1, 0, 0, 0, 0, 0),
234 NS2_PIN_DESC(54, "mfio_54", -1, 0, 0, 0, 0, 0),
235 NS2_PIN_DESC(55, "mfio_55", -1, 0, 0, 0, 0, 0),
236 NS2_PIN_DESC(56, "mfio_56", -1, 0, 0, 0, 0, 0),
237 NS2_PIN_DESC(57, "mfio_57", -1, 0, 0, 0, 0, 0),
238 NS2_PIN_DESC(58, "mfio_58", -1, 0, 0, 0, 0, 0),
239 NS2_PIN_DESC(59, "mfio_59", -1, 0, 0, 0, 0, 0),
240 NS2_PIN_DESC(60, "mfio_60", -1, 0, 0, 0, 0, 0),
241 NS2_PIN_DESC(61, "mfio_61", -1, 0, 0, 0, 0, 0),
242 NS2_PIN_DESC(62, "mfio_62", -1, 0, 0, 0, 0, 0),
243 NS2_PIN_DESC(63, "qspi_wp", 2, 0x0, 31, 30, 27, 24),
244 NS2_PIN_DESC(64, "qspi_hold", 2, 0x0, 23, 22, 19, 16),
245 NS2_PIN_DESC(65, "qspi_cs", 2, 0x0, 15, 14, 11, 8),
246 NS2_PIN_DESC(66, "qspi_sck", 2, 0x0, 7, 6, 3, 0),
247 NS2_PIN_DESC(67, "uart3_sin", 2, 0x04, 31, 30, 27, 24),
248 NS2_PIN_DESC(68, "uart3_sout", 2, 0x04, 23, 22, 19, 16),
249 NS2_PIN_DESC(69, "qspi_mosi", 2, 0x04, 15, 14, 11, 8),
250 NS2_PIN_DESC(70, "qspi_miso", 2, 0x04, 7, 6, 3, 0),
251 NS2_PIN_DESC(71, "spi0_fss", 2, 0x08, 31, 30, 27, 24),
252 NS2_PIN_DESC(72, "spi0_rxd", 2, 0x08, 23, 22, 19, 16),
253 NS2_PIN_DESC(73, "spi0_txd", 2, 0x08, 15, 14, 11, 8),
254 NS2_PIN_DESC(74, "spi0_sck", 2, 0x08, 7, 6, 3, 0),
255 NS2_PIN_DESC(75, "spi1_fss", 2, 0x0c, 31, 30, 27, 24),
256 NS2_PIN_DESC(76, "spi1_rxd", 2, 0x0c, 23, 22, 19, 16),
257 NS2_PIN_DESC(77, "spi1_txd", 2, 0x0c, 15, 14, 11, 8),
258 NS2_PIN_DESC(78, "spi1_sck", 2, 0x0c, 7, 6, 3, 0),
259 NS2_PIN_DESC(79, "sdio0_data7", 2, 0x10, 31, 30, 27, 24),
260 NS2_PIN_DESC(80, "sdio0_emmc_rst", 2, 0x10, 23, 22, 19, 16),
261 NS2_PIN_DESC(81, "sdio0_led_on", 2, 0x10, 15, 14, 11, 8),
262 NS2_PIN_DESC(82, "sdio0_wp", 2, 0x10, 7, 6, 3, 0),
263 NS2_PIN_DESC(83, "sdio0_data3", 2, 0x14, 31, 30, 27, 24),
264 NS2_PIN_DESC(84, "sdio0_data4", 2, 0x14, 23, 22, 19, 16),
265 NS2_PIN_DESC(85, "sdio0_data5", 2, 0x14, 15, 14, 11, 8),
266 NS2_PIN_DESC(86, "sdio0_data6", 2, 0x14, 7, 6, 3, 0),
267 NS2_PIN_DESC(87, "sdio0_cmd", 2, 0x18, 31, 30, 27, 24),
268 NS2_PIN_DESC(88, "sdio0_data0", 2, 0x18, 23, 22, 19, 16),
269 NS2_PIN_DESC(89, "sdio0_data1", 2, 0x18, 15, 14, 11, 8),
270 NS2_PIN_DESC(90, "sdio0_data2", 2, 0x18, 7, 6, 3, 0),
271 NS2_PIN_DESC(91, "sdio1_led_on", 2, 0x1c, 31, 30, 27, 24),
272 NS2_PIN_DESC(92, "sdio1_wp", 2, 0x1c, 23, 22, 19, 16),
273 NS2_PIN_DESC(93, "sdio0_cd_l", 2, 0x1c, 15, 14, 11, 8),
274 NS2_PIN_DESC(94, "sdio0_clk", 2, 0x1c, 7, 6, 3, 0),
275 NS2_PIN_DESC(95, "sdio1_data5", 2, 0x20, 31, 30, 27, 24),
276 NS2_PIN_DESC(96, "sdio1_data6", 2, 0x20, 23, 22, 19, 16),
277 NS2_PIN_DESC(97, "sdio1_data7", 2, 0x20, 15, 14, 11, 8),
278 NS2_PIN_DESC(98, "sdio1_emmc_rst", 2, 0x20, 7, 6, 3, 0),
279 NS2_PIN_DESC(99, "sdio1_data1", 2, 0x24, 31, 30, 27, 24),
280 NS2_PIN_DESC(100, "sdio1_data2", 2, 0x24, 23, 22, 19, 16),
281 NS2_PIN_DESC(101, "sdio1_data3", 2, 0x24, 15, 14, 11, 8),
282 NS2_PIN_DESC(102, "sdio1_data4", 2, 0x24, 7, 6, 3, 0),
283 NS2_PIN_DESC(103, "sdio1_cd_l", 2, 0x28, 31, 30, 27, 24),
284 NS2_PIN_DESC(104, "sdio1_clk", 2, 0x28, 23, 22, 19, 16),
285 NS2_PIN_DESC(105, "sdio1_cmd", 2, 0x28, 15, 14, 11, 8),
286 NS2_PIN_DESC(106, "sdio1_data0", 2, 0x28, 7, 6, 3, 0),
287 NS2_PIN_DESC(107, "ext_mdio_0", 2, 0x2c, 15, 14, 11, 8),
288 NS2_PIN_DESC(108, "ext_mdc_0", 2, 0x2c, 7, 6, 3, 0),
289 NS2_PIN_DESC(109, "usb3_p1_vbus_ppc", 2, 0x34, 31, 30, 27, 24),
290 NS2_PIN_DESC(110, "usb3_p1_overcurrent", 2, 0x34, 23, 22, 19, 16),
291 NS2_PIN_DESC(111, "usb3_p0_vbus_ppc", 2, 0x34, 15, 14, 11, 8),
292 NS2_PIN_DESC(112, "usb3_p0_overcurrent", 2, 0x34, 7, 6, 3, 0),
293 NS2_PIN_DESC(113, "usb2_presence_indication", 2, 0x38, 31, 30, 27, 24),
294 NS2_PIN_DESC(114, "usb2_vbus_present", 2, 0x38, 23, 22, 19, 16),
295 NS2_PIN_DESC(115, "usb2_vbus_ppc", 2, 0x38, 15, 14, 11, 8),
296 NS2_PIN_DESC(116, "usb2_overcurrent", 2, 0x38, 7, 6, 3, 0),
297 NS2_PIN_DESC(117, "sata_led1", 2, 0x3c, 15, 14, 11, 8),
298 NS2_PIN_DESC(118, "sata_led0", 2, 0x3c, 7, 6, 3, 0),
299 };
300
301 /*
302 * List of groups of pins
303 */
304
305 static const unsigned int nand_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
306 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23};
307 static const unsigned int nor_data_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
308 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25};
309
310 static const unsigned int gpio_0_1_pins[] = {24, 25};
311 static const unsigned int pwm_0_pins[] = {24};
312 static const unsigned int pwm_1_pins[] = {25};
313
314 static const unsigned int uart1_ext_clk_pins[] = {26};
315 static const unsigned int nor_adv_pins[] = {26};
316
317 static const unsigned int gpio_2_5_pins[] = {27, 28, 29, 30};
318 static const unsigned int pcie_ab1_clk_wak_pins[] = {27, 28, 29, 30};
319 static const unsigned int nor_addr_0_3_pins[] = {27, 28, 29, 30};
320 static const unsigned int pwm_2_pins[] = {27};
321 static const unsigned int pwm_3_pins[] = {28};
322
323 static const unsigned int gpio_6_7_pins[] = {31, 32};
324 static const unsigned int pcie_a3_clk_wak_pins[] = {31, 32};
325 static const unsigned int nor_addr_4_5_pins[] = {31, 32};
326
327 static const unsigned int gpio_8_9_pins[] = {33, 34};
328 static const unsigned int pcie_b3_clk_wak_pins[] = {33, 34};
329 static const unsigned int nor_addr_6_7_pins[] = {33, 34};
330
331 static const unsigned int gpio_10_11_pins[] = {35, 36};
332 static const unsigned int pcie_b2_clk_wak_pins[] = {35, 36};
333 static const unsigned int nor_addr_8_9_pins[] = {35, 36};
334
335 static const unsigned int gpio_12_13_pins[] = {37, 38};
336 static const unsigned int pcie_a2_clk_wak_pins[] = {37, 38};
337 static const unsigned int nor_addr_10_11_pins[] = {37, 38};
338
339 static const unsigned int gpio_14_17_pins[] = {39, 40, 41, 42};
340 static const unsigned int uart0_modem_pins[] = {39, 40, 41, 42};
341 static const unsigned int nor_addr_12_15_pins[] = {39, 40, 41, 42};
342
343 static const unsigned int gpio_18_19_pins[] = {43, 44};
344 static const unsigned int uart0_rts_cts_pins[] = {43, 44};
345
346 static const unsigned int gpio_20_21_pins[] = {45, 46};
347 static const unsigned int uart0_in_out_pins[] = {45, 46};
348
349 static const unsigned int gpio_22_23_pins[] = {47, 48};
350 static const unsigned int uart1_dcd_dsr_pins[] = {47, 48};
351
352 static const unsigned int gpio_24_25_pins[] = {49, 50};
353 static const unsigned int uart1_ri_dtr_pins[] = {49, 50};
354
355 static const unsigned int gpio_26_27_pins[] = {51, 52};
356 static const unsigned int uart1_rts_cts_pins[] = {51, 52};
357
358 static const unsigned int gpio_28_29_pins[] = {53, 54};
359 static const unsigned int uart1_in_out_pins[] = {53, 54};
360
361 static const unsigned int gpio_30_31_pins[] = {55, 56};
362 static const unsigned int uart2_rts_cts_pins[] = {55, 56};
363
364 #define NS2_PIN_GROUP(group_name, ba, off, sh, ma, al) \
365 { \
366 .name = __stringify(group_name) "_grp", \
367 .pins = group_name ## _pins, \
368 .num_pins = ARRAY_SIZE(group_name ## _pins), \
369 .mux = { \
370 .base = ba, \
371 .offset = off, \
372 .shift = sh, \
373 .mask = ma, \
374 .alt = al, \
375 } \
376 }
377
378 /*
379 * List of Northstar2 pin groups
380 */
381 static const struct ns2_pin_group ns2_pin_groups[] = {
382 NS2_PIN_GROUP(nand, 0, 0, 31, 1, 0),
383 NS2_PIN_GROUP(nor_data, 0, 0, 31, 1, 1),
384 NS2_PIN_GROUP(gpio_0_1, 0, 0, 31, 1, 0),
385
386 NS2_PIN_GROUP(uart1_ext_clk, 0, 4, 30, 3, 1),
387 NS2_PIN_GROUP(nor_adv, 0, 4, 30, 3, 2),
388
389 NS2_PIN_GROUP(gpio_2_5, 0, 4, 28, 3, 0),
390 NS2_PIN_GROUP(pcie_ab1_clk_wak, 0, 4, 28, 3, 1),
391 NS2_PIN_GROUP(nor_addr_0_3, 0, 4, 28, 3, 2),
392
393 NS2_PIN_GROUP(gpio_6_7, 0, 4, 26, 3, 0),
394 NS2_PIN_GROUP(pcie_a3_clk_wak, 0, 4, 26, 3, 1),
395 NS2_PIN_GROUP(nor_addr_4_5, 0, 4, 26, 3, 2),
396
397 NS2_PIN_GROUP(gpio_8_9, 0, 4, 24, 3, 0),
398 NS2_PIN_GROUP(pcie_b3_clk_wak, 0, 4, 24, 3, 1),
399 NS2_PIN_GROUP(nor_addr_6_7, 0, 4, 24, 3, 2),
400
401 NS2_PIN_GROUP(gpio_10_11, 0, 4, 22, 3, 0),
402 NS2_PIN_GROUP(pcie_b2_clk_wak, 0, 4, 22, 3, 1),
403 NS2_PIN_GROUP(nor_addr_8_9, 0, 4, 22, 3, 2),
404
405 NS2_PIN_GROUP(gpio_12_13, 0, 4, 20, 3, 0),
406 NS2_PIN_GROUP(pcie_a2_clk_wak, 0, 4, 20, 3, 1),
407 NS2_PIN_GROUP(nor_addr_10_11, 0, 4, 20, 3, 2),
408
409 NS2_PIN_GROUP(gpio_14_17, 0, 4, 18, 3, 0),
410 NS2_PIN_GROUP(uart0_modem, 0, 4, 18, 3, 1),
411 NS2_PIN_GROUP(nor_addr_12_15, 0, 4, 18, 3, 2),
412
413 NS2_PIN_GROUP(gpio_18_19, 0, 4, 16, 3, 0),
414 NS2_PIN_GROUP(uart0_rts_cts, 0, 4, 16, 3, 1),
415
416 NS2_PIN_GROUP(gpio_20_21, 0, 4, 14, 3, 0),
417 NS2_PIN_GROUP(uart0_in_out, 0, 4, 14, 3, 1),
418
419 NS2_PIN_GROUP(gpio_22_23, 0, 4, 12, 3, 0),
420 NS2_PIN_GROUP(uart1_dcd_dsr, 0, 4, 12, 3, 1),
421
422 NS2_PIN_GROUP(gpio_24_25, 0, 4, 10, 3, 0),
423 NS2_PIN_GROUP(uart1_ri_dtr, 0, 4, 10, 3, 1),
424
425 NS2_PIN_GROUP(gpio_26_27, 0, 4, 8, 3, 0),
426 NS2_PIN_GROUP(uart1_rts_cts, 0, 4, 8, 3, 1),
427
428 NS2_PIN_GROUP(gpio_28_29, 0, 4, 6, 3, 0),
429 NS2_PIN_GROUP(uart1_in_out, 0, 4, 6, 3, 1),
430
431 NS2_PIN_GROUP(gpio_30_31, 0, 4, 4, 3, 0),
432 NS2_PIN_GROUP(uart2_rts_cts, 0, 4, 4, 3, 1),
433
434 NS2_PIN_GROUP(pwm_0, 1, 0, 0, 1, 1),
435 NS2_PIN_GROUP(pwm_1, 1, 0, 1, 1, 1),
436 NS2_PIN_GROUP(pwm_2, 1, 0, 2, 1, 1),
437 NS2_PIN_GROUP(pwm_3, 1, 0, 3, 1, 1),
438 };
439
440 /*
441 * List of groups supported by functions
442 */
443
444 static const char * const nand_grps[] = {"nand_grp"};
445
446 static const char * const nor_grps[] = {"nor_data_grp", "nor_adv_grp",
447 "nor_addr_0_3_grp", "nor_addr_4_5_grp", "nor_addr_6_7_grp",
448 "nor_addr_8_9_grp", "nor_addr_10_11_grp", "nor_addr_12_15_grp"};
449
450 static const char * const gpio_grps[] = {"gpio_0_1_grp", "gpio_2_5_grp",
451 "gpio_6_7_grp", "gpio_8_9_grp", "gpio_10_11_grp", "gpio_12_13_grp",
452 "gpio_14_17_grp", "gpio_18_19_grp", "gpio_20_21_grp", "gpio_22_23_grp",
453 "gpio_24_25_grp", "gpio_26_27_grp", "gpio_28_29_grp",
454 "gpio_30_31_grp"};
455
456 static const char * const pcie_grps[] = {"pcie_ab1_clk_wak_grp",
457 "pcie_a3_clk_wak_grp", "pcie_b3_clk_wak_grp", "pcie_b2_clk_wak_grp",
458 "pcie_a2_clk_wak_grp"};
459
460 static const char * const uart0_grps[] = {"uart0_modem_grp",
461 "uart0_rts_cts_grp", "uart0_in_out_grp"};
462
463 static const char * const uart1_grps[] = {"uart1_ext_clk_grp",
464 "uart1_dcd_dsr_grp", "uart1_ri_dtr_grp", "uart1_rts_cts_grp",
465 "uart1_in_out_grp"};
466
467 static const char * const uart2_grps[] = {"uart2_rts_cts_grp"};
468
469 static const char * const pwm_grps[] = {"pwm_0_grp", "pwm_1_grp",
470 "pwm_2_grp", "pwm_3_grp"};
471
472 #define NS2_PIN_FUNCTION(func) \
473 { \
474 .name = #func, \
475 .groups = func ## _grps, \
476 .num_groups = ARRAY_SIZE(func ## _grps), \
477 }
478
479 /*
480 * List of supported functions
481 */
482 static const struct ns2_pin_function ns2_pin_functions[] = {
483 NS2_PIN_FUNCTION(nand),
484 NS2_PIN_FUNCTION(nor),
485 NS2_PIN_FUNCTION(gpio),
486 NS2_PIN_FUNCTION(pcie),
487 NS2_PIN_FUNCTION(uart0),
488 NS2_PIN_FUNCTION(uart1),
489 NS2_PIN_FUNCTION(uart2),
490 NS2_PIN_FUNCTION(pwm),
491 };
492
ns2_get_groups_count(struct pinctrl_dev * pctrl_dev)493 static int ns2_get_groups_count(struct pinctrl_dev *pctrl_dev)
494 {
495 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
496
497 return pinctrl->num_groups;
498 }
499
ns2_get_group_name(struct pinctrl_dev * pctrl_dev,unsigned int selector)500 static const char *ns2_get_group_name(struct pinctrl_dev *pctrl_dev,
501 unsigned int selector)
502 {
503 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
504
505 return pinctrl->groups[selector].name;
506 }
507
ns2_get_group_pins(struct pinctrl_dev * pctrl_dev,unsigned int selector,const unsigned int ** pins,unsigned int * num_pins)508 static int ns2_get_group_pins(struct pinctrl_dev *pctrl_dev,
509 unsigned int selector, const unsigned int **pins,
510 unsigned int *num_pins)
511 {
512 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
513
514 *pins = pinctrl->groups[selector].pins;
515 *num_pins = pinctrl->groups[selector].num_pins;
516
517 return 0;
518 }
519
ns2_pin_dbg_show(struct pinctrl_dev * pctrl_dev,struct seq_file * s,unsigned int offset)520 static void ns2_pin_dbg_show(struct pinctrl_dev *pctrl_dev,
521 struct seq_file *s, unsigned int offset)
522 {
523 seq_printf(s, " %s", dev_name(pctrl_dev->dev));
524 }
525
526 static const struct pinctrl_ops ns2_pinctrl_ops = {
527 .get_groups_count = ns2_get_groups_count,
528 .get_group_name = ns2_get_group_name,
529 .get_group_pins = ns2_get_group_pins,
530 .pin_dbg_show = ns2_pin_dbg_show,
531 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
532 .dt_free_map = pinctrl_utils_free_map,
533 };
534
ns2_get_functions_count(struct pinctrl_dev * pctrl_dev)535 static int ns2_get_functions_count(struct pinctrl_dev *pctrl_dev)
536 {
537 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
538
539 return pinctrl->num_functions;
540 }
541
ns2_get_function_name(struct pinctrl_dev * pctrl_dev,unsigned int selector)542 static const char *ns2_get_function_name(struct pinctrl_dev *pctrl_dev,
543 unsigned int selector)
544 {
545 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
546
547 return pinctrl->functions[selector].name;
548 }
549
ns2_get_function_groups(struct pinctrl_dev * pctrl_dev,unsigned int selector,const char * const ** groups,unsigned int * const num_groups)550 static int ns2_get_function_groups(struct pinctrl_dev *pctrl_dev,
551 unsigned int selector,
552 const char * const **groups,
553 unsigned int * const num_groups)
554 {
555 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
556
557 *groups = pinctrl->functions[selector].groups;
558 *num_groups = pinctrl->functions[selector].num_groups;
559
560 return 0;
561 }
562
ns2_pinmux_set(struct ns2_pinctrl * pinctrl,const struct ns2_pin_function * func,const struct ns2_pin_group * grp,struct ns2_mux_log * mux_log)563 static int ns2_pinmux_set(struct ns2_pinctrl *pinctrl,
564 const struct ns2_pin_function *func,
565 const struct ns2_pin_group *grp,
566 struct ns2_mux_log *mux_log)
567 {
568 const struct ns2_mux *mux = &grp->mux;
569 int i;
570 u32 val, mask;
571 unsigned long flags;
572 void __iomem *base_address;
573
574 for (i = 0; i < NS2_NUM_IOMUX; i++) {
575 if ((mux->shift != mux_log[i].mux.shift) ||
576 (mux->base != mux_log[i].mux.base) ||
577 (mux->offset != mux_log[i].mux.offset))
578 continue;
579
580 /* if this is a new configuration, just do it! */
581 if (!mux_log[i].is_configured)
582 break;
583
584 /*
585 * IOMUX has been configured previously and one is trying to
586 * configure it to a different function
587 */
588 if (mux_log[i].mux.alt != mux->alt) {
589 dev_err(pinctrl->dev,
590 "double configuration error detected!\n");
591 dev_err(pinctrl->dev, "func:%s grp:%s\n",
592 func->name, grp->name);
593 return -EINVAL;
594 }
595
596 return 0;
597 }
598 if (i == NS2_NUM_IOMUX)
599 return -EINVAL;
600
601 mask = mux->mask;
602 mux_log[i].mux.alt = mux->alt;
603 mux_log[i].is_configured = true;
604
605 switch (mux->base) {
606 case NS2_PIN_MUX_BASE0:
607 base_address = pinctrl->base0;
608 break;
609
610 case NS2_PIN_MUX_BASE1:
611 base_address = pinctrl->base1;
612 break;
613
614 default:
615 return -EINVAL;
616 }
617
618 spin_lock_irqsave(&pinctrl->lock, flags);
619 val = readl(base_address + grp->mux.offset);
620 val &= ~(mask << grp->mux.shift);
621 val |= grp->mux.alt << grp->mux.shift;
622 writel(val, (base_address + grp->mux.offset));
623 spin_unlock_irqrestore(&pinctrl->lock, flags);
624
625 return 0;
626 }
627
ns2_pinmux_enable(struct pinctrl_dev * pctrl_dev,unsigned int func_select,unsigned int grp_select)628 static int ns2_pinmux_enable(struct pinctrl_dev *pctrl_dev,
629 unsigned int func_select, unsigned int grp_select)
630 {
631 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
632 const struct ns2_pin_function *func;
633 const struct ns2_pin_group *grp;
634
635 if (grp_select >= pinctrl->num_groups ||
636 func_select >= pinctrl->num_functions)
637 return -EINVAL;
638
639 func = &pinctrl->functions[func_select];
640 grp = &pinctrl->groups[grp_select];
641
642 dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",
643 func_select, func->name, grp_select, grp->name);
644
645 dev_dbg(pctrl_dev->dev, "offset:0x%08x shift:%u alt:%u\n",
646 grp->mux.offset, grp->mux.shift, grp->mux.alt);
647
648 return ns2_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);
649 }
650
ns2_pin_set_enable(struct pinctrl_dev * pctrldev,unsigned int pin,u16 enable)651 static int ns2_pin_set_enable(struct pinctrl_dev *pctrldev, unsigned int pin,
652 u16 enable)
653 {
654 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
655 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
656 unsigned long flags;
657 u32 val;
658 void __iomem *base_address;
659
660 base_address = pinctrl->pinconf_base;
661 spin_lock_irqsave(&pinctrl->lock, flags);
662 val = readl(base_address + pin_data->pin_conf.offset);
663 val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.input_en);
664
665 if (!enable)
666 val |= NS2_PIN_INPUT_EN_MASK << pin_data->pin_conf.input_en;
667
668 writel(val, (base_address + pin_data->pin_conf.offset));
669 spin_unlock_irqrestore(&pinctrl->lock, flags);
670
671 dev_dbg(pctrldev->dev, "pin:%u set enable:%d\n", pin, enable);
672 return 0;
673 }
674
ns2_pin_get_enable(struct pinctrl_dev * pctrldev,unsigned int pin)675 static int ns2_pin_get_enable(struct pinctrl_dev *pctrldev, unsigned int pin)
676 {
677 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
678 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
679 unsigned long flags;
680 int enable;
681
682 spin_lock_irqsave(&pinctrl->lock, flags);
683 enable = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
684 enable = (enable >> pin_data->pin_conf.input_en) &
685 NS2_PIN_INPUT_EN_MASK;
686 spin_unlock_irqrestore(&pinctrl->lock, flags);
687
688 if (!enable)
689 enable = NS2_PIN_INPUT_EN_MASK;
690 else
691 enable = 0;
692
693 dev_dbg(pctrldev->dev, "pin:%u get disable:%d\n", pin, enable);
694 return enable;
695 }
696
ns2_pin_set_slew(struct pinctrl_dev * pctrldev,unsigned int pin,u32 slew)697 static int ns2_pin_set_slew(struct pinctrl_dev *pctrldev, unsigned int pin,
698 u32 slew)
699 {
700 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
701 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
702 unsigned long flags;
703 u32 val;
704 void __iomem *base_address;
705
706 base_address = pinctrl->pinconf_base;
707 spin_lock_irqsave(&pinctrl->lock, flags);
708 val = readl(base_address + pin_data->pin_conf.offset);
709 val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift);
710
711 if (slew)
712 val |= NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift;
713
714 writel(val, (base_address + pin_data->pin_conf.offset));
715 spin_unlock_irqrestore(&pinctrl->lock, flags);
716
717 dev_dbg(pctrldev->dev, "pin:%u set slew:%d\n", pin, slew);
718 return 0;
719 }
720
ns2_pin_get_slew(struct pinctrl_dev * pctrldev,unsigned int pin,u16 * slew)721 static int ns2_pin_get_slew(struct pinctrl_dev *pctrldev, unsigned int pin,
722 u16 *slew)
723 {
724 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
725 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
726 unsigned long flags;
727 u32 val;
728
729 spin_lock_irqsave(&pinctrl->lock, flags);
730 val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
731 *slew = (val >> pin_data->pin_conf.src_shift) & NS2_PIN_SRC_MASK;
732 spin_unlock_irqrestore(&pinctrl->lock, flags);
733
734 dev_dbg(pctrldev->dev, "pin:%u get slew:%d\n", pin, *slew);
735 return 0;
736 }
737
ns2_pin_set_pull(struct pinctrl_dev * pctrldev,unsigned int pin,bool pull_up,bool pull_down)738 static int ns2_pin_set_pull(struct pinctrl_dev *pctrldev, unsigned int pin,
739 bool pull_up, bool pull_down)
740 {
741 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
742 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
743 unsigned long flags;
744 u32 val;
745 void __iomem *base_address;
746
747 base_address = pinctrl->pinconf_base;
748 spin_lock_irqsave(&pinctrl->lock, flags);
749 val = readl(base_address + pin_data->pin_conf.offset);
750 val &= ~(NS2_PIN_PULL_MASK << pin_data->pin_conf.pull_shift);
751
752 if (pull_up == true)
753 val |= NS2_PIN_PULL_UP << pin_data->pin_conf.pull_shift;
754 if (pull_down == true)
755 val |= NS2_PIN_PULL_DOWN << pin_data->pin_conf.pull_shift;
756 writel(val, (base_address + pin_data->pin_conf.offset));
757 spin_unlock_irqrestore(&pinctrl->lock, flags);
758
759 dev_dbg(pctrldev->dev, "pin:%u set pullup:%d pulldown: %d\n",
760 pin, pull_up, pull_down);
761 return 0;
762 }
763
ns2_pin_get_pull(struct pinctrl_dev * pctrldev,unsigned int pin,bool * pull_up,bool * pull_down)764 static void ns2_pin_get_pull(struct pinctrl_dev *pctrldev,
765 unsigned int pin, bool *pull_up,
766 bool *pull_down)
767 {
768 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
769 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
770 unsigned long flags;
771 u32 val;
772
773 spin_lock_irqsave(&pinctrl->lock, flags);
774 val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
775 val = (val >> pin_data->pin_conf.pull_shift) & NS2_PIN_PULL_MASK;
776 *pull_up = false;
777 *pull_down = false;
778
779 if (val == NS2_PIN_PULL_UP)
780 *pull_up = true;
781
782 if (val == NS2_PIN_PULL_DOWN)
783 *pull_down = true;
784 spin_unlock_irqrestore(&pinctrl->lock, flags);
785 }
786
ns2_pin_set_strength(struct pinctrl_dev * pctrldev,unsigned int pin,u32 strength)787 static int ns2_pin_set_strength(struct pinctrl_dev *pctrldev, unsigned int pin,
788 u32 strength)
789 {
790 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
791 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
792 u32 val;
793 unsigned long flags;
794 void __iomem *base_address;
795
796 /* make sure drive strength is supported */
797 if (strength < 2 || strength > 16 || (strength % 2))
798 return -ENOTSUPP;
799
800 base_address = pinctrl->pinconf_base;
801 spin_lock_irqsave(&pinctrl->lock, flags);
802 val = readl(base_address + pin_data->pin_conf.offset);
803 val &= ~(NS2_PIN_DRIVE_STRENGTH_MASK << pin_data->pin_conf.drive_shift);
804 val |= ((strength / 2) - 1) << pin_data->pin_conf.drive_shift;
805 writel(val, (base_address + pin_data->pin_conf.offset));
806 spin_unlock_irqrestore(&pinctrl->lock, flags);
807
808 dev_dbg(pctrldev->dev, "pin:%u set drive strength:%d mA\n",
809 pin, strength);
810 return 0;
811 }
812
ns2_pin_get_strength(struct pinctrl_dev * pctrldev,unsigned int pin,u16 * strength)813 static int ns2_pin_get_strength(struct pinctrl_dev *pctrldev, unsigned int pin,
814 u16 *strength)
815 {
816 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
817 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
818 u32 val;
819 unsigned long flags;
820
821 spin_lock_irqsave(&pinctrl->lock, flags);
822 val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
823 *strength = (val >> pin_data->pin_conf.drive_shift) &
824 NS2_PIN_DRIVE_STRENGTH_MASK;
825 *strength = (*strength + 1) * 2;
826 spin_unlock_irqrestore(&pinctrl->lock, flags);
827
828 dev_dbg(pctrldev->dev, "pin:%u get drive strength:%d mA\n",
829 pin, *strength);
830 return 0;
831 }
832
ns2_pin_config_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)833 static int ns2_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
834 unsigned long *config)
835 {
836 struct ns2_pin *pin_data = pctldev->desc->pins[pin].drv_data;
837 enum pin_config_param param = pinconf_to_config_param(*config);
838 bool pull_up, pull_down;
839 u16 arg = 0;
840 int ret;
841
842 if (pin_data->pin_conf.base == -1)
843 return -ENOTSUPP;
844
845 switch (param) {
846 case PIN_CONFIG_BIAS_DISABLE:
847 ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
848 if (!pull_up && !pull_down)
849 return 0;
850 else
851 return -EINVAL;
852
853 case PIN_CONFIG_BIAS_PULL_UP:
854 ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
855 if (pull_up)
856 return 0;
857 else
858 return -EINVAL;
859
860 case PIN_CONFIG_BIAS_PULL_DOWN:
861 ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
862 if (pull_down)
863 return 0;
864 else
865 return -EINVAL;
866
867 case PIN_CONFIG_DRIVE_STRENGTH:
868 ret = ns2_pin_get_strength(pctldev, pin, &arg);
869 if (ret)
870 return ret;
871 *config = pinconf_to_config_packed(param, arg);
872 return 0;
873
874 case PIN_CONFIG_SLEW_RATE:
875 ret = ns2_pin_get_slew(pctldev, pin, &arg);
876 if (ret)
877 return ret;
878 *config = pinconf_to_config_packed(param, arg);
879 return 0;
880
881 case PIN_CONFIG_INPUT_ENABLE:
882 ret = ns2_pin_get_enable(pctldev, pin);
883 if (ret)
884 return 0;
885 else
886 return -EINVAL;
887
888 default:
889 return -ENOTSUPP;
890 }
891 }
892
ns2_pin_config_set(struct pinctrl_dev * pctrldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)893 static int ns2_pin_config_set(struct pinctrl_dev *pctrldev, unsigned int pin,
894 unsigned long *configs, unsigned int num_configs)
895 {
896 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
897 enum pin_config_param param;
898 unsigned int i;
899 u32 arg;
900 int ret = -ENOTSUPP;
901
902 if (pin_data->pin_conf.base == -1)
903 return -ENOTSUPP;
904
905 for (i = 0; i < num_configs; i++) {
906 param = pinconf_to_config_param(configs[i]);
907 arg = pinconf_to_config_argument(configs[i]);
908
909 switch (param) {
910 case PIN_CONFIG_BIAS_DISABLE:
911 ret = ns2_pin_set_pull(pctrldev, pin, false, false);
912 if (ret < 0)
913 goto out;
914 break;
915
916 case PIN_CONFIG_BIAS_PULL_UP:
917 ret = ns2_pin_set_pull(pctrldev, pin, true, false);
918 if (ret < 0)
919 goto out;
920 break;
921
922 case PIN_CONFIG_BIAS_PULL_DOWN:
923 ret = ns2_pin_set_pull(pctrldev, pin, false, true);
924 if (ret < 0)
925 goto out;
926 break;
927
928 case PIN_CONFIG_DRIVE_STRENGTH:
929 ret = ns2_pin_set_strength(pctrldev, pin, arg);
930 if (ret < 0)
931 goto out;
932 break;
933
934 case PIN_CONFIG_SLEW_RATE:
935 ret = ns2_pin_set_slew(pctrldev, pin, arg);
936 if (ret < 0)
937 goto out;
938 break;
939
940 case PIN_CONFIG_INPUT_ENABLE:
941 ret = ns2_pin_set_enable(pctrldev, pin, arg);
942 if (ret < 0)
943 goto out;
944 break;
945
946 default:
947 dev_err(pctrldev->dev, "invalid configuration\n");
948 return -ENOTSUPP;
949 }
950 }
951 out:
952 return ret;
953 }
954 static const struct pinmux_ops ns2_pinmux_ops = {
955 .get_functions_count = ns2_get_functions_count,
956 .get_function_name = ns2_get_function_name,
957 .get_function_groups = ns2_get_function_groups,
958 .set_mux = ns2_pinmux_enable,
959 };
960
961 static const struct pinconf_ops ns2_pinconf_ops = {
962 .is_generic = true,
963 .pin_config_get = ns2_pin_config_get,
964 .pin_config_set = ns2_pin_config_set,
965 };
966
967 static struct pinctrl_desc ns2_pinctrl_desc = {
968 .name = "ns2-pinmux",
969 .pctlops = &ns2_pinctrl_ops,
970 .pmxops = &ns2_pinmux_ops,
971 .confops = &ns2_pinconf_ops,
972 };
973
ns2_mux_log_init(struct ns2_pinctrl * pinctrl)974 static int ns2_mux_log_init(struct ns2_pinctrl *pinctrl)
975 {
976 struct ns2_mux_log *log;
977 unsigned int i;
978
979 pinctrl->mux_log = devm_kcalloc(pinctrl->dev, NS2_NUM_IOMUX,
980 sizeof(struct ns2_mux_log),
981 GFP_KERNEL);
982 if (!pinctrl->mux_log)
983 return -ENOMEM;
984
985 for (i = 0; i < NS2_NUM_IOMUX; i++)
986 pinctrl->mux_log[i].is_configured = false;
987 /* Group 0 uses bit 31 in the IOMUX_PAD_FUNCTION_0 register */
988 log = &pinctrl->mux_log[0];
989 log->mux.base = NS2_PIN_MUX_BASE0;
990 log->mux.offset = 0;
991 log->mux.shift = 31;
992 log->mux.alt = 0;
993
994 /*
995 * Groups 1 through 14 use two bits each in the
996 * IOMUX_PAD_FUNCTION_1 register starting with
997 * bit position 30.
998 */
999 for (i = 1; i < (NS2_NUM_IOMUX - NS2_NUM_PWM_MUX); i++) {
1000 log = &pinctrl->mux_log[i];
1001 log->mux.base = NS2_PIN_MUX_BASE0;
1002 log->mux.offset = NS2_MUX_PAD_FUNC1_OFFSET;
1003 log->mux.shift = 32 - (i * 2);
1004 log->mux.alt = 0;
1005 }
1006
1007 /*
1008 * Groups 15 through 18 use one bit each in the
1009 * AUX_SEL register.
1010 */
1011 for (i = 0; i < NS2_NUM_PWM_MUX; i++) {
1012 log = &pinctrl->mux_log[(NS2_NUM_IOMUX - NS2_NUM_PWM_MUX) + i];
1013 log->mux.base = NS2_PIN_MUX_BASE1;
1014 log->mux.offset = 0;
1015 log->mux.shift = i;
1016 log->mux.alt = 0;
1017 }
1018 return 0;
1019 }
1020
ns2_pinmux_probe(struct platform_device * pdev)1021 static int ns2_pinmux_probe(struct platform_device *pdev)
1022 {
1023 struct ns2_pinctrl *pinctrl;
1024 struct resource *res;
1025 int i, ret;
1026 struct pinctrl_pin_desc *pins;
1027 unsigned int num_pins = ARRAY_SIZE(ns2_pins);
1028
1029 pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
1030 if (!pinctrl)
1031 return -ENOMEM;
1032
1033 pinctrl->dev = &pdev->dev;
1034 platform_set_drvdata(pdev, pinctrl);
1035 spin_lock_init(&pinctrl->lock);
1036
1037 pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
1038 if (IS_ERR(pinctrl->base0))
1039 return PTR_ERR(pinctrl->base0);
1040
1041 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1042 if (!res)
1043 return -EINVAL;
1044 pinctrl->base1 = devm_ioremap(&pdev->dev, res->start,
1045 resource_size(res));
1046 if (!pinctrl->base1) {
1047 dev_err(&pdev->dev, "unable to map I/O space\n");
1048 return -ENOMEM;
1049 }
1050
1051 pinctrl->pinconf_base = devm_platform_ioremap_resource(pdev, 2);
1052 if (IS_ERR(pinctrl->pinconf_base))
1053 return PTR_ERR(pinctrl->pinconf_base);
1054
1055 ret = ns2_mux_log_init(pinctrl);
1056 if (ret) {
1057 dev_err(&pdev->dev, "unable to initialize IOMUX log\n");
1058 return ret;
1059 }
1060
1061 pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
1062 if (!pins)
1063 return -ENOMEM;
1064
1065 for (i = 0; i < num_pins; i++) {
1066 pins[i].number = ns2_pins[i].pin;
1067 pins[i].name = ns2_pins[i].name;
1068 pins[i].drv_data = &ns2_pins[i];
1069 }
1070
1071 pinctrl->groups = ns2_pin_groups;
1072 pinctrl->num_groups = ARRAY_SIZE(ns2_pin_groups);
1073 pinctrl->functions = ns2_pin_functions;
1074 pinctrl->num_functions = ARRAY_SIZE(ns2_pin_functions);
1075 ns2_pinctrl_desc.pins = pins;
1076 ns2_pinctrl_desc.npins = num_pins;
1077
1078 pinctrl->pctl = pinctrl_register(&ns2_pinctrl_desc, &pdev->dev,
1079 pinctrl);
1080 if (IS_ERR(pinctrl->pctl)) {
1081 dev_err(&pdev->dev, "unable to register IOMUX pinctrl\n");
1082 return PTR_ERR(pinctrl->pctl);
1083 }
1084
1085 return 0;
1086 }
1087
1088 static const struct of_device_id ns2_pinmux_of_match[] = {
1089 {.compatible = "brcm,ns2-pinmux"},
1090 { }
1091 };
1092
1093 static struct platform_driver ns2_pinmux_driver = {
1094 .driver = {
1095 .name = "ns2-pinmux",
1096 .of_match_table = ns2_pinmux_of_match,
1097 },
1098 .probe = ns2_pinmux_probe,
1099 };
1100
ns2_pinmux_init(void)1101 static int __init ns2_pinmux_init(void)
1102 {
1103 return platform_driver_register(&ns2_pinmux_driver);
1104 }
1105 arch_initcall(ns2_pinmux_init);
1106
