1 /*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/of.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_device.h>
29 #include <linux/platform_data/davinci_asp.h>
30 #include <linux/math64.h>
31
32 #include <sound/asoundef.h>
33 #include <sound/core.h>
34 #include <sound/pcm.h>
35 #include <sound/pcm_params.h>
36 #include <sound/initval.h>
37 #include <sound/soc.h>
38 #include <sound/dmaengine_pcm.h>
39
40 #include "edma-pcm.h"
41 #include "../omap/sdma-pcm.h"
42 #include "davinci-mcasp.h"
43
44 #define MCASP_MAX_AFIFO_DEPTH 64
45
46 static u32 context_regs[] = {
47 DAVINCI_MCASP_TXFMCTL_REG,
48 DAVINCI_MCASP_RXFMCTL_REG,
49 DAVINCI_MCASP_TXFMT_REG,
50 DAVINCI_MCASP_RXFMT_REG,
51 DAVINCI_MCASP_ACLKXCTL_REG,
52 DAVINCI_MCASP_ACLKRCTL_REG,
53 DAVINCI_MCASP_AHCLKXCTL_REG,
54 DAVINCI_MCASP_AHCLKRCTL_REG,
55 DAVINCI_MCASP_PDIR_REG,
56 DAVINCI_MCASP_RXMASK_REG,
57 DAVINCI_MCASP_TXMASK_REG,
58 DAVINCI_MCASP_RXTDM_REG,
59 DAVINCI_MCASP_TXTDM_REG,
60 };
61
62 struct davinci_mcasp_context {
63 u32 config_regs[ARRAY_SIZE(context_regs)];
64 u32 afifo_regs[2]; /* for read/write fifo control registers */
65 u32 *xrsr_regs; /* for serializer configuration */
66 bool pm_state;
67 };
68
69 struct davinci_mcasp_ruledata {
70 struct davinci_mcasp *mcasp;
71 int serializers;
72 };
73
74 struct davinci_mcasp {
75 struct snd_dmaengine_dai_dma_data dma_data[2];
76 void __iomem *base;
77 u32 fifo_base;
78 struct device *dev;
79 struct snd_pcm_substream *substreams[2];
80 unsigned int dai_fmt;
81
82 /* McASP specific data */
83 int tdm_slots;
84 u32 tdm_mask[2];
85 int slot_width;
86 u8 op_mode;
87 u8 num_serializer;
88 u8 *serial_dir;
89 u8 version;
90 u8 bclk_div;
91 int streams;
92 u32 irq_request[2];
93 int dma_request[2];
94
95 int sysclk_freq;
96 bool bclk_master;
97
98 /* McASP FIFO related */
99 u8 txnumevt;
100 u8 rxnumevt;
101
102 bool dat_port;
103
104 /* Used for comstraint setting on the second stream */
105 u32 channels;
106
107 #ifdef CONFIG_PM_SLEEP
108 struct davinci_mcasp_context context;
109 #endif
110
111 struct davinci_mcasp_ruledata ruledata[2];
112 struct snd_pcm_hw_constraint_list chconstr[2];
113 };
114
mcasp_set_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val)115 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
116 u32 val)
117 {
118 void __iomem *reg = mcasp->base + offset;
119 __raw_writel(__raw_readl(reg) | val, reg);
120 }
121
mcasp_clr_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val)122 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
123 u32 val)
124 {
125 void __iomem *reg = mcasp->base + offset;
126 __raw_writel((__raw_readl(reg) & ~(val)), reg);
127 }
128
mcasp_mod_bits(struct davinci_mcasp * mcasp,u32 offset,u32 val,u32 mask)129 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
130 u32 val, u32 mask)
131 {
132 void __iomem *reg = mcasp->base + offset;
133 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
134 }
135
mcasp_set_reg(struct davinci_mcasp * mcasp,u32 offset,u32 val)136 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
137 u32 val)
138 {
139 __raw_writel(val, mcasp->base + offset);
140 }
141
mcasp_get_reg(struct davinci_mcasp * mcasp,u32 offset)142 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
143 {
144 return (u32)__raw_readl(mcasp->base + offset);
145 }
146
mcasp_set_ctl_reg(struct davinci_mcasp * mcasp,u32 ctl_reg,u32 val)147 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
148 {
149 int i = 0;
150
151 mcasp_set_bits(mcasp, ctl_reg, val);
152
153 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
154 /* loop count is to avoid the lock-up */
155 for (i = 0; i < 1000; i++) {
156 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
157 break;
158 }
159
160 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
161 printk(KERN_ERR "GBLCTL write error\n");
162 }
163
mcasp_is_synchronous(struct davinci_mcasp * mcasp)164 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
165 {
166 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
167 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
168
169 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
170 }
171
mcasp_start_rx(struct davinci_mcasp * mcasp)172 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
173 {
174 if (mcasp->rxnumevt) { /* enable FIFO */
175 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
176
177 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
178 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
179 }
180
181 /* Start clocks */
182 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
183 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
184 /*
185 * When ASYNC == 0 the transmit and receive sections operate
186 * synchronously from the transmit clock and frame sync. We need to make
187 * sure that the TX signlas are enabled when starting reception.
188 */
189 if (mcasp_is_synchronous(mcasp)) {
190 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
191 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
192 }
193
194 /* Activate serializer(s) */
195 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
196 /* Release RX state machine */
197 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
198 /* Release Frame Sync generator */
199 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
200 if (mcasp_is_synchronous(mcasp))
201 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
202
203 /* enable receive IRQs */
204 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
205 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
206 }
207
mcasp_start_tx(struct davinci_mcasp * mcasp)208 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
209 {
210 u32 cnt;
211
212 if (mcasp->txnumevt) { /* enable FIFO */
213 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
214
215 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
216 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
217 }
218
219 /* Start clocks */
220 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
221 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
222 /* Activate serializer(s) */
223 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
224
225 /* wait for XDATA to be cleared */
226 cnt = 0;
227 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
228 (cnt < 100000))
229 cnt++;
230
231 /* Release TX state machine */
232 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
233 /* Release Frame Sync generator */
234 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
235
236 /* enable transmit IRQs */
237 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
238 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
239 }
240
davinci_mcasp_start(struct davinci_mcasp * mcasp,int stream)241 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
242 {
243 mcasp->streams++;
244
245 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
246 mcasp_start_tx(mcasp);
247 else
248 mcasp_start_rx(mcasp);
249 }
250
mcasp_stop_rx(struct davinci_mcasp * mcasp)251 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
252 {
253 /* disable IRQ sources */
254 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
255 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
256
257 /*
258 * In synchronous mode stop the TX clocks if no other stream is
259 * running
260 */
261 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
262 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
263
264 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
265 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
266
267 if (mcasp->rxnumevt) { /* disable FIFO */
268 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
269
270 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
271 }
272 }
273
mcasp_stop_tx(struct davinci_mcasp * mcasp)274 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
275 {
276 u32 val = 0;
277
278 /* disable IRQ sources */
279 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
280 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
281
282 /*
283 * In synchronous mode keep TX clocks running if the capture stream is
284 * still running.
285 */
286 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
287 val = TXHCLKRST | TXCLKRST | TXFSRST;
288
289 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
290 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
291
292 if (mcasp->txnumevt) { /* disable FIFO */
293 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
294
295 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
296 }
297 }
298
davinci_mcasp_stop(struct davinci_mcasp * mcasp,int stream)299 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
300 {
301 mcasp->streams--;
302
303 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
304 mcasp_stop_tx(mcasp);
305 else
306 mcasp_stop_rx(mcasp);
307 }
308
davinci_mcasp_tx_irq_handler(int irq,void * data)309 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
310 {
311 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
312 struct snd_pcm_substream *substream;
313 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
314 u32 handled_mask = 0;
315 u32 stat;
316
317 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
318 if (stat & XUNDRN & irq_mask) {
319 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
320 handled_mask |= XUNDRN;
321
322 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
323 if (substream)
324 snd_pcm_stop_xrun(substream);
325 }
326
327 if (!handled_mask)
328 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
329 stat);
330
331 if (stat & XRERR)
332 handled_mask |= XRERR;
333
334 /* Ack the handled event only */
335 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
336
337 return IRQ_RETVAL(handled_mask);
338 }
339
davinci_mcasp_rx_irq_handler(int irq,void * data)340 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
341 {
342 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
343 struct snd_pcm_substream *substream;
344 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
345 u32 handled_mask = 0;
346 u32 stat;
347
348 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
349 if (stat & ROVRN & irq_mask) {
350 dev_warn(mcasp->dev, "Receive buffer overflow\n");
351 handled_mask |= ROVRN;
352
353 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
354 if (substream)
355 snd_pcm_stop_xrun(substream);
356 }
357
358 if (!handled_mask)
359 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
360 stat);
361
362 if (stat & XRERR)
363 handled_mask |= XRERR;
364
365 /* Ack the handled event only */
366 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
367
368 return IRQ_RETVAL(handled_mask);
369 }
370
davinci_mcasp_common_irq_handler(int irq,void * data)371 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
372 {
373 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
374 irqreturn_t ret = IRQ_NONE;
375
376 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
377 ret = davinci_mcasp_tx_irq_handler(irq, data);
378
379 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
380 ret |= davinci_mcasp_rx_irq_handler(irq, data);
381
382 return ret;
383 }
384
davinci_mcasp_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)385 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
386 unsigned int fmt)
387 {
388 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
389 int ret = 0;
390 u32 data_delay;
391 bool fs_pol_rising;
392 bool inv_fs = false;
393
394 if (!fmt)
395 return 0;
396
397 pm_runtime_get_sync(mcasp->dev);
398 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
399 case SND_SOC_DAIFMT_DSP_A:
400 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
401 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
402 /* 1st data bit occur one ACLK cycle after the frame sync */
403 data_delay = 1;
404 break;
405 case SND_SOC_DAIFMT_DSP_B:
406 case SND_SOC_DAIFMT_AC97:
407 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
408 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
409 /* No delay after FS */
410 data_delay = 0;
411 break;
412 case SND_SOC_DAIFMT_I2S:
413 /* configure a full-word SYNC pulse (LRCLK) */
414 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
415 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
416 /* 1st data bit occur one ACLK cycle after the frame sync */
417 data_delay = 1;
418 /* FS need to be inverted */
419 inv_fs = true;
420 break;
421 case SND_SOC_DAIFMT_LEFT_J:
422 /* configure a full-word SYNC pulse (LRCLK) */
423 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
424 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
425 /* No delay after FS */
426 data_delay = 0;
427 break;
428 default:
429 ret = -EINVAL;
430 goto out;
431 }
432
433 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
434 FSXDLY(3));
435 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
436 FSRDLY(3));
437
438 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
439 case SND_SOC_DAIFMT_CBS_CFS:
440 /* codec is clock and frame slave */
441 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
442 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
443
444 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
445 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
446
447 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
448 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
449 mcasp->bclk_master = 1;
450 break;
451 case SND_SOC_DAIFMT_CBS_CFM:
452 /* codec is clock slave and frame master */
453 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
454 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
455
456 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
457 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
458
459 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
460 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
461 mcasp->bclk_master = 1;
462 break;
463 case SND_SOC_DAIFMT_CBM_CFS:
464 /* codec is clock master and frame slave */
465 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
466 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
467
468 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
469 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
470
471 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
472 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
473 mcasp->bclk_master = 0;
474 break;
475 case SND_SOC_DAIFMT_CBM_CFM:
476 /* codec is clock and frame master */
477 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
478 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
479
480 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
481 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
482
483 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
484 ACLKX | AFSX | ACLKR | AHCLKR | AFSR);
485 mcasp->bclk_master = 0;
486 break;
487 default:
488 ret = -EINVAL;
489 goto out;
490 }
491
492 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
493 case SND_SOC_DAIFMT_IB_NF:
494 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
495 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
496 fs_pol_rising = true;
497 break;
498 case SND_SOC_DAIFMT_NB_IF:
499 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
500 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
501 fs_pol_rising = false;
502 break;
503 case SND_SOC_DAIFMT_IB_IF:
504 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
505 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
506 fs_pol_rising = false;
507 break;
508 case SND_SOC_DAIFMT_NB_NF:
509 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
510 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
511 fs_pol_rising = true;
512 break;
513 default:
514 ret = -EINVAL;
515 goto out;
516 }
517
518 if (inv_fs)
519 fs_pol_rising = !fs_pol_rising;
520
521 if (fs_pol_rising) {
522 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
523 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
524 } else {
525 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
526 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
527 }
528
529 mcasp->dai_fmt = fmt;
530 out:
531 pm_runtime_put(mcasp->dev);
532 return ret;
533 }
534
__davinci_mcasp_set_clkdiv(struct davinci_mcasp * mcasp,int div_id,int div,bool explicit)535 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
536 int div, bool explicit)
537 {
538 pm_runtime_get_sync(mcasp->dev);
539 switch (div_id) {
540 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
541 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
542 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
543 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
544 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
545 break;
546
547 case MCASP_CLKDIV_BCLK: /* BCLK divider */
548 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
549 ACLKXDIV(div - 1), ACLKXDIV_MASK);
550 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
551 ACLKRDIV(div - 1), ACLKRDIV_MASK);
552 if (explicit)
553 mcasp->bclk_div = div;
554 break;
555
556 case MCASP_CLKDIV_BCLK_FS_RATIO:
557 /*
558 * BCLK/LRCLK ratio descries how many bit-clock cycles
559 * fit into one frame. The clock ratio is given for a
560 * full period of data (for I2S format both left and
561 * right channels), so it has to be divided by number
562 * of tdm-slots (for I2S - divided by 2).
563 * Instead of storing this ratio, we calculate a new
564 * tdm_slot width by dividing the the ratio by the
565 * number of configured tdm slots.
566 */
567 mcasp->slot_width = div / mcasp->tdm_slots;
568 if (div % mcasp->tdm_slots)
569 dev_warn(mcasp->dev,
570 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
571 __func__, div, mcasp->tdm_slots);
572 break;
573
574 default:
575 return -EINVAL;
576 }
577
578 pm_runtime_put(mcasp->dev);
579 return 0;
580 }
581
davinci_mcasp_set_clkdiv(struct snd_soc_dai * dai,int div_id,int div)582 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
583 int div)
584 {
585 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
586
587 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
588 }
589
davinci_mcasp_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)590 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
591 unsigned int freq, int dir)
592 {
593 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
594
595 pm_runtime_get_sync(mcasp->dev);
596 if (dir == SND_SOC_CLOCK_OUT) {
597 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
598 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
599 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
600 } else {
601 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
602 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
603 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
604 }
605
606 mcasp->sysclk_freq = freq;
607
608 pm_runtime_put(mcasp->dev);
609 return 0;
610 }
611
612 /* All serializers must have equal number of channels */
davinci_mcasp_ch_constraint(struct davinci_mcasp * mcasp,int stream,int serializers)613 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
614 int serializers)
615 {
616 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
617 unsigned int *list = (unsigned int *) cl->list;
618 int slots = mcasp->tdm_slots;
619 int i, count = 0;
620
621 if (mcasp->tdm_mask[stream])
622 slots = hweight32(mcasp->tdm_mask[stream]);
623
624 for (i = 1; i <= slots; i++)
625 list[count++] = i;
626
627 for (i = 2; i <= serializers; i++)
628 list[count++] = i*slots;
629
630 cl->count = count;
631
632 return 0;
633 }
634
davinci_mcasp_set_ch_constraints(struct davinci_mcasp * mcasp)635 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
636 {
637 int rx_serializers = 0, tx_serializers = 0, ret, i;
638
639 for (i = 0; i < mcasp->num_serializer; i++)
640 if (mcasp->serial_dir[i] == TX_MODE)
641 tx_serializers++;
642 else if (mcasp->serial_dir[i] == RX_MODE)
643 rx_serializers++;
644
645 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
646 tx_serializers);
647 if (ret)
648 return ret;
649
650 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
651 rx_serializers);
652
653 return ret;
654 }
655
656
davinci_mcasp_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)657 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
658 unsigned int tx_mask,
659 unsigned int rx_mask,
660 int slots, int slot_width)
661 {
662 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
663
664 dev_dbg(mcasp->dev,
665 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
666 __func__, tx_mask, rx_mask, slots, slot_width);
667
668 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
669 dev_err(mcasp->dev,
670 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
671 tx_mask, rx_mask, slots);
672 return -EINVAL;
673 }
674
675 if (slot_width &&
676 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
677 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
678 __func__, slot_width);
679 return -EINVAL;
680 }
681
682 mcasp->tdm_slots = slots;
683 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
684 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
685 mcasp->slot_width = slot_width;
686
687 return davinci_mcasp_set_ch_constraints(mcasp);
688 }
689
davinci_config_channel_size(struct davinci_mcasp * mcasp,int sample_width)690 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
691 int sample_width)
692 {
693 u32 fmt;
694 u32 tx_rotate = (sample_width / 4) & 0x7;
695 u32 mask = (1ULL << sample_width) - 1;
696 u32 slot_width = sample_width;
697
698 /*
699 * For captured data we should not rotate, inversion and masking is
700 * enoguh to get the data to the right position:
701 * Format data from bus after reverse (XRBUF)
702 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
703 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
704 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
705 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
706 */
707 u32 rx_rotate = 0;
708
709 /*
710 * Setting the tdm slot width either with set_clkdiv() or
711 * set_tdm_slot() allows us to for example send 32 bits per
712 * channel to the codec, while only 16 of them carry audio
713 * payload.
714 */
715 if (mcasp->slot_width) {
716 /*
717 * When we have more bclk then it is needed for the
718 * data, we need to use the rotation to move the
719 * received samples to have correct alignment.
720 */
721 slot_width = mcasp->slot_width;
722 rx_rotate = (slot_width - sample_width) / 4;
723 }
724
725 /* mapping of the XSSZ bit-field as described in the datasheet */
726 fmt = (slot_width >> 1) - 1;
727
728 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
729 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
730 RXSSZ(0x0F));
731 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
732 TXSSZ(0x0F));
733 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
734 TXROT(7));
735 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
736 RXROT(7));
737 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
738 }
739
740 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
741
742 return 0;
743 }
744
mcasp_common_hw_param(struct davinci_mcasp * mcasp,int stream,int period_words,int channels)745 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
746 int period_words, int channels)
747 {
748 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
749 int i;
750 u8 tx_ser = 0;
751 u8 rx_ser = 0;
752 u8 slots = mcasp->tdm_slots;
753 u8 max_active_serializers = (channels + slots - 1) / slots;
754 int active_serializers, numevt;
755 u32 reg;
756 /* Default configuration */
757 if (mcasp->version < MCASP_VERSION_3)
758 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
759
760 /* All PINS as McASP */
761 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
762
763 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
764 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
765 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
766 } else {
767 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
768 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
769 }
770
771 for (i = 0; i < mcasp->num_serializer; i++) {
772 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
773 mcasp->serial_dir[i]);
774 if (mcasp->serial_dir[i] == TX_MODE &&
775 tx_ser < max_active_serializers) {
776 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
777 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
778 DISMOD_LOW, DISMOD_MASK);
779 tx_ser++;
780 } else if (mcasp->serial_dir[i] == RX_MODE &&
781 rx_ser < max_active_serializers) {
782 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
783 rx_ser++;
784 } else if (mcasp->serial_dir[i] == INACTIVE_MODE) {
785 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
786 SRMOD_INACTIVE, SRMOD_MASK);
787 }
788 }
789
790 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
791 active_serializers = tx_ser;
792 numevt = mcasp->txnumevt;
793 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
794 } else {
795 active_serializers = rx_ser;
796 numevt = mcasp->rxnumevt;
797 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
798 }
799
800 if (active_serializers < max_active_serializers) {
801 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
802 "enabled in mcasp (%d)\n", channels,
803 active_serializers * slots);
804 return -EINVAL;
805 }
806
807 /* AFIFO is not in use */
808 if (!numevt) {
809 /* Configure the burst size for platform drivers */
810 if (active_serializers > 1) {
811 /*
812 * If more than one serializers are in use we have one
813 * DMA request to provide data for all serializers.
814 * For example if three serializers are enabled the DMA
815 * need to transfer three words per DMA request.
816 */
817 dma_data->maxburst = active_serializers;
818 } else {
819 dma_data->maxburst = 0;
820 }
821 return 0;
822 }
823
824 if (period_words % active_serializers) {
825 dev_err(mcasp->dev, "Invalid combination of period words and "
826 "active serializers: %d, %d\n", period_words,
827 active_serializers);
828 return -EINVAL;
829 }
830
831 /*
832 * Calculate the optimal AFIFO depth for platform side:
833 * The number of words for numevt need to be in steps of active
834 * serializers.
835 */
836 numevt = (numevt / active_serializers) * active_serializers;
837
838 while (period_words % numevt && numevt > 0)
839 numevt -= active_serializers;
840 if (numevt <= 0)
841 numevt = active_serializers;
842
843 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
844 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
845
846 /* Configure the burst size for platform drivers */
847 if (numevt == 1)
848 numevt = 0;
849 dma_data->maxburst = numevt;
850
851 return 0;
852 }
853
mcasp_i2s_hw_param(struct davinci_mcasp * mcasp,int stream,int channels)854 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
855 int channels)
856 {
857 int i, active_slots;
858 int total_slots;
859 int active_serializers;
860 u32 mask = 0;
861 u32 busel = 0;
862
863 total_slots = mcasp->tdm_slots;
864
865 /*
866 * If more than one serializer is needed, then use them with
867 * all the specified tdm_slots. Otherwise, one serializer can
868 * cope with the transaction using just as many slots as there
869 * are channels in the stream.
870 */
871 if (mcasp->tdm_mask[stream]) {
872 active_slots = hweight32(mcasp->tdm_mask[stream]);
873 active_serializers = (channels + active_slots - 1) /
874 active_slots;
875 if (active_serializers == 1) {
876 active_slots = channels;
877 for (i = 0; i < total_slots; i++) {
878 if ((1 << i) & mcasp->tdm_mask[stream]) {
879 mask |= (1 << i);
880 if (--active_slots <= 0)
881 break;
882 }
883 }
884 }
885 } else {
886 active_serializers = (channels + total_slots - 1) / total_slots;
887 if (active_serializers == 1)
888 active_slots = channels;
889 else
890 active_slots = total_slots;
891
892 for (i = 0; i < active_slots; i++)
893 mask |= (1 << i);
894 }
895 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
896
897 if (!mcasp->dat_port)
898 busel = TXSEL;
899
900 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
901 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
902 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
903 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
904 FSXMOD(total_slots), FSXMOD(0x1FF));
905 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
906 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
907 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
908 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
909 FSRMOD(total_slots), FSRMOD(0x1FF));
910 /*
911 * If McASP is set to be TX/RX synchronous and the playback is
912 * not running already we need to configure the TX slots in
913 * order to have correct FSX on the bus
914 */
915 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
916 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
917 FSXMOD(total_slots), FSXMOD(0x1FF));
918 }
919
920 return 0;
921 }
922
923 /* S/PDIF */
mcasp_dit_hw_param(struct davinci_mcasp * mcasp,unsigned int rate)924 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
925 unsigned int rate)
926 {
927 u32 cs_value = 0;
928 u8 *cs_bytes = (u8*) &cs_value;
929
930 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
931 and LSB first */
932 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
933
934 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
935 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
936
937 /* Set the TX tdm : for all the slots */
938 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
939
940 /* Set the TX clock controls : div = 1 and internal */
941 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
942
943 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
944
945 /* Only 44100 and 48000 are valid, both have the same setting */
946 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
947
948 /* Enable the DIT */
949 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
950
951 /* Set S/PDIF channel status bits */
952 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
953 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
954
955 switch (rate) {
956 case 22050:
957 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
958 break;
959 case 24000:
960 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
961 break;
962 case 32000:
963 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
964 break;
965 case 44100:
966 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
967 break;
968 case 48000:
969 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
970 break;
971 case 88200:
972 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
973 break;
974 case 96000:
975 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
976 break;
977 case 176400:
978 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
979 break;
980 case 192000:
981 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
982 break;
983 default:
984 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
985 return -EINVAL;
986 }
987
988 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
989 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
990
991 return 0;
992 }
993
davinci_mcasp_calc_clk_div(struct davinci_mcasp * mcasp,unsigned int bclk_freq,bool set)994 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
995 unsigned int bclk_freq, bool set)
996 {
997 int error_ppm;
998 unsigned int sysclk_freq = mcasp->sysclk_freq;
999 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1000 int div = sysclk_freq / bclk_freq;
1001 int rem = sysclk_freq % bclk_freq;
1002 int aux_div = 1;
1003
1004 if (div > (ACLKXDIV_MASK + 1)) {
1005 if (reg & AHCLKXE) {
1006 aux_div = div / (ACLKXDIV_MASK + 1);
1007 if (div % (ACLKXDIV_MASK + 1))
1008 aux_div++;
1009
1010 sysclk_freq /= aux_div;
1011 div = sysclk_freq / bclk_freq;
1012 rem = sysclk_freq % bclk_freq;
1013 } else if (set) {
1014 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1015 sysclk_freq);
1016 }
1017 }
1018
1019 if (rem != 0) {
1020 if (div == 0 ||
1021 ((sysclk_freq / div) - bclk_freq) >
1022 (bclk_freq - (sysclk_freq / (div+1)))) {
1023 div++;
1024 rem = rem - bclk_freq;
1025 }
1026 }
1027 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1028 (int)bclk_freq)) / div - 1000000;
1029
1030 if (set) {
1031 if (error_ppm)
1032 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1033 error_ppm);
1034
1035 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1036 if (reg & AHCLKXE)
1037 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1038 aux_div, 0);
1039 }
1040
1041 return error_ppm;
1042 }
1043
davinci_mcasp_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)1044 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1045 struct snd_pcm_hw_params *params,
1046 struct snd_soc_dai *cpu_dai)
1047 {
1048 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1049 int word_length;
1050 int channels = params_channels(params);
1051 int period_size = params_period_size(params);
1052 int ret;
1053
1054 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1055 if (ret)
1056 return ret;
1057
1058 /*
1059 * If mcasp is BCLK master, and a BCLK divider was not provided by
1060 * the machine driver, we need to calculate the ratio.
1061 */
1062 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1063 int slots = mcasp->tdm_slots;
1064 int rate = params_rate(params);
1065 int sbits = params_width(params);
1066
1067 if (mcasp->slot_width)
1068 sbits = mcasp->slot_width;
1069
1070 davinci_mcasp_calc_clk_div(mcasp, rate * sbits * slots, true);
1071 }
1072
1073 ret = mcasp_common_hw_param(mcasp, substream->stream,
1074 period_size * channels, channels);
1075 if (ret)
1076 return ret;
1077
1078 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1079 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1080 else
1081 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1082 channels);
1083
1084 if (ret)
1085 return ret;
1086
1087 switch (params_format(params)) {
1088 case SNDRV_PCM_FORMAT_U8:
1089 case SNDRV_PCM_FORMAT_S8:
1090 word_length = 8;
1091 break;
1092
1093 case SNDRV_PCM_FORMAT_U16_LE:
1094 case SNDRV_PCM_FORMAT_S16_LE:
1095 word_length = 16;
1096 break;
1097
1098 case SNDRV_PCM_FORMAT_U24_3LE:
1099 case SNDRV_PCM_FORMAT_S24_3LE:
1100 word_length = 24;
1101 break;
1102
1103 case SNDRV_PCM_FORMAT_U24_LE:
1104 case SNDRV_PCM_FORMAT_S24_LE:
1105 word_length = 24;
1106 break;
1107
1108 case SNDRV_PCM_FORMAT_U32_LE:
1109 case SNDRV_PCM_FORMAT_S32_LE:
1110 word_length = 32;
1111 break;
1112
1113 default:
1114 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1115 return -EINVAL;
1116 }
1117
1118 davinci_config_channel_size(mcasp, word_length);
1119
1120 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1121 mcasp->channels = channels;
1122
1123 return 0;
1124 }
1125
davinci_mcasp_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)1126 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1127 int cmd, struct snd_soc_dai *cpu_dai)
1128 {
1129 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1130 int ret = 0;
1131
1132 switch (cmd) {
1133 case SNDRV_PCM_TRIGGER_RESUME:
1134 case SNDRV_PCM_TRIGGER_START:
1135 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1136 davinci_mcasp_start(mcasp, substream->stream);
1137 break;
1138 case SNDRV_PCM_TRIGGER_SUSPEND:
1139 case SNDRV_PCM_TRIGGER_STOP:
1140 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1141 davinci_mcasp_stop(mcasp, substream->stream);
1142 break;
1143
1144 default:
1145 ret = -EINVAL;
1146 }
1147
1148 return ret;
1149 }
1150
1151 static const unsigned int davinci_mcasp_dai_rates[] = {
1152 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1153 88200, 96000, 176400, 192000,
1154 };
1155
1156 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1157
davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1158 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1159 struct snd_pcm_hw_rule *rule)
1160 {
1161 struct davinci_mcasp_ruledata *rd = rule->private;
1162 struct snd_interval *ri =
1163 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1164 int sbits = params_width(params);
1165 int slots = rd->mcasp->tdm_slots;
1166 struct snd_interval range;
1167 int i;
1168
1169 if (rd->mcasp->slot_width)
1170 sbits = rd->mcasp->slot_width;
1171
1172 snd_interval_any(&range);
1173 range.empty = 1;
1174
1175 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1176 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1177 uint bclk_freq = sbits*slots*
1178 davinci_mcasp_dai_rates[i];
1179 int ppm;
1180
1181 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq,
1182 false);
1183 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1184 if (range.empty) {
1185 range.min = davinci_mcasp_dai_rates[i];
1186 range.empty = 0;
1187 }
1188 range.max = davinci_mcasp_dai_rates[i];
1189 }
1190 }
1191 }
1192
1193 dev_dbg(rd->mcasp->dev,
1194 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1195 ri->min, ri->max, range.min, range.max, sbits, slots);
1196
1197 return snd_interval_refine(hw_param_interval(params, rule->var),
1198 &range);
1199 }
1200
davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1201 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1202 struct snd_pcm_hw_rule *rule)
1203 {
1204 struct davinci_mcasp_ruledata *rd = rule->private;
1205 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1206 struct snd_mask nfmt;
1207 int rate = params_rate(params);
1208 int slots = rd->mcasp->tdm_slots;
1209 int i, count = 0;
1210
1211 snd_mask_none(&nfmt);
1212
1213 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1214 if (snd_mask_test(fmt, i)) {
1215 uint sbits = snd_pcm_format_width(i);
1216 int ppm;
1217
1218 if (rd->mcasp->slot_width)
1219 sbits = rd->mcasp->slot_width;
1220
1221 ppm = davinci_mcasp_calc_clk_div(rd->mcasp,
1222 sbits * slots * rate,
1223 false);
1224 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1225 snd_mask_set(&nfmt, i);
1226 count++;
1227 }
1228 }
1229 }
1230 dev_dbg(rd->mcasp->dev,
1231 "%d possible sample format for %d Hz and %d tdm slots\n",
1232 count, rate, slots);
1233
1234 return snd_mask_refine(fmt, &nfmt);
1235 }
1236
davinci_mcasp_hw_rule_min_periodsize(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)1237 static int davinci_mcasp_hw_rule_min_periodsize(
1238 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
1239 {
1240 struct snd_interval *period_size = hw_param_interval(params,
1241 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1242 struct snd_interval frames;
1243
1244 snd_interval_any(&frames);
1245 frames.min = 64;
1246 frames.integer = 1;
1247
1248 return snd_interval_refine(period_size, &frames);
1249 }
1250
davinci_mcasp_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)1251 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1252 struct snd_soc_dai *cpu_dai)
1253 {
1254 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1255 struct davinci_mcasp_ruledata *ruledata =
1256 &mcasp->ruledata[substream->stream];
1257 u32 max_channels = 0;
1258 int i, dir;
1259 int tdm_slots = mcasp->tdm_slots;
1260
1261 /* Do not allow more then one stream per direction */
1262 if (mcasp->substreams[substream->stream])
1263 return -EBUSY;
1264
1265 mcasp->substreams[substream->stream] = substream;
1266
1267 if (mcasp->tdm_mask[substream->stream])
1268 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1269
1270 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1271 return 0;
1272
1273 /*
1274 * Limit the maximum allowed channels for the first stream:
1275 * number of serializers for the direction * tdm slots per serializer
1276 */
1277 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1278 dir = TX_MODE;
1279 else
1280 dir = RX_MODE;
1281
1282 for (i = 0; i < mcasp->num_serializer; i++) {
1283 if (mcasp->serial_dir[i] == dir)
1284 max_channels++;
1285 }
1286 ruledata->serializers = max_channels;
1287 max_channels *= tdm_slots;
1288 /*
1289 * If the already active stream has less channels than the calculated
1290 * limnit based on the seirializers * tdm_slots, we need to use that as
1291 * a constraint for the second stream.
1292 * Otherwise (first stream or less allowed channels) we use the
1293 * calculated constraint.
1294 */
1295 if (mcasp->channels && mcasp->channels < max_channels)
1296 max_channels = mcasp->channels;
1297 /*
1298 * But we can always allow channels upto the amount of
1299 * the available tdm_slots.
1300 */
1301 if (max_channels < tdm_slots)
1302 max_channels = tdm_slots;
1303
1304 snd_pcm_hw_constraint_minmax(substream->runtime,
1305 SNDRV_PCM_HW_PARAM_CHANNELS,
1306 0, max_channels);
1307
1308 snd_pcm_hw_constraint_list(substream->runtime,
1309 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1310 &mcasp->chconstr[substream->stream]);
1311
1312 if (mcasp->slot_width)
1313 snd_pcm_hw_constraint_minmax(substream->runtime,
1314 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1315 8, mcasp->slot_width);
1316
1317 /*
1318 * If we rely on implicit BCLK divider setting we should
1319 * set constraints based on what we can provide.
1320 */
1321 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1322 int ret;
1323
1324 ruledata->mcasp = mcasp;
1325
1326 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1327 SNDRV_PCM_HW_PARAM_RATE,
1328 davinci_mcasp_hw_rule_rate,
1329 ruledata,
1330 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1331 if (ret)
1332 return ret;
1333 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1334 SNDRV_PCM_HW_PARAM_FORMAT,
1335 davinci_mcasp_hw_rule_format,
1336 ruledata,
1337 SNDRV_PCM_HW_PARAM_RATE, -1);
1338 if (ret)
1339 return ret;
1340 }
1341
1342 snd_pcm_hw_rule_add(substream->runtime, 0,
1343 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1344 davinci_mcasp_hw_rule_min_periodsize, NULL,
1345 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
1346
1347 return 0;
1348 }
1349
davinci_mcasp_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)1350 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1351 struct snd_soc_dai *cpu_dai)
1352 {
1353 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1354
1355 mcasp->substreams[substream->stream] = NULL;
1356
1357 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1358 return;
1359
1360 if (!cpu_dai->active)
1361 mcasp->channels = 0;
1362 }
1363
1364 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1365 .startup = davinci_mcasp_startup,
1366 .shutdown = davinci_mcasp_shutdown,
1367 .trigger = davinci_mcasp_trigger,
1368 .hw_params = davinci_mcasp_hw_params,
1369 .set_fmt = davinci_mcasp_set_dai_fmt,
1370 .set_clkdiv = davinci_mcasp_set_clkdiv,
1371 .set_sysclk = davinci_mcasp_set_sysclk,
1372 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
1373 };
1374
davinci_mcasp_dai_probe(struct snd_soc_dai * dai)1375 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1376 {
1377 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1378
1379 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1380 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1381
1382 return 0;
1383 }
1384
1385 #ifdef CONFIG_PM_SLEEP
davinci_mcasp_suspend(struct snd_soc_dai * dai)1386 static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1387 {
1388 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1389 struct davinci_mcasp_context *context = &mcasp->context;
1390 u32 reg;
1391 int i;
1392
1393 context->pm_state = pm_runtime_active(mcasp->dev);
1394 if (!context->pm_state)
1395 pm_runtime_get_sync(mcasp->dev);
1396
1397 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1398 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
1399
1400 if (mcasp->txnumevt) {
1401 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1402 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1403 }
1404 if (mcasp->rxnumevt) {
1405 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1406 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1407 }
1408
1409 for (i = 0; i < mcasp->num_serializer; i++)
1410 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1411 DAVINCI_MCASP_XRSRCTL_REG(i));
1412
1413 pm_runtime_put_sync(mcasp->dev);
1414
1415 return 0;
1416 }
1417
davinci_mcasp_resume(struct snd_soc_dai * dai)1418 static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1419 {
1420 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1421 struct davinci_mcasp_context *context = &mcasp->context;
1422 u32 reg;
1423 int i;
1424
1425 pm_runtime_get_sync(mcasp->dev);
1426
1427 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1428 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
1429
1430 if (mcasp->txnumevt) {
1431 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1432 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1433 }
1434 if (mcasp->rxnumevt) {
1435 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1436 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1437 }
1438
1439 for (i = 0; i < mcasp->num_serializer; i++)
1440 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1441 context->xrsr_regs[i]);
1442
1443 if (!context->pm_state)
1444 pm_runtime_put_sync(mcasp->dev);
1445
1446 return 0;
1447 }
1448 #else
1449 #define davinci_mcasp_suspend NULL
1450 #define davinci_mcasp_resume NULL
1451 #endif
1452
1453 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1454
1455 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1456 SNDRV_PCM_FMTBIT_U8 | \
1457 SNDRV_PCM_FMTBIT_S16_LE | \
1458 SNDRV_PCM_FMTBIT_U16_LE | \
1459 SNDRV_PCM_FMTBIT_S24_LE | \
1460 SNDRV_PCM_FMTBIT_U24_LE | \
1461 SNDRV_PCM_FMTBIT_S24_3LE | \
1462 SNDRV_PCM_FMTBIT_U24_3LE | \
1463 SNDRV_PCM_FMTBIT_S32_LE | \
1464 SNDRV_PCM_FMTBIT_U32_LE)
1465
1466 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1467 {
1468 .name = "davinci-mcasp.0",
1469 .probe = davinci_mcasp_dai_probe,
1470 .suspend = davinci_mcasp_suspend,
1471 .resume = davinci_mcasp_resume,
1472 .playback = {
1473 .channels_min = 1,
1474 .channels_max = 32 * 16,
1475 .rates = DAVINCI_MCASP_RATES,
1476 .formats = DAVINCI_MCASP_PCM_FMTS,
1477 },
1478 .capture = {
1479 .channels_min = 1,
1480 .channels_max = 32 * 16,
1481 .rates = DAVINCI_MCASP_RATES,
1482 .formats = DAVINCI_MCASP_PCM_FMTS,
1483 },
1484 .ops = &davinci_mcasp_dai_ops,
1485
1486 .symmetric_samplebits = 1,
1487 .symmetric_rates = 1,
1488 },
1489 {
1490 .name = "davinci-mcasp.1",
1491 .probe = davinci_mcasp_dai_probe,
1492 .playback = {
1493 .channels_min = 1,
1494 .channels_max = 384,
1495 .rates = DAVINCI_MCASP_RATES,
1496 .formats = DAVINCI_MCASP_PCM_FMTS,
1497 },
1498 .ops = &davinci_mcasp_dai_ops,
1499 },
1500
1501 };
1502
1503 static const struct snd_soc_component_driver davinci_mcasp_component = {
1504 .name = "davinci-mcasp",
1505 };
1506
1507 /* Some HW specific values and defaults. The rest is filled in from DT. */
1508 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1509 .tx_dma_offset = 0x400,
1510 .rx_dma_offset = 0x400,
1511 .version = MCASP_VERSION_1,
1512 };
1513
1514 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1515 .tx_dma_offset = 0x2000,
1516 .rx_dma_offset = 0x2000,
1517 .version = MCASP_VERSION_2,
1518 };
1519
1520 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1521 .tx_dma_offset = 0,
1522 .rx_dma_offset = 0,
1523 .version = MCASP_VERSION_3,
1524 };
1525
1526 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1527 /* The CFG port offset will be calculated if it is needed */
1528 .tx_dma_offset = 0,
1529 .rx_dma_offset = 0,
1530 .version = MCASP_VERSION_4,
1531 };
1532
1533 static const struct of_device_id mcasp_dt_ids[] = {
1534 {
1535 .compatible = "ti,dm646x-mcasp-audio",
1536 .data = &dm646x_mcasp_pdata,
1537 },
1538 {
1539 .compatible = "ti,da830-mcasp-audio",
1540 .data = &da830_mcasp_pdata,
1541 },
1542 {
1543 .compatible = "ti,am33xx-mcasp-audio",
1544 .data = &am33xx_mcasp_pdata,
1545 },
1546 {
1547 .compatible = "ti,dra7-mcasp-audio",
1548 .data = &dra7_mcasp_pdata,
1549 },
1550 { /* sentinel */ }
1551 };
1552 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1553
mcasp_reparent_fck(struct platform_device * pdev)1554 static int mcasp_reparent_fck(struct platform_device *pdev)
1555 {
1556 struct device_node *node = pdev->dev.of_node;
1557 struct clk *gfclk, *parent_clk;
1558 const char *parent_name;
1559 int ret;
1560
1561 if (!node)
1562 return 0;
1563
1564 parent_name = of_get_property(node, "fck_parent", NULL);
1565 if (!parent_name)
1566 return 0;
1567
1568 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1569
1570 gfclk = clk_get(&pdev->dev, "fck");
1571 if (IS_ERR(gfclk)) {
1572 dev_err(&pdev->dev, "failed to get fck\n");
1573 return PTR_ERR(gfclk);
1574 }
1575
1576 parent_clk = clk_get(NULL, parent_name);
1577 if (IS_ERR(parent_clk)) {
1578 dev_err(&pdev->dev, "failed to get parent clock\n");
1579 ret = PTR_ERR(parent_clk);
1580 goto err1;
1581 }
1582
1583 ret = clk_set_parent(gfclk, parent_clk);
1584 if (ret) {
1585 dev_err(&pdev->dev, "failed to reparent fck\n");
1586 goto err2;
1587 }
1588
1589 err2:
1590 clk_put(parent_clk);
1591 err1:
1592 clk_put(gfclk);
1593 return ret;
1594 }
1595
davinci_mcasp_set_pdata_from_of(struct platform_device * pdev)1596 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1597 struct platform_device *pdev)
1598 {
1599 struct device_node *np = pdev->dev.of_node;
1600 struct davinci_mcasp_pdata *pdata = NULL;
1601 const struct of_device_id *match =
1602 of_match_device(mcasp_dt_ids, &pdev->dev);
1603 struct of_phandle_args dma_spec;
1604
1605 const u32 *of_serial_dir32;
1606 u32 val;
1607 int i, ret = 0;
1608
1609 if (pdev->dev.platform_data) {
1610 pdata = pdev->dev.platform_data;
1611 return pdata;
1612 } else if (match) {
1613 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1614 GFP_KERNEL);
1615 if (!pdata) {
1616 ret = -ENOMEM;
1617 return pdata;
1618 }
1619 } else {
1620 /* control shouldn't reach here. something is wrong */
1621 ret = -EINVAL;
1622 goto nodata;
1623 }
1624
1625 ret = of_property_read_u32(np, "op-mode", &val);
1626 if (ret >= 0)
1627 pdata->op_mode = val;
1628
1629 ret = of_property_read_u32(np, "tdm-slots", &val);
1630 if (ret >= 0) {
1631 if (val < 2 || val > 32) {
1632 dev_err(&pdev->dev,
1633 "tdm-slots must be in rage [2-32]\n");
1634 ret = -EINVAL;
1635 goto nodata;
1636 }
1637
1638 pdata->tdm_slots = val;
1639 }
1640
1641 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1642 val /= sizeof(u32);
1643 if (of_serial_dir32) {
1644 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1645 (sizeof(*of_serial_dir) * val),
1646 GFP_KERNEL);
1647 if (!of_serial_dir) {
1648 ret = -ENOMEM;
1649 goto nodata;
1650 }
1651
1652 for (i = 0; i < val; i++)
1653 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1654
1655 pdata->num_serializer = val;
1656 pdata->serial_dir = of_serial_dir;
1657 }
1658
1659 ret = of_property_match_string(np, "dma-names", "tx");
1660 if (ret < 0)
1661 goto nodata;
1662
1663 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1664 &dma_spec);
1665 if (ret < 0)
1666 goto nodata;
1667
1668 pdata->tx_dma_channel = dma_spec.args[0];
1669
1670 /* RX is not valid in DIT mode */
1671 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1672 ret = of_property_match_string(np, "dma-names", "rx");
1673 if (ret < 0)
1674 goto nodata;
1675
1676 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1677 &dma_spec);
1678 if (ret < 0)
1679 goto nodata;
1680
1681 pdata->rx_dma_channel = dma_spec.args[0];
1682 }
1683
1684 ret = of_property_read_u32(np, "tx-num-evt", &val);
1685 if (ret >= 0)
1686 pdata->txnumevt = val;
1687
1688 ret = of_property_read_u32(np, "rx-num-evt", &val);
1689 if (ret >= 0)
1690 pdata->rxnumevt = val;
1691
1692 ret = of_property_read_u32(np, "sram-size-playback", &val);
1693 if (ret >= 0)
1694 pdata->sram_size_playback = val;
1695
1696 ret = of_property_read_u32(np, "sram-size-capture", &val);
1697 if (ret >= 0)
1698 pdata->sram_size_capture = val;
1699
1700 return pdata;
1701
1702 nodata:
1703 if (ret < 0) {
1704 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1705 ret);
1706 pdata = NULL;
1707 }
1708 return pdata;
1709 }
1710
1711 enum {
1712 PCM_EDMA,
1713 PCM_SDMA,
1714 };
1715 static const char *sdma_prefix = "ti,omap";
1716
davinci_mcasp_get_dma_type(struct davinci_mcasp * mcasp)1717 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1718 {
1719 struct dma_chan *chan;
1720 const char *tmp;
1721 int ret = PCM_EDMA;
1722
1723 if (!mcasp->dev->of_node)
1724 return PCM_EDMA;
1725
1726 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1727 chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1728 if (IS_ERR(chan)) {
1729 if (PTR_ERR(chan) != -EPROBE_DEFER)
1730 dev_err(mcasp->dev,
1731 "Can't verify DMA configuration (%ld)\n",
1732 PTR_ERR(chan));
1733 return PTR_ERR(chan);
1734 }
1735 if (WARN_ON(!chan->device || !chan->device->dev))
1736 return -EINVAL;
1737
1738 if (chan->device->dev->of_node)
1739 ret = of_property_read_string(chan->device->dev->of_node,
1740 "compatible", &tmp);
1741 else
1742 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1743
1744 dma_release_channel(chan);
1745 if (ret)
1746 return ret;
1747
1748 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1749 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1750 return PCM_SDMA;
1751
1752 return PCM_EDMA;
1753 }
1754
davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata * pdata)1755 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
1756 {
1757 int i;
1758 u32 offset = 0;
1759
1760 if (pdata->version != MCASP_VERSION_4)
1761 return pdata->tx_dma_offset;
1762
1763 for (i = 0; i < pdata->num_serializer; i++) {
1764 if (pdata->serial_dir[i] == TX_MODE) {
1765 if (!offset) {
1766 offset = DAVINCI_MCASP_TXBUF_REG(i);
1767 } else {
1768 pr_err("%s: Only one serializer allowed!\n",
1769 __func__);
1770 break;
1771 }
1772 }
1773 }
1774
1775 return offset;
1776 }
1777
davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata * pdata)1778 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
1779 {
1780 int i;
1781 u32 offset = 0;
1782
1783 if (pdata->version != MCASP_VERSION_4)
1784 return pdata->rx_dma_offset;
1785
1786 for (i = 0; i < pdata->num_serializer; i++) {
1787 if (pdata->serial_dir[i] == RX_MODE) {
1788 if (!offset) {
1789 offset = DAVINCI_MCASP_RXBUF_REG(i);
1790 } else {
1791 pr_err("%s: Only one serializer allowed!\n",
1792 __func__);
1793 break;
1794 }
1795 }
1796 }
1797
1798 return offset;
1799 }
1800
davinci_mcasp_probe(struct platform_device * pdev)1801 static int davinci_mcasp_probe(struct platform_device *pdev)
1802 {
1803 struct snd_dmaengine_dai_dma_data *dma_data;
1804 struct resource *mem, *res, *dat;
1805 struct davinci_mcasp_pdata *pdata;
1806 struct davinci_mcasp *mcasp;
1807 char *irq_name;
1808 int *dma;
1809 int irq;
1810 int ret;
1811
1812 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1813 dev_err(&pdev->dev, "No platform data supplied\n");
1814 return -EINVAL;
1815 }
1816
1817 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1818 GFP_KERNEL);
1819 if (!mcasp)
1820 return -ENOMEM;
1821
1822 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1823 if (!pdata) {
1824 dev_err(&pdev->dev, "no platform data\n");
1825 return -EINVAL;
1826 }
1827
1828 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1829 if (!mem) {
1830 dev_warn(mcasp->dev,
1831 "\"mpu\" mem resource not found, using index 0\n");
1832 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1833 if (!mem) {
1834 dev_err(&pdev->dev, "no mem resource?\n");
1835 return -ENODEV;
1836 }
1837 }
1838
1839 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
1840 if (IS_ERR(mcasp->base))
1841 return PTR_ERR(mcasp->base);
1842
1843 pm_runtime_enable(&pdev->dev);
1844
1845 mcasp->op_mode = pdata->op_mode;
1846 /* sanity check for tdm slots parameter */
1847 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1848 if (pdata->tdm_slots < 2) {
1849 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1850 pdata->tdm_slots);
1851 mcasp->tdm_slots = 2;
1852 } else if (pdata->tdm_slots > 32) {
1853 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1854 pdata->tdm_slots);
1855 mcasp->tdm_slots = 32;
1856 } else {
1857 mcasp->tdm_slots = pdata->tdm_slots;
1858 }
1859 }
1860
1861 mcasp->num_serializer = pdata->num_serializer;
1862 #ifdef CONFIG_PM_SLEEP
1863 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
1864 mcasp->num_serializer, sizeof(u32),
1865 GFP_KERNEL);
1866 if (!mcasp->context.xrsr_regs) {
1867 ret = -ENOMEM;
1868 goto err;
1869 }
1870 #endif
1871 mcasp->serial_dir = pdata->serial_dir;
1872 mcasp->version = pdata->version;
1873 mcasp->txnumevt = pdata->txnumevt;
1874 mcasp->rxnumevt = pdata->rxnumevt;
1875
1876 mcasp->dev = &pdev->dev;
1877
1878 irq = platform_get_irq_byname(pdev, "common");
1879 if (irq >= 0) {
1880 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
1881 dev_name(&pdev->dev));
1882 if (!irq_name) {
1883 ret = -ENOMEM;
1884 goto err;
1885 }
1886 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1887 davinci_mcasp_common_irq_handler,
1888 IRQF_ONESHOT | IRQF_SHARED,
1889 irq_name, mcasp);
1890 if (ret) {
1891 dev_err(&pdev->dev, "common IRQ request failed\n");
1892 goto err;
1893 }
1894
1895 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1896 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1897 }
1898
1899 irq = platform_get_irq_byname(pdev, "rx");
1900 if (irq >= 0) {
1901 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
1902 dev_name(&pdev->dev));
1903 if (!irq_name) {
1904 ret = -ENOMEM;
1905 goto err;
1906 }
1907 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1908 davinci_mcasp_rx_irq_handler,
1909 IRQF_ONESHOT, irq_name, mcasp);
1910 if (ret) {
1911 dev_err(&pdev->dev, "RX IRQ request failed\n");
1912 goto err;
1913 }
1914
1915 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1916 }
1917
1918 irq = platform_get_irq_byname(pdev, "tx");
1919 if (irq >= 0) {
1920 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
1921 dev_name(&pdev->dev));
1922 if (!irq_name) {
1923 ret = -ENOMEM;
1924 goto err;
1925 }
1926 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1927 davinci_mcasp_tx_irq_handler,
1928 IRQF_ONESHOT, irq_name, mcasp);
1929 if (ret) {
1930 dev_err(&pdev->dev, "TX IRQ request failed\n");
1931 goto err;
1932 }
1933
1934 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1935 }
1936
1937 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1938 if (dat)
1939 mcasp->dat_port = true;
1940
1941 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1942 if (dat)
1943 dma_data->addr = dat->start;
1944 else
1945 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
1946
1947 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
1948 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1949 if (res)
1950 *dma = res->start;
1951 else
1952 *dma = pdata->tx_dma_channel;
1953
1954 /* dmaengine filter data for DT and non-DT boot */
1955 if (pdev->dev.of_node)
1956 dma_data->filter_data = "tx";
1957 else
1958 dma_data->filter_data = dma;
1959
1960 /* RX is not valid in DIT mode */
1961 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
1962 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1963 if (dat)
1964 dma_data->addr = dat->start;
1965 else
1966 dma_data->addr =
1967 mem->start + davinci_mcasp_rxdma_offset(pdata);
1968
1969 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
1970 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1971 if (res)
1972 *dma = res->start;
1973 else
1974 *dma = pdata->rx_dma_channel;
1975
1976 /* dmaengine filter data for DT and non-DT boot */
1977 if (pdev->dev.of_node)
1978 dma_data->filter_data = "rx";
1979 else
1980 dma_data->filter_data = dma;
1981 }
1982
1983 if (mcasp->version < MCASP_VERSION_3) {
1984 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1985 /* dma_params->dma_addr is pointing to the data port address */
1986 mcasp->dat_port = true;
1987 } else {
1988 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1989 }
1990
1991 /* Allocate memory for long enough list for all possible
1992 * scenarios. Maximum number tdm slots is 32 and there cannot
1993 * be more serializers than given in the configuration. The
1994 * serializer directions could be taken into account, but it
1995 * would make code much more complex and save only couple of
1996 * bytes.
1997 */
1998 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
1999 devm_kcalloc(mcasp->dev,
2000 32 + mcasp->num_serializer - 1,
2001 sizeof(unsigned int),
2002 GFP_KERNEL);
2003
2004 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2005 devm_kcalloc(mcasp->dev,
2006 32 + mcasp->num_serializer - 1,
2007 sizeof(unsigned int),
2008 GFP_KERNEL);
2009
2010 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2011 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2012 ret = -ENOMEM;
2013 goto err;
2014 }
2015
2016 ret = davinci_mcasp_set_ch_constraints(mcasp);
2017 if (ret)
2018 goto err;
2019
2020 dev_set_drvdata(&pdev->dev, mcasp);
2021
2022 mcasp_reparent_fck(pdev);
2023
2024 ret = devm_snd_soc_register_component(&pdev->dev,
2025 &davinci_mcasp_component,
2026 &davinci_mcasp_dai[pdata->op_mode], 1);
2027
2028 if (ret != 0)
2029 goto err;
2030
2031 ret = davinci_mcasp_get_dma_type(mcasp);
2032 switch (ret) {
2033 case PCM_EDMA:
2034 #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
2035 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
2036 IS_MODULE(CONFIG_SND_EDMA_SOC))
2037 ret = edma_pcm_platform_register(&pdev->dev);
2038 #else
2039 dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n");
2040 ret = -EINVAL;
2041 goto err;
2042 #endif
2043 break;
2044 case PCM_SDMA:
2045 #if IS_BUILTIN(CONFIG_SND_SDMA_SOC) || \
2046 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
2047 IS_MODULE(CONFIG_SND_SDMA_SOC))
2048 ret = sdma_pcm_platform_register(&pdev->dev, NULL, NULL);
2049 #else
2050 dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n");
2051 ret = -EINVAL;
2052 goto err;
2053 #endif
2054 break;
2055 default:
2056 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2057 case -EPROBE_DEFER:
2058 goto err;
2059 break;
2060 }
2061
2062 if (ret) {
2063 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
2064 goto err;
2065 }
2066
2067 return 0;
2068
2069 err:
2070 pm_runtime_disable(&pdev->dev);
2071 return ret;
2072 }
2073
davinci_mcasp_remove(struct platform_device * pdev)2074 static int davinci_mcasp_remove(struct platform_device *pdev)
2075 {
2076 pm_runtime_disable(&pdev->dev);
2077
2078 return 0;
2079 }
2080
2081 static struct platform_driver davinci_mcasp_driver = {
2082 .probe = davinci_mcasp_probe,
2083 .remove = davinci_mcasp_remove,
2084 .driver = {
2085 .name = "davinci-mcasp",
2086 .of_match_table = mcasp_dt_ids,
2087 },
2088 };
2089
2090 module_platform_driver(davinci_mcasp_driver);
2091
2092 MODULE_AUTHOR("Steve Chen");
2093 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2094 MODULE_LICENSE("GPL");
2095
