1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26
27 #include <linux/firmware.h>
28 #include <linux/module.h>
29 #include <linux/dmi.h>
30 #include <linux/pci.h>
31 #include <linux/debugfs.h>
32 #include <drm/drm_drv.h>
33
34 #include "amdgpu.h"
35 #include "amdgpu_pm.h"
36 #include "amdgpu_vcn.h"
37 #include "soc15d.h"
38
39 /* Firmware Names */
40 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin"
41 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin"
42 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin"
43 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin"
44 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin"
45 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin"
46 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin"
47 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin"
48 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin"
49 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin"
50 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin"
51 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin"
52 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin"
53 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin"
54 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin"
55 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin"
56 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin"
57 #define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin"
58 #define FIRMWARE_VCN4_0_2 "amdgpu/vcn_4_0_2.bin"
59 #define FIRMWARE_VCN4_0_3 "amdgpu/vcn_4_0_3.bin"
60 #define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin"
61
62 MODULE_FIRMWARE(FIRMWARE_RAVEN);
63 MODULE_FIRMWARE(FIRMWARE_PICASSO);
64 MODULE_FIRMWARE(FIRMWARE_RAVEN2);
65 MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
66 MODULE_FIRMWARE(FIRMWARE_RENOIR);
67 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE);
68 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN);
69 MODULE_FIRMWARE(FIRMWARE_NAVI10);
70 MODULE_FIRMWARE(FIRMWARE_NAVI14);
71 MODULE_FIRMWARE(FIRMWARE_NAVI12);
72 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID);
73 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER);
74 MODULE_FIRMWARE(FIRMWARE_VANGOGH);
75 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH);
76 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY);
77 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP);
78 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2);
79 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0);
80 MODULE_FIRMWARE(FIRMWARE_VCN4_0_2);
81 MODULE_FIRMWARE(FIRMWARE_VCN4_0_3);
82 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4);
83
84 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
85
amdgpu_vcn_early_init(struct amdgpu_device * adev)86 int amdgpu_vcn_early_init(struct amdgpu_device *adev)
87 {
88 char ucode_prefix[30];
89 char fw_name[40];
90 int r;
91
92 amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix));
93 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);
94 r = amdgpu_ucode_request(adev, &adev->vcn.fw, fw_name);
95 if (r)
96 amdgpu_ucode_release(&adev->vcn.fw);
97
98 return r;
99 }
100
amdgpu_vcn_sw_init(struct amdgpu_device * adev)101 int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
102 {
103 unsigned long bo_size;
104 const struct common_firmware_header *hdr;
105 unsigned char fw_check;
106 unsigned int fw_shared_size, log_offset;
107 int i, r;
108
109 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
110 mutex_init(&adev->vcn.vcn_pg_lock);
111 mutex_init(&adev->vcn.vcn1_jpeg1_workaround);
112 atomic_set(&adev->vcn.total_submission_cnt, 0);
113 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
114 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
115
116 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
117 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
118 adev->vcn.indirect_sram = true;
119
120 /*
121 * Some Steam Deck's BIOS versions are incompatible with the
122 * indirect SRAM mode, leading to amdgpu being unable to get
123 * properly probed (and even potentially crashing the kernel).
124 * Hence, check for these versions here - notice this is
125 * restricted to Vangogh (Deck's APU).
126 */
127 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 2)) {
128 const char *bios_ver = dmi_get_system_info(DMI_BIOS_VERSION);
129
130 if (bios_ver && (!strncmp("F7A0113", bios_ver, 7) ||
131 !strncmp("F7A0114", bios_ver, 7))) {
132 adev->vcn.indirect_sram = false;
133 dev_info(adev->dev,
134 "Steam Deck quirk: indirect SRAM disabled on BIOS %s\n", bios_ver);
135 }
136 }
137
138 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
139 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
140
141 /* Bit 20-23, it is encode major and non-zero for new naming convention.
142 * This field is part of version minor and DRM_DISABLED_FLAG in old naming
143 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
144 * is zero in old naming convention, this field is always zero so far.
145 * These four bits are used to tell which naming convention is present.
146 */
147 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
148 if (fw_check) {
149 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
150
151 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
152 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
153 enc_major = fw_check;
154 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
155 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
156 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n",
157 enc_major, enc_minor, dec_ver, vep, fw_rev);
158 } else {
159 unsigned int version_major, version_minor, family_id;
160
161 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
162 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
163 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
164 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n",
165 version_major, version_minor, family_id);
166 }
167
168 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
169 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
170 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
171
172 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)) {
173 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared));
174 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log);
175 } else {
176 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
177 log_offset = offsetof(struct amdgpu_fw_shared, fw_log);
178 }
179
180 bo_size += fw_shared_size;
181
182 if (amdgpu_vcnfw_log)
183 bo_size += AMDGPU_VCNFW_LOG_SIZE;
184
185 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
186 if (adev->vcn.harvest_config & (1 << i))
187 continue;
188
189 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
190 AMDGPU_GEM_DOMAIN_VRAM |
191 AMDGPU_GEM_DOMAIN_GTT,
192 &adev->vcn.inst[i].vcpu_bo,
193 &adev->vcn.inst[i].gpu_addr,
194 &adev->vcn.inst[i].cpu_addr);
195 if (r) {
196 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
197 return r;
198 }
199
200 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr +
201 bo_size - fw_shared_size;
202 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr +
203 bo_size - fw_shared_size;
204
205 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size;
206
207 if (amdgpu_vcnfw_log) {
208 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
209 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
210 adev->vcn.inst[i].fw_shared.log_offset = log_offset;
211 }
212
213 if (adev->vcn.indirect_sram) {
214 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
215 AMDGPU_GEM_DOMAIN_VRAM |
216 AMDGPU_GEM_DOMAIN_GTT,
217 &adev->vcn.inst[i].dpg_sram_bo,
218 &adev->vcn.inst[i].dpg_sram_gpu_addr,
219 &adev->vcn.inst[i].dpg_sram_cpu_addr);
220 if (r) {
221 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r);
222 return r;
223 }
224 }
225 }
226
227 return 0;
228 }
229
amdgpu_vcn_sw_fini(struct amdgpu_device * adev)230 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
231 {
232 int i, j;
233
234 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
235 if (adev->vcn.harvest_config & (1 << j))
236 continue;
237
238 amdgpu_bo_free_kernel(
239 &adev->vcn.inst[j].dpg_sram_bo,
240 &adev->vcn.inst[j].dpg_sram_gpu_addr,
241 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr);
242
243 kvfree(adev->vcn.inst[j].saved_bo);
244
245 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
246 &adev->vcn.inst[j].gpu_addr,
247 (void **)&adev->vcn.inst[j].cpu_addr);
248
249 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
250
251 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
252 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
253 }
254
255 amdgpu_ucode_release(&adev->vcn.fw);
256 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
257 mutex_destroy(&adev->vcn.vcn_pg_lock);
258
259 return 0;
260 }
261
262 /* from vcn4 and above, only unified queue is used */
amdgpu_vcn_using_unified_queue(struct amdgpu_ring * ring)263 static bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring)
264 {
265 struct amdgpu_device *adev = ring->adev;
266 bool ret = false;
267
268 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0))
269 ret = true;
270
271 return ret;
272 }
273
amdgpu_vcn_is_disabled_vcn(struct amdgpu_device * adev,enum vcn_ring_type type,uint32_t vcn_instance)274 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)
275 {
276 bool ret = false;
277 int vcn_config = adev->vcn.vcn_config[vcn_instance];
278
279 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK))
280 ret = true;
281 else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK))
282 ret = true;
283 else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK))
284 ret = true;
285
286 return ret;
287 }
288
amdgpu_vcn_suspend(struct amdgpu_device * adev)289 int amdgpu_vcn_suspend(struct amdgpu_device *adev)
290 {
291 unsigned int size;
292 void *ptr;
293 int i, idx;
294
295 cancel_delayed_work_sync(&adev->vcn.idle_work);
296
297 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
298 if (adev->vcn.harvest_config & (1 << i))
299 continue;
300 if (adev->vcn.inst[i].vcpu_bo == NULL)
301 return 0;
302
303 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
304 ptr = adev->vcn.inst[i].cpu_addr;
305
306 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
307 if (!adev->vcn.inst[i].saved_bo)
308 return -ENOMEM;
309
310 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
311 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
312 drm_dev_exit(idx);
313 }
314 }
315 return 0;
316 }
317
amdgpu_vcn_resume(struct amdgpu_device * adev)318 int amdgpu_vcn_resume(struct amdgpu_device *adev)
319 {
320 unsigned int size;
321 void *ptr;
322 int i, idx;
323
324 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
325 if (adev->vcn.harvest_config & (1 << i))
326 continue;
327 if (adev->vcn.inst[i].vcpu_bo == NULL)
328 return -EINVAL;
329
330 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
331 ptr = adev->vcn.inst[i].cpu_addr;
332
333 if (adev->vcn.inst[i].saved_bo != NULL) {
334 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
335 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
336 drm_dev_exit(idx);
337 }
338 kvfree(adev->vcn.inst[i].saved_bo);
339 adev->vcn.inst[i].saved_bo = NULL;
340 } else {
341 const struct common_firmware_header *hdr;
342 unsigned int offset;
343
344 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
345 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
346 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
347 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
348 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
349 le32_to_cpu(hdr->ucode_size_bytes));
350 drm_dev_exit(idx);
351 }
352 size -= le32_to_cpu(hdr->ucode_size_bytes);
353 ptr += le32_to_cpu(hdr->ucode_size_bytes);
354 }
355 memset_io(ptr, 0, size);
356 }
357 }
358 return 0;
359 }
360
amdgpu_vcn_idle_work_handler(struct work_struct * work)361 static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
362 {
363 struct amdgpu_device *adev =
364 container_of(work, struct amdgpu_device, vcn.idle_work.work);
365 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
366 unsigned int i, j;
367 int r = 0;
368
369 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
370 if (adev->vcn.harvest_config & (1 << j))
371 continue;
372
373 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
374 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
375
376 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
377 struct dpg_pause_state new_state;
378
379 if (fence[j] ||
380 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt)))
381 new_state.fw_based = VCN_DPG_STATE__PAUSE;
382 else
383 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
384
385 adev->vcn.pause_dpg_mode(adev, j, &new_state);
386 }
387
388 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
389 fences += fence[j];
390 }
391
392 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
393 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
394 AMD_PG_STATE_GATE);
395 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
396 false);
397 if (r)
398 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r);
399 } else {
400 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
401 }
402 }
403
amdgpu_vcn_ring_begin_use(struct amdgpu_ring * ring)404 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
405 {
406 struct amdgpu_device *adev = ring->adev;
407 int r = 0;
408
409 atomic_inc(&adev->vcn.total_submission_cnt);
410
411 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
412 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
413 true);
414 if (r)
415 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r);
416 }
417
418 mutex_lock(&adev->vcn.vcn_pg_lock);
419 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
420 AMD_PG_STATE_UNGATE);
421
422 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
423 struct dpg_pause_state new_state;
424
425 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) {
426 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
427 new_state.fw_based = VCN_DPG_STATE__PAUSE;
428 } else {
429 unsigned int fences = 0;
430 unsigned int i;
431
432 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
433 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
434
435 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt))
436 new_state.fw_based = VCN_DPG_STATE__PAUSE;
437 else
438 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
439 }
440
441 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state);
442 }
443 mutex_unlock(&adev->vcn.vcn_pg_lock);
444 }
445
amdgpu_vcn_ring_end_use(struct amdgpu_ring * ring)446 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
447 {
448 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
449 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
450 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
451
452 atomic_dec(&ring->adev->vcn.total_submission_cnt);
453
454 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
455 }
456
amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring * ring)457 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
458 {
459 struct amdgpu_device *adev = ring->adev;
460 uint32_t tmp = 0;
461 unsigned int i;
462 int r;
463
464 /* VCN in SRIOV does not support direct register read/write */
465 if (amdgpu_sriov_vf(adev))
466 return 0;
467
468 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
469 r = amdgpu_ring_alloc(ring, 3);
470 if (r)
471 return r;
472 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
473 amdgpu_ring_write(ring, 0xDEADBEEF);
474 amdgpu_ring_commit(ring);
475 for (i = 0; i < adev->usec_timeout; i++) {
476 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
477 if (tmp == 0xDEADBEEF)
478 break;
479 udelay(1);
480 }
481
482 if (i >= adev->usec_timeout)
483 r = -ETIMEDOUT;
484
485 return r;
486 }
487
amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring * ring)488 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
489 {
490 struct amdgpu_device *adev = ring->adev;
491 uint32_t rptr;
492 unsigned int i;
493 int r;
494
495 if (amdgpu_sriov_vf(adev))
496 return 0;
497
498 r = amdgpu_ring_alloc(ring, 16);
499 if (r)
500 return r;
501
502 rptr = amdgpu_ring_get_rptr(ring);
503
504 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
505 amdgpu_ring_commit(ring);
506
507 for (i = 0; i < adev->usec_timeout; i++) {
508 if (amdgpu_ring_get_rptr(ring) != rptr)
509 break;
510 udelay(1);
511 }
512
513 if (i >= adev->usec_timeout)
514 r = -ETIMEDOUT;
515
516 return r;
517 }
518
amdgpu_vcn_dec_send_msg(struct amdgpu_ring * ring,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)519 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
520 struct amdgpu_ib *ib_msg,
521 struct dma_fence **fence)
522 {
523 u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
524 struct amdgpu_device *adev = ring->adev;
525 struct dma_fence *f = NULL;
526 struct amdgpu_job *job;
527 struct amdgpu_ib *ib;
528 int i, r;
529
530 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
531 64, AMDGPU_IB_POOL_DIRECT,
532 &job);
533 if (r)
534 goto err;
535
536 ib = &job->ibs[0];
537 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
538 ib->ptr[1] = addr;
539 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
540 ib->ptr[3] = addr >> 32;
541 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
542 ib->ptr[5] = 0;
543 for (i = 6; i < 16; i += 2) {
544 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
545 ib->ptr[i+1] = 0;
546 }
547 ib->length_dw = 16;
548
549 r = amdgpu_job_submit_direct(job, ring, &f);
550 if (r)
551 goto err_free;
552
553 amdgpu_ib_free(adev, ib_msg, f);
554
555 if (fence)
556 *fence = dma_fence_get(f);
557 dma_fence_put(f);
558
559 return 0;
560
561 err_free:
562 amdgpu_job_free(job);
563 err:
564 amdgpu_ib_free(adev, ib_msg, f);
565 return r;
566 }
567
amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib)568 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
569 struct amdgpu_ib *ib)
570 {
571 struct amdgpu_device *adev = ring->adev;
572 uint32_t *msg;
573 int r, i;
574
575 memset(ib, 0, sizeof(*ib));
576 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
577 AMDGPU_IB_POOL_DIRECT,
578 ib);
579 if (r)
580 return r;
581
582 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
583 msg[0] = cpu_to_le32(0x00000028);
584 msg[1] = cpu_to_le32(0x00000038);
585 msg[2] = cpu_to_le32(0x00000001);
586 msg[3] = cpu_to_le32(0x00000000);
587 msg[4] = cpu_to_le32(handle);
588 msg[5] = cpu_to_le32(0x00000000);
589 msg[6] = cpu_to_le32(0x00000001);
590 msg[7] = cpu_to_le32(0x00000028);
591 msg[8] = cpu_to_le32(0x00000010);
592 msg[9] = cpu_to_le32(0x00000000);
593 msg[10] = cpu_to_le32(0x00000007);
594 msg[11] = cpu_to_le32(0x00000000);
595 msg[12] = cpu_to_le32(0x00000780);
596 msg[13] = cpu_to_le32(0x00000440);
597 for (i = 14; i < 1024; ++i)
598 msg[i] = cpu_to_le32(0x0);
599
600 return 0;
601 }
602
amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib)603 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
604 struct amdgpu_ib *ib)
605 {
606 struct amdgpu_device *adev = ring->adev;
607 uint32_t *msg;
608 int r, i;
609
610 memset(ib, 0, sizeof(*ib));
611 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
612 AMDGPU_IB_POOL_DIRECT,
613 ib);
614 if (r)
615 return r;
616
617 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
618 msg[0] = cpu_to_le32(0x00000028);
619 msg[1] = cpu_to_le32(0x00000018);
620 msg[2] = cpu_to_le32(0x00000000);
621 msg[3] = cpu_to_le32(0x00000002);
622 msg[4] = cpu_to_le32(handle);
623 msg[5] = cpu_to_le32(0x00000000);
624 for (i = 6; i < 1024; ++i)
625 msg[i] = cpu_to_le32(0x0);
626
627 return 0;
628 }
629
amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring * ring,long timeout)630 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
631 {
632 struct dma_fence *fence = NULL;
633 struct amdgpu_ib ib;
634 long r;
635
636 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
637 if (r)
638 goto error;
639
640 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL);
641 if (r)
642 goto error;
643 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
644 if (r)
645 goto error;
646
647 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence);
648 if (r)
649 goto error;
650
651 r = dma_fence_wait_timeout(fence, false, timeout);
652 if (r == 0)
653 r = -ETIMEDOUT;
654 else if (r > 0)
655 r = 0;
656
657 dma_fence_put(fence);
658 error:
659 return r;
660 }
661
amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib * ib,uint32_t ib_pack_in_dw,bool enc)662 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib,
663 uint32_t ib_pack_in_dw, bool enc)
664 {
665 uint32_t *ib_checksum;
666
667 ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */
668 ib->ptr[ib->length_dw++] = 0x30000002;
669 ib_checksum = &ib->ptr[ib->length_dw++];
670 ib->ptr[ib->length_dw++] = ib_pack_in_dw;
671
672 ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */
673 ib->ptr[ib->length_dw++] = 0x30000001;
674 ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3;
675 ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t);
676
677 return ib_checksum;
678 }
679
amdgpu_vcn_unified_ring_ib_checksum(uint32_t ** ib_checksum,uint32_t ib_pack_in_dw)680 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum,
681 uint32_t ib_pack_in_dw)
682 {
683 uint32_t i;
684 uint32_t checksum = 0;
685
686 for (i = 0; i < ib_pack_in_dw; i++)
687 checksum += *(*ib_checksum + 2 + i);
688
689 **ib_checksum = checksum;
690 }
691
amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring * ring,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)692 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
693 struct amdgpu_ib *ib_msg,
694 struct dma_fence **fence)
695 {
696 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
697 unsigned int ib_size_dw = 64;
698 struct amdgpu_device *adev = ring->adev;
699 struct dma_fence *f = NULL;
700 struct amdgpu_job *job;
701 struct amdgpu_ib *ib;
702 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
703 bool sq = amdgpu_vcn_using_unified_queue(ring);
704 uint32_t *ib_checksum;
705 uint32_t ib_pack_in_dw;
706 int i, r;
707
708 if (sq)
709 ib_size_dw += 8;
710
711 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
712 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
713 &job);
714 if (r)
715 goto err;
716
717 ib = &job->ibs[0];
718 ib->length_dw = 0;
719
720 /* single queue headers */
721 if (sq) {
722 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t)
723 + 4 + 2; /* engine info + decoding ib in dw */
724 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false);
725 }
726
727 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
728 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
729 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
730 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;
731 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));
732
733 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);
734 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);
735 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);
736
737 for (i = ib->length_dw; i < ib_size_dw; ++i)
738 ib->ptr[i] = 0x0;
739
740 if (sq)
741 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw);
742
743 r = amdgpu_job_submit_direct(job, ring, &f);
744 if (r)
745 goto err_free;
746
747 amdgpu_ib_free(adev, ib_msg, f);
748
749 if (fence)
750 *fence = dma_fence_get(f);
751 dma_fence_put(f);
752
753 return 0;
754
755 err_free:
756 amdgpu_job_free(job);
757 err:
758 amdgpu_ib_free(adev, ib_msg, f);
759 return r;
760 }
761
amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring * ring,long timeout)762 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout)
763 {
764 struct dma_fence *fence = NULL;
765 struct amdgpu_ib ib;
766 long r;
767
768 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
769 if (r)
770 goto error;
771
772 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL);
773 if (r)
774 goto error;
775 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
776 if (r)
777 goto error;
778
779 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence);
780 if (r)
781 goto error;
782
783 r = dma_fence_wait_timeout(fence, false, timeout);
784 if (r == 0)
785 r = -ETIMEDOUT;
786 else if (r > 0)
787 r = 0;
788
789 dma_fence_put(fence);
790 error:
791 return r;
792 }
793
amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring * ring)794 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
795 {
796 struct amdgpu_device *adev = ring->adev;
797 uint32_t rptr;
798 unsigned int i;
799 int r;
800
801 if (amdgpu_sriov_vf(adev))
802 return 0;
803
804 r = amdgpu_ring_alloc(ring, 16);
805 if (r)
806 return r;
807
808 rptr = amdgpu_ring_get_rptr(ring);
809
810 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
811 amdgpu_ring_commit(ring);
812
813 for (i = 0; i < adev->usec_timeout; i++) {
814 if (amdgpu_ring_get_rptr(ring) != rptr)
815 break;
816 udelay(1);
817 }
818
819 if (i >= adev->usec_timeout)
820 r = -ETIMEDOUT;
821
822 return r;
823 }
824
amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)825 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
826 struct amdgpu_ib *ib_msg,
827 struct dma_fence **fence)
828 {
829 unsigned int ib_size_dw = 16;
830 struct amdgpu_job *job;
831 struct amdgpu_ib *ib;
832 struct dma_fence *f = NULL;
833 uint32_t *ib_checksum = NULL;
834 uint64_t addr;
835 bool sq = amdgpu_vcn_using_unified_queue(ring);
836 int i, r;
837
838 if (sq)
839 ib_size_dw += 8;
840
841 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
842 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
843 &job);
844 if (r)
845 return r;
846
847 ib = &job->ibs[0];
848 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
849
850 ib->length_dw = 0;
851
852 if (sq)
853 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
854
855 ib->ptr[ib->length_dw++] = 0x00000018;
856 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
857 ib->ptr[ib->length_dw++] = handle;
858 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
859 ib->ptr[ib->length_dw++] = addr;
860 ib->ptr[ib->length_dw++] = 0x0000000b;
861
862 ib->ptr[ib->length_dw++] = 0x00000014;
863 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
864 ib->ptr[ib->length_dw++] = 0x0000001c;
865 ib->ptr[ib->length_dw++] = 0x00000000;
866 ib->ptr[ib->length_dw++] = 0x00000000;
867
868 ib->ptr[ib->length_dw++] = 0x00000008;
869 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
870
871 for (i = ib->length_dw; i < ib_size_dw; ++i)
872 ib->ptr[i] = 0x0;
873
874 if (sq)
875 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
876
877 r = amdgpu_job_submit_direct(job, ring, &f);
878 if (r)
879 goto err;
880
881 if (fence)
882 *fence = dma_fence_get(f);
883 dma_fence_put(f);
884
885 return 0;
886
887 err:
888 amdgpu_job_free(job);
889 return r;
890 }
891
amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)892 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
893 struct amdgpu_ib *ib_msg,
894 struct dma_fence **fence)
895 {
896 unsigned int ib_size_dw = 16;
897 struct amdgpu_job *job;
898 struct amdgpu_ib *ib;
899 struct dma_fence *f = NULL;
900 uint32_t *ib_checksum = NULL;
901 uint64_t addr;
902 bool sq = amdgpu_vcn_using_unified_queue(ring);
903 int i, r;
904
905 if (sq)
906 ib_size_dw += 8;
907
908 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
909 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
910 &job);
911 if (r)
912 return r;
913
914 ib = &job->ibs[0];
915 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
916
917 ib->length_dw = 0;
918
919 if (sq)
920 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
921
922 ib->ptr[ib->length_dw++] = 0x00000018;
923 ib->ptr[ib->length_dw++] = 0x00000001;
924 ib->ptr[ib->length_dw++] = handle;
925 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
926 ib->ptr[ib->length_dw++] = addr;
927 ib->ptr[ib->length_dw++] = 0x0000000b;
928
929 ib->ptr[ib->length_dw++] = 0x00000014;
930 ib->ptr[ib->length_dw++] = 0x00000002;
931 ib->ptr[ib->length_dw++] = 0x0000001c;
932 ib->ptr[ib->length_dw++] = 0x00000000;
933 ib->ptr[ib->length_dw++] = 0x00000000;
934
935 ib->ptr[ib->length_dw++] = 0x00000008;
936 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
937
938 for (i = ib->length_dw; i < ib_size_dw; ++i)
939 ib->ptr[i] = 0x0;
940
941 if (sq)
942 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
943
944 r = amdgpu_job_submit_direct(job, ring, &f);
945 if (r)
946 goto err;
947
948 if (fence)
949 *fence = dma_fence_get(f);
950 dma_fence_put(f);
951
952 return 0;
953
954 err:
955 amdgpu_job_free(job);
956 return r;
957 }
958
amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring * ring,long timeout)959 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
960 {
961 struct amdgpu_device *adev = ring->adev;
962 struct dma_fence *fence = NULL;
963 struct amdgpu_ib ib;
964 long r;
965
966 memset(&ib, 0, sizeof(ib));
967 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE,
968 AMDGPU_IB_POOL_DIRECT,
969 &ib);
970 if (r)
971 return r;
972
973 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL);
974 if (r)
975 goto error;
976
977 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence);
978 if (r)
979 goto error;
980
981 r = dma_fence_wait_timeout(fence, false, timeout);
982 if (r == 0)
983 r = -ETIMEDOUT;
984 else if (r > 0)
985 r = 0;
986
987 error:
988 amdgpu_ib_free(adev, &ib, fence);
989 dma_fence_put(fence);
990
991 return r;
992 }
993
amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring * ring,long timeout)994 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout)
995 {
996 struct amdgpu_device *adev = ring->adev;
997 long r;
998
999 if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(4, 0, 3)) {
1000 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout);
1001 if (r)
1002 goto error;
1003 }
1004
1005 r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout);
1006
1007 error:
1008 return r;
1009 }
1010
amdgpu_vcn_get_enc_ring_prio(int ring)1011 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring)
1012 {
1013 switch (ring) {
1014 case 0:
1015 return AMDGPU_RING_PRIO_0;
1016 case 1:
1017 return AMDGPU_RING_PRIO_1;
1018 case 2:
1019 return AMDGPU_RING_PRIO_2;
1020 default:
1021 return AMDGPU_RING_PRIO_0;
1022 }
1023 }
1024
amdgpu_vcn_setup_ucode(struct amdgpu_device * adev)1025 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
1026 {
1027 int i;
1028 unsigned int idx;
1029
1030 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1031 const struct common_firmware_header *hdr;
1032
1033 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
1034
1035 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1036 if (adev->vcn.harvest_config & (1 << i))
1037 continue;
1038 /* currently only support 2 FW instances */
1039 if (i >= 2) {
1040 dev_info(adev->dev, "More then 2 VCN FW instances!\n");
1041 break;
1042 }
1043 idx = AMDGPU_UCODE_ID_VCN + i;
1044 adev->firmware.ucode[idx].ucode_id = idx;
1045 adev->firmware.ucode[idx].fw = adev->vcn.fw;
1046 adev->firmware.fw_size +=
1047 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
1048
1049 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(4, 0, 3))
1050 break;
1051 }
1052 dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
1053 }
1054 }
1055
1056 /*
1057 * debugfs for mapping vcn firmware log buffer.
1058 */
1059 #if defined(CONFIG_DEBUG_FS)
amdgpu_debugfs_vcn_fwlog_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1060 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf,
1061 size_t size, loff_t *pos)
1062 {
1063 struct amdgpu_vcn_inst *vcn;
1064 void *log_buf;
1065 volatile struct amdgpu_vcn_fwlog *plog;
1066 unsigned int read_pos, write_pos, available, i, read_bytes = 0;
1067 unsigned int read_num[2] = {0};
1068
1069 vcn = file_inode(f)->i_private;
1070 if (!vcn)
1071 return -ENODEV;
1072
1073 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log)
1074 return -EFAULT;
1075
1076 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1077
1078 plog = (volatile struct amdgpu_vcn_fwlog *)log_buf;
1079 read_pos = plog->rptr;
1080 write_pos = plog->wptr;
1081
1082 if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE)
1083 return -EFAULT;
1084
1085 if (!size || (read_pos == write_pos))
1086 return 0;
1087
1088 if (write_pos > read_pos) {
1089 available = write_pos - read_pos;
1090 read_num[0] = min(size, (size_t)available);
1091 } else {
1092 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos;
1093 available = read_num[0] + write_pos - plog->header_size;
1094 if (size > available)
1095 read_num[1] = write_pos - plog->header_size;
1096 else if (size > read_num[0])
1097 read_num[1] = size - read_num[0];
1098 else
1099 read_num[0] = size;
1100 }
1101
1102 for (i = 0; i < 2; i++) {
1103 if (read_num[i]) {
1104 if (read_pos == AMDGPU_VCNFW_LOG_SIZE)
1105 read_pos = plog->header_size;
1106 if (read_num[i] == copy_to_user((buf + read_bytes),
1107 (log_buf + read_pos), read_num[i]))
1108 return -EFAULT;
1109
1110 read_bytes += read_num[i];
1111 read_pos += read_num[i];
1112 }
1113 }
1114
1115 plog->rptr = read_pos;
1116 *pos += read_bytes;
1117 return read_bytes;
1118 }
1119
1120 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = {
1121 .owner = THIS_MODULE,
1122 .read = amdgpu_debugfs_vcn_fwlog_read,
1123 .llseek = default_llseek
1124 };
1125 #endif
1126
amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device * adev,uint8_t i,struct amdgpu_vcn_inst * vcn)1127 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i,
1128 struct amdgpu_vcn_inst *vcn)
1129 {
1130 #if defined(CONFIG_DEBUG_FS)
1131 struct drm_minor *minor = adev_to_drm(adev)->primary;
1132 struct dentry *root = minor->debugfs_root;
1133 char name[32];
1134
1135 sprintf(name, "amdgpu_vcn_%d_fwlog", i);
1136 debugfs_create_file_size(name, S_IFREG | 0444, root, vcn,
1137 &amdgpu_debugfs_vcnfwlog_fops,
1138 AMDGPU_VCNFW_LOG_SIZE);
1139 #endif
1140 }
1141
amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst * vcn)1142 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn)
1143 {
1144 #if defined(CONFIG_DEBUG_FS)
1145 volatile uint32_t *flag = vcn->fw_shared.cpu_addr;
1146 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1147 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size;
1148 volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr;
1149 volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr
1150 + vcn->fw_shared.log_offset;
1151 *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG);
1152 fw_log->is_enabled = 1;
1153 fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF);
1154 fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32);
1155 fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE);
1156
1157 log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog);
1158 log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE;
1159 log_buf->rptr = log_buf->header_size;
1160 log_buf->wptr = log_buf->header_size;
1161 log_buf->wrapped = 0;
1162 #endif
1163 }
1164
amdgpu_vcn_process_poison_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1165 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev,
1166 struct amdgpu_irq_src *source,
1167 struct amdgpu_iv_entry *entry)
1168 {
1169 struct ras_common_if *ras_if = adev->vcn.ras_if;
1170 struct ras_dispatch_if ih_data = {
1171 .entry = entry,
1172 };
1173
1174 if (!ras_if)
1175 return 0;
1176
1177 if (!amdgpu_sriov_vf(adev)) {
1178 ih_data.head = *ras_if;
1179 amdgpu_ras_interrupt_dispatch(adev, &ih_data);
1180 } else {
1181 if (adev->virt.ops && adev->virt.ops->ras_poison_handler)
1182 adev->virt.ops->ras_poison_handler(adev);
1183 else
1184 dev_warn(adev->dev,
1185 "No ras_poison_handler interface in SRIOV for VCN!\n");
1186 }
1187
1188 return 0;
1189 }
1190
amdgpu_vcn_ras_late_init(struct amdgpu_device * adev,struct ras_common_if * ras_block)1191 int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
1192 {
1193 int r, i;
1194
1195 r = amdgpu_ras_block_late_init(adev, ras_block);
1196 if (r)
1197 return r;
1198
1199 if (amdgpu_ras_is_supported(adev, ras_block->block)) {
1200 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1201 if (adev->vcn.harvest_config & (1 << i) ||
1202 !adev->vcn.inst[i].ras_poison_irq.funcs)
1203 continue;
1204
1205 r = amdgpu_irq_get(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
1206 if (r)
1207 goto late_fini;
1208 }
1209 }
1210 return 0;
1211
1212 late_fini:
1213 amdgpu_ras_block_late_fini(adev, ras_block);
1214 return r;
1215 }
1216
amdgpu_vcn_ras_sw_init(struct amdgpu_device * adev)1217 int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev)
1218 {
1219 int err;
1220 struct amdgpu_vcn_ras *ras;
1221
1222 if (!adev->vcn.ras)
1223 return 0;
1224
1225 ras = adev->vcn.ras;
1226 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
1227 if (err) {
1228 dev_err(adev->dev, "Failed to register vcn ras block!\n");
1229 return err;
1230 }
1231
1232 strcpy(ras->ras_block.ras_comm.name, "vcn");
1233 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN;
1234 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON;
1235 adev->vcn.ras_if = &ras->ras_block.ras_comm;
1236
1237 if (!ras->ras_block.ras_late_init)
1238 ras->ras_block.ras_late_init = amdgpu_vcn_ras_late_init;
1239
1240 return 0;
1241 }
1242
amdgpu_vcn_psp_update_sram(struct amdgpu_device * adev,int inst_idx,enum AMDGPU_UCODE_ID ucode_id)1243 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
1244 enum AMDGPU_UCODE_ID ucode_id)
1245 {
1246 struct amdgpu_firmware_info ucode = {
1247 .ucode_id = (ucode_id ? ucode_id :
1248 (inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
1249 AMDGPU_UCODE_ID_VCN0_RAM)),
1250 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
1251 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
1252 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr),
1253 };
1254
1255 return psp_execute_ip_fw_load(&adev->psp, &ucode);
1256 }
1257
