1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc.
3 *
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/pci.h>
9
10 #include "mt7921.h"
11 #include "mac.h"
12 #include "mcu.h"
13 #include "../trace.h"
14
15 static const struct pci_device_id mt7921_pci_device_table[] = {
16 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961) },
17 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922) },
18 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608) },
19 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616) },
20 { },
21 };
22
23 static bool mt7921_disable_aspm;
24 module_param_named(disable_aspm, mt7921_disable_aspm, bool, 0644);
25 MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support");
26
27 static void
mt7921_rx_poll_complete(struct mt76_dev * mdev,enum mt76_rxq_id q)28 mt7921_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
29 {
30 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
31
32 if (q == MT_RXQ_MAIN)
33 mt7921_irq_enable(dev, MT_INT_RX_DONE_DATA);
34 else if (q == MT_RXQ_MCU_WA)
35 mt7921_irq_enable(dev, MT_INT_RX_DONE_WM2);
36 else
37 mt7921_irq_enable(dev, MT_INT_RX_DONE_WM);
38 }
39
mt7921_irq_handler(int irq,void * dev_instance)40 static irqreturn_t mt7921_irq_handler(int irq, void *dev_instance)
41 {
42 struct mt7921_dev *dev = dev_instance;
43
44 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
45
46 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
47 return IRQ_NONE;
48
49 tasklet_schedule(&dev->irq_tasklet);
50
51 return IRQ_HANDLED;
52 }
53
mt7921_irq_tasklet(unsigned long data)54 static void mt7921_irq_tasklet(unsigned long data)
55 {
56 struct mt7921_dev *dev = (struct mt7921_dev *)data;
57 u32 intr, mask = 0;
58
59 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
60
61 intr = mt76_rr(dev, MT_WFDMA0_HOST_INT_STA);
62 intr &= dev->mt76.mmio.irqmask;
63 mt76_wr(dev, MT_WFDMA0_HOST_INT_STA, intr);
64
65 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
66
67 mask |= intr & MT_INT_RX_DONE_ALL;
68 if (intr & MT_INT_TX_DONE_MCU)
69 mask |= MT_INT_TX_DONE_MCU;
70
71 if (intr & MT_INT_MCU_CMD) {
72 u32 intr_sw;
73
74 intr_sw = mt76_rr(dev, MT_MCU_CMD);
75 /* ack MCU2HOST_SW_INT_STA */
76 mt76_wr(dev, MT_MCU_CMD, intr_sw);
77 if (intr_sw & MT_MCU_CMD_WAKE_RX_PCIE) {
78 mask |= MT_INT_RX_DONE_DATA;
79 intr |= MT_INT_RX_DONE_DATA;
80 }
81 }
82
83 mt76_set_irq_mask(&dev->mt76, MT_WFDMA0_HOST_INT_ENA, mask, 0);
84
85 if (intr & MT_INT_TX_DONE_ALL)
86 napi_schedule(&dev->mt76.tx_napi);
87
88 if (intr & MT_INT_RX_DONE_WM)
89 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]);
90
91 if (intr & MT_INT_RX_DONE_WM2)
92 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]);
93
94 if (intr & MT_INT_RX_DONE_DATA)
95 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]);
96 }
97
mt7921e_init_reset(struct mt7921_dev * dev)98 static int mt7921e_init_reset(struct mt7921_dev *dev)
99 {
100 return mt7921_wpdma_reset(dev, true);
101 }
102
mt7921e_unregister_device(struct mt7921_dev * dev)103 static void mt7921e_unregister_device(struct mt7921_dev *dev)
104 {
105 int i;
106 struct mt76_connac_pm *pm = &dev->pm;
107
108 cancel_work_sync(&dev->init_work);
109 mt76_unregister_device(&dev->mt76);
110 mt76_for_each_q_rx(&dev->mt76, i)
111 napi_disable(&dev->mt76.napi[i]);
112 cancel_delayed_work_sync(&pm->ps_work);
113 cancel_work_sync(&pm->wake_work);
114
115 mt7921_tx_token_put(dev);
116 mt7921_mcu_drv_pmctrl(dev);
117 mt7921_dma_cleanup(dev);
118 mt7921_wfsys_reset(dev);
119 skb_queue_purge(&dev->mt76.mcu.res_q);
120
121 tasklet_disable(&dev->irq_tasklet);
122 }
123
__mt7921_reg_addr(struct mt7921_dev * dev,u32 addr)124 static u32 __mt7921_reg_addr(struct mt7921_dev *dev, u32 addr)
125 {
126 static const struct mt76_connac_reg_map fixed_map[] = {
127 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
128 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
129 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
130 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
131 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
132 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
133 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
134 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
135 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
136 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
137 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
138 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */
139 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */
140 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
141 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */
142 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
143 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
144 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
145 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
146 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
147 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
148 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
149 { 0x820cc000, 0x0e000, 0x01000 }, /* WF_UMAC_TOP (PP) */
150 { 0x820cd000, 0x0f000, 0x01000 }, /* WF_MDP_TOP */
151 { 0x74030000, 0x10000, 0x10000 }, /* PCIE_MAC_IREG */
152 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
153 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
154 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
155 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
156 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
157 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
158 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
159 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
160 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
161 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
162 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
163 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
164 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
165 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
166 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
167 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
168 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
169 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
170 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
171 };
172 int i;
173
174 if (addr < 0x100000)
175 return addr;
176
177 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
178 u32 ofs;
179
180 if (addr < fixed_map[i].phys)
181 continue;
182
183 ofs = addr - fixed_map[i].phys;
184 if (ofs > fixed_map[i].size)
185 continue;
186
187 return fixed_map[i].maps + ofs;
188 }
189
190 if ((addr >= 0x18000000 && addr < 0x18c00000) ||
191 (addr >= 0x70000000 && addr < 0x78000000) ||
192 (addr >= 0x7c000000 && addr < 0x7c400000))
193 return mt7921_reg_map_l1(dev, addr);
194
195 dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n",
196 addr);
197
198 return 0;
199 }
200
mt7921_rr(struct mt76_dev * mdev,u32 offset)201 static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset)
202 {
203 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
204 u32 addr = __mt7921_reg_addr(dev, offset);
205
206 return dev->bus_ops->rr(mdev, addr);
207 }
208
mt7921_wr(struct mt76_dev * mdev,u32 offset,u32 val)209 static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val)
210 {
211 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
212 u32 addr = __mt7921_reg_addr(dev, offset);
213
214 dev->bus_ops->wr(mdev, addr, val);
215 }
216
mt7921_rmw(struct mt76_dev * mdev,u32 offset,u32 mask,u32 val)217 static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
218 {
219 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
220 u32 addr = __mt7921_reg_addr(dev, offset);
221
222 return dev->bus_ops->rmw(mdev, addr, mask, val);
223 }
224
mt7921_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)225 static int mt7921_pci_probe(struct pci_dev *pdev,
226 const struct pci_device_id *id)
227 {
228 static const struct mt76_driver_ops drv_ops = {
229 /* txwi_size = txd size + txp size */
230 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_hw_txp),
231 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ,
232 .survey_flags = SURVEY_INFO_TIME_TX |
233 SURVEY_INFO_TIME_RX |
234 SURVEY_INFO_TIME_BSS_RX,
235 .token_size = MT7921_TOKEN_SIZE,
236 .tx_prepare_skb = mt7921e_tx_prepare_skb,
237 .tx_complete_skb = mt76_connac_tx_complete_skb,
238 .rx_check = mt7921_rx_check,
239 .rx_skb = mt7921_queue_rx_skb,
240 .rx_poll_complete = mt7921_rx_poll_complete,
241 .sta_ps = mt7921_sta_ps,
242 .sta_add = mt7921_mac_sta_add,
243 .sta_assoc = mt7921_mac_sta_assoc,
244 .sta_remove = mt7921_mac_sta_remove,
245 .update_survey = mt7921_update_channel,
246 };
247 static const struct mt7921_hif_ops mt7921_pcie_ops = {
248 .init_reset = mt7921e_init_reset,
249 .reset = mt7921e_mac_reset,
250 .mcu_init = mt7921e_mcu_init,
251 .drv_own = mt7921e_mcu_drv_pmctrl,
252 .fw_own = mt7921e_mcu_fw_pmctrl,
253 };
254
255 struct mt76_bus_ops *bus_ops;
256 struct mt7921_dev *dev;
257 struct mt76_dev *mdev;
258 int ret;
259
260 ret = pcim_enable_device(pdev);
261 if (ret)
262 return ret;
263
264 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
265 if (ret)
266 return ret;
267
268 pci_set_master(pdev);
269
270 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
271 if (ret < 0)
272 return ret;
273
274 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
275 if (ret)
276 goto err_free_pci_vec;
277
278 if (mt7921_disable_aspm)
279 mt76_pci_disable_aspm(pdev);
280
281 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), &mt7921_ops,
282 &drv_ops);
283 if (!mdev) {
284 ret = -ENOMEM;
285 goto err_free_pci_vec;
286 }
287
288 pci_set_drvdata(pdev, mdev);
289
290 dev = container_of(mdev, struct mt7921_dev, mt76);
291 dev->hif_ops = &mt7921_pcie_ops;
292
293 mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]);
294 tasklet_init(&dev->irq_tasklet, mt7921_irq_tasklet, (unsigned long)dev);
295
296 dev->phy.dev = dev;
297 dev->phy.mt76 = &dev->mt76.phy;
298 dev->mt76.phy.priv = &dev->phy;
299 dev->bus_ops = dev->mt76.bus;
300 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
301 GFP_KERNEL);
302 if (!bus_ops) {
303 ret = -ENOMEM;
304 goto err_free_dev;
305 }
306
307 bus_ops->rr = mt7921_rr;
308 bus_ops->wr = mt7921_wr;
309 bus_ops->rmw = mt7921_rmw;
310 dev->mt76.bus = bus_ops;
311
312 ret = __mt7921e_mcu_drv_pmctrl(dev);
313 if (ret)
314 goto err_free_dev;
315
316 mdev->rev = (mt7921_l1_rr(dev, MT_HW_CHIPID) << 16) |
317 (mt7921_l1_rr(dev, MT_HW_REV) & 0xff);
318 dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
319
320 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
321
322 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
323
324 ret = devm_request_irq(mdev->dev, pdev->irq, mt7921_irq_handler,
325 IRQF_SHARED, KBUILD_MODNAME, dev);
326 if (ret)
327 goto err_free_dev;
328
329 ret = mt7921_dma_init(dev);
330 if (ret)
331 goto err_free_irq;
332
333 ret = mt7921_register_device(dev);
334 if (ret)
335 goto err_free_irq;
336
337 return 0;
338
339 err_free_irq:
340 devm_free_irq(&pdev->dev, pdev->irq, dev);
341 err_free_dev:
342 mt76_free_device(&dev->mt76);
343 err_free_pci_vec:
344 pci_free_irq_vectors(pdev);
345
346 return ret;
347 }
348
mt7921_pci_remove(struct pci_dev * pdev)349 static void mt7921_pci_remove(struct pci_dev *pdev)
350 {
351 struct mt76_dev *mdev = pci_get_drvdata(pdev);
352 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
353
354 mt7921e_unregister_device(dev);
355 devm_free_irq(&pdev->dev, pdev->irq, dev);
356 mt76_free_device(&dev->mt76);
357 pci_free_irq_vectors(pdev);
358 }
359
mt7921_pci_suspend(struct device * device)360 static int mt7921_pci_suspend(struct device *device)
361 {
362 struct pci_dev *pdev = to_pci_dev(device);
363 struct mt76_dev *mdev = pci_get_drvdata(pdev);
364 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
365 struct mt76_connac_pm *pm = &dev->pm;
366 int i, err;
367
368 pm->suspended = true;
369 flush_work(&dev->reset_work);
370 cancel_delayed_work_sync(&pm->ps_work);
371 cancel_work_sync(&pm->wake_work);
372
373 err = mt7921_mcu_drv_pmctrl(dev);
374 if (err < 0)
375 goto restore_suspend;
376
377 err = mt76_connac_mcu_set_hif_suspend(mdev, true);
378 if (err)
379 goto restore_suspend;
380
381 /* always enable deep sleep during suspend to reduce
382 * power consumption
383 */
384 mt76_connac_mcu_set_deep_sleep(&dev->mt76, true);
385
386 napi_disable(&mdev->tx_napi);
387 mt76_worker_disable(&mdev->tx_worker);
388
389 mt76_for_each_q_rx(mdev, i) {
390 napi_disable(&mdev->napi[i]);
391 }
392
393 /* wait until dma is idle */
394 mt76_poll(dev, MT_WFDMA0_GLO_CFG,
395 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
396 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000);
397
398 /* put dma disabled */
399 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
400 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
401
402 /* disable interrupt */
403 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
404 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);
405 synchronize_irq(pdev->irq);
406 tasklet_kill(&dev->irq_tasklet);
407
408 err = mt7921_mcu_fw_pmctrl(dev);
409 if (err)
410 goto restore_napi;
411
412 return 0;
413
414 restore_napi:
415 mt76_for_each_q_rx(mdev, i) {
416 napi_enable(&mdev->napi[i]);
417 }
418 napi_enable(&mdev->tx_napi);
419
420 if (!pm->ds_enable)
421 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
422
423 mt76_connac_mcu_set_hif_suspend(mdev, false);
424
425 restore_suspend:
426 pm->suspended = false;
427
428 if (err < 0)
429 mt7921_reset(&dev->mt76);
430
431 return err;
432 }
433
mt7921_pci_resume(struct device * device)434 static int mt7921_pci_resume(struct device *device)
435 {
436 struct pci_dev *pdev = to_pci_dev(device);
437 struct mt76_dev *mdev = pci_get_drvdata(pdev);
438 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
439 struct mt76_connac_pm *pm = &dev->pm;
440 int i, err;
441
442 err = mt7921_mcu_drv_pmctrl(dev);
443 if (err < 0)
444 goto failed;
445
446 mt7921_wpdma_reinit_cond(dev);
447
448 /* enable interrupt */
449 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
450 mt7921_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
451 MT_INT_MCU_CMD);
452 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);
453
454 /* put dma enabled */
455 mt76_set(dev, MT_WFDMA0_GLO_CFG,
456 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
457
458 mt76_worker_enable(&mdev->tx_worker);
459
460 local_bh_disable();
461 mt76_for_each_q_rx(mdev, i) {
462 napi_enable(&mdev->napi[i]);
463 napi_schedule(&mdev->napi[i]);
464 }
465 napi_enable(&mdev->tx_napi);
466 napi_schedule(&mdev->tx_napi);
467 local_bh_enable();
468
469 /* restore previous ds setting */
470 if (!pm->ds_enable)
471 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
472
473 err = mt76_connac_mcu_set_hif_suspend(mdev, false);
474 failed:
475 pm->suspended = false;
476
477 if (err < 0)
478 mt7921_reset(&dev->mt76);
479
480 return err;
481 }
482
483 static DEFINE_SIMPLE_DEV_PM_OPS(mt7921_pm_ops, mt7921_pci_suspend, mt7921_pci_resume);
484
485 static struct pci_driver mt7921_pci_driver = {
486 .name = KBUILD_MODNAME,
487 .id_table = mt7921_pci_device_table,
488 .probe = mt7921_pci_probe,
489 .remove = mt7921_pci_remove,
490 .driver.pm = pm_sleep_ptr(&mt7921_pm_ops),
491 };
492
493 module_pci_driver(mt7921_pci_driver);
494
495 MODULE_DEVICE_TABLE(pci, mt7921_pci_device_table);
496 MODULE_FIRMWARE(MT7921_FIRMWARE_WM);
497 MODULE_FIRMWARE(MT7921_ROM_PATCH);
498 MODULE_FIRMWARE(MT7922_FIRMWARE_WM);
499 MODULE_FIRMWARE(MT7922_ROM_PATCH);
500 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
501 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
502 MODULE_LICENSE("Dual BSD/GPL");
503
