1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
4 // http://www.samsung.com
5 //
6 // Exynos - Suspend support
7 //
8 // Based on arch/arm/mach-s3c2410/pm.c
9 // Copyright (c) 2006 Simtec Electronics
10 // Ben Dooks <ben@simtec.co.uk>
11
12 #include <linux/init.h>
13 #include <linux/suspend.h>
14 #include <linux/syscore_ops.h>
15 #include <linux/cpu_pm.h>
16 #include <linux/io.h>
17 #include <linux/irq.h>
18 #include <linux/irqchip.h>
19 #include <linux/irqdomain.h>
20 #include <linux/of_address.h>
21 #include <linux/err.h>
22 #include <linux/regulator/machine.h>
23 #include <linux/soc/samsung/exynos-pmu.h>
24 #include <linux/soc/samsung/exynos-regs-pmu.h>
25
26 #include <asm/cacheflush.h>
27 #include <asm/hardware/cache-l2x0.h>
28 #include <asm/firmware.h>
29 #include <asm/mcpm.h>
30 #include <asm/smp_scu.h>
31 #include <asm/suspend.h>
32
33 #include "common.h"
34 #include "smc.h"
35
36 #define REG_TABLE_END (-1U)
37
38 #define EXYNOS5420_CPU_STATE 0x28
39
40 /**
41 * struct exynos_wkup_irq - PMU IRQ to mask mapping
42 * @hwirq: Hardware IRQ signal of the PMU
43 * @mask: Mask in PMU wake-up mask register
44 */
45 struct exynos_wkup_irq {
46 unsigned int hwirq;
47 u32 mask;
48 };
49
50 struct exynos_pm_data {
51 const struct exynos_wkup_irq *wkup_irq;
52 unsigned int wake_disable_mask;
53
54 void (*pm_prepare)(void);
55 void (*pm_resume_prepare)(void);
56 void (*pm_resume)(void);
57 int (*pm_suspend)(void);
58 int (*cpu_suspend)(unsigned long);
59 };
60
61 /* Used only on Exynos542x/5800 */
62 struct exynos_pm_state {
63 int cpu_state;
64 unsigned int pmu_spare3;
65 void __iomem *sysram_base;
66 phys_addr_t sysram_phys;
67 bool secure_firmware;
68 };
69
70 static const struct exynos_pm_data *pm_data __ro_after_init;
71 static struct exynos_pm_state pm_state;
72
73 /*
74 * GIC wake-up support
75 */
76
77 static u32 exynos_irqwake_intmask = 0xffffffff;
78
79 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
80 { 73, BIT(1) }, /* RTC alarm */
81 { 74, BIT(2) }, /* RTC tick */
82 { /* sentinel */ },
83 };
84
85 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
86 { 44, BIT(1) }, /* RTC alarm */
87 { 45, BIT(2) }, /* RTC tick */
88 { /* sentinel */ },
89 };
90
91 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
92 { 43, BIT(1) }, /* RTC alarm */
93 { 44, BIT(2) }, /* RTC tick */
94 { /* sentinel */ },
95 };
96
exynos_read_eint_wakeup_mask(void)97 static u32 exynos_read_eint_wakeup_mask(void)
98 {
99 return pmu_raw_readl(EXYNOS_EINT_WAKEUP_MASK);
100 }
101
exynos_irq_set_wake(struct irq_data * data,unsigned int state)102 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
103 {
104 const struct exynos_wkup_irq *wkup_irq;
105
106 if (!pm_data->wkup_irq)
107 return -ENOENT;
108 wkup_irq = pm_data->wkup_irq;
109
110 while (wkup_irq->mask) {
111 if (wkup_irq->hwirq == data->hwirq) {
112 if (!state)
113 exynos_irqwake_intmask |= wkup_irq->mask;
114 else
115 exynos_irqwake_intmask &= ~wkup_irq->mask;
116 return 0;
117 }
118 ++wkup_irq;
119 }
120
121 return -ENOENT;
122 }
123
124 static struct irq_chip exynos_pmu_chip = {
125 .name = "PMU",
126 .irq_eoi = irq_chip_eoi_parent,
127 .irq_mask = irq_chip_mask_parent,
128 .irq_unmask = irq_chip_unmask_parent,
129 .irq_retrigger = irq_chip_retrigger_hierarchy,
130 .irq_set_wake = exynos_irq_set_wake,
131 #ifdef CONFIG_SMP
132 .irq_set_affinity = irq_chip_set_affinity_parent,
133 #endif
134 };
135
exynos_pmu_domain_translate(struct irq_domain * d,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)136 static int exynos_pmu_domain_translate(struct irq_domain *d,
137 struct irq_fwspec *fwspec,
138 unsigned long *hwirq,
139 unsigned int *type)
140 {
141 if (is_of_node(fwspec->fwnode)) {
142 if (fwspec->param_count != 3)
143 return -EINVAL;
144
145 /* No PPI should point to this domain */
146 if (fwspec->param[0] != 0)
147 return -EINVAL;
148
149 *hwirq = fwspec->param[1];
150 *type = fwspec->param[2];
151 return 0;
152 }
153
154 return -EINVAL;
155 }
156
exynos_pmu_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * data)157 static int exynos_pmu_domain_alloc(struct irq_domain *domain,
158 unsigned int virq,
159 unsigned int nr_irqs, void *data)
160 {
161 struct irq_fwspec *fwspec = data;
162 struct irq_fwspec parent_fwspec;
163 irq_hw_number_t hwirq;
164 int i;
165
166 if (fwspec->param_count != 3)
167 return -EINVAL; /* Not GIC compliant */
168 if (fwspec->param[0] != 0)
169 return -EINVAL; /* No PPI should point to this domain */
170
171 hwirq = fwspec->param[1];
172
173 for (i = 0; i < nr_irqs; i++)
174 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
175 &exynos_pmu_chip, NULL);
176
177 parent_fwspec = *fwspec;
178 parent_fwspec.fwnode = domain->parent->fwnode;
179 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
180 &parent_fwspec);
181 }
182
183 static const struct irq_domain_ops exynos_pmu_domain_ops = {
184 .translate = exynos_pmu_domain_translate,
185 .alloc = exynos_pmu_domain_alloc,
186 .free = irq_domain_free_irqs_common,
187 };
188
exynos_pmu_irq_init(struct device_node * node,struct device_node * parent)189 static int __init exynos_pmu_irq_init(struct device_node *node,
190 struct device_node *parent)
191 {
192 struct irq_domain *parent_domain, *domain;
193
194 if (!parent) {
195 pr_err("%pOF: no parent, giving up\n", node);
196 return -ENODEV;
197 }
198
199 parent_domain = irq_find_host(parent);
200 if (!parent_domain) {
201 pr_err("%pOF: unable to obtain parent domain\n", node);
202 return -ENXIO;
203 }
204
205 pmu_base_addr = of_iomap(node, 0);
206
207 if (!pmu_base_addr) {
208 pr_err("%pOF: failed to find exynos pmu register\n", node);
209 return -ENOMEM;
210 }
211
212 domain = irq_domain_add_hierarchy(parent_domain, 0, 0,
213 node, &exynos_pmu_domain_ops,
214 NULL);
215 if (!domain) {
216 iounmap(pmu_base_addr);
217 pmu_base_addr = NULL;
218 return -ENOMEM;
219 }
220
221 /*
222 * Clear the OF_POPULATED flag set in of_irq_init so that
223 * later the Exynos PMU platform device won't be skipped.
224 */
225 of_node_clear_flag(node, OF_POPULATED);
226
227 return 0;
228 }
229
230 #define EXYNOS_PMU_IRQ(symbol, name) IRQCHIP_DECLARE(symbol, name, exynos_pmu_irq_init)
231
232 EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu");
233 EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu");
234 EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu");
235 EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu");
236 EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu");
237 EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu");
238
exynos_cpu_do_idle(void)239 static int exynos_cpu_do_idle(void)
240 {
241 /* issue the standby signal into the pm unit. */
242 cpu_do_idle();
243
244 pr_info("Failed to suspend the system\n");
245 return 1; /* Aborting suspend */
246 }
exynos_flush_cache_all(void)247 static void exynos_flush_cache_all(void)
248 {
249 flush_cache_all();
250 outer_flush_all();
251 }
252
exynos_cpu_suspend(unsigned long arg)253 static int exynos_cpu_suspend(unsigned long arg)
254 {
255 exynos_flush_cache_all();
256 return exynos_cpu_do_idle();
257 }
258
exynos3250_cpu_suspend(unsigned long arg)259 static int exynos3250_cpu_suspend(unsigned long arg)
260 {
261 flush_cache_all();
262 return exynos_cpu_do_idle();
263 }
264
exynos5420_cpu_suspend(unsigned long arg)265 static int exynos5420_cpu_suspend(unsigned long arg)
266 {
267 /* MCPM works with HW CPU identifiers */
268 unsigned int mpidr = read_cpuid_mpidr();
269 unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
270 unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
271
272 if (IS_ENABLED(CONFIG_EXYNOS_MCPM)) {
273 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
274 mcpm_cpu_suspend();
275 }
276
277 pr_info("Failed to suspend the system\n");
278
279 /* return value != 0 means failure */
280 return 1;
281 }
282
exynos_pm_set_wakeup_mask(void)283 static void exynos_pm_set_wakeup_mask(void)
284 {
285 /*
286 * Set wake-up mask registers
287 * EXYNOS_EINT_WAKEUP_MASK is set by pinctrl driver in late suspend.
288 */
289 pmu_raw_writel(exynos_irqwake_intmask & ~BIT(31), S5P_WAKEUP_MASK);
290 }
291
exynos_pm_enter_sleep_mode(void)292 static void exynos_pm_enter_sleep_mode(void)
293 {
294 /* Set value of power down register for sleep mode */
295 exynos_sys_powerdown_conf(SYS_SLEEP);
296 pmu_raw_writel(EXYNOS_SLEEP_MAGIC, S5P_INFORM1);
297 }
298
exynos_pm_prepare(void)299 static void exynos_pm_prepare(void)
300 {
301 exynos_set_delayed_reset_assertion(false);
302
303 /* Set wake-up mask registers */
304 exynos_pm_set_wakeup_mask();
305
306 exynos_pm_enter_sleep_mode();
307
308 /* ensure at least INFORM0 has the resume address */
309 pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
310 }
311
exynos3250_pm_prepare(void)312 static void exynos3250_pm_prepare(void)
313 {
314 unsigned int tmp;
315
316 /* Set wake-up mask registers */
317 exynos_pm_set_wakeup_mask();
318
319 tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
320 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
321 pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
322
323 exynos_pm_enter_sleep_mode();
324
325 /* ensure at least INFORM0 has the resume address */
326 pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
327 }
328
exynos5420_pm_prepare(void)329 static void exynos5420_pm_prepare(void)
330 {
331 unsigned int tmp;
332
333 /* Set wake-up mask registers */
334 exynos_pm_set_wakeup_mask();
335
336 pm_state.pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
337 /*
338 * The cpu state needs to be saved and restored so that the
339 * secondary CPUs will enter low power start. Though the U-Boot
340 * is setting the cpu state with low power flag, the kernel
341 * needs to restore it back in case, the primary cpu fails to
342 * suspend for any reason.
343 */
344 pm_state.cpu_state = readl_relaxed(pm_state.sysram_base +
345 EXYNOS5420_CPU_STATE);
346 writel_relaxed(0x0, pm_state.sysram_base + EXYNOS5420_CPU_STATE);
347 if (pm_state.secure_firmware)
348 exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(pm_state.sysram_phys +
349 EXYNOS5420_CPU_STATE),
350 0, 0);
351
352 exynos_pm_enter_sleep_mode();
353
354 /* ensure at least INFORM0 has the resume address */
355 if (IS_ENABLED(CONFIG_EXYNOS_MCPM))
356 pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0);
357
358 tmp = pmu_raw_readl(EXYNOS_L2_OPTION(0));
359 tmp &= ~EXYNOS_L2_USE_RETENTION;
360 pmu_raw_writel(tmp, EXYNOS_L2_OPTION(0));
361
362 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
363 tmp |= EXYNOS5420_UFS;
364 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
365
366 tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
367 tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
368 pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
369
370 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
371 tmp |= EXYNOS5420_EMULATION;
372 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
373
374 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
375 tmp |= EXYNOS5420_EMULATION;
376 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
377 }
378
379
exynos_pm_suspend(void)380 static int exynos_pm_suspend(void)
381 {
382 exynos_pm_central_suspend();
383
384 /* Setting SEQ_OPTION register */
385 pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
386 S5P_CENTRAL_SEQ_OPTION);
387
388 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
389 exynos_cpu_save_register();
390
391 return 0;
392 }
393
exynos5420_pm_suspend(void)394 static int exynos5420_pm_suspend(void)
395 {
396 u32 this_cluster;
397
398 exynos_pm_central_suspend();
399
400 /* Setting SEQ_OPTION register */
401
402 this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
403 if (!this_cluster)
404 pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
405 S5P_CENTRAL_SEQ_OPTION);
406 else
407 pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
408 S5P_CENTRAL_SEQ_OPTION);
409 return 0;
410 }
411
exynos_pm_resume(void)412 static void exynos_pm_resume(void)
413 {
414 u32 cpuid = read_cpuid_part();
415
416 if (exynos_pm_central_resume())
417 goto early_wakeup;
418
419 if (cpuid == ARM_CPU_PART_CORTEX_A9)
420 exynos_scu_enable();
421
422 if (call_firmware_op(resume) == -ENOSYS
423 && cpuid == ARM_CPU_PART_CORTEX_A9)
424 exynos_cpu_restore_register();
425
426 early_wakeup:
427
428 /* Clear SLEEP mode set in INFORM1 */
429 pmu_raw_writel(0x0, S5P_INFORM1);
430 exynos_set_delayed_reset_assertion(true);
431 }
432
exynos3250_pm_resume(void)433 static void exynos3250_pm_resume(void)
434 {
435 u32 cpuid = read_cpuid_part();
436
437 if (exynos_pm_central_resume())
438 goto early_wakeup;
439
440 pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
441
442 if (call_firmware_op(resume) == -ENOSYS
443 && cpuid == ARM_CPU_PART_CORTEX_A9)
444 exynos_cpu_restore_register();
445
446 early_wakeup:
447
448 /* Clear SLEEP mode set in INFORM1 */
449 pmu_raw_writel(0x0, S5P_INFORM1);
450 }
451
exynos5420_prepare_pm_resume(void)452 static void exynos5420_prepare_pm_resume(void)
453 {
454 unsigned int mpidr, cluster;
455
456 mpidr = read_cpuid_mpidr();
457 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
458
459 if (IS_ENABLED(CONFIG_EXYNOS_MCPM))
460 WARN_ON(mcpm_cpu_powered_up());
461
462 if (IS_ENABLED(CONFIG_HW_PERF_EVENTS) && cluster != 0) {
463 /*
464 * When system is resumed on the LITTLE/KFC core (cluster 1),
465 * the DSCR is not properly updated until the power is turned
466 * on also for the cluster 0. Enable it for a while to
467 * propagate the SPNIDEN and SPIDEN signals from Secure JTAG
468 * block and avoid undefined instruction issue on CP14 reset.
469 */
470 pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
471 EXYNOS_COMMON_CONFIGURATION(0));
472 pmu_raw_writel(0,
473 EXYNOS_COMMON_CONFIGURATION(0));
474 }
475 }
476
exynos5420_pm_resume(void)477 static void exynos5420_pm_resume(void)
478 {
479 unsigned long tmp;
480
481 /* Restore the CPU0 low power state register */
482 tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
483 pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
484 EXYNOS5_ARM_CORE0_SYS_PWR_REG);
485
486 /* Restore the sysram cpu state register */
487 writel_relaxed(pm_state.cpu_state,
488 pm_state.sysram_base + EXYNOS5420_CPU_STATE);
489 if (pm_state.secure_firmware)
490 exynos_smc(SMC_CMD_REG,
491 SMC_REG_ID_SFR_W(pm_state.sysram_phys +
492 EXYNOS5420_CPU_STATE),
493 EXYNOS_AFTR_MAGIC, 0);
494
495 pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
496 S5P_CENTRAL_SEQ_OPTION);
497
498 if (exynos_pm_central_resume())
499 goto early_wakeup;
500
501 pmu_raw_writel(pm_state.pmu_spare3, S5P_PMU_SPARE3);
502
503 early_wakeup:
504
505 tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
506 tmp &= ~EXYNOS5420_UFS;
507 pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
508
509 tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
510 tmp &= ~EXYNOS5420_EMULATION;
511 pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
512
513 tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
514 tmp &= ~EXYNOS5420_EMULATION;
515 pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
516
517 /* Clear SLEEP mode set in INFORM1 */
518 pmu_raw_writel(0x0, S5P_INFORM1);
519 }
520
521 /*
522 * Suspend Ops
523 */
524
exynos_suspend_enter(suspend_state_t state)525 static int exynos_suspend_enter(suspend_state_t state)
526 {
527 u32 eint_wakeup_mask = exynos_read_eint_wakeup_mask();
528 int ret;
529
530 pr_debug("%s: suspending the system...\n", __func__);
531
532 pr_debug("%s: wakeup masks: %08x,%08x\n", __func__,
533 exynos_irqwake_intmask, eint_wakeup_mask);
534
535 if (exynos_irqwake_intmask == -1U
536 && eint_wakeup_mask == EXYNOS_EINT_WAKEUP_MASK_DISABLED) {
537 pr_err("%s: No wake-up sources!\n", __func__);
538 pr_err("%s: Aborting sleep\n", __func__);
539 return -EINVAL;
540 }
541
542 if (pm_data->pm_prepare)
543 pm_data->pm_prepare();
544 flush_cache_all();
545
546 ret = call_firmware_op(suspend);
547 if (ret == -ENOSYS)
548 ret = cpu_suspend(0, pm_data->cpu_suspend);
549 if (ret)
550 return ret;
551
552 if (pm_data->pm_resume_prepare)
553 pm_data->pm_resume_prepare();
554
555 pr_debug("%s: wakeup stat: %08x\n", __func__,
556 pmu_raw_readl(S5P_WAKEUP_STAT));
557
558 pr_debug("%s: resuming the system...\n", __func__);
559
560 return 0;
561 }
562
exynos_suspend_prepare(void)563 static int exynos_suspend_prepare(void)
564 {
565 int ret;
566
567 /*
568 * REVISIT: It would be better if struct platform_suspend_ops
569 * .prepare handler get the suspend_state_t as a parameter to
570 * avoid hard-coding the suspend to mem state. It's safe to do
571 * it now only because the suspend_valid_only_mem function is
572 * used as the .valid callback used to check if a given state
573 * is supported by the platform anyways.
574 */
575 ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
576 if (ret) {
577 pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
578 return ret;
579 }
580
581 return 0;
582 }
583
exynos_suspend_finish(void)584 static void exynos_suspend_finish(void)
585 {
586 int ret;
587
588 ret = regulator_suspend_finish();
589 if (ret)
590 pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
591 }
592
593 static const struct platform_suspend_ops exynos_suspend_ops = {
594 .enter = exynos_suspend_enter,
595 .prepare = exynos_suspend_prepare,
596 .finish = exynos_suspend_finish,
597 .valid = suspend_valid_only_mem,
598 };
599
600 static const struct exynos_pm_data exynos3250_pm_data = {
601 .wkup_irq = exynos3250_wkup_irq,
602 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
603 .pm_suspend = exynos_pm_suspend,
604 .pm_resume = exynos3250_pm_resume,
605 .pm_prepare = exynos3250_pm_prepare,
606 .cpu_suspend = exynos3250_cpu_suspend,
607 };
608
609 static const struct exynos_pm_data exynos4_pm_data = {
610 .wkup_irq = exynos4_wkup_irq,
611 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
612 .pm_suspend = exynos_pm_suspend,
613 .pm_resume = exynos_pm_resume,
614 .pm_prepare = exynos_pm_prepare,
615 .cpu_suspend = exynos_cpu_suspend,
616 };
617
618 static const struct exynos_pm_data exynos5250_pm_data = {
619 .wkup_irq = exynos5250_wkup_irq,
620 .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
621 .pm_suspend = exynos_pm_suspend,
622 .pm_resume = exynos_pm_resume,
623 .pm_prepare = exynos_pm_prepare,
624 .cpu_suspend = exynos_cpu_suspend,
625 };
626
627 static const struct exynos_pm_data exynos5420_pm_data = {
628 .wkup_irq = exynos5250_wkup_irq,
629 .wake_disable_mask = (0x7F << 7) | (0x1F << 1),
630 .pm_resume_prepare = exynos5420_prepare_pm_resume,
631 .pm_resume = exynos5420_pm_resume,
632 .pm_suspend = exynos5420_pm_suspend,
633 .pm_prepare = exynos5420_pm_prepare,
634 .cpu_suspend = exynos5420_cpu_suspend,
635 };
636
637 static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = {
638 {
639 .compatible = "samsung,exynos3250-pmu",
640 .data = &exynos3250_pm_data,
641 }, {
642 .compatible = "samsung,exynos4210-pmu",
643 .data = &exynos4_pm_data,
644 }, {
645 .compatible = "samsung,exynos4212-pmu",
646 .data = &exynos4_pm_data,
647 }, {
648 .compatible = "samsung,exynos4412-pmu",
649 .data = &exynos4_pm_data,
650 }, {
651 .compatible = "samsung,exynos5250-pmu",
652 .data = &exynos5250_pm_data,
653 }, {
654 .compatible = "samsung,exynos5420-pmu",
655 .data = &exynos5420_pm_data,
656 },
657 { /*sentinel*/ },
658 };
659
660 static struct syscore_ops exynos_pm_syscore_ops;
661
exynos_pm_init(void)662 void __init exynos_pm_init(void)
663 {
664 const struct of_device_id *match;
665 struct device_node *np;
666 u32 tmp;
667
668 np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
669 if (!np) {
670 pr_err("Failed to find PMU node\n");
671 return;
672 }
673
674 if (WARN_ON(!of_property_read_bool(np, "interrupt-controller"))) {
675 pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
676 of_node_put(np);
677 return;
678 }
679 of_node_put(np);
680
681 pm_data = (const struct exynos_pm_data *) match->data;
682
683 /* All wakeup disable */
684 tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
685 tmp |= pm_data->wake_disable_mask;
686 pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
687
688 exynos_pm_syscore_ops.suspend = pm_data->pm_suspend;
689 exynos_pm_syscore_ops.resume = pm_data->pm_resume;
690
691 register_syscore_ops(&exynos_pm_syscore_ops);
692 suspend_set_ops(&exynos_suspend_ops);
693
694 /*
695 * Applicable as of now only to Exynos542x. If booted under secure
696 * firmware, the non-secure region of sysram should be used.
697 */
698 if (exynos_secure_firmware_available()) {
699 pm_state.sysram_phys = sysram_base_phys;
700 pm_state.sysram_base = sysram_ns_base_addr;
701 pm_state.secure_firmware = true;
702 } else {
703 pm_state.sysram_base = sysram_base_addr;
704 }
705 }
706
