1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2012 Freescale Semiconductor, Inc.
4
5#include <dt-bindings/gpio/gpio.h>
6#include "imx28-pinfunc.h"
7
8/ {
9	#address-cells = <1>;
10	#size-cells = <1>;
11
12	interrupt-parent = <&icoll>;
13	/*
14	 * The decompressor and also some bootloaders rely on a
15	 * pre-existing /chosen node to be available to insert the
16	 * command line and merge other ATAGS info.
17	 * Also for U-Boot there must be a pre-existing /memory node.
18	 */
19	chosen {};
20	memory { device_type = "memory"; };
21
22	aliases {
23		ethernet0 = &mac0;
24		ethernet1 = &mac1;
25		gpio0 = &gpio0;
26		gpio1 = &gpio1;
27		gpio2 = &gpio2;
28		gpio3 = &gpio3;
29		gpio4 = &gpio4;
30		saif0 = &saif0;
31		saif1 = &saif1;
32		serial0 = &auart0;
33		serial1 = &auart1;
34		serial2 = &auart2;
35		serial3 = &auart3;
36		serial4 = &auart4;
37		spi0 = &ssp1;
38		spi1 = &ssp2;
39		usbphy0 = &usbphy0;
40		usbphy1 = &usbphy1;
41	};
42
43	cpus {
44		#address-cells = <1>;
45		#size-cells = <0>;
46
47		cpu@0 {
48			compatible = "arm,arm926ej-s";
49			device_type = "cpu";
50			reg = <0>;
51		};
52	};
53
54	apb@80000000 {
55		compatible = "simple-bus";
56		#address-cells = <1>;
57		#size-cells = <1>;
58		reg = <0x80000000 0x80000>;
59		ranges;
60
61		apbh@80000000 {
62			compatible = "simple-bus";
63			#address-cells = <1>;
64			#size-cells = <1>;
65			reg = <0x80000000 0x3c900>;
66			ranges;
67
68			icoll: interrupt-controller@80000000 {
69				compatible = "fsl,imx28-icoll", "fsl,icoll";
70				interrupt-controller;
71				#interrupt-cells = <1>;
72				reg = <0x80000000 0x2000>;
73			};
74
75			hsadc: hsadc@80002000 {
76				reg = <0x80002000 0x2000>;
77				interrupts = <13>;
78				dmas = <&dma_apbh 12>;
79				dma-names = "rx";
80				status = "disabled";
81			};
82
83			dma_apbh: dma-apbh@80004000 {
84				compatible = "fsl,imx28-dma-apbh";
85				reg = <0x80004000 0x2000>;
86				interrupts = <82 83 84 85
87					      88 88 88 88
88					      88 88 88 88
89					      87 86 0 0>;
90				interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
91						  "gpmi0", "gmpi1", "gpmi2", "gmpi3",
92						  "gpmi4", "gmpi5", "gpmi6", "gmpi7",
93						  "hsadc", "lcdif", "empty", "empty";
94				#dma-cells = <1>;
95				dma-channels = <16>;
96				clocks = <&clks 25>;
97			};
98
99			perfmon: perfmon@80006000 {
100				reg = <0x80006000 0x800>;
101				interrupts = <27>;
102				status = "disabled";
103			};
104
105			gpmi: gpmi-nand@8000c000 {
106				compatible = "fsl,imx28-gpmi-nand";
107				#address-cells = <1>;
108				#size-cells = <1>;
109				reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
110				reg-names = "gpmi-nand", "bch";
111				interrupts = <41>;
112				interrupt-names = "bch";
113				clocks = <&clks 50>;
114				clock-names = "gpmi_io";
115				dmas = <&dma_apbh 4>;
116				dma-names = "rx-tx";
117				status = "disabled";
118			};
119
120			ssp0: ssp@80010000 {
121				#address-cells = <1>;
122				#size-cells = <0>;
123				reg = <0x80010000 0x2000>;
124				interrupts = <96>;
125				clocks = <&clks 46>;
126				dmas = <&dma_apbh 0>;
127				dma-names = "rx-tx";
128				status = "disabled";
129			};
130
131			ssp1: ssp@80012000 {
132				#address-cells = <1>;
133				#size-cells = <0>;
134				reg = <0x80012000 0x2000>;
135				interrupts = <97>;
136				clocks = <&clks 47>;
137				dmas = <&dma_apbh 1>;
138				dma-names = "rx-tx";
139				status = "disabled";
140			};
141
142			ssp2: ssp@80014000 {
143				#address-cells = <1>;
144				#size-cells = <0>;
145				reg = <0x80014000 0x2000>;
146				interrupts = <98>;
147				clocks = <&clks 48>;
148				dmas = <&dma_apbh 2>;
149				dma-names = "rx-tx";
150				status = "disabled";
151			};
152
153			ssp3: ssp@80016000 {
154				#address-cells = <1>;
155				#size-cells = <0>;
156				reg = <0x80016000 0x2000>;
157				interrupts = <99>;
158				clocks = <&clks 49>;
159				dmas = <&dma_apbh 3>;
160				dma-names = "rx-tx";
161				status = "disabled";
162			};
163
164			pinctrl: pinctrl@80018000 {
165				#address-cells = <1>;
166				#size-cells = <0>;
167				compatible = "fsl,imx28-pinctrl", "simple-bus";
168				reg = <0x80018000 0x2000>;
169
170				gpio0: gpio@0 {
171					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
172					reg = <0>;
173					interrupts = <127>;
174					gpio-controller;
175					#gpio-cells = <2>;
176					interrupt-controller;
177					#interrupt-cells = <2>;
178				};
179
180				gpio1: gpio@1 {
181					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
182					reg = <1>;
183					interrupts = <126>;
184					gpio-controller;
185					#gpio-cells = <2>;
186					interrupt-controller;
187					#interrupt-cells = <2>;
188				};
189
190				gpio2: gpio@2 {
191					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
192					reg = <2>;
193					interrupts = <125>;
194					gpio-controller;
195					#gpio-cells = <2>;
196					interrupt-controller;
197					#interrupt-cells = <2>;
198				};
199
200				gpio3: gpio@3 {
201					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
202					reg = <3>;
203					interrupts = <124>;
204					gpio-controller;
205					#gpio-cells = <2>;
206					interrupt-controller;
207					#interrupt-cells = <2>;
208				};
209
210				gpio4: gpio@4 {
211					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
212					reg = <4>;
213					interrupts = <123>;
214					gpio-controller;
215					#gpio-cells = <2>;
216					interrupt-controller;
217					#interrupt-cells = <2>;
218				};
219
220				duart_pins_a: duart@0 {
221					reg = <0>;
222					fsl,pinmux-ids = <
223						MX28_PAD_PWM0__DUART_RX
224						MX28_PAD_PWM1__DUART_TX
225					>;
226					fsl,drive-strength = <MXS_DRIVE_4mA>;
227					fsl,voltage = <MXS_VOLTAGE_HIGH>;
228					fsl,pull-up = <MXS_PULL_DISABLE>;
229				};
230
231				duart_pins_b: duart@1 {
232					reg = <1>;
233					fsl,pinmux-ids = <
234						MX28_PAD_AUART0_CTS__DUART_RX
235						MX28_PAD_AUART0_RTS__DUART_TX
236					>;
237					fsl,drive-strength = <MXS_DRIVE_4mA>;
238					fsl,voltage = <MXS_VOLTAGE_HIGH>;
239					fsl,pull-up = <MXS_PULL_DISABLE>;
240				};
241
242				duart_4pins_a: duart-4pins@0 {
243					reg = <0>;
244					fsl,pinmux-ids = <
245						MX28_PAD_AUART0_CTS__DUART_RX
246						MX28_PAD_AUART0_RTS__DUART_TX
247						MX28_PAD_AUART0_RX__DUART_CTS
248						MX28_PAD_AUART0_TX__DUART_RTS
249					>;
250					fsl,drive-strength = <MXS_DRIVE_4mA>;
251					fsl,voltage = <MXS_VOLTAGE_HIGH>;
252					fsl,pull-up = <MXS_PULL_DISABLE>;
253				};
254
255				gpmi_pins_a: gpmi-nand@0 {
256					reg = <0>;
257					fsl,pinmux-ids = <
258						MX28_PAD_GPMI_D00__GPMI_D0
259						MX28_PAD_GPMI_D01__GPMI_D1
260						MX28_PAD_GPMI_D02__GPMI_D2
261						MX28_PAD_GPMI_D03__GPMI_D3
262						MX28_PAD_GPMI_D04__GPMI_D4
263						MX28_PAD_GPMI_D05__GPMI_D5
264						MX28_PAD_GPMI_D06__GPMI_D6
265						MX28_PAD_GPMI_D07__GPMI_D7
266						MX28_PAD_GPMI_CE0N__GPMI_CE0N
267						MX28_PAD_GPMI_RDY0__GPMI_READY0
268						MX28_PAD_GPMI_RDN__GPMI_RDN
269						MX28_PAD_GPMI_WRN__GPMI_WRN
270						MX28_PAD_GPMI_ALE__GPMI_ALE
271						MX28_PAD_GPMI_CLE__GPMI_CLE
272						MX28_PAD_GPMI_RESETN__GPMI_RESETN
273					>;
274					fsl,drive-strength = <MXS_DRIVE_4mA>;
275					fsl,voltage = <MXS_VOLTAGE_HIGH>;
276					fsl,pull-up = <MXS_PULL_DISABLE>;
277				};
278
279				gpmi_status_cfg: gpmi-status-cfg@0 {
280					reg = <0>;
281					fsl,pinmux-ids = <
282						MX28_PAD_GPMI_RDN__GPMI_RDN
283						MX28_PAD_GPMI_WRN__GPMI_WRN
284						MX28_PAD_GPMI_RESETN__GPMI_RESETN
285					>;
286					fsl,drive-strength = <MXS_DRIVE_12mA>;
287				};
288
289				auart0_pins_a: auart0@0 {
290					reg = <0>;
291					fsl,pinmux-ids = <
292						MX28_PAD_AUART0_RX__AUART0_RX
293						MX28_PAD_AUART0_TX__AUART0_TX
294						MX28_PAD_AUART0_CTS__AUART0_CTS
295						MX28_PAD_AUART0_RTS__AUART0_RTS
296					>;
297					fsl,drive-strength = <MXS_DRIVE_4mA>;
298					fsl,voltage = <MXS_VOLTAGE_HIGH>;
299					fsl,pull-up = <MXS_PULL_DISABLE>;
300				};
301
302				auart0_2pins_a: auart0-2pins@0 {
303					reg = <0>;
304					fsl,pinmux-ids = <
305						MX28_PAD_AUART0_RX__AUART0_RX
306						MX28_PAD_AUART0_TX__AUART0_TX
307					>;
308					fsl,drive-strength = <MXS_DRIVE_4mA>;
309					fsl,voltage = <MXS_VOLTAGE_HIGH>;
310					fsl,pull-up = <MXS_PULL_DISABLE>;
311				};
312
313				auart1_pins_a: auart1@0 {
314					reg = <0>;
315					fsl,pinmux-ids = <
316						MX28_PAD_AUART1_RX__AUART1_RX
317						MX28_PAD_AUART1_TX__AUART1_TX
318						MX28_PAD_AUART1_CTS__AUART1_CTS
319						MX28_PAD_AUART1_RTS__AUART1_RTS
320					>;
321					fsl,drive-strength = <MXS_DRIVE_4mA>;
322					fsl,voltage = <MXS_VOLTAGE_HIGH>;
323					fsl,pull-up = <MXS_PULL_DISABLE>;
324				};
325
326				auart1_2pins_a: auart1-2pins@0 {
327					reg = <0>;
328					fsl,pinmux-ids = <
329						MX28_PAD_AUART1_RX__AUART1_RX
330						MX28_PAD_AUART1_TX__AUART1_TX
331					>;
332					fsl,drive-strength = <MXS_DRIVE_4mA>;
333					fsl,voltage = <MXS_VOLTAGE_HIGH>;
334					fsl,pull-up = <MXS_PULL_DISABLE>;
335				};
336
337				auart2_2pins_a: auart2-2pins@0 {
338					reg = <0>;
339					fsl,pinmux-ids = <
340						MX28_PAD_SSP2_SCK__AUART2_RX
341						MX28_PAD_SSP2_MOSI__AUART2_TX
342					>;
343					fsl,drive-strength = <MXS_DRIVE_4mA>;
344					fsl,voltage = <MXS_VOLTAGE_HIGH>;
345					fsl,pull-up = <MXS_PULL_DISABLE>;
346				};
347
348				auart2_2pins_b: auart2-2pins@1 {
349					reg = <1>;
350					fsl,pinmux-ids = <
351						MX28_PAD_AUART2_RX__AUART2_RX
352						MX28_PAD_AUART2_TX__AUART2_TX
353					>;
354					fsl,drive-strength = <MXS_DRIVE_4mA>;
355					fsl,voltage = <MXS_VOLTAGE_HIGH>;
356					fsl,pull-up = <MXS_PULL_DISABLE>;
357				};
358
359				auart2_pins_a: auart2-pins@0 {
360					reg = <0>;
361					fsl,pinmux-ids = <
362						MX28_PAD_AUART2_RX__AUART2_RX
363						MX28_PAD_AUART2_TX__AUART2_TX
364						MX28_PAD_AUART2_CTS__AUART2_CTS
365						MX28_PAD_AUART2_RTS__AUART2_RTS
366					>;
367					fsl,drive-strength = <MXS_DRIVE_4mA>;
368					fsl,voltage = <MXS_VOLTAGE_HIGH>;
369					fsl,pull-up = <MXS_PULL_DISABLE>;
370				};
371
372				auart3_pins_a: auart3@0 {
373					reg = <0>;
374					fsl,pinmux-ids = <
375						MX28_PAD_AUART3_RX__AUART3_RX
376						MX28_PAD_AUART3_TX__AUART3_TX
377						MX28_PAD_AUART3_CTS__AUART3_CTS
378						MX28_PAD_AUART3_RTS__AUART3_RTS
379					>;
380					fsl,drive-strength = <MXS_DRIVE_4mA>;
381					fsl,voltage = <MXS_VOLTAGE_HIGH>;
382					fsl,pull-up = <MXS_PULL_DISABLE>;
383				};
384
385				auart3_2pins_a: auart3-2pins@0 {
386					reg = <0>;
387					fsl,pinmux-ids = <
388						MX28_PAD_SSP2_MISO__AUART3_RX
389						MX28_PAD_SSP2_SS0__AUART3_TX
390					>;
391					fsl,drive-strength = <MXS_DRIVE_4mA>;
392					fsl,voltage = <MXS_VOLTAGE_HIGH>;
393					fsl,pull-up = <MXS_PULL_DISABLE>;
394				};
395
396				auart3_2pins_b: auart3-2pins@1 {
397					reg = <1>;
398					fsl,pinmux-ids = <
399						MX28_PAD_AUART3_RX__AUART3_RX
400						MX28_PAD_AUART3_TX__AUART3_TX
401					>;
402					fsl,drive-strength = <MXS_DRIVE_4mA>;
403					fsl,voltage = <MXS_VOLTAGE_HIGH>;
404					fsl,pull-up = <MXS_PULL_DISABLE>;
405				};
406
407				auart4_2pins_a: auart4@0 {
408					reg = <0>;
409					fsl,pinmux-ids = <
410						MX28_PAD_SSP3_SCK__AUART4_TX
411						MX28_PAD_SSP3_MOSI__AUART4_RX
412					>;
413					fsl,drive-strength = <MXS_DRIVE_4mA>;
414					fsl,voltage = <MXS_VOLTAGE_HIGH>;
415					fsl,pull-up = <MXS_PULL_DISABLE>;
416				};
417
418				auart4_2pins_b: auart4@1 {
419					reg = <1>;
420					fsl,pinmux-ids = <
421						MX28_PAD_AUART0_CTS__AUART4_RX
422						MX28_PAD_AUART0_RTS__AUART4_TX
423					>;
424					fsl,drive-strength = <MXS_DRIVE_4mA>;
425					fsl,voltage = <MXS_VOLTAGE_HIGH>;
426					fsl,pull-up = <MXS_PULL_DISABLE>;
427				};
428
429				mac0_pins_a: mac0@0 {
430					reg = <0>;
431					fsl,pinmux-ids = <
432						MX28_PAD_ENET0_MDC__ENET0_MDC
433						MX28_PAD_ENET0_MDIO__ENET0_MDIO
434						MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
435						MX28_PAD_ENET0_RXD0__ENET0_RXD0
436						MX28_PAD_ENET0_RXD1__ENET0_RXD1
437						MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
438						MX28_PAD_ENET0_TXD0__ENET0_TXD0
439						MX28_PAD_ENET0_TXD1__ENET0_TXD1
440						MX28_PAD_ENET_CLK__CLKCTRL_ENET
441					>;
442					fsl,drive-strength = <MXS_DRIVE_8mA>;
443					fsl,voltage = <MXS_VOLTAGE_HIGH>;
444					fsl,pull-up = <MXS_PULL_ENABLE>;
445				};
446
447				mac0_pins_b: mac0@1 {
448					reg = <1>;
449					fsl,pinmux-ids = <
450						MX28_PAD_ENET0_MDC__ENET0_MDC
451						MX28_PAD_ENET0_MDIO__ENET0_MDIO
452						MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
453						MX28_PAD_ENET0_RXD0__ENET0_RXD0
454						MX28_PAD_ENET0_RXD1__ENET0_RXD1
455						MX28_PAD_ENET0_RXD2__ENET0_RXD2
456						MX28_PAD_ENET0_RXD3__ENET0_RXD3
457						MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
458						MX28_PAD_ENET0_TXD0__ENET0_TXD0
459						MX28_PAD_ENET0_TXD1__ENET0_TXD1
460						MX28_PAD_ENET0_TXD2__ENET0_TXD2
461						MX28_PAD_ENET0_TXD3__ENET0_TXD3
462						MX28_PAD_ENET_CLK__CLKCTRL_ENET
463						MX28_PAD_ENET0_COL__ENET0_COL
464						MX28_PAD_ENET0_CRS__ENET0_CRS
465						MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
466						MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
467						>;
468					fsl,drive-strength = <MXS_DRIVE_8mA>;
469					fsl,voltage = <MXS_VOLTAGE_HIGH>;
470					fsl,pull-up = <MXS_PULL_ENABLE>;
471				};
472
473				mac1_pins_a: mac1@0 {
474					reg = <0>;
475					fsl,pinmux-ids = <
476						MX28_PAD_ENET0_CRS__ENET1_RX_EN
477						MX28_PAD_ENET0_RXD2__ENET1_RXD0
478						MX28_PAD_ENET0_RXD3__ENET1_RXD1
479						MX28_PAD_ENET0_COL__ENET1_TX_EN
480						MX28_PAD_ENET0_TXD2__ENET1_TXD0
481						MX28_PAD_ENET0_TXD3__ENET1_TXD1
482					>;
483					fsl,drive-strength = <MXS_DRIVE_8mA>;
484					fsl,voltage = <MXS_VOLTAGE_HIGH>;
485					fsl,pull-up = <MXS_PULL_ENABLE>;
486				};
487
488				mmc0_8bit_pins_a: mmc0-8bit@0 {
489					reg = <0>;
490					fsl,pinmux-ids = <
491						MX28_PAD_SSP0_DATA0__SSP0_D0
492						MX28_PAD_SSP0_DATA1__SSP0_D1
493						MX28_PAD_SSP0_DATA2__SSP0_D2
494						MX28_PAD_SSP0_DATA3__SSP0_D3
495						MX28_PAD_SSP0_DATA4__SSP0_D4
496						MX28_PAD_SSP0_DATA5__SSP0_D5
497						MX28_PAD_SSP0_DATA6__SSP0_D6
498						MX28_PAD_SSP0_DATA7__SSP0_D7
499						MX28_PAD_SSP0_CMD__SSP0_CMD
500						MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
501						MX28_PAD_SSP0_SCK__SSP0_SCK
502					>;
503					fsl,drive-strength = <MXS_DRIVE_8mA>;
504					fsl,voltage = <MXS_VOLTAGE_HIGH>;
505					fsl,pull-up = <MXS_PULL_ENABLE>;
506				};
507
508				mmc0_4bit_pins_a: mmc0-4bit@0 {
509					reg = <0>;
510					fsl,pinmux-ids = <
511						MX28_PAD_SSP0_DATA0__SSP0_D0
512						MX28_PAD_SSP0_DATA1__SSP0_D1
513						MX28_PAD_SSP0_DATA2__SSP0_D2
514						MX28_PAD_SSP0_DATA3__SSP0_D3
515						MX28_PAD_SSP0_CMD__SSP0_CMD
516						MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
517						MX28_PAD_SSP0_SCK__SSP0_SCK
518					>;
519					fsl,drive-strength = <MXS_DRIVE_8mA>;
520					fsl,voltage = <MXS_VOLTAGE_HIGH>;
521					fsl,pull-up = <MXS_PULL_ENABLE>;
522				};
523
524				mmc0_cd_cfg: mmc0-cd-cfg@0 {
525					reg = <0>;
526					fsl,pinmux-ids = <
527						MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
528					>;
529					fsl,pull-up = <MXS_PULL_DISABLE>;
530				};
531
532				mmc0_sck_cfg: mmc0-sck-cfg@0 {
533					reg = <0>;
534					fsl,pinmux-ids = <
535						MX28_PAD_SSP0_SCK__SSP0_SCK
536					>;
537					fsl,drive-strength = <MXS_DRIVE_12mA>;
538					fsl,pull-up = <MXS_PULL_DISABLE>;
539				};
540
541				mmc1_4bit_pins_a: mmc1-4bit@0 {
542					reg = <0>;
543					fsl,pinmux-ids = <
544						MX28_PAD_GPMI_D00__SSP1_D0
545						MX28_PAD_GPMI_D01__SSP1_D1
546						MX28_PAD_GPMI_D02__SSP1_D2
547						MX28_PAD_GPMI_D03__SSP1_D3
548						MX28_PAD_GPMI_RDY1__SSP1_CMD
549						MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
550						MX28_PAD_GPMI_WRN__SSP1_SCK
551					>;
552					fsl,drive-strength = <MXS_DRIVE_8mA>;
553					fsl,voltage = <MXS_VOLTAGE_HIGH>;
554					fsl,pull-up = <MXS_PULL_ENABLE>;
555				};
556
557				mmc1_cd_cfg: mmc1-cd-cfg@0 {
558					reg = <0>;
559					fsl,pinmux-ids = <
560						MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
561					>;
562					fsl,pull-up = <MXS_PULL_DISABLE>;
563				};
564
565				mmc1_sck_cfg: mmc1-sck-cfg@0 {
566					reg = <0>;
567					fsl,pinmux-ids = <
568						MX28_PAD_GPMI_WRN__SSP1_SCK
569					>;
570					fsl,drive-strength = <MXS_DRIVE_12mA>;
571					fsl,pull-up = <MXS_PULL_DISABLE>;
572				};
573
574
575				mmc2_4bit_pins_a: mmc2-4bit@0 {
576					reg = <0>;
577					fsl,pinmux-ids = <
578						MX28_PAD_SSP0_DATA4__SSP2_D0
579						MX28_PAD_SSP1_SCK__SSP2_D1
580						MX28_PAD_SSP1_CMD__SSP2_D2
581						MX28_PAD_SSP0_DATA5__SSP2_D3
582						MX28_PAD_SSP0_DATA6__SSP2_CMD
583						MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
584						MX28_PAD_SSP0_DATA7__SSP2_SCK
585					>;
586					fsl,drive-strength = <MXS_DRIVE_8mA>;
587					fsl,voltage = <MXS_VOLTAGE_HIGH>;
588					fsl,pull-up = <MXS_PULL_ENABLE>;
589				};
590
591				mmc2_4bit_pins_b: mmc2-4bit@1 {
592					reg = <1>;
593					fsl,pinmux-ids = <
594						MX28_PAD_SSP2_SCK__SSP2_SCK
595						MX28_PAD_SSP2_MOSI__SSP2_CMD
596						MX28_PAD_SSP2_MISO__SSP2_D0
597						MX28_PAD_SSP2_SS0__SSP2_D3
598						MX28_PAD_SSP2_SS1__SSP2_D1
599						MX28_PAD_SSP2_SS2__SSP2_D2
600						MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
601					>;
602					fsl,drive-strength = <MXS_DRIVE_8mA>;
603					fsl,voltage = <MXS_VOLTAGE_HIGH>;
604					fsl,pull-up = <MXS_PULL_ENABLE>;
605				};
606
607				mmc2_cd_cfg: mmc2-cd-cfg@0 {
608					reg = <0>;
609					fsl,pinmux-ids = <
610						MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
611					>;
612					fsl,pull-up = <MXS_PULL_DISABLE>;
613				};
614
615				mmc2_sck_cfg_a: mmc2-sck-cfg@0 {
616					reg = <0>;
617					fsl,pinmux-ids = <
618						MX28_PAD_SSP0_DATA7__SSP2_SCK
619					>;
620					fsl,drive-strength = <MXS_DRIVE_12mA>;
621					fsl,pull-up = <MXS_PULL_DISABLE>;
622				};
623
624				mmc2_sck_cfg_b: mmc2-sck-cfg@1 {
625					reg = <1>;
626					fsl,pinmux-ids = <
627						MX28_PAD_SSP2_SCK__SSP2_SCK
628					>;
629					fsl,drive-strength = <MXS_DRIVE_12mA>;
630					fsl,pull-up = <MXS_PULL_DISABLE>;
631				};
632
633				i2c0_pins_a: i2c0@0 {
634					reg = <0>;
635					fsl,pinmux-ids = <
636						MX28_PAD_I2C0_SCL__I2C0_SCL
637						MX28_PAD_I2C0_SDA__I2C0_SDA
638					>;
639					fsl,drive-strength = <MXS_DRIVE_8mA>;
640					fsl,voltage = <MXS_VOLTAGE_HIGH>;
641					fsl,pull-up = <MXS_PULL_ENABLE>;
642				};
643
644				i2c0_pins_b: i2c0@1 {
645					reg = <1>;
646					fsl,pinmux-ids = <
647						MX28_PAD_AUART0_RX__I2C0_SCL
648						MX28_PAD_AUART0_TX__I2C0_SDA
649					>;
650					fsl,drive-strength = <MXS_DRIVE_8mA>;
651					fsl,voltage = <MXS_VOLTAGE_HIGH>;
652					fsl,pull-up = <MXS_PULL_ENABLE>;
653				};
654
655				i2c1_pins_a: i2c1@0 {
656					reg = <0>;
657					fsl,pinmux-ids = <
658						MX28_PAD_PWM0__I2C1_SCL
659						MX28_PAD_PWM1__I2C1_SDA
660					>;
661					fsl,drive-strength = <MXS_DRIVE_8mA>;
662					fsl,voltage = <MXS_VOLTAGE_HIGH>;
663					fsl,pull-up = <MXS_PULL_ENABLE>;
664				};
665
666				i2c1_pins_b: i2c1@1 {
667					reg = <1>;
668					fsl,pinmux-ids = <
669						MX28_PAD_AUART2_CTS__I2C1_SCL
670						MX28_PAD_AUART2_RTS__I2C1_SDA
671					>;
672					fsl,drive-strength = <MXS_DRIVE_8mA>;
673					fsl,voltage = <MXS_VOLTAGE_HIGH>;
674					fsl,pull-up = <MXS_PULL_ENABLE>;
675				};
676
677				saif0_pins_a: saif0@0 {
678					reg = <0>;
679					fsl,pinmux-ids = <
680						MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
681						MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
682						MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
683						MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
684					>;
685					fsl,drive-strength = <MXS_DRIVE_12mA>;
686					fsl,voltage = <MXS_VOLTAGE_HIGH>;
687					fsl,pull-up = <MXS_PULL_ENABLE>;
688				};
689
690				saif0_pins_b: saif0@1 {
691					reg = <1>;
692					fsl,pinmux-ids = <
693						MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
694						MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
695						MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
696					>;
697					fsl,drive-strength = <MXS_DRIVE_12mA>;
698					fsl,voltage = <MXS_VOLTAGE_HIGH>;
699					fsl,pull-up = <MXS_PULL_ENABLE>;
700				};
701
702				saif1_pins_a: saif1@0 {
703					reg = <0>;
704					fsl,pinmux-ids = <
705						MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
706					>;
707					fsl,drive-strength = <MXS_DRIVE_12mA>;
708					fsl,voltage = <MXS_VOLTAGE_HIGH>;
709					fsl,pull-up = <MXS_PULL_ENABLE>;
710				};
711
712				pwm0_pins_a: pwm0@0 {
713					reg = <0>;
714					fsl,pinmux-ids = <
715						MX28_PAD_PWM0__PWM_0
716					>;
717					fsl,drive-strength = <MXS_DRIVE_4mA>;
718					fsl,voltage = <MXS_VOLTAGE_HIGH>;
719					fsl,pull-up = <MXS_PULL_DISABLE>;
720				};
721
722				pwm2_pins_a: pwm2@0 {
723					reg = <0>;
724					fsl,pinmux-ids = <
725						MX28_PAD_PWM2__PWM_2
726					>;
727					fsl,drive-strength = <MXS_DRIVE_4mA>;
728					fsl,voltage = <MXS_VOLTAGE_HIGH>;
729					fsl,pull-up = <MXS_PULL_DISABLE>;
730				};
731
732				pwm3_pins_a: pwm3@0 {
733					reg = <0>;
734					fsl,pinmux-ids = <
735						MX28_PAD_PWM3__PWM_3
736					>;
737					fsl,drive-strength = <MXS_DRIVE_4mA>;
738					fsl,voltage = <MXS_VOLTAGE_HIGH>;
739					fsl,pull-up = <MXS_PULL_DISABLE>;
740				};
741
742				pwm3_pins_b: pwm3@1 {
743					reg = <1>;
744					fsl,pinmux-ids = <
745						MX28_PAD_SAIF0_MCLK__PWM_3
746					>;
747					fsl,drive-strength = <MXS_DRIVE_4mA>;
748					fsl,voltage = <MXS_VOLTAGE_HIGH>;
749					fsl,pull-up = <MXS_PULL_DISABLE>;
750				};
751
752				pwm4_pins_a: pwm4@0 {
753					reg = <0>;
754					fsl,pinmux-ids = <
755						MX28_PAD_PWM4__PWM_4
756					>;
757					fsl,drive-strength = <MXS_DRIVE_4mA>;
758					fsl,voltage = <MXS_VOLTAGE_HIGH>;
759					fsl,pull-up = <MXS_PULL_DISABLE>;
760				};
761
762				lcdif_24bit_pins_a: lcdif-24bit@0 {
763					reg = <0>;
764					fsl,pinmux-ids = <
765						MX28_PAD_LCD_D00__LCD_D0
766						MX28_PAD_LCD_D01__LCD_D1
767						MX28_PAD_LCD_D02__LCD_D2
768						MX28_PAD_LCD_D03__LCD_D3
769						MX28_PAD_LCD_D04__LCD_D4
770						MX28_PAD_LCD_D05__LCD_D5
771						MX28_PAD_LCD_D06__LCD_D6
772						MX28_PAD_LCD_D07__LCD_D7
773						MX28_PAD_LCD_D08__LCD_D8
774						MX28_PAD_LCD_D09__LCD_D9
775						MX28_PAD_LCD_D10__LCD_D10
776						MX28_PAD_LCD_D11__LCD_D11
777						MX28_PAD_LCD_D12__LCD_D12
778						MX28_PAD_LCD_D13__LCD_D13
779						MX28_PAD_LCD_D14__LCD_D14
780						MX28_PAD_LCD_D15__LCD_D15
781						MX28_PAD_LCD_D16__LCD_D16
782						MX28_PAD_LCD_D17__LCD_D17
783						MX28_PAD_LCD_D18__LCD_D18
784						MX28_PAD_LCD_D19__LCD_D19
785						MX28_PAD_LCD_D20__LCD_D20
786						MX28_PAD_LCD_D21__LCD_D21
787						MX28_PAD_LCD_D22__LCD_D22
788						MX28_PAD_LCD_D23__LCD_D23
789					>;
790					fsl,drive-strength = <MXS_DRIVE_4mA>;
791					fsl,voltage = <MXS_VOLTAGE_HIGH>;
792					fsl,pull-up = <MXS_PULL_DISABLE>;
793				};
794
795				lcdif_18bit_pins_a: lcdif-18bit@0 {
796					reg = <0>;
797					fsl,pinmux-ids = <
798						MX28_PAD_LCD_D00__LCD_D0
799						MX28_PAD_LCD_D01__LCD_D1
800						MX28_PAD_LCD_D02__LCD_D2
801						MX28_PAD_LCD_D03__LCD_D3
802						MX28_PAD_LCD_D04__LCD_D4
803						MX28_PAD_LCD_D05__LCD_D5
804						MX28_PAD_LCD_D06__LCD_D6
805						MX28_PAD_LCD_D07__LCD_D7
806						MX28_PAD_LCD_D08__LCD_D8
807						MX28_PAD_LCD_D09__LCD_D9
808						MX28_PAD_LCD_D10__LCD_D10
809						MX28_PAD_LCD_D11__LCD_D11
810						MX28_PAD_LCD_D12__LCD_D12
811						MX28_PAD_LCD_D13__LCD_D13
812						MX28_PAD_LCD_D14__LCD_D14
813						MX28_PAD_LCD_D15__LCD_D15
814						MX28_PAD_LCD_D16__LCD_D16
815						MX28_PAD_LCD_D17__LCD_D17
816					>;
817					fsl,drive-strength = <MXS_DRIVE_4mA>;
818					fsl,voltage = <MXS_VOLTAGE_HIGH>;
819					fsl,pull-up = <MXS_PULL_DISABLE>;
820				};
821
822				lcdif_16bit_pins_a: lcdif-16bit@0 {
823					reg = <0>;
824					fsl,pinmux-ids = <
825						MX28_PAD_LCD_D00__LCD_D0
826						MX28_PAD_LCD_D01__LCD_D1
827						MX28_PAD_LCD_D02__LCD_D2
828						MX28_PAD_LCD_D03__LCD_D3
829						MX28_PAD_LCD_D04__LCD_D4
830						MX28_PAD_LCD_D05__LCD_D5
831						MX28_PAD_LCD_D06__LCD_D6
832						MX28_PAD_LCD_D07__LCD_D7
833						MX28_PAD_LCD_D08__LCD_D8
834						MX28_PAD_LCD_D09__LCD_D9
835						MX28_PAD_LCD_D10__LCD_D10
836						MX28_PAD_LCD_D11__LCD_D11
837						MX28_PAD_LCD_D12__LCD_D12
838						MX28_PAD_LCD_D13__LCD_D13
839						MX28_PAD_LCD_D14__LCD_D14
840						MX28_PAD_LCD_D15__LCD_D15
841					>;
842					fsl,drive-strength = <MXS_DRIVE_4mA>;
843					fsl,voltage = <MXS_VOLTAGE_HIGH>;
844					fsl,pull-up = <MXS_PULL_DISABLE>;
845				};
846
847				lcdif_sync_pins_a: lcdif-sync@0 {
848					reg = <0>;
849					fsl,pinmux-ids = <
850						MX28_PAD_LCD_RS__LCD_DOTCLK
851						MX28_PAD_LCD_CS__LCD_ENABLE
852						MX28_PAD_LCD_RD_E__LCD_VSYNC
853						MX28_PAD_LCD_WR_RWN__LCD_HSYNC
854					>;
855					fsl,drive-strength = <MXS_DRIVE_4mA>;
856					fsl,voltage = <MXS_VOLTAGE_HIGH>;
857					fsl,pull-up = <MXS_PULL_DISABLE>;
858				};
859
860				can0_pins_a: can0@0 {
861					reg = <0>;
862					fsl,pinmux-ids = <
863						MX28_PAD_GPMI_RDY2__CAN0_TX
864						MX28_PAD_GPMI_RDY3__CAN0_RX
865					>;
866					fsl,drive-strength = <MXS_DRIVE_4mA>;
867					fsl,voltage = <MXS_VOLTAGE_HIGH>;
868					fsl,pull-up = <MXS_PULL_DISABLE>;
869				};
870
871				can1_pins_a: can1@0 {
872					reg = <0>;
873					fsl,pinmux-ids = <
874						MX28_PAD_GPMI_CE2N__CAN1_TX
875						MX28_PAD_GPMI_CE3N__CAN1_RX
876					>;
877					fsl,drive-strength = <MXS_DRIVE_4mA>;
878					fsl,voltage = <MXS_VOLTAGE_HIGH>;
879					fsl,pull-up = <MXS_PULL_DISABLE>;
880				};
881
882				spi2_pins_a: spi2@0 {
883					reg = <0>;
884					fsl,pinmux-ids = <
885						MX28_PAD_SSP2_SCK__SSP2_SCK
886						MX28_PAD_SSP2_MOSI__SSP2_CMD
887						MX28_PAD_SSP2_MISO__SSP2_D0
888						MX28_PAD_SSP2_SS0__SSP2_D3
889					>;
890					fsl,drive-strength = <MXS_DRIVE_8mA>;
891					fsl,voltage = <MXS_VOLTAGE_HIGH>;
892					fsl,pull-up = <MXS_PULL_ENABLE>;
893				};
894
895				spi3_pins_a: spi3@0 {
896					reg = <0>;
897					fsl,pinmux-ids = <
898						MX28_PAD_AUART2_RX__SSP3_D4
899						MX28_PAD_AUART2_TX__SSP3_D5
900						MX28_PAD_SSP3_SCK__SSP3_SCK
901						MX28_PAD_SSP3_MOSI__SSP3_CMD
902						MX28_PAD_SSP3_MISO__SSP3_D0
903						MX28_PAD_SSP3_SS0__SSP3_D3
904					>;
905					fsl,drive-strength = <MXS_DRIVE_8mA>;
906					fsl,voltage = <MXS_VOLTAGE_HIGH>;
907					fsl,pull-up = <MXS_PULL_DISABLE>;
908				};
909
910				spi3_pins_b: spi3@1 {
911					reg = <1>;
912					fsl,pinmux-ids = <
913						MX28_PAD_SSP3_SCK__SSP3_SCK
914						MX28_PAD_SSP3_MOSI__SSP3_CMD
915						MX28_PAD_SSP3_MISO__SSP3_D0
916						MX28_PAD_SSP3_SS0__SSP3_D3
917					>;
918					fsl,drive-strength = <MXS_DRIVE_8mA>;
919					fsl,voltage = <MXS_VOLTAGE_HIGH>;
920					fsl,pull-up = <MXS_PULL_ENABLE>;
921				};
922
923				usb0_pins_a: usb0@0 {
924					reg = <0>;
925					fsl,pinmux-ids = <
926						MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
927					>;
928					fsl,drive-strength = <MXS_DRIVE_12mA>;
929					fsl,voltage = <MXS_VOLTAGE_HIGH>;
930					fsl,pull-up = <MXS_PULL_DISABLE>;
931				};
932
933				usb0_pins_b: usb0@1 {
934					reg = <1>;
935					fsl,pinmux-ids = <
936						MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
937					>;
938					fsl,drive-strength = <MXS_DRIVE_12mA>;
939					fsl,voltage = <MXS_VOLTAGE_HIGH>;
940					fsl,pull-up = <MXS_PULL_DISABLE>;
941				};
942
943				usb1_pins_a: usb1@0 {
944					reg = <0>;
945					fsl,pinmux-ids = <
946						MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
947					>;
948					fsl,drive-strength = <MXS_DRIVE_12mA>;
949					fsl,voltage = <MXS_VOLTAGE_HIGH>;
950					fsl,pull-up = <MXS_PULL_DISABLE>;
951				};
952
953				usb0_id_pins_a: usb0id@0 {
954					reg = <0>;
955					fsl,pinmux-ids = <
956						MX28_PAD_AUART1_RTS__USB0_ID
957					>;
958					fsl,drive-strength = <MXS_DRIVE_12mA>;
959					fsl,voltage = <MXS_VOLTAGE_HIGH>;
960					fsl,pull-up = <MXS_PULL_ENABLE>;
961				};
962
963				usb0_id_pins_b: usb0id1@0 {
964					reg = <0>;
965					fsl,pinmux-ids = <
966						MX28_PAD_PWM2__USB0_ID
967					>;
968					fsl,drive-strength = <MXS_DRIVE_12mA>;
969					fsl,voltage = <MXS_VOLTAGE_HIGH>;
970					fsl,pull-up = <MXS_PULL_ENABLE>;
971				};
972
973			};
974
975			digctl: digctl@8001c000 {
976				compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
977				reg = <0x8001c000 0x2000>;
978				interrupts = <89>;
979				status = "disabled";
980			};
981
982			etm: etm@80022000 {
983				reg = <0x80022000 0x2000>;
984				status = "disabled";
985			};
986
987			dma_apbx: dma-apbx@80024000 {
988				compatible = "fsl,imx28-dma-apbx";
989				reg = <0x80024000 0x2000>;
990				interrupts = <78 79 66 0
991					      80 81 68 69
992					      70 71 72 73
993					      74 75 76 77>;
994				interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
995						  "saif0", "saif1", "i2c0", "i2c1",
996						  "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
997						  "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
998				#dma-cells = <1>;
999				dma-channels = <16>;
1000				clocks = <&clks 26>;
1001			};
1002
1003			dcp: dcp@80028000 {
1004				compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
1005				reg = <0x80028000 0x2000>;
1006				interrupts = <52 53 54>;
1007				status = "okay";
1008			};
1009
1010			pxp: pxp@8002a000 {
1011				reg = <0x8002a000 0x2000>;
1012				interrupts = <39>;
1013				status = "disabled";
1014			};
1015
1016			ocotp: ocotp@8002c000 {
1017				compatible = "fsl,imx28-ocotp", "fsl,ocotp";
1018				#address-cells = <1>;
1019				#size-cells = <1>;
1020				reg = <0x8002c000 0x2000>;
1021				clocks = <&clks 25>;
1022			};
1023
1024			axi-ahb@8002e000 {
1025				reg = <0x8002e000 0x2000>;
1026				status = "disabled";
1027			};
1028
1029			lcdif: lcdif@80030000 {
1030				compatible = "fsl,imx28-lcdif";
1031				reg = <0x80030000 0x2000>;
1032				interrupts = <38>;
1033				clocks = <&clks 55>;
1034				dmas = <&dma_apbh 13>;
1035				dma-names = "rx";
1036				status = "disabled";
1037			};
1038
1039			can0: can@80032000 {
1040				compatible = "fsl,imx28-flexcan";
1041				reg = <0x80032000 0x2000>;
1042				interrupts = <8>;
1043				clocks = <&clks 58>, <&clks 58>;
1044				clock-names = "ipg", "per";
1045				status = "disabled";
1046			};
1047
1048			can1: can@80034000 {
1049				compatible = "fsl,imx28-flexcan";
1050				reg = <0x80034000 0x2000>;
1051				interrupts = <9>;
1052				clocks = <&clks 59>, <&clks 59>;
1053				clock-names = "ipg", "per";
1054				status = "disabled";
1055			};
1056
1057			simdbg: simdbg@8003c000 {
1058				reg = <0x8003c000 0x200>;
1059				status = "disabled";
1060			};
1061
1062			simgpmisel: simgpmisel@8003c200 {
1063				reg = <0x8003c200 0x100>;
1064				status = "disabled";
1065			};
1066
1067			simsspsel: simsspsel@8003c300 {
1068				reg = <0x8003c300 0x100>;
1069				status = "disabled";
1070			};
1071
1072			simmemsel: simmemsel@8003c400 {
1073				reg = <0x8003c400 0x100>;
1074				status = "disabled";
1075			};
1076
1077			gpiomon: gpiomon@8003c500 {
1078				reg = <0x8003c500 0x100>;
1079				status = "disabled";
1080			};
1081
1082			simenet: simenet@8003c700 {
1083				reg = <0x8003c700 0x100>;
1084				status = "disabled";
1085			};
1086
1087			armjtag: armjtag@8003c800 {
1088				reg = <0x8003c800 0x100>;
1089				status = "disabled";
1090			};
1091		};
1092
1093		apbx@80040000 {
1094			compatible = "simple-bus";
1095			#address-cells = <1>;
1096			#size-cells = <1>;
1097			reg = <0x80040000 0x40000>;
1098			ranges;
1099
1100			clks: clkctrl@80040000 {
1101				compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
1102				reg = <0x80040000 0x2000>;
1103				#clock-cells = <1>;
1104			};
1105
1106			saif0: saif@80042000 {
1107				#sound-dai-cells = <0>;
1108				compatible = "fsl,imx28-saif";
1109				reg = <0x80042000 0x2000>;
1110				interrupts = <59>;
1111				#clock-cells = <0>;
1112				clocks = <&clks 53>;
1113				dmas = <&dma_apbx 4>;
1114				dma-names = "rx-tx";
1115				status = "disabled";
1116			};
1117
1118			power: power@80044000 {
1119				reg = <0x80044000 0x2000>;
1120				status = "disabled";
1121			};
1122
1123			saif1: saif@80046000 {
1124				#sound-dai-cells = <0>;
1125				compatible = "fsl,imx28-saif";
1126				reg = <0x80046000 0x2000>;
1127				interrupts = <58>;
1128				clocks = <&clks 54>;
1129				dmas = <&dma_apbx 5>;
1130				dma-names = "rx-tx";
1131				status = "disabled";
1132			};
1133
1134			lradc: lradc@80050000 {
1135				compatible = "fsl,imx28-lradc";
1136				reg = <0x80050000 0x2000>;
1137				interrupts = <10 14 15 16 17 18 19
1138						20 21 22 23 24 25>;
1139				status = "disabled";
1140				clocks = <&clks 41>;
1141				#io-channel-cells = <1>;
1142			};
1143
1144			spdif: spdif@80054000 {
1145				reg = <0x80054000 0x2000>;
1146				interrupts = <45>;
1147				dmas = <&dma_apbx 2>;
1148				dma-names = "tx";
1149				status = "disabled";
1150			};
1151
1152			mxs_rtc: rtc@80056000 {
1153				compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
1154				reg = <0x80056000 0x2000>;
1155				interrupts = <29>;
1156			};
1157
1158			i2c0: i2c@80058000 {
1159				#address-cells = <1>;
1160				#size-cells = <0>;
1161				compatible = "fsl,imx28-i2c";
1162				reg = <0x80058000 0x2000>;
1163				interrupts = <111>;
1164				clock-frequency = <100000>;
1165				dmas = <&dma_apbx 6>;
1166				dma-names = "rx-tx";
1167				status = "disabled";
1168			};
1169
1170			i2c1: i2c@8005a000 {
1171				#address-cells = <1>;
1172				#size-cells = <0>;
1173				compatible = "fsl,imx28-i2c";
1174				reg = <0x8005a000 0x2000>;
1175				interrupts = <110>;
1176				clock-frequency = <100000>;
1177				dmas = <&dma_apbx 7>;
1178				dma-names = "rx-tx";
1179				status = "disabled";
1180			};
1181
1182			pwm: pwm@80064000 {
1183				compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
1184				reg = <0x80064000 0x2000>;
1185				clocks = <&clks 44>;
1186				#pwm-cells = <2>;
1187				fsl,pwm-number = <8>;
1188				status = "disabled";
1189			};
1190
1191			timer: timrot@80068000 {
1192				compatible = "fsl,imx28-timrot", "fsl,timrot";
1193				reg = <0x80068000 0x2000>;
1194				interrupts = <48 49 50 51>;
1195				clocks = <&clks 26>;
1196			};
1197
1198			auart0: serial@8006a000 {
1199				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1200				reg = <0x8006a000 0x2000>;
1201				interrupts = <112>;
1202				dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1203				dma-names = "rx", "tx";
1204				clocks = <&clks 45>;
1205				status = "disabled";
1206			};
1207
1208			auart1: serial@8006c000 {
1209				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1210				reg = <0x8006c000 0x2000>;
1211				interrupts = <113>;
1212				dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1213				dma-names = "rx", "tx";
1214				clocks = <&clks 45>;
1215				status = "disabled";
1216			};
1217
1218			auart2: serial@8006e000 {
1219				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1220				reg = <0x8006e000 0x2000>;
1221				interrupts = <114>;
1222				dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1223				dma-names = "rx", "tx";
1224				clocks = <&clks 45>;
1225				status = "disabled";
1226			};
1227
1228			auart3: serial@80070000 {
1229				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1230				reg = <0x80070000 0x2000>;
1231				interrupts = <115>;
1232				dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1233				dma-names = "rx", "tx";
1234				clocks = <&clks 45>;
1235				status = "disabled";
1236			};
1237
1238			auart4: serial@80072000 {
1239				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1240				reg = <0x80072000 0x2000>;
1241				interrupts = <116>;
1242				dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1243				dma-names = "rx", "tx";
1244				clocks = <&clks 45>;
1245				status = "disabled";
1246			};
1247
1248			duart: serial@80074000 {
1249				compatible = "arm,pl011", "arm,primecell";
1250				reg = <0x80074000 0x1000>;
1251				interrupts = <47>;
1252				clocks = <&clks 45>, <&clks 26>;
1253				clock-names = "uart", "apb_pclk";
1254				status = "disabled";
1255			};
1256
1257			usbphy0: usbphy@8007c000 {
1258				compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1259				reg = <0x8007c000 0x2000>;
1260				clocks = <&clks 62>;
1261				status = "disabled";
1262			};
1263
1264			usbphy1: usbphy@8007e000 {
1265				compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1266				reg = <0x8007e000 0x2000>;
1267				clocks = <&clks 63>;
1268				status = "disabled";
1269			};
1270		};
1271	};
1272
1273	ahb@80080000 {
1274		compatible = "simple-bus";
1275		#address-cells = <1>;
1276		#size-cells = <1>;
1277		reg = <0x80080000 0x80000>;
1278		ranges;
1279
1280		usb0: usb@80080000 {
1281			compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1282			reg = <0x80080000 0x10000>;
1283			interrupts = <93>;
1284			clocks = <&clks 60>;
1285			fsl,usbphy = <&usbphy0>;
1286			status = "disabled";
1287		};
1288
1289		usb1: usb@80090000 {
1290			compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1291			reg = <0x80090000 0x10000>;
1292			interrupts = <92>;
1293			clocks = <&clks 61>;
1294			fsl,usbphy = <&usbphy1>;
1295			dr_mode = "host";
1296			status = "disabled";
1297		};
1298
1299		dflpt: dflpt@800c0000 {
1300			reg = <0x800c0000 0x10000>;
1301			status = "disabled";
1302		};
1303
1304		mac0: ethernet@800f0000 {
1305			compatible = "fsl,imx28-fec";
1306			reg = <0x800f0000 0x4000>;
1307			interrupts = <101>;
1308			clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1309			clock-names = "ipg", "ahb", "enet_out";
1310			status = "disabled";
1311		};
1312
1313		mac1: ethernet@800f4000 {
1314			compatible = "fsl,imx28-fec";
1315			reg = <0x800f4000 0x4000>;
1316			interrupts = <102>;
1317			clocks = <&clks 57>, <&clks 57>;
1318			clock-names = "ipg", "ahb";
1319			status = "disabled";
1320		};
1321
1322		etn_switch: switch@800f8000 {
1323			reg = <0x800f8000 0x8000>;
1324			status = "disabled";
1325		};
1326	};
1327
1328	iio-hwmon {
1329		compatible = "iio-hwmon";
1330		io-channels = <&lradc 8>;
1331	};
1332};
1333