1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
4 *
5 * Description: CoreSight Program Flow Trace driver
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/moduleparam.h>
10 #include <linux/init.h>
11 #include <linux/types.h>
12 #include <linux/device.h>
13 #include <linux/io.h>
14 #include <linux/err.h>
15 #include <linux/fs.h>
16 #include <linux/slab.h>
17 #include <linux/delay.h>
18 #include <linux/smp.h>
19 #include <linux/sysfs.h>
20 #include <linux/stat.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/cpu.h>
23 #include <linux/of.h>
24 #include <linux/coresight.h>
25 #include <linux/coresight-pmu.h>
26 #include <linux/amba/bus.h>
27 #include <linux/seq_file.h>
28 #include <linux/uaccess.h>
29 #include <linux/clk.h>
30 #include <linux/perf_event.h>
31 #include <asm/sections.h>
32
33 #include "coresight-etm.h"
34 #include "coresight-etm-perf.h"
35
36 /*
37 * Not really modular but using module_param is the easiest way to
38 * remain consistent with existing use cases for now.
39 */
40 static int boot_enable;
41 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
42
43 /* The number of ETM/PTM currently registered */
44 static int etm_count;
45 static struct etm_drvdata *etmdrvdata[NR_CPUS];
46
47 static enum cpuhp_state hp_online;
48
49 /*
50 * Memory mapped writes to clear os lock are not supported on some processors
51 * and OS lock must be unlocked before any memory mapped access on such
52 * processors, otherwise memory mapped reads/writes will be invalid.
53 */
etm_os_unlock(struct etm_drvdata * drvdata)54 static void etm_os_unlock(struct etm_drvdata *drvdata)
55 {
56 /* Writing any value to ETMOSLAR unlocks the trace registers */
57 etm_writel(drvdata, 0x0, ETMOSLAR);
58 drvdata->os_unlock = true;
59 isb();
60 }
61
etm_set_pwrdwn(struct etm_drvdata * drvdata)62 static void etm_set_pwrdwn(struct etm_drvdata *drvdata)
63 {
64 u32 etmcr;
65
66 /* Ensure pending cp14 accesses complete before setting pwrdwn */
67 mb();
68 isb();
69 etmcr = etm_readl(drvdata, ETMCR);
70 etmcr |= ETMCR_PWD_DWN;
71 etm_writel(drvdata, etmcr, ETMCR);
72 }
73
etm_clr_pwrdwn(struct etm_drvdata * drvdata)74 static void etm_clr_pwrdwn(struct etm_drvdata *drvdata)
75 {
76 u32 etmcr;
77
78 etmcr = etm_readl(drvdata, ETMCR);
79 etmcr &= ~ETMCR_PWD_DWN;
80 etm_writel(drvdata, etmcr, ETMCR);
81 /* Ensure pwrup completes before subsequent cp14 accesses */
82 mb();
83 isb();
84 }
85
etm_set_pwrup(struct etm_drvdata * drvdata)86 static void etm_set_pwrup(struct etm_drvdata *drvdata)
87 {
88 u32 etmpdcr;
89
90 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
91 etmpdcr |= ETMPDCR_PWD_UP;
92 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
93 /* Ensure pwrup completes before subsequent cp14 accesses */
94 mb();
95 isb();
96 }
97
etm_clr_pwrup(struct etm_drvdata * drvdata)98 static void etm_clr_pwrup(struct etm_drvdata *drvdata)
99 {
100 u32 etmpdcr;
101
102 /* Ensure pending cp14 accesses complete before clearing pwrup */
103 mb();
104 isb();
105 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
106 etmpdcr &= ~ETMPDCR_PWD_UP;
107 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
108 }
109
110 /**
111 * coresight_timeout_etm - loop until a bit has changed to a specific state.
112 * @drvdata: etm's private data structure.
113 * @offset: address of a register, starting from @addr.
114 * @position: the position of the bit of interest.
115 * @value: the value the bit should have.
116 *
117 * Basically the same as @coresight_timeout except for the register access
118 * method where we have to account for CP14 configurations.
119
120 * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
121 * TIMEOUT_US has elapsed, which ever happens first.
122 */
123
coresight_timeout_etm(struct etm_drvdata * drvdata,u32 offset,int position,int value)124 static int coresight_timeout_etm(struct etm_drvdata *drvdata, u32 offset,
125 int position, int value)
126 {
127 int i;
128 u32 val;
129
130 for (i = TIMEOUT_US; i > 0; i--) {
131 val = etm_readl(drvdata, offset);
132 /* Waiting on the bit to go from 0 to 1 */
133 if (value) {
134 if (val & BIT(position))
135 return 0;
136 /* Waiting on the bit to go from 1 to 0 */
137 } else {
138 if (!(val & BIT(position)))
139 return 0;
140 }
141
142 /*
143 * Delay is arbitrary - the specification doesn't say how long
144 * we are expected to wait. Extra check required to make sure
145 * we don't wait needlessly on the last iteration.
146 */
147 if (i - 1)
148 udelay(1);
149 }
150
151 return -EAGAIN;
152 }
153
154
etm_set_prog(struct etm_drvdata * drvdata)155 static void etm_set_prog(struct etm_drvdata *drvdata)
156 {
157 u32 etmcr;
158
159 etmcr = etm_readl(drvdata, ETMCR);
160 etmcr |= ETMCR_ETM_PRG;
161 etm_writel(drvdata, etmcr, ETMCR);
162 /*
163 * Recommended by spec for cp14 accesses to ensure etmcr write is
164 * complete before polling etmsr
165 */
166 isb();
167 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 1)) {
168 dev_err(drvdata->dev,
169 "%s: timeout observed when probing at offset %#x\n",
170 __func__, ETMSR);
171 }
172 }
173
etm_clr_prog(struct etm_drvdata * drvdata)174 static void etm_clr_prog(struct etm_drvdata *drvdata)
175 {
176 u32 etmcr;
177
178 etmcr = etm_readl(drvdata, ETMCR);
179 etmcr &= ~ETMCR_ETM_PRG;
180 etm_writel(drvdata, etmcr, ETMCR);
181 /*
182 * Recommended by spec for cp14 accesses to ensure etmcr write is
183 * complete before polling etmsr
184 */
185 isb();
186 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 0)) {
187 dev_err(drvdata->dev,
188 "%s: timeout observed when probing at offset %#x\n",
189 __func__, ETMSR);
190 }
191 }
192
etm_set_default(struct etm_config * config)193 void etm_set_default(struct etm_config *config)
194 {
195 int i;
196
197 if (WARN_ON_ONCE(!config))
198 return;
199
200 /*
201 * Taken verbatim from the TRM:
202 *
203 * To trace all memory:
204 * set bit [24] in register 0x009, the ETMTECR1, to 1
205 * set all other bits in register 0x009, the ETMTECR1, to 0
206 * set all bits in register 0x007, the ETMTECR2, to 0
207 * set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
208 */
209 config->enable_ctrl1 = BIT(24);
210 config->enable_ctrl2 = 0x0;
211 config->enable_event = ETM_HARD_WIRE_RES_A;
212
213 config->trigger_event = ETM_DEFAULT_EVENT_VAL;
214 config->enable_event = ETM_HARD_WIRE_RES_A;
215
216 config->seq_12_event = ETM_DEFAULT_EVENT_VAL;
217 config->seq_21_event = ETM_DEFAULT_EVENT_VAL;
218 config->seq_23_event = ETM_DEFAULT_EVENT_VAL;
219 config->seq_31_event = ETM_DEFAULT_EVENT_VAL;
220 config->seq_32_event = ETM_DEFAULT_EVENT_VAL;
221 config->seq_13_event = ETM_DEFAULT_EVENT_VAL;
222 config->timestamp_event = ETM_DEFAULT_EVENT_VAL;
223
224 for (i = 0; i < ETM_MAX_CNTR; i++) {
225 config->cntr_rld_val[i] = 0x0;
226 config->cntr_event[i] = ETM_DEFAULT_EVENT_VAL;
227 config->cntr_rld_event[i] = ETM_DEFAULT_EVENT_VAL;
228 config->cntr_val[i] = 0x0;
229 }
230
231 config->seq_curr_state = 0x0;
232 config->ctxid_idx = 0x0;
233 for (i = 0; i < ETM_MAX_CTXID_CMP; i++)
234 config->ctxid_pid[i] = 0x0;
235
236 config->ctxid_mask = 0x0;
237 /* Setting default to 1024 as per TRM recommendation */
238 config->sync_freq = 0x400;
239 }
240
etm_config_trace_mode(struct etm_config * config)241 void etm_config_trace_mode(struct etm_config *config)
242 {
243 u32 flags, mode;
244
245 mode = config->mode;
246
247 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
248
249 /* excluding kernel AND user space doesn't make sense */
250 if (mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER))
251 return;
252
253 /* nothing to do if neither flags are set */
254 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
255 return;
256
257 flags = (1 << 0 | /* instruction execute */
258 3 << 3 | /* ARM instruction */
259 0 << 5 | /* No data value comparison */
260 0 << 7 | /* No exact mach */
261 0 << 8); /* Ignore context ID */
262
263 /* No need to worry about single address comparators. */
264 config->enable_ctrl2 = 0x0;
265
266 /* Bit 0 is address range comparator 1 */
267 config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
268
269 /*
270 * On ETMv3.5:
271 * ETMACTRn[13,11] == Non-secure state comparison control
272 * ETMACTRn[12,10] == Secure state comparison control
273 *
274 * b00 == Match in all modes in this state
275 * b01 == Do not match in any more in this state
276 * b10 == Match in all modes excepts user mode in this state
277 * b11 == Match only in user mode in this state
278 */
279
280 /* Tracing in secure mode is not supported at this time */
281 flags |= (0 << 12 | 1 << 10);
282
283 if (mode & ETM_MODE_EXCL_USER) {
284 /* exclude user, match all modes except user mode */
285 flags |= (1 << 13 | 0 << 11);
286 } else {
287 /* exclude kernel, match only in user mode */
288 flags |= (1 << 13 | 1 << 11);
289 }
290
291 /*
292 * The ETMEEVR register is already set to "hard wire A". As such
293 * all there is to do is setup an address comparator that spans
294 * the entire address range and configure the state and mode bits.
295 */
296 config->addr_val[0] = (u32) 0x0;
297 config->addr_val[1] = (u32) ~0x0;
298 config->addr_acctype[0] = flags;
299 config->addr_acctype[1] = flags;
300 config->addr_type[0] = ETM_ADDR_TYPE_RANGE;
301 config->addr_type[1] = ETM_ADDR_TYPE_RANGE;
302 }
303
304 #define ETM3X_SUPPORTED_OPTIONS (ETMCR_CYC_ACC | \
305 ETMCR_TIMESTAMP_EN | \
306 ETMCR_RETURN_STACK)
307
etm_parse_event_config(struct etm_drvdata * drvdata,struct perf_event * event)308 static int etm_parse_event_config(struct etm_drvdata *drvdata,
309 struct perf_event *event)
310 {
311 struct etm_config *config = &drvdata->config;
312 struct perf_event_attr *attr = &event->attr;
313
314 if (!attr)
315 return -EINVAL;
316
317 /* Clear configuration from previous run */
318 memset(config, 0, sizeof(struct etm_config));
319
320 if (attr->exclude_kernel)
321 config->mode = ETM_MODE_EXCL_KERN;
322
323 if (attr->exclude_user)
324 config->mode = ETM_MODE_EXCL_USER;
325
326 /* Always start from the default config */
327 etm_set_default(config);
328
329 /*
330 * By default the tracers are configured to trace the whole address
331 * range. Narrow the field only if requested by user space.
332 */
333 if (config->mode)
334 etm_config_trace_mode(config);
335
336 /*
337 * At this time only cycle accurate, return stack and timestamp
338 * options are available.
339 */
340 if (attr->config & ~ETM3X_SUPPORTED_OPTIONS)
341 return -EINVAL;
342
343 config->ctrl = attr->config;
344
345 /*
346 * Possible to have cores with PTM (supports ret stack) and ETM
347 * (never has ret stack) on the same SoC. So if we have a request
348 * for return stack that can't be honoured on this core then
349 * clear the bit - trace will still continue normally
350 */
351 if ((config->ctrl & ETMCR_RETURN_STACK) &&
352 !(drvdata->etmccer & ETMCCER_RETSTACK))
353 config->ctrl &= ~ETMCR_RETURN_STACK;
354
355 return 0;
356 }
357
etm_enable_hw(void * info)358 static void etm_enable_hw(void *info)
359 {
360 int i;
361 u32 etmcr;
362 struct etm_drvdata *drvdata = info;
363 struct etm_config *config = &drvdata->config;
364
365 CS_UNLOCK(drvdata->base);
366
367 /* Turn engine on */
368 etm_clr_pwrdwn(drvdata);
369 /* Apply power to trace registers */
370 etm_set_pwrup(drvdata);
371 /* Make sure all registers are accessible */
372 etm_os_unlock(drvdata);
373
374 etm_set_prog(drvdata);
375
376 etmcr = etm_readl(drvdata, ETMCR);
377 /* Clear setting from a previous run if need be */
378 etmcr &= ~ETM3X_SUPPORTED_OPTIONS;
379 etmcr |= drvdata->port_size;
380 etmcr |= ETMCR_ETM_EN;
381 etm_writel(drvdata, config->ctrl | etmcr, ETMCR);
382 etm_writel(drvdata, config->trigger_event, ETMTRIGGER);
383 etm_writel(drvdata, config->startstop_ctrl, ETMTSSCR);
384 etm_writel(drvdata, config->enable_event, ETMTEEVR);
385 etm_writel(drvdata, config->enable_ctrl1, ETMTECR1);
386 etm_writel(drvdata, config->fifofull_level, ETMFFLR);
387 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
388 etm_writel(drvdata, config->addr_val[i], ETMACVRn(i));
389 etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i));
390 }
391 for (i = 0; i < drvdata->nr_cntr; i++) {
392 etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i));
393 etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i));
394 etm_writel(drvdata, config->cntr_rld_event[i],
395 ETMCNTRLDEVRn(i));
396 etm_writel(drvdata, config->cntr_val[i], ETMCNTVRn(i));
397 }
398 etm_writel(drvdata, config->seq_12_event, ETMSQ12EVR);
399 etm_writel(drvdata, config->seq_21_event, ETMSQ21EVR);
400 etm_writel(drvdata, config->seq_23_event, ETMSQ23EVR);
401 etm_writel(drvdata, config->seq_31_event, ETMSQ31EVR);
402 etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR);
403 etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR);
404 etm_writel(drvdata, config->seq_curr_state, ETMSQR);
405 for (i = 0; i < drvdata->nr_ext_out; i++)
406 etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
407 for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
408 etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i));
409 etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR);
410 etm_writel(drvdata, config->sync_freq, ETMSYNCFR);
411 /* No external input selected */
412 etm_writel(drvdata, 0x0, ETMEXTINSELR);
413 etm_writel(drvdata, config->timestamp_event, ETMTSEVR);
414 /* No auxiliary control selected */
415 etm_writel(drvdata, 0x0, ETMAUXCR);
416 etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR);
417 /* No VMID comparator value selected */
418 etm_writel(drvdata, 0x0, ETMVMIDCVR);
419
420 etm_clr_prog(drvdata);
421 CS_LOCK(drvdata->base);
422
423 dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
424 }
425
etm_cpu_id(struct coresight_device * csdev)426 static int etm_cpu_id(struct coresight_device *csdev)
427 {
428 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
429
430 return drvdata->cpu;
431 }
432
etm_get_trace_id(struct etm_drvdata * drvdata)433 int etm_get_trace_id(struct etm_drvdata *drvdata)
434 {
435 unsigned long flags;
436 int trace_id = -1;
437
438 if (!drvdata)
439 goto out;
440
441 if (!local_read(&drvdata->mode))
442 return drvdata->traceid;
443
444 pm_runtime_get_sync(drvdata->dev);
445
446 spin_lock_irqsave(&drvdata->spinlock, flags);
447
448 CS_UNLOCK(drvdata->base);
449 trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
450 CS_LOCK(drvdata->base);
451
452 spin_unlock_irqrestore(&drvdata->spinlock, flags);
453 pm_runtime_put(drvdata->dev);
454
455 out:
456 return trace_id;
457
458 }
459
etm_trace_id(struct coresight_device * csdev)460 static int etm_trace_id(struct coresight_device *csdev)
461 {
462 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
463
464 return etm_get_trace_id(drvdata);
465 }
466
etm_enable_perf(struct coresight_device * csdev,struct perf_event * event)467 static int etm_enable_perf(struct coresight_device *csdev,
468 struct perf_event *event)
469 {
470 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
471
472 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
473 return -EINVAL;
474
475 /* Configure the tracer based on the session's specifics */
476 etm_parse_event_config(drvdata, event);
477 /* And enable it */
478 etm_enable_hw(drvdata);
479
480 return 0;
481 }
482
etm_enable_sysfs(struct coresight_device * csdev)483 static int etm_enable_sysfs(struct coresight_device *csdev)
484 {
485 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
486 int ret;
487
488 spin_lock(&drvdata->spinlock);
489
490 /*
491 * Configure the ETM only if the CPU is online. If it isn't online
492 * hw configuration will take place on the local CPU during bring up.
493 */
494 if (cpu_online(drvdata->cpu)) {
495 ret = smp_call_function_single(drvdata->cpu,
496 etm_enable_hw, drvdata, 1);
497 if (ret)
498 goto err;
499 }
500
501 drvdata->sticky_enable = true;
502 spin_unlock(&drvdata->spinlock);
503
504 dev_info(drvdata->dev, "ETM tracing enabled\n");
505 return 0;
506
507 err:
508 spin_unlock(&drvdata->spinlock);
509 return ret;
510 }
511
etm_enable(struct coresight_device * csdev,struct perf_event * event,u32 mode)512 static int etm_enable(struct coresight_device *csdev,
513 struct perf_event *event, u32 mode)
514 {
515 int ret;
516 u32 val;
517 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
518
519 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
520
521 /* Someone is already using the tracer */
522 if (val)
523 return -EBUSY;
524
525 switch (mode) {
526 case CS_MODE_SYSFS:
527 ret = etm_enable_sysfs(csdev);
528 break;
529 case CS_MODE_PERF:
530 ret = etm_enable_perf(csdev, event);
531 break;
532 default:
533 ret = -EINVAL;
534 }
535
536 /* The tracer didn't start */
537 if (ret)
538 local_set(&drvdata->mode, CS_MODE_DISABLED);
539
540 return ret;
541 }
542
etm_disable_hw(void * info)543 static void etm_disable_hw(void *info)
544 {
545 int i;
546 struct etm_drvdata *drvdata = info;
547 struct etm_config *config = &drvdata->config;
548
549 CS_UNLOCK(drvdata->base);
550 etm_set_prog(drvdata);
551
552 /* Read back sequencer and counters for post trace analysis */
553 config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
554
555 for (i = 0; i < drvdata->nr_cntr; i++)
556 config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
557
558 etm_set_pwrdwn(drvdata);
559 CS_LOCK(drvdata->base);
560
561 dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
562 }
563
etm_disable_perf(struct coresight_device * csdev)564 static void etm_disable_perf(struct coresight_device *csdev)
565 {
566 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
567
568 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
569 return;
570
571 CS_UNLOCK(drvdata->base);
572
573 /* Setting the prog bit disables tracing immediately */
574 etm_set_prog(drvdata);
575
576 /*
577 * There is no way to know when the tracer will be used again so
578 * power down the tracer.
579 */
580 etm_set_pwrdwn(drvdata);
581
582 CS_LOCK(drvdata->base);
583 }
584
etm_disable_sysfs(struct coresight_device * csdev)585 static void etm_disable_sysfs(struct coresight_device *csdev)
586 {
587 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
588
589 /*
590 * Taking hotplug lock here protects from clocks getting disabled
591 * with tracing being left on (crash scenario) if user disable occurs
592 * after cpu online mask indicates the cpu is offline but before the
593 * DYING hotplug callback is serviced by the ETM driver.
594 */
595 cpus_read_lock();
596 spin_lock(&drvdata->spinlock);
597
598 /*
599 * Executing etm_disable_hw on the cpu whose ETM is being disabled
600 * ensures that register writes occur when cpu is powered.
601 */
602 smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1);
603
604 spin_unlock(&drvdata->spinlock);
605 cpus_read_unlock();
606
607 dev_info(drvdata->dev, "ETM tracing disabled\n");
608 }
609
etm_disable(struct coresight_device * csdev,struct perf_event * event)610 static void etm_disable(struct coresight_device *csdev,
611 struct perf_event *event)
612 {
613 u32 mode;
614 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
615
616 /*
617 * For as long as the tracer isn't disabled another entity can't
618 * change its status. As such we can read the status here without
619 * fearing it will change under us.
620 */
621 mode = local_read(&drvdata->mode);
622
623 switch (mode) {
624 case CS_MODE_DISABLED:
625 break;
626 case CS_MODE_SYSFS:
627 etm_disable_sysfs(csdev);
628 break;
629 case CS_MODE_PERF:
630 etm_disable_perf(csdev);
631 break;
632 default:
633 WARN_ON_ONCE(mode);
634 return;
635 }
636
637 if (mode)
638 local_set(&drvdata->mode, CS_MODE_DISABLED);
639 }
640
641 static const struct coresight_ops_source etm_source_ops = {
642 .cpu_id = etm_cpu_id,
643 .trace_id = etm_trace_id,
644 .enable = etm_enable,
645 .disable = etm_disable,
646 };
647
648 static const struct coresight_ops etm_cs_ops = {
649 .source_ops = &etm_source_ops,
650 };
651
etm_online_cpu(unsigned int cpu)652 static int etm_online_cpu(unsigned int cpu)
653 {
654 if (!etmdrvdata[cpu])
655 return 0;
656
657 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
658 coresight_enable(etmdrvdata[cpu]->csdev);
659 return 0;
660 }
661
etm_starting_cpu(unsigned int cpu)662 static int etm_starting_cpu(unsigned int cpu)
663 {
664 if (!etmdrvdata[cpu])
665 return 0;
666
667 spin_lock(&etmdrvdata[cpu]->spinlock);
668 if (!etmdrvdata[cpu]->os_unlock) {
669 etm_os_unlock(etmdrvdata[cpu]);
670 etmdrvdata[cpu]->os_unlock = true;
671 }
672
673 if (local_read(&etmdrvdata[cpu]->mode))
674 etm_enable_hw(etmdrvdata[cpu]);
675 spin_unlock(&etmdrvdata[cpu]->spinlock);
676 return 0;
677 }
678
etm_dying_cpu(unsigned int cpu)679 static int etm_dying_cpu(unsigned int cpu)
680 {
681 if (!etmdrvdata[cpu])
682 return 0;
683
684 spin_lock(&etmdrvdata[cpu]->spinlock);
685 if (local_read(&etmdrvdata[cpu]->mode))
686 etm_disable_hw(etmdrvdata[cpu]);
687 spin_unlock(&etmdrvdata[cpu]->spinlock);
688 return 0;
689 }
690
etm_arch_supported(u8 arch)691 static bool etm_arch_supported(u8 arch)
692 {
693 switch (arch) {
694 case ETM_ARCH_V3_3:
695 break;
696 case ETM_ARCH_V3_5:
697 break;
698 case PFT_ARCH_V1_0:
699 break;
700 case PFT_ARCH_V1_1:
701 break;
702 default:
703 return false;
704 }
705 return true;
706 }
707
etm_init_arch_data(void * info)708 static void etm_init_arch_data(void *info)
709 {
710 u32 etmidr;
711 u32 etmccr;
712 struct etm_drvdata *drvdata = info;
713
714 /* Make sure all registers are accessible */
715 etm_os_unlock(drvdata);
716
717 CS_UNLOCK(drvdata->base);
718
719 /* First dummy read */
720 (void)etm_readl(drvdata, ETMPDSR);
721 /* Provide power to ETM: ETMPDCR[3] == 1 */
722 etm_set_pwrup(drvdata);
723 /*
724 * Clear power down bit since when this bit is set writes to
725 * certain registers might be ignored.
726 */
727 etm_clr_pwrdwn(drvdata);
728 /*
729 * Set prog bit. It will be set from reset but this is included to
730 * ensure it is set
731 */
732 etm_set_prog(drvdata);
733
734 /* Find all capabilities */
735 etmidr = etm_readl(drvdata, ETMIDR);
736 drvdata->arch = BMVAL(etmidr, 4, 11);
737 drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
738
739 drvdata->etmccer = etm_readl(drvdata, ETMCCER);
740 etmccr = etm_readl(drvdata, ETMCCR);
741 drvdata->etmccr = etmccr;
742 drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
743 drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
744 drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
745 drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
746 drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
747
748 etm_set_pwrdwn(drvdata);
749 etm_clr_pwrup(drvdata);
750 CS_LOCK(drvdata->base);
751 }
752
etm_init_trace_id(struct etm_drvdata * drvdata)753 static void etm_init_trace_id(struct etm_drvdata *drvdata)
754 {
755 drvdata->traceid = coresight_get_trace_id(drvdata->cpu);
756 }
757
etm_probe(struct amba_device * adev,const struct amba_id * id)758 static int etm_probe(struct amba_device *adev, const struct amba_id *id)
759 {
760 int ret;
761 void __iomem *base;
762 struct device *dev = &adev->dev;
763 struct coresight_platform_data *pdata = NULL;
764 struct etm_drvdata *drvdata;
765 struct resource *res = &adev->res;
766 struct coresight_desc desc = { 0 };
767 struct device_node *np = adev->dev.of_node;
768
769 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
770 if (!drvdata)
771 return -ENOMEM;
772
773 if (np) {
774 pdata = of_get_coresight_platform_data(dev, np);
775 if (IS_ERR(pdata))
776 return PTR_ERR(pdata);
777
778 adev->dev.platform_data = pdata;
779 drvdata->use_cp14 = of_property_read_bool(np, "arm,cp14");
780 }
781
782 drvdata->dev = &adev->dev;
783 dev_set_drvdata(dev, drvdata);
784
785 /* Validity for the resource is already checked by the AMBA core */
786 base = devm_ioremap_resource(dev, res);
787 if (IS_ERR(base))
788 return PTR_ERR(base);
789
790 drvdata->base = base;
791
792 spin_lock_init(&drvdata->spinlock);
793
794 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
795 if (!IS_ERR(drvdata->atclk)) {
796 ret = clk_prepare_enable(drvdata->atclk);
797 if (ret)
798 return ret;
799 }
800
801 drvdata->cpu = pdata ? pdata->cpu : 0;
802
803 cpus_read_lock();
804 etmdrvdata[drvdata->cpu] = drvdata;
805
806 if (smp_call_function_single(drvdata->cpu,
807 etm_init_arch_data, drvdata, 1))
808 dev_err(dev, "ETM arch init failed\n");
809
810 if (!etm_count++) {
811 cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING,
812 "arm/coresight:starting",
813 etm_starting_cpu, etm_dying_cpu);
814 ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN,
815 "arm/coresight:online",
816 etm_online_cpu, NULL);
817 if (ret < 0)
818 goto err_arch_supported;
819 hp_online = ret;
820 }
821 cpus_read_unlock();
822
823 if (etm_arch_supported(drvdata->arch) == false) {
824 ret = -EINVAL;
825 goto err_arch_supported;
826 }
827
828 etm_init_trace_id(drvdata);
829 etm_set_default(&drvdata->config);
830
831 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
832 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
833 desc.ops = &etm_cs_ops;
834 desc.pdata = pdata;
835 desc.dev = dev;
836 desc.groups = coresight_etm_groups;
837 drvdata->csdev = coresight_register(&desc);
838 if (IS_ERR(drvdata->csdev)) {
839 ret = PTR_ERR(drvdata->csdev);
840 goto err_arch_supported;
841 }
842
843 ret = etm_perf_symlink(drvdata->csdev, true);
844 if (ret) {
845 coresight_unregister(drvdata->csdev);
846 goto err_arch_supported;
847 }
848
849 pm_runtime_put(&adev->dev);
850 dev_info(dev, "%s initialized\n", (char *)id->data);
851 if (boot_enable) {
852 coresight_enable(drvdata->csdev);
853 drvdata->boot_enable = true;
854 }
855
856 return 0;
857
858 err_arch_supported:
859 if (--etm_count == 0) {
860 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
861 if (hp_online)
862 cpuhp_remove_state_nocalls(hp_online);
863 }
864 return ret;
865 }
866
867 #ifdef CONFIG_PM
etm_runtime_suspend(struct device * dev)868 static int etm_runtime_suspend(struct device *dev)
869 {
870 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
871
872 if (drvdata && !IS_ERR(drvdata->atclk))
873 clk_disable_unprepare(drvdata->atclk);
874
875 return 0;
876 }
877
etm_runtime_resume(struct device * dev)878 static int etm_runtime_resume(struct device *dev)
879 {
880 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
881
882 if (drvdata && !IS_ERR(drvdata->atclk))
883 clk_prepare_enable(drvdata->atclk);
884
885 return 0;
886 }
887 #endif
888
889 static const struct dev_pm_ops etm_dev_pm_ops = {
890 SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL)
891 };
892
893 static const struct amba_id etm_ids[] = {
894 { /* ETM 3.3 */
895 .id = 0x000bb921,
896 .mask = 0x000fffff,
897 .data = "ETM 3.3",
898 },
899 { /* ETM 3.5 - Cortex-A5 */
900 .id = 0x000bb955,
901 .mask = 0x000fffff,
902 .data = "ETM 3.5",
903 },
904 { /* ETM 3.5 */
905 .id = 0x000bb956,
906 .mask = 0x000fffff,
907 .data = "ETM 3.5",
908 },
909 { /* PTM 1.0 */
910 .id = 0x000bb950,
911 .mask = 0x000fffff,
912 .data = "PTM 1.0",
913 },
914 { /* PTM 1.1 */
915 .id = 0x000bb95f,
916 .mask = 0x000fffff,
917 .data = "PTM 1.1",
918 },
919 { /* PTM 1.1 Qualcomm */
920 .id = 0x000b006f,
921 .mask = 0x000fffff,
922 .data = "PTM 1.1",
923 },
924 { 0, 0},
925 };
926
927 static struct amba_driver etm_driver = {
928 .drv = {
929 .name = "coresight-etm3x",
930 .owner = THIS_MODULE,
931 .pm = &etm_dev_pm_ops,
932 .suppress_bind_attrs = true,
933 },
934 .probe = etm_probe,
935 .id_table = etm_ids,
936 };
937 builtin_amba_driver(etm_driver);
938
