1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * This file is part of STM32 ADC driver
4 *
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
7 *
8 * Inspired from: fsl-imx25-tsadc
9 *
10 */
11
12 #include <linux/bitfield.h>
13 #include <linux/clk.h>
14 #include <linux/interrupt.h>
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/irqdesc.h>
17 #include <linux/irqdomain.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/slab.h>
25
26 #include "stm32-adc-core.h"
27
28 #define STM32_ADC_CORE_SLEEP_DELAY_MS 2000
29
30 /* SYSCFG registers */
31 #define STM32MP1_SYSCFG_PMCSETR 0x04
32 #define STM32MP1_SYSCFG_PMCCLRR 0x44
33
34 /* SYSCFG bit fields */
35 #define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9)
36
37 /* SYSCFG capability flags */
38 #define HAS_VBOOSTER BIT(0)
39 #define HAS_ANASWVDD BIT(1)
40
41 /**
42 * struct stm32_adc_common_regs - stm32 common registers
43 * @csr: common status register offset
44 * @ccr: common control register offset
45 * @eoc_msk: array of eoc (end of conversion flag) masks in csr for adc1..n
46 * @ovr_msk: array of ovr (overrun flag) masks in csr for adc1..n
47 * @ier: interrupt enable register offset for each adc
48 * @eocie_msk: end of conversion interrupt enable mask in @ier
49 */
50 struct stm32_adc_common_regs {
51 u32 csr;
52 u32 ccr;
53 u32 eoc_msk[STM32_ADC_MAX_ADCS];
54 u32 ovr_msk[STM32_ADC_MAX_ADCS];
55 u32 ier;
56 u32 eocie_msk;
57 };
58
59 struct stm32_adc_priv;
60
61 /**
62 * struct stm32_adc_priv_cfg - stm32 core compatible configuration data
63 * @regs: common registers for all instances
64 * @clk_sel: clock selection routine
65 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet)
66 * @ipid: adc identification number
67 * @has_syscfg: SYSCFG capability flags
68 * @num_irqs: number of interrupt lines
69 * @num_adcs: maximum number of ADC instances in the common registers
70 */
71 struct stm32_adc_priv_cfg {
72 const struct stm32_adc_common_regs *regs;
73 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
74 u32 max_clk_rate_hz;
75 u32 ipid;
76 unsigned int has_syscfg;
77 unsigned int num_irqs;
78 unsigned int num_adcs;
79 };
80
81 /**
82 * struct stm32_adc_priv - stm32 ADC core private data
83 * @irq: irq(s) for ADC block
84 * @nb_adc_max: actual maximum number of instance per ADC block
85 * @domain: irq domain reference
86 * @aclk: clock reference for the analog circuitry
87 * @bclk: bus clock common for all ADCs, depends on part used
88 * @max_clk_rate: desired maximum clock rate
89 * @booster: booster supply reference
90 * @vdd: vdd supply reference
91 * @vdda: vdda analog supply reference
92 * @vref: regulator reference
93 * @vdd_uv: vdd supply voltage (microvolts)
94 * @vdda_uv: vdda supply voltage (microvolts)
95 * @cfg: compatible configuration data
96 * @common: common data for all ADC instances
97 * @ccr_bak: backup CCR in low power mode
98 * @syscfg: reference to syscon, system control registers
99 */
100 struct stm32_adc_priv {
101 int irq[STM32_ADC_MAX_ADCS];
102 unsigned int nb_adc_max;
103 struct irq_domain *domain;
104 struct clk *aclk;
105 struct clk *bclk;
106 u32 max_clk_rate;
107 struct regulator *booster;
108 struct regulator *vdd;
109 struct regulator *vdda;
110 struct regulator *vref;
111 int vdd_uv;
112 int vdda_uv;
113 const struct stm32_adc_priv_cfg *cfg;
114 struct stm32_adc_common common;
115 u32 ccr_bak;
116 struct regmap *syscfg;
117 };
118
to_stm32_adc_priv(struct stm32_adc_common * com)119 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
120 {
121 return container_of(com, struct stm32_adc_priv, common);
122 }
123
124 /* STM32F4 ADC internal common clock prescaler division ratios */
125 static int stm32f4_pclk_div[] = {2, 4, 6, 8};
126
127 /**
128 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
129 * @pdev: platform device
130 * @priv: stm32 ADC core private data
131 * Select clock prescaler used for analog conversions, before using ADC.
132 */
stm32f4_adc_clk_sel(struct platform_device * pdev,struct stm32_adc_priv * priv)133 static int stm32f4_adc_clk_sel(struct platform_device *pdev,
134 struct stm32_adc_priv *priv)
135 {
136 unsigned long rate;
137 u32 val;
138 int i;
139
140 /* stm32f4 has one clk input for analog (mandatory), enforce it here */
141 if (!priv->aclk) {
142 dev_err(&pdev->dev, "No 'adc' clock found\n");
143 return -ENOENT;
144 }
145
146 rate = clk_get_rate(priv->aclk);
147 if (!rate) {
148 dev_err(&pdev->dev, "Invalid clock rate: 0\n");
149 return -EINVAL;
150 }
151
152 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
153 if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate)
154 break;
155 }
156 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
157 dev_err(&pdev->dev, "adc clk selection failed\n");
158 return -EINVAL;
159 }
160
161 priv->common.rate = rate / stm32f4_pclk_div[i];
162 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
163 val &= ~STM32F4_ADC_ADCPRE_MASK;
164 val |= i << STM32F4_ADC_ADCPRE_SHIFT;
165 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
166
167 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
168 priv->common.rate / 1000);
169
170 return 0;
171 }
172
173 /**
174 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
175 * @ckmode: ADC clock mode, Async or sync with prescaler.
176 * @presc: prescaler bitfield for async clock mode
177 * @div: prescaler division ratio
178 */
179 struct stm32h7_adc_ck_spec {
180 u32 ckmode;
181 u32 presc;
182 int div;
183 };
184
185 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
186 /* 00: CK_ADC[1..3]: Asynchronous clock modes */
187 { 0, 0, 1 },
188 { 0, 1, 2 },
189 { 0, 2, 4 },
190 { 0, 3, 6 },
191 { 0, 4, 8 },
192 { 0, 5, 10 },
193 { 0, 6, 12 },
194 { 0, 7, 16 },
195 { 0, 8, 32 },
196 { 0, 9, 64 },
197 { 0, 10, 128 },
198 { 0, 11, 256 },
199 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
200 { 1, 0, 1 },
201 { 2, 0, 2 },
202 { 3, 0, 4 },
203 };
204
stm32h7_adc_clk_sel(struct platform_device * pdev,struct stm32_adc_priv * priv)205 static int stm32h7_adc_clk_sel(struct platform_device *pdev,
206 struct stm32_adc_priv *priv)
207 {
208 u32 ckmode, presc, val;
209 unsigned long rate;
210 int i, div, duty;
211
212 /* stm32h7 bus clock is common for all ADC instances (mandatory) */
213 if (!priv->bclk) {
214 dev_err(&pdev->dev, "No 'bus' clock found\n");
215 return -ENOENT;
216 }
217
218 /*
219 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
220 * So, choice is to have bus clock mandatory and adc clock optional.
221 * If optional 'adc' clock has been found, then try to use it first.
222 */
223 if (priv->aclk) {
224 /*
225 * Asynchronous clock modes (e.g. ckmode == 0)
226 * From spec: PLL output musn't exceed max rate
227 */
228 rate = clk_get_rate(priv->aclk);
229 if (!rate) {
230 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
231 return -EINVAL;
232 }
233
234 /* If duty is an error, kindly use at least /2 divider */
235 duty = clk_get_scaled_duty_cycle(priv->aclk, 100);
236 if (duty < 0)
237 dev_warn(&pdev->dev, "adc clock duty: %d\n", duty);
238
239 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
240 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
241 presc = stm32h7_adc_ckmodes_spec[i].presc;
242 div = stm32h7_adc_ckmodes_spec[i].div;
243
244 if (ckmode)
245 continue;
246
247 /*
248 * For proper operation, clock duty cycle range is 49%
249 * to 51%. Apply at least /2 prescaler otherwise.
250 */
251 if (div == 1 && (duty < 49 || duty > 51))
252 continue;
253
254 if ((rate / div) <= priv->max_clk_rate)
255 goto out;
256 }
257 }
258
259 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
260 rate = clk_get_rate(priv->bclk);
261 if (!rate) {
262 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
263 return -EINVAL;
264 }
265
266 duty = clk_get_scaled_duty_cycle(priv->bclk, 100);
267 if (duty < 0)
268 dev_warn(&pdev->dev, "bus clock duty: %d\n", duty);
269
270 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
271 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
272 presc = stm32h7_adc_ckmodes_spec[i].presc;
273 div = stm32h7_adc_ckmodes_spec[i].div;
274
275 if (!ckmode)
276 continue;
277
278 if (div == 1 && (duty < 49 || duty > 51))
279 continue;
280
281 if ((rate / div) <= priv->max_clk_rate)
282 goto out;
283 }
284
285 dev_err(&pdev->dev, "adc clk selection failed\n");
286 return -EINVAL;
287
288 out:
289 /* rate used later by each ADC instance to control BOOST mode */
290 priv->common.rate = rate / div;
291
292 /* Set common clock mode and prescaler */
293 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
294 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
295 val |= ckmode << STM32H7_CKMODE_SHIFT;
296 val |= presc << STM32H7_PRESC_SHIFT;
297 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
298
299 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
300 ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
301
302 return 0;
303 }
304
305 /* STM32F4 common registers definitions */
306 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
307 .csr = STM32F4_ADC_CSR,
308 .ccr = STM32F4_ADC_CCR,
309 .eoc_msk = { STM32F4_EOC1, STM32F4_EOC2, STM32F4_EOC3},
310 .ovr_msk = { STM32F4_OVR1, STM32F4_OVR2, STM32F4_OVR3},
311 .ier = STM32F4_ADC_CR1,
312 .eocie_msk = STM32F4_EOCIE,
313 };
314
315 /* STM32H7 common registers definitions */
316 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
317 .csr = STM32H7_ADC_CSR,
318 .ccr = STM32H7_ADC_CCR,
319 .eoc_msk = { STM32H7_EOC_MST, STM32H7_EOC_SLV},
320 .ovr_msk = { STM32H7_OVR_MST, STM32H7_OVR_SLV},
321 .ier = STM32H7_ADC_IER,
322 .eocie_msk = STM32H7_EOCIE,
323 };
324
325 static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = {
326 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2,
327 };
328
stm32_adc_eoc_enabled(struct stm32_adc_priv * priv,unsigned int adc)329 static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv,
330 unsigned int adc)
331 {
332 u32 ier, offset = stm32_adc_offset[adc];
333
334 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier);
335
336 return ier & priv->cfg->regs->eocie_msk;
337 }
338
339 /* ADC common interrupt for all instances */
stm32_adc_irq_handler(struct irq_desc * desc)340 static void stm32_adc_irq_handler(struct irq_desc *desc)
341 {
342 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
343 struct irq_chip *chip = irq_desc_get_chip(desc);
344 int i;
345 u32 status;
346
347 chained_irq_enter(chip, desc);
348 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
349
350 /*
351 * End of conversion may be handled by using IRQ or DMA. There may be a
352 * race here when two conversions complete at the same time on several
353 * ADCs. EOC may be read 'set' for several ADCs, with:
354 * - an ADC configured to use DMA (EOC triggers the DMA request, and
355 * is then automatically cleared by DR read in hardware)
356 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must
357 * be called in this case)
358 * So both EOC status bit in CSR and EOCIE control bit must be checked
359 * before invoking the interrupt handler (e.g. call ISR only for
360 * IRQ-enabled ADCs).
361 */
362 for (i = 0; i < priv->nb_adc_max; i++) {
363 if ((status & priv->cfg->regs->eoc_msk[i] &&
364 stm32_adc_eoc_enabled(priv, i)) ||
365 (status & priv->cfg->regs->ovr_msk[i]))
366 generic_handle_domain_irq(priv->domain, i);
367 }
368
369 chained_irq_exit(chip, desc);
370 };
371
stm32_adc_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)372 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
373 irq_hw_number_t hwirq)
374 {
375 irq_set_chip_data(irq, d->host_data);
376 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
377
378 return 0;
379 }
380
stm32_adc_domain_unmap(struct irq_domain * d,unsigned int irq)381 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
382 {
383 irq_set_chip_and_handler(irq, NULL, NULL);
384 irq_set_chip_data(irq, NULL);
385 }
386
387 static const struct irq_domain_ops stm32_adc_domain_ops = {
388 .map = stm32_adc_domain_map,
389 .unmap = stm32_adc_domain_unmap,
390 .xlate = irq_domain_xlate_onecell,
391 };
392
stm32_adc_irq_probe(struct platform_device * pdev,struct stm32_adc_priv * priv)393 static int stm32_adc_irq_probe(struct platform_device *pdev,
394 struct stm32_adc_priv *priv)
395 {
396 struct device_node *np = pdev->dev.of_node;
397 unsigned int i;
398
399 /*
400 * Interrupt(s) must be provided, depending on the compatible:
401 * - stm32f4/h7 shares a common interrupt line.
402 * - stm32mp1, has one line per ADC
403 */
404 for (i = 0; i < priv->cfg->num_irqs; i++) {
405 priv->irq[i] = platform_get_irq(pdev, i);
406 if (priv->irq[i] < 0)
407 return priv->irq[i];
408 }
409
410 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
411 &stm32_adc_domain_ops,
412 priv);
413 if (!priv->domain) {
414 dev_err(&pdev->dev, "Failed to add irq domain\n");
415 return -ENOMEM;
416 }
417
418 for (i = 0; i < priv->cfg->num_irqs; i++) {
419 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler);
420 irq_set_handler_data(priv->irq[i], priv);
421 }
422
423 return 0;
424 }
425
stm32_adc_irq_remove(struct platform_device * pdev,struct stm32_adc_priv * priv)426 static void stm32_adc_irq_remove(struct platform_device *pdev,
427 struct stm32_adc_priv *priv)
428 {
429 int hwirq;
430 unsigned int i;
431
432 for (hwirq = 0; hwirq < priv->nb_adc_max; hwirq++)
433 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
434 irq_domain_remove(priv->domain);
435
436 for (i = 0; i < priv->cfg->num_irqs; i++)
437 irq_set_chained_handler(priv->irq[i], NULL);
438 }
439
stm32_adc_core_switches_supply_en(struct stm32_adc_priv * priv,struct device * dev)440 static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv,
441 struct device *dev)
442 {
443 int ret;
444
445 /*
446 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog
447 * switches (via PCSEL) which have reduced performances when their
448 * supply is below 2.7V (vdda by default):
449 * - Voltage booster can be used, to get full ADC performances
450 * (increases power consumption).
451 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only).
452 *
453 * Recommended settings for ANASWVDD and EN_BOOSTER:
454 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1)
455 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1
456 * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default)
457 */
458 if (priv->vdda_uv < 2700000) {
459 if (priv->syscfg && priv->vdd_uv > 2700000) {
460 ret = regulator_enable(priv->vdd);
461 if (ret < 0) {
462 dev_err(dev, "vdd enable failed %d\n", ret);
463 return ret;
464 }
465
466 ret = regmap_write(priv->syscfg,
467 STM32MP1_SYSCFG_PMCSETR,
468 STM32MP1_SYSCFG_ANASWVDD_MASK);
469 if (ret < 0) {
470 regulator_disable(priv->vdd);
471 dev_err(dev, "vdd select failed, %d\n", ret);
472 return ret;
473 }
474 dev_dbg(dev, "analog switches supplied by vdd\n");
475
476 return 0;
477 }
478
479 if (priv->booster) {
480 /*
481 * This is optional, as this is a trade-off between
482 * analog performance and power consumption.
483 */
484 ret = regulator_enable(priv->booster);
485 if (ret < 0) {
486 dev_err(dev, "booster enable failed %d\n", ret);
487 return ret;
488 }
489 dev_dbg(dev, "analog switches supplied by booster\n");
490
491 return 0;
492 }
493 }
494
495 /* Fallback using vdda (default), nothing to do */
496 dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n",
497 priv->vdda_uv);
498
499 return 0;
500 }
501
stm32_adc_core_switches_supply_dis(struct stm32_adc_priv * priv)502 static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv)
503 {
504 if (priv->vdda_uv < 2700000) {
505 if (priv->syscfg && priv->vdd_uv > 2700000) {
506 regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR,
507 STM32MP1_SYSCFG_ANASWVDD_MASK);
508 regulator_disable(priv->vdd);
509 return;
510 }
511 if (priv->booster)
512 regulator_disable(priv->booster);
513 }
514 }
515
stm32_adc_core_hw_start(struct device * dev)516 static int stm32_adc_core_hw_start(struct device *dev)
517 {
518 struct stm32_adc_common *common = dev_get_drvdata(dev);
519 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
520 int ret;
521
522 ret = regulator_enable(priv->vdda);
523 if (ret < 0) {
524 dev_err(dev, "vdda enable failed %d\n", ret);
525 return ret;
526 }
527
528 ret = regulator_get_voltage(priv->vdda);
529 if (ret < 0) {
530 dev_err(dev, "vdda get voltage failed, %d\n", ret);
531 goto err_vdda_disable;
532 }
533 priv->vdda_uv = ret;
534
535 ret = stm32_adc_core_switches_supply_en(priv, dev);
536 if (ret < 0)
537 goto err_vdda_disable;
538
539 ret = regulator_enable(priv->vref);
540 if (ret < 0) {
541 dev_err(dev, "vref enable failed\n");
542 goto err_switches_dis;
543 }
544
545 ret = clk_prepare_enable(priv->bclk);
546 if (ret < 0) {
547 dev_err(dev, "bus clk enable failed\n");
548 goto err_regulator_disable;
549 }
550
551 ret = clk_prepare_enable(priv->aclk);
552 if (ret < 0) {
553 dev_err(dev, "adc clk enable failed\n");
554 goto err_bclk_disable;
555 }
556
557 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr);
558
559 return 0;
560
561 err_bclk_disable:
562 clk_disable_unprepare(priv->bclk);
563 err_regulator_disable:
564 regulator_disable(priv->vref);
565 err_switches_dis:
566 stm32_adc_core_switches_supply_dis(priv);
567 err_vdda_disable:
568 regulator_disable(priv->vdda);
569
570 return ret;
571 }
572
stm32_adc_core_hw_stop(struct device * dev)573 static void stm32_adc_core_hw_stop(struct device *dev)
574 {
575 struct stm32_adc_common *common = dev_get_drvdata(dev);
576 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
577
578 /* Backup CCR that may be lost (depends on power state to achieve) */
579 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr);
580 clk_disable_unprepare(priv->aclk);
581 clk_disable_unprepare(priv->bclk);
582 regulator_disable(priv->vref);
583 stm32_adc_core_switches_supply_dis(priv);
584 regulator_disable(priv->vdda);
585 }
586
stm32_adc_core_switches_probe(struct device * dev,struct stm32_adc_priv * priv)587 static int stm32_adc_core_switches_probe(struct device *dev,
588 struct stm32_adc_priv *priv)
589 {
590 struct device_node *np = dev->of_node;
591 int ret;
592
593 /* Analog switches supply can be controlled by syscfg (optional) */
594 priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
595 if (IS_ERR(priv->syscfg)) {
596 ret = PTR_ERR(priv->syscfg);
597 if (ret != -ENODEV)
598 return dev_err_probe(dev, ret, "Can't probe syscfg\n");
599
600 priv->syscfg = NULL;
601 }
602
603 /* Booster can be used to supply analog switches (optional) */
604 if (priv->cfg->has_syscfg & HAS_VBOOSTER &&
605 of_property_read_bool(np, "booster-supply")) {
606 priv->booster = devm_regulator_get_optional(dev, "booster");
607 if (IS_ERR(priv->booster)) {
608 ret = PTR_ERR(priv->booster);
609 if (ret != -ENODEV)
610 return dev_err_probe(dev, ret, "can't get booster\n");
611
612 priv->booster = NULL;
613 }
614 }
615
616 /* Vdd can be used to supply analog switches (optional) */
617 if (priv->cfg->has_syscfg & HAS_ANASWVDD &&
618 of_property_read_bool(np, "vdd-supply")) {
619 priv->vdd = devm_regulator_get_optional(dev, "vdd");
620 if (IS_ERR(priv->vdd)) {
621 ret = PTR_ERR(priv->vdd);
622 if (ret != -ENODEV)
623 return dev_err_probe(dev, ret, "can't get vdd\n");
624
625 priv->vdd = NULL;
626 }
627 }
628
629 if (priv->vdd) {
630 ret = regulator_enable(priv->vdd);
631 if (ret < 0) {
632 dev_err(dev, "vdd enable failed %d\n", ret);
633 return ret;
634 }
635
636 ret = regulator_get_voltage(priv->vdd);
637 if (ret < 0) {
638 dev_err(dev, "vdd get voltage failed %d\n", ret);
639 regulator_disable(priv->vdd);
640 return ret;
641 }
642 priv->vdd_uv = ret;
643
644 regulator_disable(priv->vdd);
645 }
646
647 return 0;
648 }
649
stm32_adc_probe_identification(struct platform_device * pdev,struct stm32_adc_priv * priv)650 static int stm32_adc_probe_identification(struct platform_device *pdev,
651 struct stm32_adc_priv *priv)
652 {
653 struct device_node *np = pdev->dev.of_node;
654 struct device_node *child;
655 const char *compat;
656 int ret, count = 0;
657 u32 id, val;
658
659 if (!priv->cfg->ipid)
660 return 0;
661
662 id = FIELD_GET(STM32MP1_IPIDR_MASK,
663 readl_relaxed(priv->common.base + STM32MP1_ADC_IPDR));
664 if (id != priv->cfg->ipid) {
665 dev_err(&pdev->dev, "Unexpected IP version: 0x%x", id);
666 return -EINVAL;
667 }
668
669 for_each_child_of_node(np, child) {
670 ret = of_property_read_string(child, "compatible", &compat);
671 if (ret)
672 continue;
673 /* Count child nodes with stm32 adc compatible */
674 if (strstr(compat, "st,stm32") && strstr(compat, "adc"))
675 count++;
676 }
677
678 val = readl_relaxed(priv->common.base + STM32MP1_ADC_HWCFGR0);
679 priv->nb_adc_max = FIELD_GET(STM32MP1_ADCNUM_MASK, val);
680 if (count > priv->nb_adc_max) {
681 dev_err(&pdev->dev, "Unexpected child number: %d", count);
682 return -EINVAL;
683 }
684
685 val = readl_relaxed(priv->common.base + STM32MP1_ADC_VERR);
686 dev_dbg(&pdev->dev, "ADC version: %lu.%lu\n",
687 FIELD_GET(STM32MP1_MAJREV_MASK, val),
688 FIELD_GET(STM32MP1_MINREV_MASK, val));
689
690 return 0;
691 }
692
stm32_adc_probe(struct platform_device * pdev)693 static int stm32_adc_probe(struct platform_device *pdev)
694 {
695 struct stm32_adc_priv *priv;
696 struct device *dev = &pdev->dev;
697 struct device_node *np = pdev->dev.of_node;
698 struct resource *res;
699 u32 max_rate;
700 int ret;
701
702 if (!pdev->dev.of_node)
703 return -ENODEV;
704
705 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
706 if (!priv)
707 return -ENOMEM;
708 platform_set_drvdata(pdev, &priv->common);
709
710 priv->cfg = (const struct stm32_adc_priv_cfg *)
711 of_match_device(dev->driver->of_match_table, dev)->data;
712 priv->nb_adc_max = priv->cfg->num_adcs;
713 spin_lock_init(&priv->common.lock);
714
715 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
716 priv->common.base = devm_ioremap_resource(&pdev->dev, res);
717 if (IS_ERR(priv->common.base))
718 return PTR_ERR(priv->common.base);
719 priv->common.phys_base = res->start;
720
721 priv->vdda = devm_regulator_get(&pdev->dev, "vdda");
722 if (IS_ERR(priv->vdda))
723 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vdda),
724 "vdda get failed\n");
725
726 priv->vref = devm_regulator_get(&pdev->dev, "vref");
727 if (IS_ERR(priv->vref))
728 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref),
729 "vref get failed\n");
730
731 priv->aclk = devm_clk_get_optional(&pdev->dev, "adc");
732 if (IS_ERR(priv->aclk))
733 return dev_err_probe(&pdev->dev, PTR_ERR(priv->aclk),
734 "Can't get 'adc' clock\n");
735
736 priv->bclk = devm_clk_get_optional(&pdev->dev, "bus");
737 if (IS_ERR(priv->bclk))
738 return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk),
739 "Can't get 'bus' clock\n");
740
741 ret = stm32_adc_core_switches_probe(dev, priv);
742 if (ret)
743 return ret;
744
745 pm_runtime_get_noresume(dev);
746 pm_runtime_set_active(dev);
747 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS);
748 pm_runtime_use_autosuspend(dev);
749 pm_runtime_enable(dev);
750
751 ret = stm32_adc_core_hw_start(dev);
752 if (ret)
753 goto err_pm_stop;
754
755 ret = stm32_adc_probe_identification(pdev, priv);
756 if (ret < 0)
757 goto err_hw_stop;
758
759 ret = regulator_get_voltage(priv->vref);
760 if (ret < 0) {
761 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
762 goto err_hw_stop;
763 }
764 priv->common.vref_mv = ret / 1000;
765 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
766
767 ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz",
768 &max_rate);
769 if (!ret)
770 priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz);
771 else
772 priv->max_clk_rate = priv->cfg->max_clk_rate_hz;
773
774 ret = priv->cfg->clk_sel(pdev, priv);
775 if (ret < 0)
776 goto err_hw_stop;
777
778 ret = stm32_adc_irq_probe(pdev, priv);
779 if (ret < 0)
780 goto err_hw_stop;
781
782 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
783 if (ret < 0) {
784 dev_err(&pdev->dev, "failed to populate DT children\n");
785 goto err_irq_remove;
786 }
787
788 pm_runtime_mark_last_busy(dev);
789 pm_runtime_put_autosuspend(dev);
790
791 return 0;
792
793 err_irq_remove:
794 stm32_adc_irq_remove(pdev, priv);
795 err_hw_stop:
796 stm32_adc_core_hw_stop(dev);
797 err_pm_stop:
798 pm_runtime_disable(dev);
799 pm_runtime_set_suspended(dev);
800 pm_runtime_put_noidle(dev);
801
802 return ret;
803 }
804
stm32_adc_remove(struct platform_device * pdev)805 static int stm32_adc_remove(struct platform_device *pdev)
806 {
807 struct stm32_adc_common *common = platform_get_drvdata(pdev);
808 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
809
810 pm_runtime_get_sync(&pdev->dev);
811 of_platform_depopulate(&pdev->dev);
812 stm32_adc_irq_remove(pdev, priv);
813 stm32_adc_core_hw_stop(&pdev->dev);
814 pm_runtime_disable(&pdev->dev);
815 pm_runtime_set_suspended(&pdev->dev);
816 pm_runtime_put_noidle(&pdev->dev);
817
818 return 0;
819 }
820
stm32_adc_core_runtime_suspend(struct device * dev)821 static int stm32_adc_core_runtime_suspend(struct device *dev)
822 {
823 stm32_adc_core_hw_stop(dev);
824
825 return 0;
826 }
827
stm32_adc_core_runtime_resume(struct device * dev)828 static int stm32_adc_core_runtime_resume(struct device *dev)
829 {
830 return stm32_adc_core_hw_start(dev);
831 }
832
stm32_adc_core_runtime_idle(struct device * dev)833 static int stm32_adc_core_runtime_idle(struct device *dev)
834 {
835 pm_runtime_mark_last_busy(dev);
836
837 return 0;
838 }
839
840 static DEFINE_RUNTIME_DEV_PM_OPS(stm32_adc_core_pm_ops,
841 stm32_adc_core_runtime_suspend,
842 stm32_adc_core_runtime_resume,
843 stm32_adc_core_runtime_idle);
844
845 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
846 .regs = &stm32f4_adc_common_regs,
847 .clk_sel = stm32f4_adc_clk_sel,
848 .max_clk_rate_hz = 36000000,
849 .num_irqs = 1,
850 .num_adcs = 3,
851 };
852
853 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
854 .regs = &stm32h7_adc_common_regs,
855 .clk_sel = stm32h7_adc_clk_sel,
856 .max_clk_rate_hz = 36000000,
857 .has_syscfg = HAS_VBOOSTER,
858 .num_irqs = 1,
859 .num_adcs = 2,
860 };
861
862 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
863 .regs = &stm32h7_adc_common_regs,
864 .clk_sel = stm32h7_adc_clk_sel,
865 .max_clk_rate_hz = 36000000,
866 .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD,
867 .ipid = STM32MP15_IPIDR_NUMBER,
868 .num_irqs = 2,
869 };
870
871 static const struct of_device_id stm32_adc_of_match[] = {
872 {
873 .compatible = "st,stm32f4-adc-core",
874 .data = (void *)&stm32f4_adc_priv_cfg
875 }, {
876 .compatible = "st,stm32h7-adc-core",
877 .data = (void *)&stm32h7_adc_priv_cfg
878 }, {
879 .compatible = "st,stm32mp1-adc-core",
880 .data = (void *)&stm32mp1_adc_priv_cfg
881 }, {
882 },
883 };
884 MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
885
886 static struct platform_driver stm32_adc_driver = {
887 .probe = stm32_adc_probe,
888 .remove = stm32_adc_remove,
889 .driver = {
890 .name = "stm32-adc-core",
891 .of_match_table = stm32_adc_of_match,
892 .pm = pm_ptr(&stm32_adc_core_pm_ops),
893 },
894 };
895 module_platform_driver(stm32_adc_driver);
896
897 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
898 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
899 MODULE_LICENSE("GPL v2");
900 MODULE_ALIAS("platform:stm32-adc-core");
901
