1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * This file is part of STM32 ADC driver
4 *
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
7 *
8 * Inspired from: fsl-imx25-tsadc
9 *
10 */
11
12 #include <linux/clk.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/irqdesc.h>
16 #include <linux/irqdomain.h>
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/slab.h>
21
22 #include "stm32-adc-core.h"
23
24 /* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
25 #define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
26 #define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04)
27
28 /* STM32F4_ADC_CSR - bit fields */
29 #define STM32F4_EOC3 BIT(17)
30 #define STM32F4_EOC2 BIT(9)
31 #define STM32F4_EOC1 BIT(1)
32
33 /* STM32F4_ADC_CCR - bit fields */
34 #define STM32F4_ADC_ADCPRE_SHIFT 16
35 #define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16)
36
37 /* STM32H7 - common registers for all ADC instances */
38 #define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
39 #define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08)
40
41 /* STM32H7_ADC_CSR - bit fields */
42 #define STM32H7_EOC_SLV BIT(18)
43 #define STM32H7_EOC_MST BIT(2)
44
45 /* STM32H7_ADC_CCR - bit fields */
46 #define STM32H7_PRESC_SHIFT 18
47 #define STM32H7_PRESC_MASK GENMASK(21, 18)
48 #define STM32H7_CKMODE_SHIFT 16
49 #define STM32H7_CKMODE_MASK GENMASK(17, 16)
50
51 /**
52 * stm32_adc_common_regs - stm32 common registers, compatible dependent data
53 * @csr: common status register offset
54 * @eoc1: adc1 end of conversion flag in @csr
55 * @eoc2: adc2 end of conversion flag in @csr
56 * @eoc3: adc3 end of conversion flag in @csr
57 */
58 struct stm32_adc_common_regs {
59 u32 csr;
60 u32 eoc1_msk;
61 u32 eoc2_msk;
62 u32 eoc3_msk;
63 };
64
65 struct stm32_adc_priv;
66
67 /**
68 * stm32_adc_priv_cfg - stm32 core compatible configuration data
69 * @regs: common registers for all instances
70 * @clk_sel: clock selection routine
71 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet)
72 */
73 struct stm32_adc_priv_cfg {
74 const struct stm32_adc_common_regs *regs;
75 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
76 u32 max_clk_rate_hz;
77 };
78
79 /**
80 * struct stm32_adc_priv - stm32 ADC core private data
81 * @irq: irq(s) for ADC block
82 * @domain: irq domain reference
83 * @aclk: clock reference for the analog circuitry
84 * @bclk: bus clock common for all ADCs, depends on part used
85 * @vref: regulator reference
86 * @cfg: compatible configuration data
87 * @common: common data for all ADC instances
88 */
89 struct stm32_adc_priv {
90 int irq[STM32_ADC_MAX_ADCS];
91 struct irq_domain *domain;
92 struct clk *aclk;
93 struct clk *bclk;
94 struct regulator *vref;
95 const struct stm32_adc_priv_cfg *cfg;
96 struct stm32_adc_common common;
97 };
98
to_stm32_adc_priv(struct stm32_adc_common * com)99 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
100 {
101 return container_of(com, struct stm32_adc_priv, common);
102 }
103
104 /* STM32F4 ADC internal common clock prescaler division ratios */
105 static int stm32f4_pclk_div[] = {2, 4, 6, 8};
106
107 /**
108 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
109 * @priv: stm32 ADC core private data
110 * Select clock prescaler used for analog conversions, before using ADC.
111 */
stm32f4_adc_clk_sel(struct platform_device * pdev,struct stm32_adc_priv * priv)112 static int stm32f4_adc_clk_sel(struct platform_device *pdev,
113 struct stm32_adc_priv *priv)
114 {
115 unsigned long rate;
116 u32 val;
117 int i;
118
119 /* stm32f4 has one clk input for analog (mandatory), enforce it here */
120 if (!priv->aclk) {
121 dev_err(&pdev->dev, "No 'adc' clock found\n");
122 return -ENOENT;
123 }
124
125 rate = clk_get_rate(priv->aclk);
126 if (!rate) {
127 dev_err(&pdev->dev, "Invalid clock rate: 0\n");
128 return -EINVAL;
129 }
130
131 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
132 if ((rate / stm32f4_pclk_div[i]) <= priv->cfg->max_clk_rate_hz)
133 break;
134 }
135 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
136 dev_err(&pdev->dev, "adc clk selection failed\n");
137 return -EINVAL;
138 }
139
140 priv->common.rate = rate / stm32f4_pclk_div[i];
141 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
142 val &= ~STM32F4_ADC_ADCPRE_MASK;
143 val |= i << STM32F4_ADC_ADCPRE_SHIFT;
144 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
145
146 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
147 priv->common.rate / 1000);
148
149 return 0;
150 }
151
152 /**
153 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
154 * @ckmode: ADC clock mode, Async or sync with prescaler.
155 * @presc: prescaler bitfield for async clock mode
156 * @div: prescaler division ratio
157 */
158 struct stm32h7_adc_ck_spec {
159 u32 ckmode;
160 u32 presc;
161 int div;
162 };
163
164 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
165 /* 00: CK_ADC[1..3]: Asynchronous clock modes */
166 { 0, 0, 1 },
167 { 0, 1, 2 },
168 { 0, 2, 4 },
169 { 0, 3, 6 },
170 { 0, 4, 8 },
171 { 0, 5, 10 },
172 { 0, 6, 12 },
173 { 0, 7, 16 },
174 { 0, 8, 32 },
175 { 0, 9, 64 },
176 { 0, 10, 128 },
177 { 0, 11, 256 },
178 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
179 { 1, 0, 1 },
180 { 2, 0, 2 },
181 { 3, 0, 4 },
182 };
183
stm32h7_adc_clk_sel(struct platform_device * pdev,struct stm32_adc_priv * priv)184 static int stm32h7_adc_clk_sel(struct platform_device *pdev,
185 struct stm32_adc_priv *priv)
186 {
187 u32 ckmode, presc, val;
188 unsigned long rate;
189 int i, div;
190
191 /* stm32h7 bus clock is common for all ADC instances (mandatory) */
192 if (!priv->bclk) {
193 dev_err(&pdev->dev, "No 'bus' clock found\n");
194 return -ENOENT;
195 }
196
197 /*
198 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
199 * So, choice is to have bus clock mandatory and adc clock optional.
200 * If optional 'adc' clock has been found, then try to use it first.
201 */
202 if (priv->aclk) {
203 /*
204 * Asynchronous clock modes (e.g. ckmode == 0)
205 * From spec: PLL output musn't exceed max rate
206 */
207 rate = clk_get_rate(priv->aclk);
208 if (!rate) {
209 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
210 return -EINVAL;
211 }
212
213 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
214 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
215 presc = stm32h7_adc_ckmodes_spec[i].presc;
216 div = stm32h7_adc_ckmodes_spec[i].div;
217
218 if (ckmode)
219 continue;
220
221 if ((rate / div) <= priv->cfg->max_clk_rate_hz)
222 goto out;
223 }
224 }
225
226 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
227 rate = clk_get_rate(priv->bclk);
228 if (!rate) {
229 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
230 return -EINVAL;
231 }
232
233 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
234 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
235 presc = stm32h7_adc_ckmodes_spec[i].presc;
236 div = stm32h7_adc_ckmodes_spec[i].div;
237
238 if (!ckmode)
239 continue;
240
241 if ((rate / div) <= priv->cfg->max_clk_rate_hz)
242 goto out;
243 }
244
245 dev_err(&pdev->dev, "adc clk selection failed\n");
246 return -EINVAL;
247
248 out:
249 /* rate used later by each ADC instance to control BOOST mode */
250 priv->common.rate = rate / div;
251
252 /* Set common clock mode and prescaler */
253 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
254 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
255 val |= ckmode << STM32H7_CKMODE_SHIFT;
256 val |= presc << STM32H7_PRESC_SHIFT;
257 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
258
259 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
260 ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
261
262 return 0;
263 }
264
265 /* STM32F4 common registers definitions */
266 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
267 .csr = STM32F4_ADC_CSR,
268 .eoc1_msk = STM32F4_EOC1,
269 .eoc2_msk = STM32F4_EOC2,
270 .eoc3_msk = STM32F4_EOC3,
271 };
272
273 /* STM32H7 common registers definitions */
274 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
275 .csr = STM32H7_ADC_CSR,
276 .eoc1_msk = STM32H7_EOC_MST,
277 .eoc2_msk = STM32H7_EOC_SLV,
278 };
279
280 /* ADC common interrupt for all instances */
stm32_adc_irq_handler(struct irq_desc * desc)281 static void stm32_adc_irq_handler(struct irq_desc *desc)
282 {
283 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
284 struct irq_chip *chip = irq_desc_get_chip(desc);
285 u32 status;
286
287 chained_irq_enter(chip, desc);
288 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
289
290 if (status & priv->cfg->regs->eoc1_msk)
291 generic_handle_irq(irq_find_mapping(priv->domain, 0));
292
293 if (status & priv->cfg->regs->eoc2_msk)
294 generic_handle_irq(irq_find_mapping(priv->domain, 1));
295
296 if (status & priv->cfg->regs->eoc3_msk)
297 generic_handle_irq(irq_find_mapping(priv->domain, 2));
298
299 chained_irq_exit(chip, desc);
300 };
301
stm32_adc_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)302 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
303 irq_hw_number_t hwirq)
304 {
305 irq_set_chip_data(irq, d->host_data);
306 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
307
308 return 0;
309 }
310
stm32_adc_domain_unmap(struct irq_domain * d,unsigned int irq)311 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
312 {
313 irq_set_chip_and_handler(irq, NULL, NULL);
314 irq_set_chip_data(irq, NULL);
315 }
316
317 static const struct irq_domain_ops stm32_adc_domain_ops = {
318 .map = stm32_adc_domain_map,
319 .unmap = stm32_adc_domain_unmap,
320 .xlate = irq_domain_xlate_onecell,
321 };
322
stm32_adc_irq_probe(struct platform_device * pdev,struct stm32_adc_priv * priv)323 static int stm32_adc_irq_probe(struct platform_device *pdev,
324 struct stm32_adc_priv *priv)
325 {
326 struct device_node *np = pdev->dev.of_node;
327 unsigned int i;
328
329 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
330 priv->irq[i] = platform_get_irq(pdev, i);
331 if (priv->irq[i] < 0) {
332 /*
333 * At least one interrupt must be provided, make others
334 * optional:
335 * - stm32f4/h7 shares a common interrupt.
336 * - stm32mp1, has one line per ADC (either for ADC1,
337 * ADC2 or both).
338 */
339 if (i && priv->irq[i] == -ENXIO)
340 continue;
341 dev_err(&pdev->dev, "failed to get irq\n");
342
343 return priv->irq[i];
344 }
345 }
346
347 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
348 &stm32_adc_domain_ops,
349 priv);
350 if (!priv->domain) {
351 dev_err(&pdev->dev, "Failed to add irq domain\n");
352 return -ENOMEM;
353 }
354
355 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
356 if (priv->irq[i] < 0)
357 continue;
358 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler);
359 irq_set_handler_data(priv->irq[i], priv);
360 }
361
362 return 0;
363 }
364
stm32_adc_irq_remove(struct platform_device * pdev,struct stm32_adc_priv * priv)365 static void stm32_adc_irq_remove(struct platform_device *pdev,
366 struct stm32_adc_priv *priv)
367 {
368 int hwirq;
369 unsigned int i;
370
371 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
372 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
373 irq_domain_remove(priv->domain);
374
375 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
376 if (priv->irq[i] < 0)
377 continue;
378 irq_set_chained_handler(priv->irq[i], NULL);
379 }
380 }
381
stm32_adc_probe(struct platform_device * pdev)382 static int stm32_adc_probe(struct platform_device *pdev)
383 {
384 struct stm32_adc_priv *priv;
385 struct device *dev = &pdev->dev;
386 struct device_node *np = pdev->dev.of_node;
387 struct resource *res;
388 int ret;
389
390 if (!pdev->dev.of_node)
391 return -ENODEV;
392
393 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
394 if (!priv)
395 return -ENOMEM;
396
397 priv->cfg = (const struct stm32_adc_priv_cfg *)
398 of_match_device(dev->driver->of_match_table, dev)->data;
399
400 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
401 priv->common.base = devm_ioremap_resource(&pdev->dev, res);
402 if (IS_ERR(priv->common.base))
403 return PTR_ERR(priv->common.base);
404 priv->common.phys_base = res->start;
405
406 priv->vref = devm_regulator_get(&pdev->dev, "vref");
407 if (IS_ERR(priv->vref)) {
408 ret = PTR_ERR(priv->vref);
409 dev_err(&pdev->dev, "vref get failed, %d\n", ret);
410 return ret;
411 }
412
413 ret = regulator_enable(priv->vref);
414 if (ret < 0) {
415 dev_err(&pdev->dev, "vref enable failed\n");
416 return ret;
417 }
418
419 ret = regulator_get_voltage(priv->vref);
420 if (ret < 0) {
421 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
422 goto err_regulator_disable;
423 }
424 priv->common.vref_mv = ret / 1000;
425 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
426
427 priv->aclk = devm_clk_get(&pdev->dev, "adc");
428 if (IS_ERR(priv->aclk)) {
429 ret = PTR_ERR(priv->aclk);
430 if (ret == -ENOENT) {
431 priv->aclk = NULL;
432 } else {
433 dev_err(&pdev->dev, "Can't get 'adc' clock\n");
434 goto err_regulator_disable;
435 }
436 }
437
438 if (priv->aclk) {
439 ret = clk_prepare_enable(priv->aclk);
440 if (ret < 0) {
441 dev_err(&pdev->dev, "adc clk enable failed\n");
442 goto err_regulator_disable;
443 }
444 }
445
446 priv->bclk = devm_clk_get(&pdev->dev, "bus");
447 if (IS_ERR(priv->bclk)) {
448 ret = PTR_ERR(priv->bclk);
449 if (ret == -ENOENT) {
450 priv->bclk = NULL;
451 } else {
452 dev_err(&pdev->dev, "Can't get 'bus' clock\n");
453 goto err_aclk_disable;
454 }
455 }
456
457 if (priv->bclk) {
458 ret = clk_prepare_enable(priv->bclk);
459 if (ret < 0) {
460 dev_err(&pdev->dev, "adc clk enable failed\n");
461 goto err_aclk_disable;
462 }
463 }
464
465 ret = priv->cfg->clk_sel(pdev, priv);
466 if (ret < 0)
467 goto err_bclk_disable;
468
469 ret = stm32_adc_irq_probe(pdev, priv);
470 if (ret < 0)
471 goto err_bclk_disable;
472
473 platform_set_drvdata(pdev, &priv->common);
474
475 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
476 if (ret < 0) {
477 dev_err(&pdev->dev, "failed to populate DT children\n");
478 goto err_irq_remove;
479 }
480
481 return 0;
482
483 err_irq_remove:
484 stm32_adc_irq_remove(pdev, priv);
485
486 err_bclk_disable:
487 if (priv->bclk)
488 clk_disable_unprepare(priv->bclk);
489
490 err_aclk_disable:
491 if (priv->aclk)
492 clk_disable_unprepare(priv->aclk);
493
494 err_regulator_disable:
495 regulator_disable(priv->vref);
496
497 return ret;
498 }
499
stm32_adc_remove(struct platform_device * pdev)500 static int stm32_adc_remove(struct platform_device *pdev)
501 {
502 struct stm32_adc_common *common = platform_get_drvdata(pdev);
503 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
504
505 of_platform_depopulate(&pdev->dev);
506 stm32_adc_irq_remove(pdev, priv);
507 if (priv->bclk)
508 clk_disable_unprepare(priv->bclk);
509 if (priv->aclk)
510 clk_disable_unprepare(priv->aclk);
511 regulator_disable(priv->vref);
512
513 return 0;
514 }
515
516 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
517 .regs = &stm32f4_adc_common_regs,
518 .clk_sel = stm32f4_adc_clk_sel,
519 .max_clk_rate_hz = 36000000,
520 };
521
522 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
523 .regs = &stm32h7_adc_common_regs,
524 .clk_sel = stm32h7_adc_clk_sel,
525 .max_clk_rate_hz = 36000000,
526 };
527
528 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
529 .regs = &stm32h7_adc_common_regs,
530 .clk_sel = stm32h7_adc_clk_sel,
531 .max_clk_rate_hz = 40000000,
532 };
533
534 static const struct of_device_id stm32_adc_of_match[] = {
535 {
536 .compatible = "st,stm32f4-adc-core",
537 .data = (void *)&stm32f4_adc_priv_cfg
538 }, {
539 .compatible = "st,stm32h7-adc-core",
540 .data = (void *)&stm32h7_adc_priv_cfg
541 }, {
542 .compatible = "st,stm32mp1-adc-core",
543 .data = (void *)&stm32mp1_adc_priv_cfg
544 }, {
545 },
546 };
547 MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
548
549 static struct platform_driver stm32_adc_driver = {
550 .probe = stm32_adc_probe,
551 .remove = stm32_adc_remove,
552 .driver = {
553 .name = "stm32-adc-core",
554 .of_match_table = stm32_adc_of_match,
555 },
556 };
557 module_platform_driver(stm32_adc_driver);
558
559 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
560 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
561 MODULE_LICENSE("GPL v2");
562 MODULE_ALIAS("platform:stm32-adc-core");
563
