1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * UFS Host Controller driver for Exynos specific extensions
4 *
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
6 *
7 */
8
9 #ifndef _UFS_EXYNOS_H_
10 #define _UFS_EXYNOS_H_
11
12 /*
13 * UNIPRO registers
14 */
15 #define UNIPRO_DBG_FORCE_DME_CTRL_STATE 0x150
16
17 /*
18 * MIBs for PA debug registers
19 */
20 #define PA_DBG_CLK_PERIOD 0x9514
21 #define PA_DBG_TXPHY_CFGUPDT 0x9518
22 #define PA_DBG_RXPHY_CFGUPDT 0x9519
23 #define PA_DBG_MODE 0x9529
24 #define PA_DBG_SKIP_RESET_PHY 0x9539
25 #define PA_DBG_OV_TM 0x9540
26 #define PA_DBG_SKIP_LINE_RESET 0x9541
27 #define PA_DBG_LINE_RESET_REQ 0x9543
28 #define PA_DBG_OPTION_SUITE 0x9564
29 #define PA_DBG_OPTION_SUITE_DYN 0x9565
30
31 /*
32 * MIBs for Transport Layer debug registers
33 */
34 #define T_DBG_SKIP_INIT_HIBERN8_EXIT 0xc001
35
36 /*
37 * Exynos MPHY attributes
38 */
39 #define TX_LINERESET_N_VAL 0x0277
40 #define TX_LINERESET_N(v) (((v) >> 10) & 0xFF)
41 #define TX_LINERESET_P_VAL 0x027D
42 #define TX_LINERESET_P(v) (((v) >> 12) & 0xFF)
43 #define TX_OV_SLEEP_CNT_TIMER 0x028E
44 #define TX_OV_H8_ENTER_EN (1 << 7)
45 #define TX_OV_SLEEP_CNT(v) (((v) >> 5) & 0x7F)
46 #define TX_HIGH_Z_CNT_11_08 0x028C
47 #define TX_HIGH_Z_CNT_H(v) (((v) >> 8) & 0xF)
48 #define TX_HIGH_Z_CNT_07_00 0x028D
49 #define TX_HIGH_Z_CNT_L(v) ((v) & 0xFF)
50 #define TX_BASE_NVAL_07_00 0x0293
51 #define TX_BASE_NVAL_L(v) ((v) & 0xFF)
52 #define TX_BASE_NVAL_15_08 0x0294
53 #define TX_BASE_NVAL_H(v) (((v) >> 8) & 0xFF)
54 #define TX_GRAN_NVAL_07_00 0x0295
55 #define TX_GRAN_NVAL_L(v) ((v) & 0xFF)
56 #define TX_GRAN_NVAL_10_08 0x0296
57 #define TX_GRAN_NVAL_H(v) (((v) >> 8) & 0x3)
58
59 #define RX_FILLER_ENABLE 0x0316
60 #define RX_FILLER_EN (1 << 1)
61 #define RX_LINERESET_VAL 0x0317
62 #define RX_LINERESET(v) (((v) >> 12) & 0xFF)
63 #define RX_LCC_IGNORE 0x0318
64 #define RX_SYNC_MASK_LENGTH 0x0321
65 #define RX_HIBERN8_WAIT_VAL_BIT_20_16 0x0331
66 #define RX_HIBERN8_WAIT_VAL_BIT_15_08 0x0332
67 #define RX_HIBERN8_WAIT_VAL_BIT_07_00 0x0333
68 #define RX_OV_SLEEP_CNT_TIMER 0x0340
69 #define RX_OV_SLEEP_CNT(v) (((v) >> 6) & 0x1F)
70 #define RX_OV_STALL_CNT_TIMER 0x0341
71 #define RX_OV_STALL_CNT(v) (((v) >> 4) & 0xFF)
72 #define RX_BASE_NVAL_07_00 0x0355
73 #define RX_BASE_NVAL_L(v) ((v) & 0xFF)
74 #define RX_BASE_NVAL_15_08 0x0354
75 #define RX_BASE_NVAL_H(v) (((v) >> 8) & 0xFF)
76 #define RX_GRAN_NVAL_07_00 0x0353
77 #define RX_GRAN_NVAL_L(v) ((v) & 0xFF)
78 #define RX_GRAN_NVAL_10_08 0x0352
79 #define RX_GRAN_NVAL_H(v) (((v) >> 8) & 0x3)
80
81 #define CMN_PWM_CLK_CTRL 0x0402
82 #define PWM_CLK_CTRL_MASK 0x3
83
84 #define IATOVAL_NSEC 20000 /* unit: ns */
85 #define UNIPRO_PCLK_PERIOD(ufs) (NSEC_PER_SEC / ufs->pclk_rate)
86
87 struct exynos_ufs;
88
89 /* vendor specific pre-defined parameters */
90 #define SLOW 1
91 #define FAST 2
92
93 #define RX_ADV_FINE_GRAN_SUP_EN 0x1
94 #define RX_ADV_FINE_GRAN_STEP_VAL 0x3
95 #define RX_ADV_MIN_ACTV_TIME_CAP 0x9
96
97 #define PA_GRANULARITY_VAL 0x6
98 #define PA_TACTIVATE_VAL 0x3
99 #define PA_HIBERN8TIME_VAL 0x20
100
101 #define PCLK_AVAIL_MIN 70000000
102 #define PCLK_AVAIL_MAX 133000000
103
104 struct exynos_ufs_uic_attr {
105 /* TX Attributes */
106 unsigned int tx_trailingclks;
107 unsigned int tx_dif_p_nsec;
108 unsigned int tx_dif_n_nsec;
109 unsigned int tx_high_z_cnt_nsec;
110 unsigned int tx_base_unit_nsec;
111 unsigned int tx_gran_unit_nsec;
112 unsigned int tx_sleep_cnt;
113 unsigned int tx_min_activatetime;
114 /* RX Attributes */
115 unsigned int rx_filler_enable;
116 unsigned int rx_dif_p_nsec;
117 unsigned int rx_hibern8_wait_nsec;
118 unsigned int rx_base_unit_nsec;
119 unsigned int rx_gran_unit_nsec;
120 unsigned int rx_sleep_cnt;
121 unsigned int rx_stall_cnt;
122 unsigned int rx_hs_g1_sync_len_cap;
123 unsigned int rx_hs_g2_sync_len_cap;
124 unsigned int rx_hs_g3_sync_len_cap;
125 unsigned int rx_hs_g1_prep_sync_len_cap;
126 unsigned int rx_hs_g2_prep_sync_len_cap;
127 unsigned int rx_hs_g3_prep_sync_len_cap;
128 /* Common Attributes */
129 unsigned int cmn_pwm_clk_ctrl;
130 /* Internal Attributes */
131 unsigned int pa_dbg_option_suite;
132 /* Changeable Attributes */
133 unsigned int rx_adv_fine_gran_sup_en;
134 unsigned int rx_adv_fine_gran_step;
135 unsigned int rx_min_actv_time_cap;
136 unsigned int rx_hibern8_time_cap;
137 unsigned int rx_adv_min_actv_time_cap;
138 unsigned int rx_adv_hibern8_time_cap;
139 unsigned int pa_granularity;
140 unsigned int pa_tactivate;
141 unsigned int pa_hibern8time;
142 };
143
144 struct exynos_ufs_drv_data {
145 char *compatible;
146 struct exynos_ufs_uic_attr *uic_attr;
147 unsigned int quirks;
148 unsigned int opts;
149 /* SoC's specific operations */
150 int (*drv_init)(struct device *dev, struct exynos_ufs *ufs);
151 int (*pre_link)(struct exynos_ufs *ufs);
152 int (*post_link)(struct exynos_ufs *ufs);
153 int (*pre_pwr_change)(struct exynos_ufs *ufs,
154 struct ufs_pa_layer_attr *pwr);
155 int (*post_pwr_change)(struct exynos_ufs *ufs,
156 struct ufs_pa_layer_attr *pwr);
157 };
158
159 struct ufs_phy_time_cfg {
160 u32 tx_linereset_p;
161 u32 tx_linereset_n;
162 u32 tx_high_z_cnt;
163 u32 tx_base_n_val;
164 u32 tx_gran_n_val;
165 u32 tx_sleep_cnt;
166 u32 rx_linereset;
167 u32 rx_hibern8_wait;
168 u32 rx_base_n_val;
169 u32 rx_gran_n_val;
170 u32 rx_sleep_cnt;
171 u32 rx_stall_cnt;
172 };
173
174 struct exynos_ufs {
175 struct ufs_hba *hba;
176 struct phy *phy;
177 void __iomem *reg_hci;
178 void __iomem *reg_unipro;
179 void __iomem *reg_ufsp;
180 struct clk *clk_hci_core;
181 struct clk *clk_unipro_main;
182 struct clk *clk_apb;
183 u32 pclk_rate;
184 u32 pclk_div;
185 u32 pclk_avail_min;
186 u32 pclk_avail_max;
187 unsigned long mclk_rate;
188 int avail_ln_rx;
189 int avail_ln_tx;
190 int rx_sel_idx;
191 struct ufs_pa_layer_attr dev_req_params;
192 struct ufs_phy_time_cfg t_cfg;
193 ktime_t entry_hibern8_t;
194 struct exynos_ufs_drv_data *drv_data;
195
196 u32 opts;
197 #define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL BIT(0)
198 #define EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB BIT(1)
199 #define EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL BIT(2)
200 #define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX BIT(3)
201 #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4)
202 };
203
204 #define for_each_ufs_rx_lane(ufs, i) \
205 for (i = (ufs)->rx_sel_idx; \
206 i < (ufs)->rx_sel_idx + (ufs)->avail_ln_rx; i++)
207 #define for_each_ufs_tx_lane(ufs, i) \
208 for (i = 0; i < (ufs)->avail_ln_tx; i++)
209
210 #define EXYNOS_UFS_MMIO_FUNC(name) \
211 static inline void name##_writel(struct exynos_ufs *ufs, u32 val, u32 reg)\
212 { \
213 writel(val, ufs->reg_##name + reg); \
214 } \
215 \
216 static inline u32 name##_readl(struct exynos_ufs *ufs, u32 reg) \
217 { \
218 return readl(ufs->reg_##name + reg); \
219 }
220
221 EXYNOS_UFS_MMIO_FUNC(hci);
222 EXYNOS_UFS_MMIO_FUNC(unipro);
223 EXYNOS_UFS_MMIO_FUNC(ufsp);
224 #undef EXYNOS_UFS_MMIO_FUNC
225
226 long exynos_ufs_calc_time_cntr(struct exynos_ufs *, long);
227
exynos_ufs_enable_ov_tm(struct ufs_hba * hba)228 static inline void exynos_ufs_enable_ov_tm(struct ufs_hba *hba)
229 {
230 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), TRUE);
231 }
232
exynos_ufs_disable_ov_tm(struct ufs_hba * hba)233 static inline void exynos_ufs_disable_ov_tm(struct ufs_hba *hba)
234 {
235 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), FALSE);
236 }
237
exynos_ufs_enable_dbg_mode(struct ufs_hba * hba)238 static inline void exynos_ufs_enable_dbg_mode(struct ufs_hba *hba)
239 {
240 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), TRUE);
241 }
242
exynos_ufs_disable_dbg_mode(struct ufs_hba * hba)243 static inline void exynos_ufs_disable_dbg_mode(struct ufs_hba *hba)
244 {
245 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), FALSE);
246 }
247
248 #endif /* _UFS_EXYNOS_H_ */
249
