1 /***********************license start*************** 2 * Author: Cavium Inc. 3 * 4 * Contact: support@cavium.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2012 Cavium Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Inc. for more information 26 ***********************license end**************************************/ 27 28 #ifndef __CVMX_LMCX_DEFS_H__ 29 #define __CVMX_LMCX_DEFS_H__ 30 31 #define CVMX_LMCX_BIST_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F0ull) + ((block_id) & 1) * 0x60000000ull) 32 #define CVMX_LMCX_BIST_RESULT(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F8ull) + ((block_id) & 1) * 0x60000000ull) 33 #define CVMX_LMCX_CHAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000220ull) + ((block_id) & 3) * 0x1000000ull) 34 #define CVMX_LMCX_CHAR_MASK0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000228ull) + ((block_id) & 3) * 0x1000000ull) 35 #define CVMX_LMCX_CHAR_MASK1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000230ull) + ((block_id) & 3) * 0x1000000ull) 36 #define CVMX_LMCX_CHAR_MASK2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000238ull) + ((block_id) & 3) * 0x1000000ull) 37 #define CVMX_LMCX_CHAR_MASK3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000240ull) + ((block_id) & 3) * 0x1000000ull) 38 #define CVMX_LMCX_CHAR_MASK4(block_id) (CVMX_ADD_IO_SEG(0x0001180088000318ull) + ((block_id) & 3) * 0x1000000ull) 39 #define CVMX_LMCX_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000028ull) + ((block_id) & 1) * 0x60000000ull) 40 #define CVMX_LMCX_COMP_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B8ull) + ((block_id) & 3) * 0x1000000ull) 41 #define CVMX_LMCX_CONFIG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000188ull) + ((block_id) & 3) * 0x1000000ull) 42 #define CVMX_LMCX_CONTROL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000190ull) + ((block_id) & 3) * 0x1000000ull) 43 #define CVMX_LMCX_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000010ull) + ((block_id) & 1) * 0x60000000ull) 44 #define CVMX_LMCX_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000090ull) + ((block_id) & 1) * 0x60000000ull) 45 #define CVMX_LMCX_DCLK_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E0ull) + ((block_id) & 3) * 0x1000000ull) 46 #define CVMX_LMCX_DCLK_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000070ull) + ((block_id) & 1) * 0x60000000ull) 47 #define CVMX_LMCX_DCLK_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000068ull) + ((block_id) & 1) * 0x60000000ull) 48 #define CVMX_LMCX_DCLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B8ull) + ((block_id) & 1) * 0x60000000ull) 49 #define CVMX_LMCX_DDR2_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000018ull) + ((block_id) & 1) * 0x60000000ull) 50 #define CVMX_LMCX_DDR_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000258ull) + ((block_id) & 3) * 0x1000000ull) 51 #define CVMX_LMCX_DELAY_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000088ull) + ((block_id) & 1) * 0x60000000ull) 52 #define CVMX_LMCX_DIMMX_PARAMS(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000270ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8) 53 #define CVMX_LMCX_DIMM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000310ull) + ((block_id) & 3) * 0x1000000ull) 54 #define CVMX_LMCX_DLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000C0ull) + ((block_id) & 1) * 0x60000000ull) 55 #define CVMX_LMCX_DLL_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001C8ull) + ((block_id) & 3) * 0x1000000ull) 56 #define CVMX_LMCX_DLL_CTL3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000218ull) + ((block_id) & 3) * 0x1000000ull) CVMX_LMCX_DUAL_MEMCFG(unsigned long block_id)57 static inline uint64_t CVMX_LMCX_DUAL_MEMCFG(unsigned long block_id) 58 { 59 switch (cvmx_get_octeon_family()) { 60 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 61 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 62 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 63 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 64 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 65 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 66 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 67 return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull; 68 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 69 return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull; 70 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 71 return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x1000000ull; 72 } 73 return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull; 74 } 75 CVMX_LMCX_ECC_SYND(unsigned long block_id)76 static inline uint64_t CVMX_LMCX_ECC_SYND(unsigned long block_id) 77 { 78 switch (cvmx_get_octeon_family()) { 79 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 80 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 81 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 82 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 83 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 84 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 85 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 86 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 87 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 88 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 89 return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull; 90 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 91 return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull; 92 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 93 return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x1000000ull; 94 } 95 return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull; 96 } 97 CVMX_LMCX_FADR(unsigned long block_id)98 static inline uint64_t CVMX_LMCX_FADR(unsigned long block_id) 99 { 100 switch (cvmx_get_octeon_family()) { 101 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 102 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 103 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 104 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 105 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 106 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 107 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 108 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 109 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 110 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 111 return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull; 112 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 113 return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull; 114 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 115 return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x1000000ull; 116 } 117 return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull; 118 } 119 120 #define CVMX_LMCX_IFB_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D0ull) + ((block_id) & 3) * 0x1000000ull) 121 #define CVMX_LMCX_IFB_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000050ull) + ((block_id) & 1) * 0x60000000ull) 122 #define CVMX_LMCX_IFB_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000048ull) + ((block_id) & 1) * 0x60000000ull) 123 #define CVMX_LMCX_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F0ull) + ((block_id) & 3) * 0x1000000ull) 124 #define CVMX_LMCX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E8ull) + ((block_id) & 3) * 0x1000000ull) 125 #define CVMX_LMCX_MEM_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000000ull) + ((block_id) & 1) * 0x60000000ull) 126 #define CVMX_LMCX_MEM_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000008ull) + ((block_id) & 1) * 0x60000000ull) 127 #define CVMX_LMCX_MODEREG_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A8ull) + ((block_id) & 3) * 0x1000000ull) 128 #define CVMX_LMCX_MODEREG_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000260ull) + ((block_id) & 3) * 0x1000000ull) CVMX_LMCX_NXM(unsigned long block_id)129 static inline uint64_t CVMX_LMCX_NXM(unsigned long block_id) 130 { 131 switch (cvmx_get_octeon_family()) { 132 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 133 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 134 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 135 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 136 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 137 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 138 return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull; 139 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 140 return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull; 141 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 142 return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x1000000ull; 143 } 144 return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull; 145 } 146 147 #define CVMX_LMCX_OPS_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D8ull) + ((block_id) & 3) * 0x1000000ull) 148 #define CVMX_LMCX_OPS_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000060ull) + ((block_id) & 1) * 0x60000000ull) 149 #define CVMX_LMCX_OPS_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000058ull) + ((block_id) & 1) * 0x60000000ull) 150 #define CVMX_LMCX_PHY_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000210ull) + ((block_id) & 3) * 0x1000000ull) 151 #define CVMX_LMCX_PLL_BWCTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000040ull)) 152 #define CVMX_LMCX_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A8ull) + ((block_id) & 1) * 0x60000000ull) 153 #define CVMX_LMCX_PLL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B0ull) + ((block_id) & 1) * 0x60000000ull) 154 #define CVMX_LMCX_READ_LEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000140ull) + ((block_id) & 1) * 0x60000000ull) 155 #define CVMX_LMCX_READ_LEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000148ull) + ((block_id) & 1) * 0x60000000ull) 156 #define CVMX_LMCX_READ_LEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000100ull) + (((offset) & 3) + ((block_id) & 1) * 0xC000000ull) * 8) 157 #define CVMX_LMCX_RESET_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000180ull) + ((block_id) & 3) * 0x1000000ull) 158 #define CVMX_LMCX_RLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A0ull) + ((block_id) & 3) * 0x1000000ull) 159 #define CVMX_LMCX_RLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A8ull) + ((block_id) & 3) * 0x1000000ull) 160 #define CVMX_LMCX_RLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000280ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8) 161 #define CVMX_LMCX_RODT_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A0ull) + ((block_id) & 1) * 0x60000000ull) 162 #define CVMX_LMCX_RODT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000078ull) + ((block_id) & 1) * 0x60000000ull) 163 #define CVMX_LMCX_RODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x0001180088000268ull) + ((block_id) & 3) * 0x1000000ull) 164 #define CVMX_LMCX_SCRAMBLED_FADR(block_id) (CVMX_ADD_IO_SEG(0x0001180088000330ull)) 165 #define CVMX_LMCX_SCRAMBLE_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000320ull)) 166 #define CVMX_LMCX_SCRAMBLE_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000328ull)) 167 #define CVMX_LMCX_SLOT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F8ull) + ((block_id) & 3) * 0x1000000ull) 168 #define CVMX_LMCX_SLOT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000200ull) + ((block_id) & 3) * 0x1000000ull) 169 #define CVMX_LMCX_SLOT_CTL2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000208ull) + ((block_id) & 3) * 0x1000000ull) 170 #define CVMX_LMCX_TIMING_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000198ull) + ((block_id) & 3) * 0x1000000ull) 171 #define CVMX_LMCX_TIMING_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A0ull) + ((block_id) & 3) * 0x1000000ull) 172 #define CVMX_LMCX_TRO_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000248ull) + ((block_id) & 3) * 0x1000000ull) 173 #define CVMX_LMCX_TRO_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180088000250ull) + ((block_id) & 3) * 0x1000000ull) 174 #define CVMX_LMCX_WLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000300ull) + ((block_id) & 3) * 0x1000000ull) 175 #define CVMX_LMCX_WLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000308ull) + ((block_id) & 3) * 0x1000000ull) 176 #define CVMX_LMCX_WLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800880002B0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8) 177 #define CVMX_LMCX_WODT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000030ull) + ((block_id) & 1) * 0x60000000ull) 178 #define CVMX_LMCX_WODT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000080ull) + ((block_id) & 1) * 0x60000000ull) 179 #define CVMX_LMCX_WODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B0ull) + ((block_id) & 3) * 0x1000000ull) 180 181 union cvmx_lmcx_bist_ctl { 182 uint64_t u64; 183 struct cvmx_lmcx_bist_ctl_s { 184 #ifdef __BIG_ENDIAN_BITFIELD 185 uint64_t reserved_1_63:63; 186 uint64_t start:1; 187 #else 188 uint64_t start:1; 189 uint64_t reserved_1_63:63; 190 #endif 191 } s; 192 }; 193 194 union cvmx_lmcx_bist_result { 195 uint64_t u64; 196 struct cvmx_lmcx_bist_result_s { 197 #ifdef __BIG_ENDIAN_BITFIELD 198 uint64_t reserved_11_63:53; 199 uint64_t csrd2e:1; 200 uint64_t csre2d:1; 201 uint64_t mwf:1; 202 uint64_t mwd:3; 203 uint64_t mwc:1; 204 uint64_t mrf:1; 205 uint64_t mrd:3; 206 #else 207 uint64_t mrd:3; 208 uint64_t mrf:1; 209 uint64_t mwc:1; 210 uint64_t mwd:3; 211 uint64_t mwf:1; 212 uint64_t csre2d:1; 213 uint64_t csrd2e:1; 214 uint64_t reserved_11_63:53; 215 #endif 216 } s; 217 struct cvmx_lmcx_bist_result_cn50xx { 218 #ifdef __BIG_ENDIAN_BITFIELD 219 uint64_t reserved_9_63:55; 220 uint64_t mwf:1; 221 uint64_t mwd:3; 222 uint64_t mwc:1; 223 uint64_t mrf:1; 224 uint64_t mrd:3; 225 #else 226 uint64_t mrd:3; 227 uint64_t mrf:1; 228 uint64_t mwc:1; 229 uint64_t mwd:3; 230 uint64_t mwf:1; 231 uint64_t reserved_9_63:55; 232 #endif 233 } cn50xx; 234 }; 235 236 union cvmx_lmcx_char_ctl { 237 uint64_t u64; 238 struct cvmx_lmcx_char_ctl_s { 239 #ifdef __BIG_ENDIAN_BITFIELD 240 uint64_t reserved_44_63:20; 241 uint64_t dr:1; 242 uint64_t skew_on:1; 243 uint64_t en:1; 244 uint64_t sel:1; 245 uint64_t prog:8; 246 uint64_t prbs:32; 247 #else 248 uint64_t prbs:32; 249 uint64_t prog:8; 250 uint64_t sel:1; 251 uint64_t en:1; 252 uint64_t skew_on:1; 253 uint64_t dr:1; 254 uint64_t reserved_44_63:20; 255 #endif 256 } s; 257 struct cvmx_lmcx_char_ctl_cn63xx { 258 #ifdef __BIG_ENDIAN_BITFIELD 259 uint64_t reserved_42_63:22; 260 uint64_t en:1; 261 uint64_t sel:1; 262 uint64_t prog:8; 263 uint64_t prbs:32; 264 #else 265 uint64_t prbs:32; 266 uint64_t prog:8; 267 uint64_t sel:1; 268 uint64_t en:1; 269 uint64_t reserved_42_63:22; 270 #endif 271 } cn63xx; 272 }; 273 274 union cvmx_lmcx_char_mask0 { 275 uint64_t u64; 276 struct cvmx_lmcx_char_mask0_s { 277 #ifdef __BIG_ENDIAN_BITFIELD 278 uint64_t mask:64; 279 #else 280 uint64_t mask:64; 281 #endif 282 } s; 283 }; 284 285 union cvmx_lmcx_char_mask1 { 286 uint64_t u64; 287 struct cvmx_lmcx_char_mask1_s { 288 #ifdef __BIG_ENDIAN_BITFIELD 289 uint64_t reserved_8_63:56; 290 uint64_t mask:8; 291 #else 292 uint64_t mask:8; 293 uint64_t reserved_8_63:56; 294 #endif 295 } s; 296 }; 297 298 union cvmx_lmcx_char_mask2 { 299 uint64_t u64; 300 struct cvmx_lmcx_char_mask2_s { 301 #ifdef __BIG_ENDIAN_BITFIELD 302 uint64_t mask:64; 303 #else 304 uint64_t mask:64; 305 #endif 306 } s; 307 }; 308 309 union cvmx_lmcx_char_mask3 { 310 uint64_t u64; 311 struct cvmx_lmcx_char_mask3_s { 312 #ifdef __BIG_ENDIAN_BITFIELD 313 uint64_t reserved_8_63:56; 314 uint64_t mask:8; 315 #else 316 uint64_t mask:8; 317 uint64_t reserved_8_63:56; 318 #endif 319 } s; 320 }; 321 322 union cvmx_lmcx_char_mask4 { 323 uint64_t u64; 324 struct cvmx_lmcx_char_mask4_s { 325 #ifdef __BIG_ENDIAN_BITFIELD 326 uint64_t reserved_33_63:31; 327 uint64_t reset_n_mask:1; 328 uint64_t a_mask:16; 329 uint64_t ba_mask:3; 330 uint64_t we_n_mask:1; 331 uint64_t cas_n_mask:1; 332 uint64_t ras_n_mask:1; 333 uint64_t odt1_mask:2; 334 uint64_t odt0_mask:2; 335 uint64_t cs1_n_mask:2; 336 uint64_t cs0_n_mask:2; 337 uint64_t cke_mask:2; 338 #else 339 uint64_t cke_mask:2; 340 uint64_t cs0_n_mask:2; 341 uint64_t cs1_n_mask:2; 342 uint64_t odt0_mask:2; 343 uint64_t odt1_mask:2; 344 uint64_t ras_n_mask:1; 345 uint64_t cas_n_mask:1; 346 uint64_t we_n_mask:1; 347 uint64_t ba_mask:3; 348 uint64_t a_mask:16; 349 uint64_t reset_n_mask:1; 350 uint64_t reserved_33_63:31; 351 #endif 352 } s; 353 }; 354 355 union cvmx_lmcx_comp_ctl { 356 uint64_t u64; 357 struct cvmx_lmcx_comp_ctl_s { 358 #ifdef __BIG_ENDIAN_BITFIELD 359 uint64_t reserved_32_63:32; 360 uint64_t nctl_csr:4; 361 uint64_t nctl_clk:4; 362 uint64_t nctl_cmd:4; 363 uint64_t nctl_dat:4; 364 uint64_t pctl_csr:4; 365 uint64_t pctl_clk:4; 366 uint64_t reserved_0_7:8; 367 #else 368 uint64_t reserved_0_7:8; 369 uint64_t pctl_clk:4; 370 uint64_t pctl_csr:4; 371 uint64_t nctl_dat:4; 372 uint64_t nctl_cmd:4; 373 uint64_t nctl_clk:4; 374 uint64_t nctl_csr:4; 375 uint64_t reserved_32_63:32; 376 #endif 377 } s; 378 struct cvmx_lmcx_comp_ctl_cn30xx { 379 #ifdef __BIG_ENDIAN_BITFIELD 380 uint64_t reserved_32_63:32; 381 uint64_t nctl_csr:4; 382 uint64_t nctl_clk:4; 383 uint64_t nctl_cmd:4; 384 uint64_t nctl_dat:4; 385 uint64_t pctl_csr:4; 386 uint64_t pctl_clk:4; 387 uint64_t pctl_cmd:4; 388 uint64_t pctl_dat:4; 389 #else 390 uint64_t pctl_dat:4; 391 uint64_t pctl_cmd:4; 392 uint64_t pctl_clk:4; 393 uint64_t pctl_csr:4; 394 uint64_t nctl_dat:4; 395 uint64_t nctl_cmd:4; 396 uint64_t nctl_clk:4; 397 uint64_t nctl_csr:4; 398 uint64_t reserved_32_63:32; 399 #endif 400 } cn30xx; 401 struct cvmx_lmcx_comp_ctl_cn50xx { 402 #ifdef __BIG_ENDIAN_BITFIELD 403 uint64_t reserved_32_63:32; 404 uint64_t nctl_csr:4; 405 uint64_t reserved_20_27:8; 406 uint64_t nctl_dat:4; 407 uint64_t pctl_csr:4; 408 uint64_t reserved_5_11:7; 409 uint64_t pctl_dat:5; 410 #else 411 uint64_t pctl_dat:5; 412 uint64_t reserved_5_11:7; 413 uint64_t pctl_csr:4; 414 uint64_t nctl_dat:4; 415 uint64_t reserved_20_27:8; 416 uint64_t nctl_csr:4; 417 uint64_t reserved_32_63:32; 418 #endif 419 } cn50xx; 420 struct cvmx_lmcx_comp_ctl_cn58xxp1 { 421 #ifdef __BIG_ENDIAN_BITFIELD 422 uint64_t reserved_32_63:32; 423 uint64_t nctl_csr:4; 424 uint64_t reserved_20_27:8; 425 uint64_t nctl_dat:4; 426 uint64_t pctl_csr:4; 427 uint64_t reserved_4_11:8; 428 uint64_t pctl_dat:4; 429 #else 430 uint64_t pctl_dat:4; 431 uint64_t reserved_4_11:8; 432 uint64_t pctl_csr:4; 433 uint64_t nctl_dat:4; 434 uint64_t reserved_20_27:8; 435 uint64_t nctl_csr:4; 436 uint64_t reserved_32_63:32; 437 #endif 438 } cn58xxp1; 439 }; 440 441 union cvmx_lmcx_comp_ctl2 { 442 uint64_t u64; 443 struct cvmx_lmcx_comp_ctl2_s { 444 #ifdef __BIG_ENDIAN_BITFIELD 445 uint64_t reserved_34_63:30; 446 uint64_t ddr__ptune:4; 447 uint64_t ddr__ntune:4; 448 uint64_t m180:1; 449 uint64_t byp:1; 450 uint64_t ptune:4; 451 uint64_t ntune:4; 452 uint64_t rodt_ctl:4; 453 uint64_t cmd_ctl:4; 454 uint64_t ck_ctl:4; 455 uint64_t dqx_ctl:4; 456 #else 457 uint64_t dqx_ctl:4; 458 uint64_t ck_ctl:4; 459 uint64_t cmd_ctl:4; 460 uint64_t rodt_ctl:4; 461 uint64_t ntune:4; 462 uint64_t ptune:4; 463 uint64_t byp:1; 464 uint64_t m180:1; 465 uint64_t ddr__ntune:4; 466 uint64_t ddr__ptune:4; 467 uint64_t reserved_34_63:30; 468 #endif 469 } s; 470 }; 471 472 union cvmx_lmcx_config { 473 uint64_t u64; 474 struct cvmx_lmcx_config_s { 475 #ifdef __BIG_ENDIAN_BITFIELD 476 uint64_t reserved_61_63:3; 477 uint64_t mode32b:1; 478 uint64_t scrz:1; 479 uint64_t early_unload_d1_r1:1; 480 uint64_t early_unload_d1_r0:1; 481 uint64_t early_unload_d0_r1:1; 482 uint64_t early_unload_d0_r0:1; 483 uint64_t init_status:4; 484 uint64_t mirrmask:4; 485 uint64_t rankmask:4; 486 uint64_t rank_ena:1; 487 uint64_t sref_with_dll:1; 488 uint64_t early_dqx:1; 489 uint64_t sequence:3; 490 uint64_t ref_zqcs_int:19; 491 uint64_t reset:1; 492 uint64_t ecc_adr:1; 493 uint64_t forcewrite:4; 494 uint64_t idlepower:3; 495 uint64_t pbank_lsb:4; 496 uint64_t row_lsb:3; 497 uint64_t ecc_ena:1; 498 uint64_t init_start:1; 499 #else 500 uint64_t init_start:1; 501 uint64_t ecc_ena:1; 502 uint64_t row_lsb:3; 503 uint64_t pbank_lsb:4; 504 uint64_t idlepower:3; 505 uint64_t forcewrite:4; 506 uint64_t ecc_adr:1; 507 uint64_t reset:1; 508 uint64_t ref_zqcs_int:19; 509 uint64_t sequence:3; 510 uint64_t early_dqx:1; 511 uint64_t sref_with_dll:1; 512 uint64_t rank_ena:1; 513 uint64_t rankmask:4; 514 uint64_t mirrmask:4; 515 uint64_t init_status:4; 516 uint64_t early_unload_d0_r0:1; 517 uint64_t early_unload_d0_r1:1; 518 uint64_t early_unload_d1_r0:1; 519 uint64_t early_unload_d1_r1:1; 520 uint64_t scrz:1; 521 uint64_t mode32b:1; 522 uint64_t reserved_61_63:3; 523 #endif 524 } s; 525 struct cvmx_lmcx_config_cn63xx { 526 #ifdef __BIG_ENDIAN_BITFIELD 527 uint64_t reserved_59_63:5; 528 uint64_t early_unload_d1_r1:1; 529 uint64_t early_unload_d1_r0:1; 530 uint64_t early_unload_d0_r1:1; 531 uint64_t early_unload_d0_r0:1; 532 uint64_t init_status:4; 533 uint64_t mirrmask:4; 534 uint64_t rankmask:4; 535 uint64_t rank_ena:1; 536 uint64_t sref_with_dll:1; 537 uint64_t early_dqx:1; 538 uint64_t sequence:3; 539 uint64_t ref_zqcs_int:19; 540 uint64_t reset:1; 541 uint64_t ecc_adr:1; 542 uint64_t forcewrite:4; 543 uint64_t idlepower:3; 544 uint64_t pbank_lsb:4; 545 uint64_t row_lsb:3; 546 uint64_t ecc_ena:1; 547 uint64_t init_start:1; 548 #else 549 uint64_t init_start:1; 550 uint64_t ecc_ena:1; 551 uint64_t row_lsb:3; 552 uint64_t pbank_lsb:4; 553 uint64_t idlepower:3; 554 uint64_t forcewrite:4; 555 uint64_t ecc_adr:1; 556 uint64_t reset:1; 557 uint64_t ref_zqcs_int:19; 558 uint64_t sequence:3; 559 uint64_t early_dqx:1; 560 uint64_t sref_with_dll:1; 561 uint64_t rank_ena:1; 562 uint64_t rankmask:4; 563 uint64_t mirrmask:4; 564 uint64_t init_status:4; 565 uint64_t early_unload_d0_r0:1; 566 uint64_t early_unload_d0_r1:1; 567 uint64_t early_unload_d1_r0:1; 568 uint64_t early_unload_d1_r1:1; 569 uint64_t reserved_59_63:5; 570 #endif 571 } cn63xx; 572 struct cvmx_lmcx_config_cn63xxp1 { 573 #ifdef __BIG_ENDIAN_BITFIELD 574 uint64_t reserved_55_63:9; 575 uint64_t init_status:4; 576 uint64_t mirrmask:4; 577 uint64_t rankmask:4; 578 uint64_t rank_ena:1; 579 uint64_t sref_with_dll:1; 580 uint64_t early_dqx:1; 581 uint64_t sequence:3; 582 uint64_t ref_zqcs_int:19; 583 uint64_t reset:1; 584 uint64_t ecc_adr:1; 585 uint64_t forcewrite:4; 586 uint64_t idlepower:3; 587 uint64_t pbank_lsb:4; 588 uint64_t row_lsb:3; 589 uint64_t ecc_ena:1; 590 uint64_t init_start:1; 591 #else 592 uint64_t init_start:1; 593 uint64_t ecc_ena:1; 594 uint64_t row_lsb:3; 595 uint64_t pbank_lsb:4; 596 uint64_t idlepower:3; 597 uint64_t forcewrite:4; 598 uint64_t ecc_adr:1; 599 uint64_t reset:1; 600 uint64_t ref_zqcs_int:19; 601 uint64_t sequence:3; 602 uint64_t early_dqx:1; 603 uint64_t sref_with_dll:1; 604 uint64_t rank_ena:1; 605 uint64_t rankmask:4; 606 uint64_t mirrmask:4; 607 uint64_t init_status:4; 608 uint64_t reserved_55_63:9; 609 #endif 610 } cn63xxp1; 611 struct cvmx_lmcx_config_cn66xx { 612 #ifdef __BIG_ENDIAN_BITFIELD 613 uint64_t reserved_60_63:4; 614 uint64_t scrz:1; 615 uint64_t early_unload_d1_r1:1; 616 uint64_t early_unload_d1_r0:1; 617 uint64_t early_unload_d0_r1:1; 618 uint64_t early_unload_d0_r0:1; 619 uint64_t init_status:4; 620 uint64_t mirrmask:4; 621 uint64_t rankmask:4; 622 uint64_t rank_ena:1; 623 uint64_t sref_with_dll:1; 624 uint64_t early_dqx:1; 625 uint64_t sequence:3; 626 uint64_t ref_zqcs_int:19; 627 uint64_t reset:1; 628 uint64_t ecc_adr:1; 629 uint64_t forcewrite:4; 630 uint64_t idlepower:3; 631 uint64_t pbank_lsb:4; 632 uint64_t row_lsb:3; 633 uint64_t ecc_ena:1; 634 uint64_t init_start:1; 635 #else 636 uint64_t init_start:1; 637 uint64_t ecc_ena:1; 638 uint64_t row_lsb:3; 639 uint64_t pbank_lsb:4; 640 uint64_t idlepower:3; 641 uint64_t forcewrite:4; 642 uint64_t ecc_adr:1; 643 uint64_t reset:1; 644 uint64_t ref_zqcs_int:19; 645 uint64_t sequence:3; 646 uint64_t early_dqx:1; 647 uint64_t sref_with_dll:1; 648 uint64_t rank_ena:1; 649 uint64_t rankmask:4; 650 uint64_t mirrmask:4; 651 uint64_t init_status:4; 652 uint64_t early_unload_d0_r0:1; 653 uint64_t early_unload_d0_r1:1; 654 uint64_t early_unload_d1_r0:1; 655 uint64_t early_unload_d1_r1:1; 656 uint64_t scrz:1; 657 uint64_t reserved_60_63:4; 658 #endif 659 } cn66xx; 660 }; 661 662 union cvmx_lmcx_control { 663 uint64_t u64; 664 struct cvmx_lmcx_control_s { 665 #ifdef __BIG_ENDIAN_BITFIELD 666 uint64_t scramble_ena:1; 667 uint64_t thrcnt:12; 668 uint64_t persub:8; 669 uint64_t thrmax:4; 670 uint64_t crm_cnt:5; 671 uint64_t crm_thr:5; 672 uint64_t crm_max:5; 673 uint64_t rodt_bprch:1; 674 uint64_t wodt_bprch:1; 675 uint64_t bprch:2; 676 uint64_t ext_zqcs_dis:1; 677 uint64_t int_zqcs_dis:1; 678 uint64_t auto_dclkdis:1; 679 uint64_t xor_bank:1; 680 uint64_t max_write_batch:4; 681 uint64_t nxm_write_en:1; 682 uint64_t elev_prio_dis:1; 683 uint64_t inorder_wr:1; 684 uint64_t inorder_rd:1; 685 uint64_t throttle_wr:1; 686 uint64_t throttle_rd:1; 687 uint64_t fprch2:2; 688 uint64_t pocas:1; 689 uint64_t ddr2t:1; 690 uint64_t bwcnt:1; 691 uint64_t rdimm_ena:1; 692 #else 693 uint64_t rdimm_ena:1; 694 uint64_t bwcnt:1; 695 uint64_t ddr2t:1; 696 uint64_t pocas:1; 697 uint64_t fprch2:2; 698 uint64_t throttle_rd:1; 699 uint64_t throttle_wr:1; 700 uint64_t inorder_rd:1; 701 uint64_t inorder_wr:1; 702 uint64_t elev_prio_dis:1; 703 uint64_t nxm_write_en:1; 704 uint64_t max_write_batch:4; 705 uint64_t xor_bank:1; 706 uint64_t auto_dclkdis:1; 707 uint64_t int_zqcs_dis:1; 708 uint64_t ext_zqcs_dis:1; 709 uint64_t bprch:2; 710 uint64_t wodt_bprch:1; 711 uint64_t rodt_bprch:1; 712 uint64_t crm_max:5; 713 uint64_t crm_thr:5; 714 uint64_t crm_cnt:5; 715 uint64_t thrmax:4; 716 uint64_t persub:8; 717 uint64_t thrcnt:12; 718 uint64_t scramble_ena:1; 719 #endif 720 } s; 721 struct cvmx_lmcx_control_cn63xx { 722 #ifdef __BIG_ENDIAN_BITFIELD 723 uint64_t reserved_24_63:40; 724 uint64_t rodt_bprch:1; 725 uint64_t wodt_bprch:1; 726 uint64_t bprch:2; 727 uint64_t ext_zqcs_dis:1; 728 uint64_t int_zqcs_dis:1; 729 uint64_t auto_dclkdis:1; 730 uint64_t xor_bank:1; 731 uint64_t max_write_batch:4; 732 uint64_t nxm_write_en:1; 733 uint64_t elev_prio_dis:1; 734 uint64_t inorder_wr:1; 735 uint64_t inorder_rd:1; 736 uint64_t throttle_wr:1; 737 uint64_t throttle_rd:1; 738 uint64_t fprch2:2; 739 uint64_t pocas:1; 740 uint64_t ddr2t:1; 741 uint64_t bwcnt:1; 742 uint64_t rdimm_ena:1; 743 #else 744 uint64_t rdimm_ena:1; 745 uint64_t bwcnt:1; 746 uint64_t ddr2t:1; 747 uint64_t pocas:1; 748 uint64_t fprch2:2; 749 uint64_t throttle_rd:1; 750 uint64_t throttle_wr:1; 751 uint64_t inorder_rd:1; 752 uint64_t inorder_wr:1; 753 uint64_t elev_prio_dis:1; 754 uint64_t nxm_write_en:1; 755 uint64_t max_write_batch:4; 756 uint64_t xor_bank:1; 757 uint64_t auto_dclkdis:1; 758 uint64_t int_zqcs_dis:1; 759 uint64_t ext_zqcs_dis:1; 760 uint64_t bprch:2; 761 uint64_t wodt_bprch:1; 762 uint64_t rodt_bprch:1; 763 uint64_t reserved_24_63:40; 764 #endif 765 } cn63xx; 766 struct cvmx_lmcx_control_cn66xx { 767 #ifdef __BIG_ENDIAN_BITFIELD 768 uint64_t scramble_ena:1; 769 uint64_t reserved_24_62:39; 770 uint64_t rodt_bprch:1; 771 uint64_t wodt_bprch:1; 772 uint64_t bprch:2; 773 uint64_t ext_zqcs_dis:1; 774 uint64_t int_zqcs_dis:1; 775 uint64_t auto_dclkdis:1; 776 uint64_t xor_bank:1; 777 uint64_t max_write_batch:4; 778 uint64_t nxm_write_en:1; 779 uint64_t elev_prio_dis:1; 780 uint64_t inorder_wr:1; 781 uint64_t inorder_rd:1; 782 uint64_t throttle_wr:1; 783 uint64_t throttle_rd:1; 784 uint64_t fprch2:2; 785 uint64_t pocas:1; 786 uint64_t ddr2t:1; 787 uint64_t bwcnt:1; 788 uint64_t rdimm_ena:1; 789 #else 790 uint64_t rdimm_ena:1; 791 uint64_t bwcnt:1; 792 uint64_t ddr2t:1; 793 uint64_t pocas:1; 794 uint64_t fprch2:2; 795 uint64_t throttle_rd:1; 796 uint64_t throttle_wr:1; 797 uint64_t inorder_rd:1; 798 uint64_t inorder_wr:1; 799 uint64_t elev_prio_dis:1; 800 uint64_t nxm_write_en:1; 801 uint64_t max_write_batch:4; 802 uint64_t xor_bank:1; 803 uint64_t auto_dclkdis:1; 804 uint64_t int_zqcs_dis:1; 805 uint64_t ext_zqcs_dis:1; 806 uint64_t bprch:2; 807 uint64_t wodt_bprch:1; 808 uint64_t rodt_bprch:1; 809 uint64_t reserved_24_62:39; 810 uint64_t scramble_ena:1; 811 #endif 812 } cn66xx; 813 struct cvmx_lmcx_control_cn68xx { 814 #ifdef __BIG_ENDIAN_BITFIELD 815 uint64_t reserved_63_63:1; 816 uint64_t thrcnt:12; 817 uint64_t persub:8; 818 uint64_t thrmax:4; 819 uint64_t crm_cnt:5; 820 uint64_t crm_thr:5; 821 uint64_t crm_max:5; 822 uint64_t rodt_bprch:1; 823 uint64_t wodt_bprch:1; 824 uint64_t bprch:2; 825 uint64_t ext_zqcs_dis:1; 826 uint64_t int_zqcs_dis:1; 827 uint64_t auto_dclkdis:1; 828 uint64_t xor_bank:1; 829 uint64_t max_write_batch:4; 830 uint64_t nxm_write_en:1; 831 uint64_t elev_prio_dis:1; 832 uint64_t inorder_wr:1; 833 uint64_t inorder_rd:1; 834 uint64_t throttle_wr:1; 835 uint64_t throttle_rd:1; 836 uint64_t fprch2:2; 837 uint64_t pocas:1; 838 uint64_t ddr2t:1; 839 uint64_t bwcnt:1; 840 uint64_t rdimm_ena:1; 841 #else 842 uint64_t rdimm_ena:1; 843 uint64_t bwcnt:1; 844 uint64_t ddr2t:1; 845 uint64_t pocas:1; 846 uint64_t fprch2:2; 847 uint64_t throttle_rd:1; 848 uint64_t throttle_wr:1; 849 uint64_t inorder_rd:1; 850 uint64_t inorder_wr:1; 851 uint64_t elev_prio_dis:1; 852 uint64_t nxm_write_en:1; 853 uint64_t max_write_batch:4; 854 uint64_t xor_bank:1; 855 uint64_t auto_dclkdis:1; 856 uint64_t int_zqcs_dis:1; 857 uint64_t ext_zqcs_dis:1; 858 uint64_t bprch:2; 859 uint64_t wodt_bprch:1; 860 uint64_t rodt_bprch:1; 861 uint64_t crm_max:5; 862 uint64_t crm_thr:5; 863 uint64_t crm_cnt:5; 864 uint64_t thrmax:4; 865 uint64_t persub:8; 866 uint64_t thrcnt:12; 867 uint64_t reserved_63_63:1; 868 #endif 869 } cn68xx; 870 }; 871 872 union cvmx_lmcx_ctl { 873 uint64_t u64; 874 struct cvmx_lmcx_ctl_s { 875 #ifdef __BIG_ENDIAN_BITFIELD 876 uint64_t reserved_32_63:32; 877 uint64_t ddr__nctl:4; 878 uint64_t ddr__pctl:4; 879 uint64_t slow_scf:1; 880 uint64_t xor_bank:1; 881 uint64_t max_write_batch:4; 882 uint64_t pll_div2:1; 883 uint64_t pll_bypass:1; 884 uint64_t rdimm_ena:1; 885 uint64_t r2r_slot:1; 886 uint64_t inorder_mwf:1; 887 uint64_t inorder_mrf:1; 888 uint64_t reserved_10_11:2; 889 uint64_t fprch2:1; 890 uint64_t bprch:1; 891 uint64_t sil_lat:2; 892 uint64_t tskw:2; 893 uint64_t qs_dic:2; 894 uint64_t dic:2; 895 #else 896 uint64_t dic:2; 897 uint64_t qs_dic:2; 898 uint64_t tskw:2; 899 uint64_t sil_lat:2; 900 uint64_t bprch:1; 901 uint64_t fprch2:1; 902 uint64_t reserved_10_11:2; 903 uint64_t inorder_mrf:1; 904 uint64_t inorder_mwf:1; 905 uint64_t r2r_slot:1; 906 uint64_t rdimm_ena:1; 907 uint64_t pll_bypass:1; 908 uint64_t pll_div2:1; 909 uint64_t max_write_batch:4; 910 uint64_t xor_bank:1; 911 uint64_t slow_scf:1; 912 uint64_t ddr__pctl:4; 913 uint64_t ddr__nctl:4; 914 uint64_t reserved_32_63:32; 915 #endif 916 } s; 917 struct cvmx_lmcx_ctl_cn30xx { 918 #ifdef __BIG_ENDIAN_BITFIELD 919 uint64_t reserved_32_63:32; 920 uint64_t ddr__nctl:4; 921 uint64_t ddr__pctl:4; 922 uint64_t slow_scf:1; 923 uint64_t xor_bank:1; 924 uint64_t max_write_batch:4; 925 uint64_t pll_div2:1; 926 uint64_t pll_bypass:1; 927 uint64_t rdimm_ena:1; 928 uint64_t r2r_slot:1; 929 uint64_t inorder_mwf:1; 930 uint64_t inorder_mrf:1; 931 uint64_t dreset:1; 932 uint64_t mode32b:1; 933 uint64_t fprch2:1; 934 uint64_t bprch:1; 935 uint64_t sil_lat:2; 936 uint64_t tskw:2; 937 uint64_t qs_dic:2; 938 uint64_t dic:2; 939 #else 940 uint64_t dic:2; 941 uint64_t qs_dic:2; 942 uint64_t tskw:2; 943 uint64_t sil_lat:2; 944 uint64_t bprch:1; 945 uint64_t fprch2:1; 946 uint64_t mode32b:1; 947 uint64_t dreset:1; 948 uint64_t inorder_mrf:1; 949 uint64_t inorder_mwf:1; 950 uint64_t r2r_slot:1; 951 uint64_t rdimm_ena:1; 952 uint64_t pll_bypass:1; 953 uint64_t pll_div2:1; 954 uint64_t max_write_batch:4; 955 uint64_t xor_bank:1; 956 uint64_t slow_scf:1; 957 uint64_t ddr__pctl:4; 958 uint64_t ddr__nctl:4; 959 uint64_t reserved_32_63:32; 960 #endif 961 } cn30xx; 962 struct cvmx_lmcx_ctl_cn38xx { 963 #ifdef __BIG_ENDIAN_BITFIELD 964 uint64_t reserved_32_63:32; 965 uint64_t ddr__nctl:4; 966 uint64_t ddr__pctl:4; 967 uint64_t slow_scf:1; 968 uint64_t xor_bank:1; 969 uint64_t max_write_batch:4; 970 uint64_t reserved_16_17:2; 971 uint64_t rdimm_ena:1; 972 uint64_t r2r_slot:1; 973 uint64_t inorder_mwf:1; 974 uint64_t inorder_mrf:1; 975 uint64_t set_zero:1; 976 uint64_t mode128b:1; 977 uint64_t fprch2:1; 978 uint64_t bprch:1; 979 uint64_t sil_lat:2; 980 uint64_t tskw:2; 981 uint64_t qs_dic:2; 982 uint64_t dic:2; 983 #else 984 uint64_t dic:2; 985 uint64_t qs_dic:2; 986 uint64_t tskw:2; 987 uint64_t sil_lat:2; 988 uint64_t bprch:1; 989 uint64_t fprch2:1; 990 uint64_t mode128b:1; 991 uint64_t set_zero:1; 992 uint64_t inorder_mrf:1; 993 uint64_t inorder_mwf:1; 994 uint64_t r2r_slot:1; 995 uint64_t rdimm_ena:1; 996 uint64_t reserved_16_17:2; 997 uint64_t max_write_batch:4; 998 uint64_t xor_bank:1; 999 uint64_t slow_scf:1; 1000 uint64_t ddr__pctl:4; 1001 uint64_t ddr__nctl:4; 1002 uint64_t reserved_32_63:32; 1003 #endif 1004 } cn38xx; 1005 struct cvmx_lmcx_ctl_cn50xx { 1006 #ifdef __BIG_ENDIAN_BITFIELD 1007 uint64_t reserved_32_63:32; 1008 uint64_t ddr__nctl:4; 1009 uint64_t ddr__pctl:4; 1010 uint64_t slow_scf:1; 1011 uint64_t xor_bank:1; 1012 uint64_t max_write_batch:4; 1013 uint64_t reserved_17_17:1; 1014 uint64_t pll_bypass:1; 1015 uint64_t rdimm_ena:1; 1016 uint64_t r2r_slot:1; 1017 uint64_t inorder_mwf:1; 1018 uint64_t inorder_mrf:1; 1019 uint64_t dreset:1; 1020 uint64_t mode32b:1; 1021 uint64_t fprch2:1; 1022 uint64_t bprch:1; 1023 uint64_t sil_lat:2; 1024 uint64_t tskw:2; 1025 uint64_t qs_dic:2; 1026 uint64_t dic:2; 1027 #else 1028 uint64_t dic:2; 1029 uint64_t qs_dic:2; 1030 uint64_t tskw:2; 1031 uint64_t sil_lat:2; 1032 uint64_t bprch:1; 1033 uint64_t fprch2:1; 1034 uint64_t mode32b:1; 1035 uint64_t dreset:1; 1036 uint64_t inorder_mrf:1; 1037 uint64_t inorder_mwf:1; 1038 uint64_t r2r_slot:1; 1039 uint64_t rdimm_ena:1; 1040 uint64_t pll_bypass:1; 1041 uint64_t reserved_17_17:1; 1042 uint64_t max_write_batch:4; 1043 uint64_t xor_bank:1; 1044 uint64_t slow_scf:1; 1045 uint64_t ddr__pctl:4; 1046 uint64_t ddr__nctl:4; 1047 uint64_t reserved_32_63:32; 1048 #endif 1049 } cn50xx; 1050 struct cvmx_lmcx_ctl_cn52xx { 1051 #ifdef __BIG_ENDIAN_BITFIELD 1052 uint64_t reserved_32_63:32; 1053 uint64_t ddr__nctl:4; 1054 uint64_t ddr__pctl:4; 1055 uint64_t slow_scf:1; 1056 uint64_t xor_bank:1; 1057 uint64_t max_write_batch:4; 1058 uint64_t reserved_16_17:2; 1059 uint64_t rdimm_ena:1; 1060 uint64_t r2r_slot:1; 1061 uint64_t inorder_mwf:1; 1062 uint64_t inorder_mrf:1; 1063 uint64_t dreset:1; 1064 uint64_t mode32b:1; 1065 uint64_t fprch2:1; 1066 uint64_t bprch:1; 1067 uint64_t sil_lat:2; 1068 uint64_t tskw:2; 1069 uint64_t qs_dic:2; 1070 uint64_t dic:2; 1071 #else 1072 uint64_t dic:2; 1073 uint64_t qs_dic:2; 1074 uint64_t tskw:2; 1075 uint64_t sil_lat:2; 1076 uint64_t bprch:1; 1077 uint64_t fprch2:1; 1078 uint64_t mode32b:1; 1079 uint64_t dreset:1; 1080 uint64_t inorder_mrf:1; 1081 uint64_t inorder_mwf:1; 1082 uint64_t r2r_slot:1; 1083 uint64_t rdimm_ena:1; 1084 uint64_t reserved_16_17:2; 1085 uint64_t max_write_batch:4; 1086 uint64_t xor_bank:1; 1087 uint64_t slow_scf:1; 1088 uint64_t ddr__pctl:4; 1089 uint64_t ddr__nctl:4; 1090 uint64_t reserved_32_63:32; 1091 #endif 1092 } cn52xx; 1093 struct cvmx_lmcx_ctl_cn58xx { 1094 #ifdef __BIG_ENDIAN_BITFIELD 1095 uint64_t reserved_32_63:32; 1096 uint64_t ddr__nctl:4; 1097 uint64_t ddr__pctl:4; 1098 uint64_t slow_scf:1; 1099 uint64_t xor_bank:1; 1100 uint64_t max_write_batch:4; 1101 uint64_t reserved_16_17:2; 1102 uint64_t rdimm_ena:1; 1103 uint64_t r2r_slot:1; 1104 uint64_t inorder_mwf:1; 1105 uint64_t inorder_mrf:1; 1106 uint64_t dreset:1; 1107 uint64_t mode128b:1; 1108 uint64_t fprch2:1; 1109 uint64_t bprch:1; 1110 uint64_t sil_lat:2; 1111 uint64_t tskw:2; 1112 uint64_t qs_dic:2; 1113 uint64_t dic:2; 1114 #else 1115 uint64_t dic:2; 1116 uint64_t qs_dic:2; 1117 uint64_t tskw:2; 1118 uint64_t sil_lat:2; 1119 uint64_t bprch:1; 1120 uint64_t fprch2:1; 1121 uint64_t mode128b:1; 1122 uint64_t dreset:1; 1123 uint64_t inorder_mrf:1; 1124 uint64_t inorder_mwf:1; 1125 uint64_t r2r_slot:1; 1126 uint64_t rdimm_ena:1; 1127 uint64_t reserved_16_17:2; 1128 uint64_t max_write_batch:4; 1129 uint64_t xor_bank:1; 1130 uint64_t slow_scf:1; 1131 uint64_t ddr__pctl:4; 1132 uint64_t ddr__nctl:4; 1133 uint64_t reserved_32_63:32; 1134 #endif 1135 } cn58xx; 1136 }; 1137 1138 union cvmx_lmcx_ctl1 { 1139 uint64_t u64; 1140 struct cvmx_lmcx_ctl1_s { 1141 #ifdef __BIG_ENDIAN_BITFIELD 1142 uint64_t reserved_21_63:43; 1143 uint64_t ecc_adr:1; 1144 uint64_t forcewrite:4; 1145 uint64_t idlepower:3; 1146 uint64_t sequence:3; 1147 uint64_t sil_mode:1; 1148 uint64_t dcc_enable:1; 1149 uint64_t reserved_2_7:6; 1150 uint64_t data_layout:2; 1151 #else 1152 uint64_t data_layout:2; 1153 uint64_t reserved_2_7:6; 1154 uint64_t dcc_enable:1; 1155 uint64_t sil_mode:1; 1156 uint64_t sequence:3; 1157 uint64_t idlepower:3; 1158 uint64_t forcewrite:4; 1159 uint64_t ecc_adr:1; 1160 uint64_t reserved_21_63:43; 1161 #endif 1162 } s; 1163 struct cvmx_lmcx_ctl1_cn30xx { 1164 #ifdef __BIG_ENDIAN_BITFIELD 1165 uint64_t reserved_2_63:62; 1166 uint64_t data_layout:2; 1167 #else 1168 uint64_t data_layout:2; 1169 uint64_t reserved_2_63:62; 1170 #endif 1171 } cn30xx; 1172 struct cvmx_lmcx_ctl1_cn50xx { 1173 #ifdef __BIG_ENDIAN_BITFIELD 1174 uint64_t reserved_10_63:54; 1175 uint64_t sil_mode:1; 1176 uint64_t dcc_enable:1; 1177 uint64_t reserved_2_7:6; 1178 uint64_t data_layout:2; 1179 #else 1180 uint64_t data_layout:2; 1181 uint64_t reserved_2_7:6; 1182 uint64_t dcc_enable:1; 1183 uint64_t sil_mode:1; 1184 uint64_t reserved_10_63:54; 1185 #endif 1186 } cn50xx; 1187 struct cvmx_lmcx_ctl1_cn52xx { 1188 #ifdef __BIG_ENDIAN_BITFIELD 1189 uint64_t reserved_21_63:43; 1190 uint64_t ecc_adr:1; 1191 uint64_t forcewrite:4; 1192 uint64_t idlepower:3; 1193 uint64_t sequence:3; 1194 uint64_t sil_mode:1; 1195 uint64_t dcc_enable:1; 1196 uint64_t reserved_0_7:8; 1197 #else 1198 uint64_t reserved_0_7:8; 1199 uint64_t dcc_enable:1; 1200 uint64_t sil_mode:1; 1201 uint64_t sequence:3; 1202 uint64_t idlepower:3; 1203 uint64_t forcewrite:4; 1204 uint64_t ecc_adr:1; 1205 uint64_t reserved_21_63:43; 1206 #endif 1207 } cn52xx; 1208 struct cvmx_lmcx_ctl1_cn58xx { 1209 #ifdef __BIG_ENDIAN_BITFIELD 1210 uint64_t reserved_10_63:54; 1211 uint64_t sil_mode:1; 1212 uint64_t dcc_enable:1; 1213 uint64_t reserved_0_7:8; 1214 #else 1215 uint64_t reserved_0_7:8; 1216 uint64_t dcc_enable:1; 1217 uint64_t sil_mode:1; 1218 uint64_t reserved_10_63:54; 1219 #endif 1220 } cn58xx; 1221 }; 1222 1223 union cvmx_lmcx_dclk_cnt { 1224 uint64_t u64; 1225 struct cvmx_lmcx_dclk_cnt_s { 1226 #ifdef __BIG_ENDIAN_BITFIELD 1227 uint64_t dclkcnt:64; 1228 #else 1229 uint64_t dclkcnt:64; 1230 #endif 1231 } s; 1232 }; 1233 1234 union cvmx_lmcx_dclk_cnt_hi { 1235 uint64_t u64; 1236 struct cvmx_lmcx_dclk_cnt_hi_s { 1237 #ifdef __BIG_ENDIAN_BITFIELD 1238 uint64_t reserved_32_63:32; 1239 uint64_t dclkcnt_hi:32; 1240 #else 1241 uint64_t dclkcnt_hi:32; 1242 uint64_t reserved_32_63:32; 1243 #endif 1244 } s; 1245 }; 1246 1247 union cvmx_lmcx_dclk_cnt_lo { 1248 uint64_t u64; 1249 struct cvmx_lmcx_dclk_cnt_lo_s { 1250 #ifdef __BIG_ENDIAN_BITFIELD 1251 uint64_t reserved_32_63:32; 1252 uint64_t dclkcnt_lo:32; 1253 #else 1254 uint64_t dclkcnt_lo:32; 1255 uint64_t reserved_32_63:32; 1256 #endif 1257 } s; 1258 }; 1259 1260 union cvmx_lmcx_dclk_ctl { 1261 uint64_t u64; 1262 struct cvmx_lmcx_dclk_ctl_s { 1263 #ifdef __BIG_ENDIAN_BITFIELD 1264 uint64_t reserved_8_63:56; 1265 uint64_t off90_ena:1; 1266 uint64_t dclk90_byp:1; 1267 uint64_t dclk90_ld:1; 1268 uint64_t dclk90_vlu:5; 1269 #else 1270 uint64_t dclk90_vlu:5; 1271 uint64_t dclk90_ld:1; 1272 uint64_t dclk90_byp:1; 1273 uint64_t off90_ena:1; 1274 uint64_t reserved_8_63:56; 1275 #endif 1276 } s; 1277 }; 1278 1279 union cvmx_lmcx_ddr2_ctl { 1280 uint64_t u64; 1281 struct cvmx_lmcx_ddr2_ctl_s { 1282 #ifdef __BIG_ENDIAN_BITFIELD 1283 uint64_t reserved_32_63:32; 1284 uint64_t bank8:1; 1285 uint64_t burst8:1; 1286 uint64_t addlat:3; 1287 uint64_t pocas:1; 1288 uint64_t bwcnt:1; 1289 uint64_t twr:3; 1290 uint64_t silo_hc:1; 1291 uint64_t ddr_eof:4; 1292 uint64_t tfaw:5; 1293 uint64_t crip_mode:1; 1294 uint64_t ddr2t:1; 1295 uint64_t odt_ena:1; 1296 uint64_t qdll_ena:1; 1297 uint64_t dll90_vlu:5; 1298 uint64_t dll90_byp:1; 1299 uint64_t rdqs:1; 1300 uint64_t ddr2:1; 1301 #else 1302 uint64_t ddr2:1; 1303 uint64_t rdqs:1; 1304 uint64_t dll90_byp:1; 1305 uint64_t dll90_vlu:5; 1306 uint64_t qdll_ena:1; 1307 uint64_t odt_ena:1; 1308 uint64_t ddr2t:1; 1309 uint64_t crip_mode:1; 1310 uint64_t tfaw:5; 1311 uint64_t ddr_eof:4; 1312 uint64_t silo_hc:1; 1313 uint64_t twr:3; 1314 uint64_t bwcnt:1; 1315 uint64_t pocas:1; 1316 uint64_t addlat:3; 1317 uint64_t burst8:1; 1318 uint64_t bank8:1; 1319 uint64_t reserved_32_63:32; 1320 #endif 1321 } s; 1322 struct cvmx_lmcx_ddr2_ctl_cn30xx { 1323 #ifdef __BIG_ENDIAN_BITFIELD 1324 uint64_t reserved_32_63:32; 1325 uint64_t bank8:1; 1326 uint64_t burst8:1; 1327 uint64_t addlat:3; 1328 uint64_t pocas:1; 1329 uint64_t bwcnt:1; 1330 uint64_t twr:3; 1331 uint64_t silo_hc:1; 1332 uint64_t ddr_eof:4; 1333 uint64_t tfaw:5; 1334 uint64_t crip_mode:1; 1335 uint64_t ddr2t:1; 1336 uint64_t odt_ena:1; 1337 uint64_t qdll_ena:1; 1338 uint64_t dll90_vlu:5; 1339 uint64_t dll90_byp:1; 1340 uint64_t reserved_1_1:1; 1341 uint64_t ddr2:1; 1342 #else 1343 uint64_t ddr2:1; 1344 uint64_t reserved_1_1:1; 1345 uint64_t dll90_byp:1; 1346 uint64_t dll90_vlu:5; 1347 uint64_t qdll_ena:1; 1348 uint64_t odt_ena:1; 1349 uint64_t ddr2t:1; 1350 uint64_t crip_mode:1; 1351 uint64_t tfaw:5; 1352 uint64_t ddr_eof:4; 1353 uint64_t silo_hc:1; 1354 uint64_t twr:3; 1355 uint64_t bwcnt:1; 1356 uint64_t pocas:1; 1357 uint64_t addlat:3; 1358 uint64_t burst8:1; 1359 uint64_t bank8:1; 1360 uint64_t reserved_32_63:32; 1361 #endif 1362 } cn30xx; 1363 }; 1364 1365 union cvmx_lmcx_ddr_pll_ctl { 1366 uint64_t u64; 1367 struct cvmx_lmcx_ddr_pll_ctl_s { 1368 #ifdef __BIG_ENDIAN_BITFIELD 1369 uint64_t reserved_27_63:37; 1370 uint64_t jtg_test_mode:1; 1371 uint64_t dfm_div_reset:1; 1372 uint64_t dfm_ps_en:3; 1373 uint64_t ddr_div_reset:1; 1374 uint64_t ddr_ps_en:3; 1375 uint64_t diffamp:4; 1376 uint64_t cps:3; 1377 uint64_t cpb:3; 1378 uint64_t reset_n:1; 1379 uint64_t clkf:7; 1380 #else 1381 uint64_t clkf:7; 1382 uint64_t reset_n:1; 1383 uint64_t cpb:3; 1384 uint64_t cps:3; 1385 uint64_t diffamp:4; 1386 uint64_t ddr_ps_en:3; 1387 uint64_t ddr_div_reset:1; 1388 uint64_t dfm_ps_en:3; 1389 uint64_t dfm_div_reset:1; 1390 uint64_t jtg_test_mode:1; 1391 uint64_t reserved_27_63:37; 1392 #endif 1393 } s; 1394 }; 1395 1396 union cvmx_lmcx_delay_cfg { 1397 uint64_t u64; 1398 struct cvmx_lmcx_delay_cfg_s { 1399 #ifdef __BIG_ENDIAN_BITFIELD 1400 uint64_t reserved_15_63:49; 1401 uint64_t dq:5; 1402 uint64_t cmd:5; 1403 uint64_t clk:5; 1404 #else 1405 uint64_t clk:5; 1406 uint64_t cmd:5; 1407 uint64_t dq:5; 1408 uint64_t reserved_15_63:49; 1409 #endif 1410 } s; 1411 struct cvmx_lmcx_delay_cfg_cn38xx { 1412 #ifdef __BIG_ENDIAN_BITFIELD 1413 uint64_t reserved_14_63:50; 1414 uint64_t dq:4; 1415 uint64_t reserved_9_9:1; 1416 uint64_t cmd:4; 1417 uint64_t reserved_4_4:1; 1418 uint64_t clk:4; 1419 #else 1420 uint64_t clk:4; 1421 uint64_t reserved_4_4:1; 1422 uint64_t cmd:4; 1423 uint64_t reserved_9_9:1; 1424 uint64_t dq:4; 1425 uint64_t reserved_14_63:50; 1426 #endif 1427 } cn38xx; 1428 }; 1429 1430 union cvmx_lmcx_dimmx_params { 1431 uint64_t u64; 1432 struct cvmx_lmcx_dimmx_params_s { 1433 #ifdef __BIG_ENDIAN_BITFIELD 1434 uint64_t rc15:4; 1435 uint64_t rc14:4; 1436 uint64_t rc13:4; 1437 uint64_t rc12:4; 1438 uint64_t rc11:4; 1439 uint64_t rc10:4; 1440 uint64_t rc9:4; 1441 uint64_t rc8:4; 1442 uint64_t rc7:4; 1443 uint64_t rc6:4; 1444 uint64_t rc5:4; 1445 uint64_t rc4:4; 1446 uint64_t rc3:4; 1447 uint64_t rc2:4; 1448 uint64_t rc1:4; 1449 uint64_t rc0:4; 1450 #else 1451 uint64_t rc0:4; 1452 uint64_t rc1:4; 1453 uint64_t rc2:4; 1454 uint64_t rc3:4; 1455 uint64_t rc4:4; 1456 uint64_t rc5:4; 1457 uint64_t rc6:4; 1458 uint64_t rc7:4; 1459 uint64_t rc8:4; 1460 uint64_t rc9:4; 1461 uint64_t rc10:4; 1462 uint64_t rc11:4; 1463 uint64_t rc12:4; 1464 uint64_t rc13:4; 1465 uint64_t rc14:4; 1466 uint64_t rc15:4; 1467 #endif 1468 } s; 1469 }; 1470 1471 union cvmx_lmcx_dimm_ctl { 1472 uint64_t u64; 1473 struct cvmx_lmcx_dimm_ctl_s { 1474 #ifdef __BIG_ENDIAN_BITFIELD 1475 uint64_t reserved_46_63:18; 1476 uint64_t parity:1; 1477 uint64_t tcws:13; 1478 uint64_t dimm1_wmask:16; 1479 uint64_t dimm0_wmask:16; 1480 #else 1481 uint64_t dimm0_wmask:16; 1482 uint64_t dimm1_wmask:16; 1483 uint64_t tcws:13; 1484 uint64_t parity:1; 1485 uint64_t reserved_46_63:18; 1486 #endif 1487 } s; 1488 }; 1489 1490 union cvmx_lmcx_dll_ctl { 1491 uint64_t u64; 1492 struct cvmx_lmcx_dll_ctl_s { 1493 #ifdef __BIG_ENDIAN_BITFIELD 1494 uint64_t reserved_8_63:56; 1495 uint64_t dreset:1; 1496 uint64_t dll90_byp:1; 1497 uint64_t dll90_ena:1; 1498 uint64_t dll90_vlu:5; 1499 #else 1500 uint64_t dll90_vlu:5; 1501 uint64_t dll90_ena:1; 1502 uint64_t dll90_byp:1; 1503 uint64_t dreset:1; 1504 uint64_t reserved_8_63:56; 1505 #endif 1506 } s; 1507 }; 1508 1509 union cvmx_lmcx_dll_ctl2 { 1510 uint64_t u64; 1511 struct cvmx_lmcx_dll_ctl2_s { 1512 #ifdef __BIG_ENDIAN_BITFIELD 1513 uint64_t reserved_16_63:48; 1514 uint64_t intf_en:1; 1515 uint64_t dll_bringup:1; 1516 uint64_t dreset:1; 1517 uint64_t quad_dll_ena:1; 1518 uint64_t byp_sel:4; 1519 uint64_t byp_setting:8; 1520 #else 1521 uint64_t byp_setting:8; 1522 uint64_t byp_sel:4; 1523 uint64_t quad_dll_ena:1; 1524 uint64_t dreset:1; 1525 uint64_t dll_bringup:1; 1526 uint64_t intf_en:1; 1527 uint64_t reserved_16_63:48; 1528 #endif 1529 } s; 1530 struct cvmx_lmcx_dll_ctl2_cn63xx { 1531 #ifdef __BIG_ENDIAN_BITFIELD 1532 uint64_t reserved_15_63:49; 1533 uint64_t dll_bringup:1; 1534 uint64_t dreset:1; 1535 uint64_t quad_dll_ena:1; 1536 uint64_t byp_sel:4; 1537 uint64_t byp_setting:8; 1538 #else 1539 uint64_t byp_setting:8; 1540 uint64_t byp_sel:4; 1541 uint64_t quad_dll_ena:1; 1542 uint64_t dreset:1; 1543 uint64_t dll_bringup:1; 1544 uint64_t reserved_15_63:49; 1545 #endif 1546 } cn63xx; 1547 }; 1548 1549 union cvmx_lmcx_dll_ctl3 { 1550 uint64_t u64; 1551 struct cvmx_lmcx_dll_ctl3_s { 1552 #ifdef __BIG_ENDIAN_BITFIELD 1553 uint64_t reserved_41_63:23; 1554 uint64_t dclk90_fwd:1; 1555 uint64_t ddr_90_dly_byp:1; 1556 uint64_t dclk90_recal_dis:1; 1557 uint64_t dclk90_byp_sel:1; 1558 uint64_t dclk90_byp_setting:8; 1559 uint64_t dll_fast:1; 1560 uint64_t dll90_setting:8; 1561 uint64_t fine_tune_mode:1; 1562 uint64_t dll_mode:1; 1563 uint64_t dll90_byte_sel:4; 1564 uint64_t offset_ena:1; 1565 uint64_t load_offset:1; 1566 uint64_t mode_sel:2; 1567 uint64_t byte_sel:4; 1568 uint64_t offset:6; 1569 #else 1570 uint64_t offset:6; 1571 uint64_t byte_sel:4; 1572 uint64_t mode_sel:2; 1573 uint64_t load_offset:1; 1574 uint64_t offset_ena:1; 1575 uint64_t dll90_byte_sel:4; 1576 uint64_t dll_mode:1; 1577 uint64_t fine_tune_mode:1; 1578 uint64_t dll90_setting:8; 1579 uint64_t dll_fast:1; 1580 uint64_t dclk90_byp_setting:8; 1581 uint64_t dclk90_byp_sel:1; 1582 uint64_t dclk90_recal_dis:1; 1583 uint64_t ddr_90_dly_byp:1; 1584 uint64_t dclk90_fwd:1; 1585 uint64_t reserved_41_63:23; 1586 #endif 1587 } s; 1588 struct cvmx_lmcx_dll_ctl3_cn63xx { 1589 #ifdef __BIG_ENDIAN_BITFIELD 1590 uint64_t reserved_29_63:35; 1591 uint64_t dll_fast:1; 1592 uint64_t dll90_setting:8; 1593 uint64_t fine_tune_mode:1; 1594 uint64_t dll_mode:1; 1595 uint64_t dll90_byte_sel:4; 1596 uint64_t offset_ena:1; 1597 uint64_t load_offset:1; 1598 uint64_t mode_sel:2; 1599 uint64_t byte_sel:4; 1600 uint64_t offset:6; 1601 #else 1602 uint64_t offset:6; 1603 uint64_t byte_sel:4; 1604 uint64_t mode_sel:2; 1605 uint64_t load_offset:1; 1606 uint64_t offset_ena:1; 1607 uint64_t dll90_byte_sel:4; 1608 uint64_t dll_mode:1; 1609 uint64_t fine_tune_mode:1; 1610 uint64_t dll90_setting:8; 1611 uint64_t dll_fast:1; 1612 uint64_t reserved_29_63:35; 1613 #endif 1614 } cn63xx; 1615 }; 1616 1617 union cvmx_lmcx_dual_memcfg { 1618 uint64_t u64; 1619 struct cvmx_lmcx_dual_memcfg_s { 1620 #ifdef __BIG_ENDIAN_BITFIELD 1621 uint64_t reserved_20_63:44; 1622 uint64_t bank8:1; 1623 uint64_t row_lsb:3; 1624 uint64_t reserved_8_15:8; 1625 uint64_t cs_mask:8; 1626 #else 1627 uint64_t cs_mask:8; 1628 uint64_t reserved_8_15:8; 1629 uint64_t row_lsb:3; 1630 uint64_t bank8:1; 1631 uint64_t reserved_20_63:44; 1632 #endif 1633 } s; 1634 struct cvmx_lmcx_dual_memcfg_cn61xx { 1635 #ifdef __BIG_ENDIAN_BITFIELD 1636 uint64_t reserved_19_63:45; 1637 uint64_t row_lsb:3; 1638 uint64_t reserved_8_15:8; 1639 uint64_t cs_mask:8; 1640 #else 1641 uint64_t cs_mask:8; 1642 uint64_t reserved_8_15:8; 1643 uint64_t row_lsb:3; 1644 uint64_t reserved_19_63:45; 1645 #endif 1646 } cn61xx; 1647 }; 1648 1649 union cvmx_lmcx_ecc_synd { 1650 uint64_t u64; 1651 struct cvmx_lmcx_ecc_synd_s { 1652 #ifdef __BIG_ENDIAN_BITFIELD 1653 uint64_t reserved_32_63:32; 1654 uint64_t mrdsyn3:8; 1655 uint64_t mrdsyn2:8; 1656 uint64_t mrdsyn1:8; 1657 uint64_t mrdsyn0:8; 1658 #else 1659 uint64_t mrdsyn0:8; 1660 uint64_t mrdsyn1:8; 1661 uint64_t mrdsyn2:8; 1662 uint64_t mrdsyn3:8; 1663 uint64_t reserved_32_63:32; 1664 #endif 1665 } s; 1666 }; 1667 1668 union cvmx_lmcx_fadr { 1669 uint64_t u64; 1670 struct cvmx_lmcx_fadr_s { 1671 #ifdef __BIG_ENDIAN_BITFIELD 1672 uint64_t reserved_0_63:64; 1673 #else 1674 uint64_t reserved_0_63:64; 1675 #endif 1676 } s; 1677 struct cvmx_lmcx_fadr_cn30xx { 1678 #ifdef __BIG_ENDIAN_BITFIELD 1679 uint64_t reserved_32_63:32; 1680 uint64_t fdimm:2; 1681 uint64_t fbunk:1; 1682 uint64_t fbank:3; 1683 uint64_t frow:14; 1684 uint64_t fcol:12; 1685 #else 1686 uint64_t fcol:12; 1687 uint64_t frow:14; 1688 uint64_t fbank:3; 1689 uint64_t fbunk:1; 1690 uint64_t fdimm:2; 1691 uint64_t reserved_32_63:32; 1692 #endif 1693 } cn30xx; 1694 struct cvmx_lmcx_fadr_cn61xx { 1695 #ifdef __BIG_ENDIAN_BITFIELD 1696 uint64_t reserved_36_63:28; 1697 uint64_t fdimm:2; 1698 uint64_t fbunk:1; 1699 uint64_t fbank:3; 1700 uint64_t frow:16; 1701 uint64_t fcol:14; 1702 #else 1703 uint64_t fcol:14; 1704 uint64_t frow:16; 1705 uint64_t fbank:3; 1706 uint64_t fbunk:1; 1707 uint64_t fdimm:2; 1708 uint64_t reserved_36_63:28; 1709 #endif 1710 } cn61xx; 1711 }; 1712 1713 union cvmx_lmcx_ifb_cnt { 1714 uint64_t u64; 1715 struct cvmx_lmcx_ifb_cnt_s { 1716 #ifdef __BIG_ENDIAN_BITFIELD 1717 uint64_t ifbcnt:64; 1718 #else 1719 uint64_t ifbcnt:64; 1720 #endif 1721 } s; 1722 }; 1723 1724 union cvmx_lmcx_ifb_cnt_hi { 1725 uint64_t u64; 1726 struct cvmx_lmcx_ifb_cnt_hi_s { 1727 #ifdef __BIG_ENDIAN_BITFIELD 1728 uint64_t reserved_32_63:32; 1729 uint64_t ifbcnt_hi:32; 1730 #else 1731 uint64_t ifbcnt_hi:32; 1732 uint64_t reserved_32_63:32; 1733 #endif 1734 } s; 1735 }; 1736 1737 union cvmx_lmcx_ifb_cnt_lo { 1738 uint64_t u64; 1739 struct cvmx_lmcx_ifb_cnt_lo_s { 1740 #ifdef __BIG_ENDIAN_BITFIELD 1741 uint64_t reserved_32_63:32; 1742 uint64_t ifbcnt_lo:32; 1743 #else 1744 uint64_t ifbcnt_lo:32; 1745 uint64_t reserved_32_63:32; 1746 #endif 1747 } s; 1748 }; 1749 1750 union cvmx_lmcx_int { 1751 uint64_t u64; 1752 struct cvmx_lmcx_int_s { 1753 #ifdef __BIG_ENDIAN_BITFIELD 1754 uint64_t reserved_9_63:55; 1755 uint64_t ded_err:4; 1756 uint64_t sec_err:4; 1757 uint64_t nxm_wr_err:1; 1758 #else 1759 uint64_t nxm_wr_err:1; 1760 uint64_t sec_err:4; 1761 uint64_t ded_err:4; 1762 uint64_t reserved_9_63:55; 1763 #endif 1764 } s; 1765 }; 1766 1767 union cvmx_lmcx_int_en { 1768 uint64_t u64; 1769 struct cvmx_lmcx_int_en_s { 1770 #ifdef __BIG_ENDIAN_BITFIELD 1771 uint64_t reserved_3_63:61; 1772 uint64_t intr_ded_ena:1; 1773 uint64_t intr_sec_ena:1; 1774 uint64_t intr_nxm_wr_ena:1; 1775 #else 1776 uint64_t intr_nxm_wr_ena:1; 1777 uint64_t intr_sec_ena:1; 1778 uint64_t intr_ded_ena:1; 1779 uint64_t reserved_3_63:61; 1780 #endif 1781 } s; 1782 }; 1783 1784 union cvmx_lmcx_mem_cfg0 { 1785 uint64_t u64; 1786 struct cvmx_lmcx_mem_cfg0_s { 1787 #ifdef __BIG_ENDIAN_BITFIELD 1788 uint64_t reserved_32_63:32; 1789 uint64_t reset:1; 1790 uint64_t silo_qc:1; 1791 uint64_t bunk_ena:1; 1792 uint64_t ded_err:4; 1793 uint64_t sec_err:4; 1794 uint64_t intr_ded_ena:1; 1795 uint64_t intr_sec_ena:1; 1796 uint64_t tcl:4; 1797 uint64_t ref_int:6; 1798 uint64_t pbank_lsb:4; 1799 uint64_t row_lsb:3; 1800 uint64_t ecc_ena:1; 1801 uint64_t init_start:1; 1802 #else 1803 uint64_t init_start:1; 1804 uint64_t ecc_ena:1; 1805 uint64_t row_lsb:3; 1806 uint64_t pbank_lsb:4; 1807 uint64_t ref_int:6; 1808 uint64_t tcl:4; 1809 uint64_t intr_sec_ena:1; 1810 uint64_t intr_ded_ena:1; 1811 uint64_t sec_err:4; 1812 uint64_t ded_err:4; 1813 uint64_t bunk_ena:1; 1814 uint64_t silo_qc:1; 1815 uint64_t reset:1; 1816 uint64_t reserved_32_63:32; 1817 #endif 1818 } s; 1819 }; 1820 1821 union cvmx_lmcx_mem_cfg1 { 1822 uint64_t u64; 1823 struct cvmx_lmcx_mem_cfg1_s { 1824 #ifdef __BIG_ENDIAN_BITFIELD 1825 uint64_t reserved_32_63:32; 1826 uint64_t comp_bypass:1; 1827 uint64_t trrd:3; 1828 uint64_t caslat:3; 1829 uint64_t tmrd:3; 1830 uint64_t trfc:5; 1831 uint64_t trp:4; 1832 uint64_t twtr:4; 1833 uint64_t trcd:4; 1834 uint64_t tras:5; 1835 #else 1836 uint64_t tras:5; 1837 uint64_t trcd:4; 1838 uint64_t twtr:4; 1839 uint64_t trp:4; 1840 uint64_t trfc:5; 1841 uint64_t tmrd:3; 1842 uint64_t caslat:3; 1843 uint64_t trrd:3; 1844 uint64_t comp_bypass:1; 1845 uint64_t reserved_32_63:32; 1846 #endif 1847 } s; 1848 struct cvmx_lmcx_mem_cfg1_cn38xx { 1849 #ifdef __BIG_ENDIAN_BITFIELD 1850 uint64_t reserved_31_63:33; 1851 uint64_t trrd:3; 1852 uint64_t caslat:3; 1853 uint64_t tmrd:3; 1854 uint64_t trfc:5; 1855 uint64_t trp:4; 1856 uint64_t twtr:4; 1857 uint64_t trcd:4; 1858 uint64_t tras:5; 1859 #else 1860 uint64_t tras:5; 1861 uint64_t trcd:4; 1862 uint64_t twtr:4; 1863 uint64_t trp:4; 1864 uint64_t trfc:5; 1865 uint64_t tmrd:3; 1866 uint64_t caslat:3; 1867 uint64_t trrd:3; 1868 uint64_t reserved_31_63:33; 1869 #endif 1870 } cn38xx; 1871 }; 1872 1873 union cvmx_lmcx_modereg_params0 { 1874 uint64_t u64; 1875 struct cvmx_lmcx_modereg_params0_s { 1876 #ifdef __BIG_ENDIAN_BITFIELD 1877 uint64_t reserved_25_63:39; 1878 uint64_t ppd:1; 1879 uint64_t wrp:3; 1880 uint64_t dllr:1; 1881 uint64_t tm:1; 1882 uint64_t rbt:1; 1883 uint64_t cl:4; 1884 uint64_t bl:2; 1885 uint64_t qoff:1; 1886 uint64_t tdqs:1; 1887 uint64_t wlev:1; 1888 uint64_t al:2; 1889 uint64_t dll:1; 1890 uint64_t mpr:1; 1891 uint64_t mprloc:2; 1892 uint64_t cwl:3; 1893 #else 1894 uint64_t cwl:3; 1895 uint64_t mprloc:2; 1896 uint64_t mpr:1; 1897 uint64_t dll:1; 1898 uint64_t al:2; 1899 uint64_t wlev:1; 1900 uint64_t tdqs:1; 1901 uint64_t qoff:1; 1902 uint64_t bl:2; 1903 uint64_t cl:4; 1904 uint64_t rbt:1; 1905 uint64_t tm:1; 1906 uint64_t dllr:1; 1907 uint64_t wrp:3; 1908 uint64_t ppd:1; 1909 uint64_t reserved_25_63:39; 1910 #endif 1911 } s; 1912 }; 1913 1914 union cvmx_lmcx_modereg_params1 { 1915 uint64_t u64; 1916 struct cvmx_lmcx_modereg_params1_s { 1917 #ifdef __BIG_ENDIAN_BITFIELD 1918 uint64_t reserved_48_63:16; 1919 uint64_t rtt_nom_11:3; 1920 uint64_t dic_11:2; 1921 uint64_t rtt_wr_11:2; 1922 uint64_t srt_11:1; 1923 uint64_t asr_11:1; 1924 uint64_t pasr_11:3; 1925 uint64_t rtt_nom_10:3; 1926 uint64_t dic_10:2; 1927 uint64_t rtt_wr_10:2; 1928 uint64_t srt_10:1; 1929 uint64_t asr_10:1; 1930 uint64_t pasr_10:3; 1931 uint64_t rtt_nom_01:3; 1932 uint64_t dic_01:2; 1933 uint64_t rtt_wr_01:2; 1934 uint64_t srt_01:1; 1935 uint64_t asr_01:1; 1936 uint64_t pasr_01:3; 1937 uint64_t rtt_nom_00:3; 1938 uint64_t dic_00:2; 1939 uint64_t rtt_wr_00:2; 1940 uint64_t srt_00:1; 1941 uint64_t asr_00:1; 1942 uint64_t pasr_00:3; 1943 #else 1944 uint64_t pasr_00:3; 1945 uint64_t asr_00:1; 1946 uint64_t srt_00:1; 1947 uint64_t rtt_wr_00:2; 1948 uint64_t dic_00:2; 1949 uint64_t rtt_nom_00:3; 1950 uint64_t pasr_01:3; 1951 uint64_t asr_01:1; 1952 uint64_t srt_01:1; 1953 uint64_t rtt_wr_01:2; 1954 uint64_t dic_01:2; 1955 uint64_t rtt_nom_01:3; 1956 uint64_t pasr_10:3; 1957 uint64_t asr_10:1; 1958 uint64_t srt_10:1; 1959 uint64_t rtt_wr_10:2; 1960 uint64_t dic_10:2; 1961 uint64_t rtt_nom_10:3; 1962 uint64_t pasr_11:3; 1963 uint64_t asr_11:1; 1964 uint64_t srt_11:1; 1965 uint64_t rtt_wr_11:2; 1966 uint64_t dic_11:2; 1967 uint64_t rtt_nom_11:3; 1968 uint64_t reserved_48_63:16; 1969 #endif 1970 } s; 1971 }; 1972 1973 union cvmx_lmcx_nxm { 1974 uint64_t u64; 1975 struct cvmx_lmcx_nxm_s { 1976 #ifdef __BIG_ENDIAN_BITFIELD 1977 uint64_t reserved_40_63:24; 1978 uint64_t mem_msb_d3_r1:4; 1979 uint64_t mem_msb_d3_r0:4; 1980 uint64_t mem_msb_d2_r1:4; 1981 uint64_t mem_msb_d2_r0:4; 1982 uint64_t mem_msb_d1_r1:4; 1983 uint64_t mem_msb_d1_r0:4; 1984 uint64_t mem_msb_d0_r1:4; 1985 uint64_t mem_msb_d0_r0:4; 1986 uint64_t cs_mask:8; 1987 #else 1988 uint64_t cs_mask:8; 1989 uint64_t mem_msb_d0_r0:4; 1990 uint64_t mem_msb_d0_r1:4; 1991 uint64_t mem_msb_d1_r0:4; 1992 uint64_t mem_msb_d1_r1:4; 1993 uint64_t mem_msb_d2_r0:4; 1994 uint64_t mem_msb_d2_r1:4; 1995 uint64_t mem_msb_d3_r0:4; 1996 uint64_t mem_msb_d3_r1:4; 1997 uint64_t reserved_40_63:24; 1998 #endif 1999 } s; 2000 struct cvmx_lmcx_nxm_cn52xx { 2001 #ifdef __BIG_ENDIAN_BITFIELD 2002 uint64_t reserved_8_63:56; 2003 uint64_t cs_mask:8; 2004 #else 2005 uint64_t cs_mask:8; 2006 uint64_t reserved_8_63:56; 2007 #endif 2008 } cn52xx; 2009 }; 2010 2011 union cvmx_lmcx_ops_cnt { 2012 uint64_t u64; 2013 struct cvmx_lmcx_ops_cnt_s { 2014 #ifdef __BIG_ENDIAN_BITFIELD 2015 uint64_t opscnt:64; 2016 #else 2017 uint64_t opscnt:64; 2018 #endif 2019 } s; 2020 }; 2021 2022 union cvmx_lmcx_ops_cnt_hi { 2023 uint64_t u64; 2024 struct cvmx_lmcx_ops_cnt_hi_s { 2025 #ifdef __BIG_ENDIAN_BITFIELD 2026 uint64_t reserved_32_63:32; 2027 uint64_t opscnt_hi:32; 2028 #else 2029 uint64_t opscnt_hi:32; 2030 uint64_t reserved_32_63:32; 2031 #endif 2032 } s; 2033 }; 2034 2035 union cvmx_lmcx_ops_cnt_lo { 2036 uint64_t u64; 2037 struct cvmx_lmcx_ops_cnt_lo_s { 2038 #ifdef __BIG_ENDIAN_BITFIELD 2039 uint64_t reserved_32_63:32; 2040 uint64_t opscnt_lo:32; 2041 #else 2042 uint64_t opscnt_lo:32; 2043 uint64_t reserved_32_63:32; 2044 #endif 2045 } s; 2046 }; 2047 2048 union cvmx_lmcx_phy_ctl { 2049 uint64_t u64; 2050 struct cvmx_lmcx_phy_ctl_s { 2051 #ifdef __BIG_ENDIAN_BITFIELD 2052 uint64_t reserved_15_63:49; 2053 uint64_t rx_always_on:1; 2054 uint64_t lv_mode:1; 2055 uint64_t ck_tune1:1; 2056 uint64_t ck_dlyout1:4; 2057 uint64_t ck_tune0:1; 2058 uint64_t ck_dlyout0:4; 2059 uint64_t loopback:1; 2060 uint64_t loopback_pos:1; 2061 uint64_t ts_stagger:1; 2062 #else 2063 uint64_t ts_stagger:1; 2064 uint64_t loopback_pos:1; 2065 uint64_t loopback:1; 2066 uint64_t ck_dlyout0:4; 2067 uint64_t ck_tune0:1; 2068 uint64_t ck_dlyout1:4; 2069 uint64_t ck_tune1:1; 2070 uint64_t lv_mode:1; 2071 uint64_t rx_always_on:1; 2072 uint64_t reserved_15_63:49; 2073 #endif 2074 } s; 2075 struct cvmx_lmcx_phy_ctl_cn63xxp1 { 2076 #ifdef __BIG_ENDIAN_BITFIELD 2077 uint64_t reserved_14_63:50; 2078 uint64_t lv_mode:1; 2079 uint64_t ck_tune1:1; 2080 uint64_t ck_dlyout1:4; 2081 uint64_t ck_tune0:1; 2082 uint64_t ck_dlyout0:4; 2083 uint64_t loopback:1; 2084 uint64_t loopback_pos:1; 2085 uint64_t ts_stagger:1; 2086 #else 2087 uint64_t ts_stagger:1; 2088 uint64_t loopback_pos:1; 2089 uint64_t loopback:1; 2090 uint64_t ck_dlyout0:4; 2091 uint64_t ck_tune0:1; 2092 uint64_t ck_dlyout1:4; 2093 uint64_t ck_tune1:1; 2094 uint64_t lv_mode:1; 2095 uint64_t reserved_14_63:50; 2096 #endif 2097 } cn63xxp1; 2098 }; 2099 2100 union cvmx_lmcx_pll_bwctl { 2101 uint64_t u64; 2102 struct cvmx_lmcx_pll_bwctl_s { 2103 #ifdef __BIG_ENDIAN_BITFIELD 2104 uint64_t reserved_5_63:59; 2105 uint64_t bwupd:1; 2106 uint64_t bwctl:4; 2107 #else 2108 uint64_t bwctl:4; 2109 uint64_t bwupd:1; 2110 uint64_t reserved_5_63:59; 2111 #endif 2112 } s; 2113 }; 2114 2115 union cvmx_lmcx_pll_ctl { 2116 uint64_t u64; 2117 struct cvmx_lmcx_pll_ctl_s { 2118 #ifdef __BIG_ENDIAN_BITFIELD 2119 uint64_t reserved_30_63:34; 2120 uint64_t bypass:1; 2121 uint64_t fasten_n:1; 2122 uint64_t div_reset:1; 2123 uint64_t reset_n:1; 2124 uint64_t clkf:12; 2125 uint64_t clkr:6; 2126 uint64_t reserved_6_7:2; 2127 uint64_t en16:1; 2128 uint64_t en12:1; 2129 uint64_t en8:1; 2130 uint64_t en6:1; 2131 uint64_t en4:1; 2132 uint64_t en2:1; 2133 #else 2134 uint64_t en2:1; 2135 uint64_t en4:1; 2136 uint64_t en6:1; 2137 uint64_t en8:1; 2138 uint64_t en12:1; 2139 uint64_t en16:1; 2140 uint64_t reserved_6_7:2; 2141 uint64_t clkr:6; 2142 uint64_t clkf:12; 2143 uint64_t reset_n:1; 2144 uint64_t div_reset:1; 2145 uint64_t fasten_n:1; 2146 uint64_t bypass:1; 2147 uint64_t reserved_30_63:34; 2148 #endif 2149 } s; 2150 struct cvmx_lmcx_pll_ctl_cn50xx { 2151 #ifdef __BIG_ENDIAN_BITFIELD 2152 uint64_t reserved_29_63:35; 2153 uint64_t fasten_n:1; 2154 uint64_t div_reset:1; 2155 uint64_t reset_n:1; 2156 uint64_t clkf:12; 2157 uint64_t clkr:6; 2158 uint64_t reserved_6_7:2; 2159 uint64_t en16:1; 2160 uint64_t en12:1; 2161 uint64_t en8:1; 2162 uint64_t en6:1; 2163 uint64_t en4:1; 2164 uint64_t en2:1; 2165 #else 2166 uint64_t en2:1; 2167 uint64_t en4:1; 2168 uint64_t en6:1; 2169 uint64_t en8:1; 2170 uint64_t en12:1; 2171 uint64_t en16:1; 2172 uint64_t reserved_6_7:2; 2173 uint64_t clkr:6; 2174 uint64_t clkf:12; 2175 uint64_t reset_n:1; 2176 uint64_t div_reset:1; 2177 uint64_t fasten_n:1; 2178 uint64_t reserved_29_63:35; 2179 #endif 2180 } cn50xx; 2181 struct cvmx_lmcx_pll_ctl_cn56xxp1 { 2182 #ifdef __BIG_ENDIAN_BITFIELD 2183 uint64_t reserved_28_63:36; 2184 uint64_t div_reset:1; 2185 uint64_t reset_n:1; 2186 uint64_t clkf:12; 2187 uint64_t clkr:6; 2188 uint64_t reserved_6_7:2; 2189 uint64_t en16:1; 2190 uint64_t en12:1; 2191 uint64_t en8:1; 2192 uint64_t en6:1; 2193 uint64_t en4:1; 2194 uint64_t en2:1; 2195 #else 2196 uint64_t en2:1; 2197 uint64_t en4:1; 2198 uint64_t en6:1; 2199 uint64_t en8:1; 2200 uint64_t en12:1; 2201 uint64_t en16:1; 2202 uint64_t reserved_6_7:2; 2203 uint64_t clkr:6; 2204 uint64_t clkf:12; 2205 uint64_t reset_n:1; 2206 uint64_t div_reset:1; 2207 uint64_t reserved_28_63:36; 2208 #endif 2209 } cn56xxp1; 2210 }; 2211 2212 union cvmx_lmcx_pll_status { 2213 uint64_t u64; 2214 struct cvmx_lmcx_pll_status_s { 2215 #ifdef __BIG_ENDIAN_BITFIELD 2216 uint64_t reserved_32_63:32; 2217 uint64_t ddr__nctl:5; 2218 uint64_t ddr__pctl:5; 2219 uint64_t reserved_2_21:20; 2220 uint64_t rfslip:1; 2221 uint64_t fbslip:1; 2222 #else 2223 uint64_t fbslip:1; 2224 uint64_t rfslip:1; 2225 uint64_t reserved_2_21:20; 2226 uint64_t ddr__pctl:5; 2227 uint64_t ddr__nctl:5; 2228 uint64_t reserved_32_63:32; 2229 #endif 2230 } s; 2231 struct cvmx_lmcx_pll_status_cn58xxp1 { 2232 #ifdef __BIG_ENDIAN_BITFIELD 2233 uint64_t reserved_2_63:62; 2234 uint64_t rfslip:1; 2235 uint64_t fbslip:1; 2236 #else 2237 uint64_t fbslip:1; 2238 uint64_t rfslip:1; 2239 uint64_t reserved_2_63:62; 2240 #endif 2241 } cn58xxp1; 2242 }; 2243 2244 union cvmx_lmcx_read_level_ctl { 2245 uint64_t u64; 2246 struct cvmx_lmcx_read_level_ctl_s { 2247 #ifdef __BIG_ENDIAN_BITFIELD 2248 uint64_t reserved_44_63:20; 2249 uint64_t rankmask:4; 2250 uint64_t pattern:8; 2251 uint64_t row:16; 2252 uint64_t col:12; 2253 uint64_t reserved_3_3:1; 2254 uint64_t bnk:3; 2255 #else 2256 uint64_t bnk:3; 2257 uint64_t reserved_3_3:1; 2258 uint64_t col:12; 2259 uint64_t row:16; 2260 uint64_t pattern:8; 2261 uint64_t rankmask:4; 2262 uint64_t reserved_44_63:20; 2263 #endif 2264 } s; 2265 }; 2266 2267 union cvmx_lmcx_read_level_dbg { 2268 uint64_t u64; 2269 struct cvmx_lmcx_read_level_dbg_s { 2270 #ifdef __BIG_ENDIAN_BITFIELD 2271 uint64_t reserved_32_63:32; 2272 uint64_t bitmask:16; 2273 uint64_t reserved_4_15:12; 2274 uint64_t byte:4; 2275 #else 2276 uint64_t byte:4; 2277 uint64_t reserved_4_15:12; 2278 uint64_t bitmask:16; 2279 uint64_t reserved_32_63:32; 2280 #endif 2281 } s; 2282 }; 2283 2284 union cvmx_lmcx_read_level_rankx { 2285 uint64_t u64; 2286 struct cvmx_lmcx_read_level_rankx_s { 2287 #ifdef __BIG_ENDIAN_BITFIELD 2288 uint64_t reserved_38_63:26; 2289 uint64_t status:2; 2290 uint64_t byte8:4; 2291 uint64_t byte7:4; 2292 uint64_t byte6:4; 2293 uint64_t byte5:4; 2294 uint64_t byte4:4; 2295 uint64_t byte3:4; 2296 uint64_t byte2:4; 2297 uint64_t byte1:4; 2298 uint64_t byte0:4; 2299 #else 2300 uint64_t byte0:4; 2301 uint64_t byte1:4; 2302 uint64_t byte2:4; 2303 uint64_t byte3:4; 2304 uint64_t byte4:4; 2305 uint64_t byte5:4; 2306 uint64_t byte6:4; 2307 uint64_t byte7:4; 2308 uint64_t byte8:4; 2309 uint64_t status:2; 2310 uint64_t reserved_38_63:26; 2311 #endif 2312 } s; 2313 }; 2314 2315 union cvmx_lmcx_reset_ctl { 2316 uint64_t u64; 2317 struct cvmx_lmcx_reset_ctl_s { 2318 #ifdef __BIG_ENDIAN_BITFIELD 2319 uint64_t reserved_4_63:60; 2320 uint64_t ddr3psv:1; 2321 uint64_t ddr3psoft:1; 2322 uint64_t ddr3pwarm:1; 2323 uint64_t ddr3rst:1; 2324 #else 2325 uint64_t ddr3rst:1; 2326 uint64_t ddr3pwarm:1; 2327 uint64_t ddr3psoft:1; 2328 uint64_t ddr3psv:1; 2329 uint64_t reserved_4_63:60; 2330 #endif 2331 } s; 2332 }; 2333 2334 union cvmx_lmcx_rlevel_ctl { 2335 uint64_t u64; 2336 struct cvmx_lmcx_rlevel_ctl_s { 2337 #ifdef __BIG_ENDIAN_BITFIELD 2338 uint64_t reserved_22_63:42; 2339 uint64_t delay_unload_3:1; 2340 uint64_t delay_unload_2:1; 2341 uint64_t delay_unload_1:1; 2342 uint64_t delay_unload_0:1; 2343 uint64_t bitmask:8; 2344 uint64_t or_dis:1; 2345 uint64_t offset_en:1; 2346 uint64_t offset:4; 2347 uint64_t byte:4; 2348 #else 2349 uint64_t byte:4; 2350 uint64_t offset:4; 2351 uint64_t offset_en:1; 2352 uint64_t or_dis:1; 2353 uint64_t bitmask:8; 2354 uint64_t delay_unload_0:1; 2355 uint64_t delay_unload_1:1; 2356 uint64_t delay_unload_2:1; 2357 uint64_t delay_unload_3:1; 2358 uint64_t reserved_22_63:42; 2359 #endif 2360 } s; 2361 struct cvmx_lmcx_rlevel_ctl_cn63xxp1 { 2362 #ifdef __BIG_ENDIAN_BITFIELD 2363 uint64_t reserved_9_63:55; 2364 uint64_t offset_en:1; 2365 uint64_t offset:4; 2366 uint64_t byte:4; 2367 #else 2368 uint64_t byte:4; 2369 uint64_t offset:4; 2370 uint64_t offset_en:1; 2371 uint64_t reserved_9_63:55; 2372 #endif 2373 } cn63xxp1; 2374 }; 2375 2376 union cvmx_lmcx_rlevel_dbg { 2377 uint64_t u64; 2378 struct cvmx_lmcx_rlevel_dbg_s { 2379 #ifdef __BIG_ENDIAN_BITFIELD 2380 uint64_t bitmask:64; 2381 #else 2382 uint64_t bitmask:64; 2383 #endif 2384 } s; 2385 }; 2386 2387 union cvmx_lmcx_rlevel_rankx { 2388 uint64_t u64; 2389 struct cvmx_lmcx_rlevel_rankx_s { 2390 #ifdef __BIG_ENDIAN_BITFIELD 2391 uint64_t reserved_56_63:8; 2392 uint64_t status:2; 2393 uint64_t byte8:6; 2394 uint64_t byte7:6; 2395 uint64_t byte6:6; 2396 uint64_t byte5:6; 2397 uint64_t byte4:6; 2398 uint64_t byte3:6; 2399 uint64_t byte2:6; 2400 uint64_t byte1:6; 2401 uint64_t byte0:6; 2402 #else 2403 uint64_t byte0:6; 2404 uint64_t byte1:6; 2405 uint64_t byte2:6; 2406 uint64_t byte3:6; 2407 uint64_t byte4:6; 2408 uint64_t byte5:6; 2409 uint64_t byte6:6; 2410 uint64_t byte7:6; 2411 uint64_t byte8:6; 2412 uint64_t status:2; 2413 uint64_t reserved_56_63:8; 2414 #endif 2415 } s; 2416 }; 2417 2418 union cvmx_lmcx_rodt_comp_ctl { 2419 uint64_t u64; 2420 struct cvmx_lmcx_rodt_comp_ctl_s { 2421 #ifdef __BIG_ENDIAN_BITFIELD 2422 uint64_t reserved_17_63:47; 2423 uint64_t enable:1; 2424 uint64_t reserved_12_15:4; 2425 uint64_t nctl:4; 2426 uint64_t reserved_5_7:3; 2427 uint64_t pctl:5; 2428 #else 2429 uint64_t pctl:5; 2430 uint64_t reserved_5_7:3; 2431 uint64_t nctl:4; 2432 uint64_t reserved_12_15:4; 2433 uint64_t enable:1; 2434 uint64_t reserved_17_63:47; 2435 #endif 2436 } s; 2437 }; 2438 2439 union cvmx_lmcx_rodt_ctl { 2440 uint64_t u64; 2441 struct cvmx_lmcx_rodt_ctl_s { 2442 #ifdef __BIG_ENDIAN_BITFIELD 2443 uint64_t reserved_32_63:32; 2444 uint64_t rodt_hi3:4; 2445 uint64_t rodt_hi2:4; 2446 uint64_t rodt_hi1:4; 2447 uint64_t rodt_hi0:4; 2448 uint64_t rodt_lo3:4; 2449 uint64_t rodt_lo2:4; 2450 uint64_t rodt_lo1:4; 2451 uint64_t rodt_lo0:4; 2452 #else 2453 uint64_t rodt_lo0:4; 2454 uint64_t rodt_lo1:4; 2455 uint64_t rodt_lo2:4; 2456 uint64_t rodt_lo3:4; 2457 uint64_t rodt_hi0:4; 2458 uint64_t rodt_hi1:4; 2459 uint64_t rodt_hi2:4; 2460 uint64_t rodt_hi3:4; 2461 uint64_t reserved_32_63:32; 2462 #endif 2463 } s; 2464 }; 2465 2466 union cvmx_lmcx_rodt_mask { 2467 uint64_t u64; 2468 struct cvmx_lmcx_rodt_mask_s { 2469 #ifdef __BIG_ENDIAN_BITFIELD 2470 uint64_t rodt_d3_r1:8; 2471 uint64_t rodt_d3_r0:8; 2472 uint64_t rodt_d2_r1:8; 2473 uint64_t rodt_d2_r0:8; 2474 uint64_t rodt_d1_r1:8; 2475 uint64_t rodt_d1_r0:8; 2476 uint64_t rodt_d0_r1:8; 2477 uint64_t rodt_d0_r0:8; 2478 #else 2479 uint64_t rodt_d0_r0:8; 2480 uint64_t rodt_d0_r1:8; 2481 uint64_t rodt_d1_r0:8; 2482 uint64_t rodt_d1_r1:8; 2483 uint64_t rodt_d2_r0:8; 2484 uint64_t rodt_d2_r1:8; 2485 uint64_t rodt_d3_r0:8; 2486 uint64_t rodt_d3_r1:8; 2487 #endif 2488 } s; 2489 }; 2490 2491 union cvmx_lmcx_scramble_cfg0 { 2492 uint64_t u64; 2493 struct cvmx_lmcx_scramble_cfg0_s { 2494 #ifdef __BIG_ENDIAN_BITFIELD 2495 uint64_t key:64; 2496 #else 2497 uint64_t key:64; 2498 #endif 2499 } s; 2500 }; 2501 2502 union cvmx_lmcx_scramble_cfg1 { 2503 uint64_t u64; 2504 struct cvmx_lmcx_scramble_cfg1_s { 2505 #ifdef __BIG_ENDIAN_BITFIELD 2506 uint64_t key:64; 2507 #else 2508 uint64_t key:64; 2509 #endif 2510 } s; 2511 }; 2512 2513 union cvmx_lmcx_scrambled_fadr { 2514 uint64_t u64; 2515 struct cvmx_lmcx_scrambled_fadr_s { 2516 #ifdef __BIG_ENDIAN_BITFIELD 2517 uint64_t reserved_36_63:28; 2518 uint64_t fdimm:2; 2519 uint64_t fbunk:1; 2520 uint64_t fbank:3; 2521 uint64_t frow:16; 2522 uint64_t fcol:14; 2523 #else 2524 uint64_t fcol:14; 2525 uint64_t frow:16; 2526 uint64_t fbank:3; 2527 uint64_t fbunk:1; 2528 uint64_t fdimm:2; 2529 uint64_t reserved_36_63:28; 2530 #endif 2531 } s; 2532 }; 2533 2534 union cvmx_lmcx_slot_ctl0 { 2535 uint64_t u64; 2536 struct cvmx_lmcx_slot_ctl0_s { 2537 #ifdef __BIG_ENDIAN_BITFIELD 2538 uint64_t reserved_24_63:40; 2539 uint64_t w2w_init:6; 2540 uint64_t w2r_init:6; 2541 uint64_t r2w_init:6; 2542 uint64_t r2r_init:6; 2543 #else 2544 uint64_t r2r_init:6; 2545 uint64_t r2w_init:6; 2546 uint64_t w2r_init:6; 2547 uint64_t w2w_init:6; 2548 uint64_t reserved_24_63:40; 2549 #endif 2550 } s; 2551 }; 2552 2553 union cvmx_lmcx_slot_ctl1 { 2554 uint64_t u64; 2555 struct cvmx_lmcx_slot_ctl1_s { 2556 #ifdef __BIG_ENDIAN_BITFIELD 2557 uint64_t reserved_24_63:40; 2558 uint64_t w2w_xrank_init:6; 2559 uint64_t w2r_xrank_init:6; 2560 uint64_t r2w_xrank_init:6; 2561 uint64_t r2r_xrank_init:6; 2562 #else 2563 uint64_t r2r_xrank_init:6; 2564 uint64_t r2w_xrank_init:6; 2565 uint64_t w2r_xrank_init:6; 2566 uint64_t w2w_xrank_init:6; 2567 uint64_t reserved_24_63:40; 2568 #endif 2569 } s; 2570 }; 2571 2572 union cvmx_lmcx_slot_ctl2 { 2573 uint64_t u64; 2574 struct cvmx_lmcx_slot_ctl2_s { 2575 #ifdef __BIG_ENDIAN_BITFIELD 2576 uint64_t reserved_24_63:40; 2577 uint64_t w2w_xdimm_init:6; 2578 uint64_t w2r_xdimm_init:6; 2579 uint64_t r2w_xdimm_init:6; 2580 uint64_t r2r_xdimm_init:6; 2581 #else 2582 uint64_t r2r_xdimm_init:6; 2583 uint64_t r2w_xdimm_init:6; 2584 uint64_t w2r_xdimm_init:6; 2585 uint64_t w2w_xdimm_init:6; 2586 uint64_t reserved_24_63:40; 2587 #endif 2588 } s; 2589 }; 2590 2591 union cvmx_lmcx_timing_params0 { 2592 uint64_t u64; 2593 struct cvmx_lmcx_timing_params0_s { 2594 #ifdef __BIG_ENDIAN_BITFIELD 2595 uint64_t reserved_47_63:17; 2596 uint64_t trp_ext:1; 2597 uint64_t tcksre:4; 2598 uint64_t trp:4; 2599 uint64_t tzqinit:4; 2600 uint64_t tdllk:4; 2601 uint64_t tmod:4; 2602 uint64_t tmrd:4; 2603 uint64_t txpr:4; 2604 uint64_t tcke:4; 2605 uint64_t tzqcs:4; 2606 uint64_t tckeon:10; 2607 #else 2608 uint64_t tckeon:10; 2609 uint64_t tzqcs:4; 2610 uint64_t tcke:4; 2611 uint64_t txpr:4; 2612 uint64_t tmrd:4; 2613 uint64_t tmod:4; 2614 uint64_t tdllk:4; 2615 uint64_t tzqinit:4; 2616 uint64_t trp:4; 2617 uint64_t tcksre:4; 2618 uint64_t trp_ext:1; 2619 uint64_t reserved_47_63:17; 2620 #endif 2621 } s; 2622 struct cvmx_lmcx_timing_params0_cn61xx { 2623 #ifdef __BIG_ENDIAN_BITFIELD 2624 uint64_t reserved_47_63:17; 2625 uint64_t trp_ext:1; 2626 uint64_t tcksre:4; 2627 uint64_t trp:4; 2628 uint64_t tzqinit:4; 2629 uint64_t tdllk:4; 2630 uint64_t tmod:4; 2631 uint64_t tmrd:4; 2632 uint64_t txpr:4; 2633 uint64_t tcke:4; 2634 uint64_t tzqcs:4; 2635 uint64_t reserved_0_9:10; 2636 #else 2637 uint64_t reserved_0_9:10; 2638 uint64_t tzqcs:4; 2639 uint64_t tcke:4; 2640 uint64_t txpr:4; 2641 uint64_t tmrd:4; 2642 uint64_t tmod:4; 2643 uint64_t tdllk:4; 2644 uint64_t tzqinit:4; 2645 uint64_t trp:4; 2646 uint64_t tcksre:4; 2647 uint64_t trp_ext:1; 2648 uint64_t reserved_47_63:17; 2649 #endif 2650 } cn61xx; 2651 struct cvmx_lmcx_timing_params0_cn63xxp1 { 2652 #ifdef __BIG_ENDIAN_BITFIELD 2653 uint64_t reserved_46_63:18; 2654 uint64_t tcksre:4; 2655 uint64_t trp:4; 2656 uint64_t tzqinit:4; 2657 uint64_t tdllk:4; 2658 uint64_t tmod:4; 2659 uint64_t tmrd:4; 2660 uint64_t txpr:4; 2661 uint64_t tcke:4; 2662 uint64_t tzqcs:4; 2663 uint64_t tckeon:10; 2664 #else 2665 uint64_t tckeon:10; 2666 uint64_t tzqcs:4; 2667 uint64_t tcke:4; 2668 uint64_t txpr:4; 2669 uint64_t tmrd:4; 2670 uint64_t tmod:4; 2671 uint64_t tdllk:4; 2672 uint64_t tzqinit:4; 2673 uint64_t trp:4; 2674 uint64_t tcksre:4; 2675 uint64_t reserved_46_63:18; 2676 #endif 2677 } cn63xxp1; 2678 }; 2679 2680 union cvmx_lmcx_timing_params1 { 2681 uint64_t u64; 2682 struct cvmx_lmcx_timing_params1_s { 2683 #ifdef __BIG_ENDIAN_BITFIELD 2684 uint64_t reserved_47_63:17; 2685 uint64_t tras_ext:1; 2686 uint64_t txpdll:5; 2687 uint64_t tfaw:5; 2688 uint64_t twldqsen:4; 2689 uint64_t twlmrd:4; 2690 uint64_t txp:3; 2691 uint64_t trrd:3; 2692 uint64_t trfc:5; 2693 uint64_t twtr:4; 2694 uint64_t trcd:4; 2695 uint64_t tras:5; 2696 uint64_t tmprr:4; 2697 #else 2698 uint64_t tmprr:4; 2699 uint64_t tras:5; 2700 uint64_t trcd:4; 2701 uint64_t twtr:4; 2702 uint64_t trfc:5; 2703 uint64_t trrd:3; 2704 uint64_t txp:3; 2705 uint64_t twlmrd:4; 2706 uint64_t twldqsen:4; 2707 uint64_t tfaw:5; 2708 uint64_t txpdll:5; 2709 uint64_t tras_ext:1; 2710 uint64_t reserved_47_63:17; 2711 #endif 2712 } s; 2713 struct cvmx_lmcx_timing_params1_cn63xxp1 { 2714 #ifdef __BIG_ENDIAN_BITFIELD 2715 uint64_t reserved_46_63:18; 2716 uint64_t txpdll:5; 2717 uint64_t tfaw:5; 2718 uint64_t twldqsen:4; 2719 uint64_t twlmrd:4; 2720 uint64_t txp:3; 2721 uint64_t trrd:3; 2722 uint64_t trfc:5; 2723 uint64_t twtr:4; 2724 uint64_t trcd:4; 2725 uint64_t tras:5; 2726 uint64_t tmprr:4; 2727 #else 2728 uint64_t tmprr:4; 2729 uint64_t tras:5; 2730 uint64_t trcd:4; 2731 uint64_t twtr:4; 2732 uint64_t trfc:5; 2733 uint64_t trrd:3; 2734 uint64_t txp:3; 2735 uint64_t twlmrd:4; 2736 uint64_t twldqsen:4; 2737 uint64_t tfaw:5; 2738 uint64_t txpdll:5; 2739 uint64_t reserved_46_63:18; 2740 #endif 2741 } cn63xxp1; 2742 }; 2743 2744 union cvmx_lmcx_tro_ctl { 2745 uint64_t u64; 2746 struct cvmx_lmcx_tro_ctl_s { 2747 #ifdef __BIG_ENDIAN_BITFIELD 2748 uint64_t reserved_33_63:31; 2749 uint64_t rclk_cnt:32; 2750 uint64_t treset:1; 2751 #else 2752 uint64_t treset:1; 2753 uint64_t rclk_cnt:32; 2754 uint64_t reserved_33_63:31; 2755 #endif 2756 } s; 2757 }; 2758 2759 union cvmx_lmcx_tro_stat { 2760 uint64_t u64; 2761 struct cvmx_lmcx_tro_stat_s { 2762 #ifdef __BIG_ENDIAN_BITFIELD 2763 uint64_t reserved_32_63:32; 2764 uint64_t ring_cnt:32; 2765 #else 2766 uint64_t ring_cnt:32; 2767 uint64_t reserved_32_63:32; 2768 #endif 2769 } s; 2770 }; 2771 2772 union cvmx_lmcx_wlevel_ctl { 2773 uint64_t u64; 2774 struct cvmx_lmcx_wlevel_ctl_s { 2775 #ifdef __BIG_ENDIAN_BITFIELD 2776 uint64_t reserved_22_63:42; 2777 uint64_t rtt_nom:3; 2778 uint64_t bitmask:8; 2779 uint64_t or_dis:1; 2780 uint64_t sset:1; 2781 uint64_t lanemask:9; 2782 #else 2783 uint64_t lanemask:9; 2784 uint64_t sset:1; 2785 uint64_t or_dis:1; 2786 uint64_t bitmask:8; 2787 uint64_t rtt_nom:3; 2788 uint64_t reserved_22_63:42; 2789 #endif 2790 } s; 2791 struct cvmx_lmcx_wlevel_ctl_cn63xxp1 { 2792 #ifdef __BIG_ENDIAN_BITFIELD 2793 uint64_t reserved_10_63:54; 2794 uint64_t sset:1; 2795 uint64_t lanemask:9; 2796 #else 2797 uint64_t lanemask:9; 2798 uint64_t sset:1; 2799 uint64_t reserved_10_63:54; 2800 #endif 2801 } cn63xxp1; 2802 }; 2803 2804 union cvmx_lmcx_wlevel_dbg { 2805 uint64_t u64; 2806 struct cvmx_lmcx_wlevel_dbg_s { 2807 #ifdef __BIG_ENDIAN_BITFIELD 2808 uint64_t reserved_12_63:52; 2809 uint64_t bitmask:8; 2810 uint64_t byte:4; 2811 #else 2812 uint64_t byte:4; 2813 uint64_t bitmask:8; 2814 uint64_t reserved_12_63:52; 2815 #endif 2816 } s; 2817 }; 2818 2819 union cvmx_lmcx_wlevel_rankx { 2820 uint64_t u64; 2821 struct cvmx_lmcx_wlevel_rankx_s { 2822 #ifdef __BIG_ENDIAN_BITFIELD 2823 uint64_t reserved_47_63:17; 2824 uint64_t status:2; 2825 uint64_t byte8:5; 2826 uint64_t byte7:5; 2827 uint64_t byte6:5; 2828 uint64_t byte5:5; 2829 uint64_t byte4:5; 2830 uint64_t byte3:5; 2831 uint64_t byte2:5; 2832 uint64_t byte1:5; 2833 uint64_t byte0:5; 2834 #else 2835 uint64_t byte0:5; 2836 uint64_t byte1:5; 2837 uint64_t byte2:5; 2838 uint64_t byte3:5; 2839 uint64_t byte4:5; 2840 uint64_t byte5:5; 2841 uint64_t byte6:5; 2842 uint64_t byte7:5; 2843 uint64_t byte8:5; 2844 uint64_t status:2; 2845 uint64_t reserved_47_63:17; 2846 #endif 2847 } s; 2848 }; 2849 2850 union cvmx_lmcx_wodt_ctl0 { 2851 uint64_t u64; 2852 struct cvmx_lmcx_wodt_ctl0_s { 2853 #ifdef __BIG_ENDIAN_BITFIELD 2854 uint64_t reserved_0_63:64; 2855 #else 2856 uint64_t reserved_0_63:64; 2857 #endif 2858 } s; 2859 struct cvmx_lmcx_wodt_ctl0_cn30xx { 2860 #ifdef __BIG_ENDIAN_BITFIELD 2861 uint64_t reserved_32_63:32; 2862 uint64_t wodt_d1_r1:8; 2863 uint64_t wodt_d1_r0:8; 2864 uint64_t wodt_d0_r1:8; 2865 uint64_t wodt_d0_r0:8; 2866 #else 2867 uint64_t wodt_d0_r0:8; 2868 uint64_t wodt_d0_r1:8; 2869 uint64_t wodt_d1_r0:8; 2870 uint64_t wodt_d1_r1:8; 2871 uint64_t reserved_32_63:32; 2872 #endif 2873 } cn30xx; 2874 struct cvmx_lmcx_wodt_ctl0_cn38xx { 2875 #ifdef __BIG_ENDIAN_BITFIELD 2876 uint64_t reserved_32_63:32; 2877 uint64_t wodt_hi3:4; 2878 uint64_t wodt_hi2:4; 2879 uint64_t wodt_hi1:4; 2880 uint64_t wodt_hi0:4; 2881 uint64_t wodt_lo3:4; 2882 uint64_t wodt_lo2:4; 2883 uint64_t wodt_lo1:4; 2884 uint64_t wodt_lo0:4; 2885 #else 2886 uint64_t wodt_lo0:4; 2887 uint64_t wodt_lo1:4; 2888 uint64_t wodt_lo2:4; 2889 uint64_t wodt_lo3:4; 2890 uint64_t wodt_hi0:4; 2891 uint64_t wodt_hi1:4; 2892 uint64_t wodt_hi2:4; 2893 uint64_t wodt_hi3:4; 2894 uint64_t reserved_32_63:32; 2895 #endif 2896 } cn38xx; 2897 }; 2898 2899 union cvmx_lmcx_wodt_ctl1 { 2900 uint64_t u64; 2901 struct cvmx_lmcx_wodt_ctl1_s { 2902 #ifdef __BIG_ENDIAN_BITFIELD 2903 uint64_t reserved_32_63:32; 2904 uint64_t wodt_d3_r1:8; 2905 uint64_t wodt_d3_r0:8; 2906 uint64_t wodt_d2_r1:8; 2907 uint64_t wodt_d2_r0:8; 2908 #else 2909 uint64_t wodt_d2_r0:8; 2910 uint64_t wodt_d2_r1:8; 2911 uint64_t wodt_d3_r0:8; 2912 uint64_t wodt_d3_r1:8; 2913 uint64_t reserved_32_63:32; 2914 #endif 2915 } s; 2916 }; 2917 2918 union cvmx_lmcx_wodt_mask { 2919 uint64_t u64; 2920 struct cvmx_lmcx_wodt_mask_s { 2921 #ifdef __BIG_ENDIAN_BITFIELD 2922 uint64_t wodt_d3_r1:8; 2923 uint64_t wodt_d3_r0:8; 2924 uint64_t wodt_d2_r1:8; 2925 uint64_t wodt_d2_r0:8; 2926 uint64_t wodt_d1_r1:8; 2927 uint64_t wodt_d1_r0:8; 2928 uint64_t wodt_d0_r1:8; 2929 uint64_t wodt_d0_r0:8; 2930 #else 2931 uint64_t wodt_d0_r0:8; 2932 uint64_t wodt_d0_r1:8; 2933 uint64_t wodt_d1_r0:8; 2934 uint64_t wodt_d1_r1:8; 2935 uint64_t wodt_d2_r0:8; 2936 uint64_t wodt_d2_r1:8; 2937 uint64_t wodt_d3_r0:8; 2938 uint64_t wodt_d3_r1:8; 2939 #endif 2940 } s; 2941 }; 2942 2943 #endif 2944
