1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2019 Pengutronix, Michael Tretter <kernel@pengutronix.de>
4 *
5 * Allegro DVT video encoder driver
6 */
7
8 #include <linux/bits.h>
9 #include <linux/firmware.h>
10 #include <linux/gcd.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/kernel.h>
14 #include <linux/log2.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/regmap.h>
20 #include <linux/sizes.h>
21 #include <linux/slab.h>
22 #include <linux/videodev2.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-event.h>
26 #include <media/v4l2-ioctl.h>
27 #include <media/v4l2-mem2mem.h>
28 #include <media/videobuf2-dma-contig.h>
29 #include <media/videobuf2-v4l2.h>
30
31 #include "allegro-mail.h"
32 #include "nal-h264.h"
33
34 /*
35 * Support up to 4k video streams. The hardware actually supports higher
36 * resolutions, which are specified in PG252 June 6, 2018 (H.264/H.265 Video
37 * Codec Unit v1.1) Chapter 3.
38 */
39 #define ALLEGRO_WIDTH_MIN 128
40 #define ALLEGRO_WIDTH_DEFAULT 1920
41 #define ALLEGRO_WIDTH_MAX 3840
42 #define ALLEGRO_HEIGHT_MIN 64
43 #define ALLEGRO_HEIGHT_DEFAULT 1080
44 #define ALLEGRO_HEIGHT_MAX 2160
45
46 #define ALLEGRO_FRAMERATE_DEFAULT ((struct v4l2_fract) { 30, 1 })
47
48 #define ALLEGRO_GOP_SIZE_DEFAULT 25
49 #define ALLEGRO_GOP_SIZE_MAX 1000
50
51 /*
52 * MCU Control Registers
53 *
54 * The Zynq UltraScale+ Devices Register Reference documents the registers
55 * with an offset of 0x9000, which equals the size of the SRAM and one page
56 * gap. The driver handles SRAM and registers separately and, therefore, is
57 * oblivious of the offset.
58 */
59 #define AL5_MCU_RESET 0x0000
60 #define AL5_MCU_RESET_SOFT BIT(0)
61 #define AL5_MCU_RESET_REGS BIT(1)
62 #define AL5_MCU_RESET_MODE 0x0004
63 #define AL5_MCU_RESET_MODE_SLEEP BIT(0)
64 #define AL5_MCU_RESET_MODE_HALT BIT(1)
65 #define AL5_MCU_STA 0x0008
66 #define AL5_MCU_STA_SLEEP BIT(0)
67 #define AL5_MCU_WAKEUP 0x000c
68
69 #define AL5_ICACHE_ADDR_OFFSET_MSB 0x0010
70 #define AL5_ICACHE_ADDR_OFFSET_LSB 0x0014
71 #define AL5_DCACHE_ADDR_OFFSET_MSB 0x0018
72 #define AL5_DCACHE_ADDR_OFFSET_LSB 0x001c
73
74 #define AL5_MCU_INTERRUPT 0x0100
75 #define AL5_ITC_CPU_IRQ_MSK 0x0104
76 #define AL5_ITC_CPU_IRQ_CLR 0x0108
77 #define AL5_ITC_CPU_IRQ_STA 0x010C
78 #define AL5_ITC_CPU_IRQ_STA_TRIGGERED BIT(0)
79
80 #define AXI_ADDR_OFFSET_IP 0x0208
81
82 /*
83 * The MCU accesses the system memory with a 2G offset compared to CPU
84 * physical addresses.
85 */
86 #define MCU_CACHE_OFFSET SZ_2G
87
88 /*
89 * The driver needs to reserve some space at the beginning of capture buffers,
90 * because it needs to write SPS/PPS NAL units. The encoder writes the actual
91 * frame data after the offset.
92 */
93 #define ENCODER_STREAM_OFFSET SZ_64
94
95 #define SIZE_MACROBLOCK 16
96
97 static int debug;
98 module_param(debug, int, 0644);
99 MODULE_PARM_DESC(debug, "Debug level (0-2)");
100
101 struct allegro_buffer {
102 void *vaddr;
103 dma_addr_t paddr;
104 size_t size;
105 struct list_head head;
106 };
107
108 struct allegro_dev;
109 struct allegro_channel;
110
111 struct allegro_mbox {
112 struct allegro_dev *dev;
113 unsigned int head;
114 unsigned int tail;
115 unsigned int data;
116 size_t size;
117 /* protect mailbox from simultaneous accesses */
118 struct mutex lock;
119 };
120
121 struct allegro_dev {
122 struct v4l2_device v4l2_dev;
123 struct video_device video_dev;
124 struct v4l2_m2m_dev *m2m_dev;
125 struct platform_device *plat_dev;
126
127 /* mutex protecting vb2_queue structure */
128 struct mutex lock;
129
130 struct regmap *regmap;
131 struct regmap *sram;
132
133 const struct fw_info *fw_info;
134 struct allegro_buffer firmware;
135 struct allegro_buffer suballocator;
136
137 struct completion init_complete;
138
139 /* The mailbox interface */
140 struct allegro_mbox *mbox_command;
141 struct allegro_mbox *mbox_status;
142
143 /*
144 * The downstream driver limits the users to 64 users, thus I can use
145 * a bitfield for the user_ids that are in use. See also user_id in
146 * struct allegro_channel.
147 */
148 unsigned long channel_user_ids;
149 struct list_head channels;
150 };
151
152 static struct regmap_config allegro_regmap_config = {
153 .name = "regmap",
154 .reg_bits = 32,
155 .val_bits = 32,
156 .reg_stride = 4,
157 .max_register = 0xfff,
158 .cache_type = REGCACHE_NONE,
159 };
160
161 static struct regmap_config allegro_sram_config = {
162 .name = "sram",
163 .reg_bits = 32,
164 .val_bits = 32,
165 .reg_stride = 4,
166 .max_register = 0x7fff,
167 .cache_type = REGCACHE_NONE,
168 };
169
170 enum allegro_state {
171 ALLEGRO_STATE_ENCODING,
172 ALLEGRO_STATE_DRAIN,
173 ALLEGRO_STATE_WAIT_FOR_BUFFER,
174 ALLEGRO_STATE_STOPPED,
175 };
176
177 #define fh_to_channel(__fh) container_of(__fh, struct allegro_channel, fh)
178
179 struct allegro_channel {
180 struct allegro_dev *dev;
181 struct v4l2_fh fh;
182 struct v4l2_ctrl_handler ctrl_handler;
183
184 unsigned int width;
185 unsigned int height;
186 unsigned int stride;
187 struct v4l2_fract framerate;
188
189 enum v4l2_colorspace colorspace;
190 enum v4l2_ycbcr_encoding ycbcr_enc;
191 enum v4l2_quantization quantization;
192 enum v4l2_xfer_func xfer_func;
193
194 u32 pixelformat;
195 unsigned int sizeimage_raw;
196 unsigned int osequence;
197
198 u32 codec;
199 enum v4l2_mpeg_video_h264_profile profile;
200 enum v4l2_mpeg_video_h264_level level;
201 unsigned int sizeimage_encoded;
202 unsigned int csequence;
203
204 bool frame_rc_enable;
205 unsigned int bitrate;
206 unsigned int bitrate_peak;
207 unsigned int cpb_size;
208 unsigned int gop_size;
209
210 struct allegro_buffer config_blob;
211
212 unsigned int num_ref_idx_l0;
213 unsigned int num_ref_idx_l1;
214
215 struct v4l2_ctrl *mpeg_video_h264_profile;
216 struct v4l2_ctrl *mpeg_video_h264_level;
217 struct v4l2_ctrl *mpeg_video_h264_i_frame_qp;
218 struct v4l2_ctrl *mpeg_video_h264_max_qp;
219 struct v4l2_ctrl *mpeg_video_h264_min_qp;
220 struct v4l2_ctrl *mpeg_video_h264_p_frame_qp;
221 struct v4l2_ctrl *mpeg_video_h264_b_frame_qp;
222 struct v4l2_ctrl *mpeg_video_frame_rc_enable;
223 struct { /* video bitrate mode control cluster */
224 struct v4l2_ctrl *mpeg_video_bitrate_mode;
225 struct v4l2_ctrl *mpeg_video_bitrate;
226 struct v4l2_ctrl *mpeg_video_bitrate_peak;
227 };
228 struct v4l2_ctrl *mpeg_video_cpb_size;
229 struct v4l2_ctrl *mpeg_video_gop_size;
230
231 /* user_id is used to identify the channel during CREATE_CHANNEL */
232 /* not sure, what to set here and if this is actually required */
233 int user_id;
234 /* channel_id is set by the mcu and used by all later commands */
235 int mcu_channel_id;
236
237 struct list_head buffers_reference;
238 struct list_head buffers_intermediate;
239
240 struct list_head source_shadow_list;
241 struct list_head stream_shadow_list;
242 /* protect shadow lists of buffers passed to firmware */
243 struct mutex shadow_list_lock;
244
245 struct list_head list;
246 struct completion completion;
247
248 unsigned int error;
249 enum allegro_state state;
250 };
251
252 static inline int
allegro_set_state(struct allegro_channel * channel,enum allegro_state state)253 allegro_set_state(struct allegro_channel *channel, enum allegro_state state)
254 {
255 channel->state = state;
256
257 return 0;
258 }
259
260 static inline enum allegro_state
allegro_get_state(struct allegro_channel * channel)261 allegro_get_state(struct allegro_channel *channel)
262 {
263 return channel->state;
264 }
265
266 struct allegro_m2m_buffer {
267 struct v4l2_m2m_buffer buf;
268 struct list_head head;
269 };
270
271 #define to_allegro_m2m_buffer(__buf) \
272 container_of(__buf, struct allegro_m2m_buffer, buf)
273
274 struct fw_info {
275 unsigned int id;
276 unsigned int id_codec;
277 char *version;
278 unsigned int mailbox_cmd;
279 unsigned int mailbox_status;
280 size_t mailbox_size;
281 enum mcu_msg_version mailbox_version;
282 size_t suballocator_size;
283 };
284
285 static const struct fw_info supported_firmware[] = {
286 {
287 .id = 18296,
288 .id_codec = 96272,
289 .version = "v2018.2",
290 .mailbox_cmd = 0x7800,
291 .mailbox_status = 0x7c00,
292 .mailbox_size = 0x400 - 0x8,
293 .mailbox_version = MCU_MSG_VERSION_2018_2,
294 .suballocator_size = SZ_16M,
295 }, {
296 .id = 14680,
297 .id_codec = 126572,
298 .version = "v2019.2",
299 .mailbox_cmd = 0x7000,
300 .mailbox_status = 0x7800,
301 .mailbox_size = 0x800 - 0x8,
302 .mailbox_version = MCU_MSG_VERSION_2019_2,
303 .suballocator_size = SZ_32M,
304 },
305 };
306
to_mcu_addr(struct allegro_dev * dev,dma_addr_t phys)307 static inline u32 to_mcu_addr(struct allegro_dev *dev, dma_addr_t phys)
308 {
309 if (upper_32_bits(phys) || (lower_32_bits(phys) & MCU_CACHE_OFFSET))
310 v4l2_warn(&dev->v4l2_dev,
311 "address %pad is outside mcu window\n", &phys);
312
313 return lower_32_bits(phys) | MCU_CACHE_OFFSET;
314 }
315
to_mcu_size(struct allegro_dev * dev,size_t size)316 static inline u32 to_mcu_size(struct allegro_dev *dev, size_t size)
317 {
318 return lower_32_bits(size);
319 }
320
to_codec_addr(struct allegro_dev * dev,dma_addr_t phys)321 static inline u32 to_codec_addr(struct allegro_dev *dev, dma_addr_t phys)
322 {
323 if (upper_32_bits(phys))
324 v4l2_warn(&dev->v4l2_dev,
325 "address %pad cannot be used by codec\n", &phys);
326
327 return lower_32_bits(phys);
328 }
329
ptr_to_u64(const void * ptr)330 static inline u64 ptr_to_u64(const void *ptr)
331 {
332 return (uintptr_t)ptr;
333 }
334
335 /* Helper functions for channel and user operations */
336
allegro_next_user_id(struct allegro_dev * dev)337 static unsigned long allegro_next_user_id(struct allegro_dev *dev)
338 {
339 if (dev->channel_user_ids == ~0UL)
340 return -EBUSY;
341
342 return ffz(dev->channel_user_ids);
343 }
344
345 static struct allegro_channel *
allegro_find_channel_by_user_id(struct allegro_dev * dev,unsigned int user_id)346 allegro_find_channel_by_user_id(struct allegro_dev *dev,
347 unsigned int user_id)
348 {
349 struct allegro_channel *channel;
350
351 list_for_each_entry(channel, &dev->channels, list) {
352 if (channel->user_id == user_id)
353 return channel;
354 }
355
356 return ERR_PTR(-EINVAL);
357 }
358
359 static struct allegro_channel *
allegro_find_channel_by_channel_id(struct allegro_dev * dev,unsigned int channel_id)360 allegro_find_channel_by_channel_id(struct allegro_dev *dev,
361 unsigned int channel_id)
362 {
363 struct allegro_channel *channel;
364
365 list_for_each_entry(channel, &dev->channels, list) {
366 if (channel->mcu_channel_id == channel_id)
367 return channel;
368 }
369
370 return ERR_PTR(-EINVAL);
371 }
372
channel_exists(struct allegro_channel * channel)373 static inline bool channel_exists(struct allegro_channel *channel)
374 {
375 return channel->mcu_channel_id != -1;
376 }
377
378 #define AL_ERROR 0x80
379 #define AL_ERR_INIT_FAILED 0x81
380 #define AL_ERR_NO_FRAME_DECODED 0x82
381 #define AL_ERR_RESOLUTION_CHANGE 0x85
382 #define AL_ERR_NO_MEMORY 0x87
383 #define AL_ERR_STREAM_OVERFLOW 0x88
384 #define AL_ERR_TOO_MANY_SLICES 0x89
385 #define AL_ERR_BUF_NOT_READY 0x8c
386 #define AL_ERR_NO_CHANNEL_AVAILABLE 0x8d
387 #define AL_ERR_RESOURCE_UNAVAILABLE 0x8e
388 #define AL_ERR_NOT_ENOUGH_CORES 0x8f
389 #define AL_ERR_REQUEST_MALFORMED 0x90
390 #define AL_ERR_CMD_NOT_ALLOWED 0x91
391 #define AL_ERR_INVALID_CMD_VALUE 0x92
392
allegro_err_to_string(unsigned int err)393 static inline const char *allegro_err_to_string(unsigned int err)
394 {
395 switch (err) {
396 case AL_ERR_INIT_FAILED:
397 return "initialization failed";
398 case AL_ERR_NO_FRAME_DECODED:
399 return "no frame decoded";
400 case AL_ERR_RESOLUTION_CHANGE:
401 return "resolution change";
402 case AL_ERR_NO_MEMORY:
403 return "out of memory";
404 case AL_ERR_STREAM_OVERFLOW:
405 return "stream buffer overflow";
406 case AL_ERR_TOO_MANY_SLICES:
407 return "too many slices";
408 case AL_ERR_BUF_NOT_READY:
409 return "buffer not ready";
410 case AL_ERR_NO_CHANNEL_AVAILABLE:
411 return "no channel available";
412 case AL_ERR_RESOURCE_UNAVAILABLE:
413 return "resource unavailable";
414 case AL_ERR_NOT_ENOUGH_CORES:
415 return "not enough cores";
416 case AL_ERR_REQUEST_MALFORMED:
417 return "request malformed";
418 case AL_ERR_CMD_NOT_ALLOWED:
419 return "command not allowed";
420 case AL_ERR_INVALID_CMD_VALUE:
421 return "invalid command value";
422 case AL_ERROR:
423 default:
424 return "unknown error";
425 }
426 }
427
estimate_stream_size(unsigned int width,unsigned int height)428 static unsigned int estimate_stream_size(unsigned int width,
429 unsigned int height)
430 {
431 unsigned int offset = ENCODER_STREAM_OFFSET;
432 unsigned int num_blocks = DIV_ROUND_UP(width, SIZE_MACROBLOCK) *
433 DIV_ROUND_UP(height, SIZE_MACROBLOCK);
434 unsigned int pcm_size = SZ_256;
435 unsigned int partition_table = SZ_256;
436
437 return round_up(offset + num_blocks * pcm_size + partition_table, 32);
438 }
439
440 static enum v4l2_mpeg_video_h264_level
select_minimum_h264_level(unsigned int width,unsigned int height)441 select_minimum_h264_level(unsigned int width, unsigned int height)
442 {
443 unsigned int pic_width_in_mb = DIV_ROUND_UP(width, SIZE_MACROBLOCK);
444 unsigned int frame_height_in_mb = DIV_ROUND_UP(height, SIZE_MACROBLOCK);
445 unsigned int frame_size_in_mb = pic_width_in_mb * frame_height_in_mb;
446 enum v4l2_mpeg_video_h264_level level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
447
448 /*
449 * The level limits are specified in Rec. ITU-T H.264 Annex A.3.1 and
450 * also specify limits regarding bit rate and CBP size. Only approximate
451 * the levels using the frame size.
452 *
453 * Level 5.1 allows up to 4k video resolution.
454 */
455 if (frame_size_in_mb <= 99)
456 level = V4L2_MPEG_VIDEO_H264_LEVEL_1_0;
457 else if (frame_size_in_mb <= 396)
458 level = V4L2_MPEG_VIDEO_H264_LEVEL_1_1;
459 else if (frame_size_in_mb <= 792)
460 level = V4L2_MPEG_VIDEO_H264_LEVEL_2_1;
461 else if (frame_size_in_mb <= 1620)
462 level = V4L2_MPEG_VIDEO_H264_LEVEL_2_2;
463 else if (frame_size_in_mb <= 3600)
464 level = V4L2_MPEG_VIDEO_H264_LEVEL_3_1;
465 else if (frame_size_in_mb <= 5120)
466 level = V4L2_MPEG_VIDEO_H264_LEVEL_3_2;
467 else if (frame_size_in_mb <= 8192)
468 level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
469 else if (frame_size_in_mb <= 8704)
470 level = V4L2_MPEG_VIDEO_H264_LEVEL_4_2;
471 else if (frame_size_in_mb <= 22080)
472 level = V4L2_MPEG_VIDEO_H264_LEVEL_5_0;
473 else
474 level = V4L2_MPEG_VIDEO_H264_LEVEL_5_1;
475
476 return level;
477 }
478
maximum_bitrate(enum v4l2_mpeg_video_h264_level level)479 static unsigned int maximum_bitrate(enum v4l2_mpeg_video_h264_level level)
480 {
481 switch (level) {
482 case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
483 return 64000;
484 case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
485 return 128000;
486 case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
487 return 192000;
488 case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
489 return 384000;
490 case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
491 return 768000;
492 case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
493 return 2000000;
494 case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
495 return 4000000;
496 case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
497 return 4000000;
498 case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
499 return 10000000;
500 case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
501 return 14000000;
502 case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
503 return 20000000;
504 case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
505 return 20000000;
506 case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
507 return 50000000;
508 case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
509 return 50000000;
510 case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
511 return 135000000;
512 case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
513 default:
514 return 240000000;
515 }
516 }
517
maximum_cpb_size(enum v4l2_mpeg_video_h264_level level)518 static unsigned int maximum_cpb_size(enum v4l2_mpeg_video_h264_level level)
519 {
520 switch (level) {
521 case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
522 return 175;
523 case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
524 return 350;
525 case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
526 return 500;
527 case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
528 return 1000;
529 case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
530 return 2000;
531 case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
532 return 2000;
533 case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
534 return 4000;
535 case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
536 return 4000;
537 case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
538 return 10000;
539 case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
540 return 14000;
541 case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
542 return 20000;
543 case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
544 return 25000;
545 case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
546 return 62500;
547 case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
548 return 62500;
549 case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
550 return 135000;
551 case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
552 default:
553 return 240000;
554 }
555 }
556
557 static const struct fw_info *
allegro_get_firmware_info(struct allegro_dev * dev,const struct firmware * fw,const struct firmware * fw_codec)558 allegro_get_firmware_info(struct allegro_dev *dev,
559 const struct firmware *fw,
560 const struct firmware *fw_codec)
561 {
562 int i;
563 unsigned int id = fw->size;
564 unsigned int id_codec = fw_codec->size;
565
566 for (i = 0; i < ARRAY_SIZE(supported_firmware); i++)
567 if (supported_firmware[i].id == id &&
568 supported_firmware[i].id_codec == id_codec)
569 return &supported_firmware[i];
570
571 return NULL;
572 }
573
574 /*
575 * Buffers that are used internally by the MCU.
576 */
577
allegro_alloc_buffer(struct allegro_dev * dev,struct allegro_buffer * buffer,size_t size)578 static int allegro_alloc_buffer(struct allegro_dev *dev,
579 struct allegro_buffer *buffer, size_t size)
580 {
581 buffer->vaddr = dma_alloc_coherent(&dev->plat_dev->dev, size,
582 &buffer->paddr, GFP_KERNEL);
583 if (!buffer->vaddr)
584 return -ENOMEM;
585 buffer->size = size;
586
587 return 0;
588 }
589
allegro_free_buffer(struct allegro_dev * dev,struct allegro_buffer * buffer)590 static void allegro_free_buffer(struct allegro_dev *dev,
591 struct allegro_buffer *buffer)
592 {
593 if (buffer->vaddr) {
594 dma_free_coherent(&dev->plat_dev->dev, buffer->size,
595 buffer->vaddr, buffer->paddr);
596 buffer->vaddr = NULL;
597 buffer->size = 0;
598 }
599 }
600
601 /*
602 * Mailbox interface to send messages to the MCU.
603 */
604
605 static void allegro_mcu_interrupt(struct allegro_dev *dev);
606 static void allegro_handle_message(struct allegro_dev *dev,
607 union mcu_msg_response *msg);
608
allegro_mbox_init(struct allegro_dev * dev,unsigned int base,size_t size)609 static struct allegro_mbox *allegro_mbox_init(struct allegro_dev *dev,
610 unsigned int base, size_t size)
611 {
612 struct allegro_mbox *mbox;
613
614 mbox = devm_kmalloc(&dev->plat_dev->dev, sizeof(*mbox), GFP_KERNEL);
615 if (!mbox)
616 return ERR_PTR(-ENOMEM);
617
618 mbox->dev = dev;
619
620 mbox->head = base;
621 mbox->tail = base + 0x4;
622 mbox->data = base + 0x8;
623 mbox->size = size;
624 mutex_init(&mbox->lock);
625
626 regmap_write(dev->sram, mbox->head, 0);
627 regmap_write(dev->sram, mbox->tail, 0);
628
629 return mbox;
630 }
631
allegro_mbox_write(struct allegro_mbox * mbox,const u32 * src,size_t size)632 static int allegro_mbox_write(struct allegro_mbox *mbox,
633 const u32 *src, size_t size)
634 {
635 struct regmap *sram = mbox->dev->sram;
636 unsigned int tail;
637 size_t size_no_wrap;
638 int err = 0;
639 int stride = regmap_get_reg_stride(sram);
640
641 if (!src)
642 return -EINVAL;
643
644 if (size > mbox->size)
645 return -EINVAL;
646
647 mutex_lock(&mbox->lock);
648 regmap_read(sram, mbox->tail, &tail);
649 if (tail > mbox->size) {
650 err = -EIO;
651 goto out;
652 }
653 size_no_wrap = min(size, mbox->size - (size_t)tail);
654 regmap_bulk_write(sram, mbox->data + tail,
655 src, size_no_wrap / stride);
656 regmap_bulk_write(sram, mbox->data,
657 src + (size_no_wrap / sizeof(*src)),
658 (size - size_no_wrap) / stride);
659 regmap_write(sram, mbox->tail, (tail + size) % mbox->size);
660
661 out:
662 mutex_unlock(&mbox->lock);
663
664 return err;
665 }
666
allegro_mbox_read(struct allegro_mbox * mbox,u32 * dst,size_t nbyte)667 static ssize_t allegro_mbox_read(struct allegro_mbox *mbox,
668 u32 *dst, size_t nbyte)
669 {
670 struct {
671 u16 length;
672 u16 type;
673 } __attribute__ ((__packed__)) *header;
674 struct regmap *sram = mbox->dev->sram;
675 unsigned int head;
676 ssize_t size;
677 size_t body_no_wrap;
678 int stride = regmap_get_reg_stride(sram);
679
680 regmap_read(sram, mbox->head, &head);
681 if (head > mbox->size)
682 return -EIO;
683
684 /* Assume that the header does not wrap. */
685 regmap_bulk_read(sram, mbox->data + head,
686 dst, sizeof(*header) / stride);
687 header = (void *)dst;
688 size = header->length + sizeof(*header);
689 if (size > mbox->size || size & 0x3)
690 return -EIO;
691 if (size > nbyte)
692 return -EINVAL;
693
694 /*
695 * The message might wrap within the mailbox. If the message does not
696 * wrap, the first read will read the entire message, otherwise the
697 * first read will read message until the end of the mailbox and the
698 * second read will read the remaining bytes from the beginning of the
699 * mailbox.
700 *
701 * Skip the header, as was already read to get the size of the body.
702 */
703 body_no_wrap = min((size_t)header->length,
704 (size_t)(mbox->size - (head + sizeof(*header))));
705 regmap_bulk_read(sram, mbox->data + head + sizeof(*header),
706 dst + (sizeof(*header) / sizeof(*dst)),
707 body_no_wrap / stride);
708 regmap_bulk_read(sram, mbox->data,
709 dst + (sizeof(*header) + body_no_wrap) / sizeof(*dst),
710 (header->length - body_no_wrap) / stride);
711
712 regmap_write(sram, mbox->head, (head + size) % mbox->size);
713
714 return size;
715 }
716
717 /**
718 * allegro_mbox_send() - Send a message via the mailbox
719 * @mbox: the mailbox which is used to send the message
720 * @msg: the message to send
721 */
allegro_mbox_send(struct allegro_mbox * mbox,void * msg)722 static int allegro_mbox_send(struct allegro_mbox *mbox, void *msg)
723 {
724 struct allegro_dev *dev = mbox->dev;
725 ssize_t size;
726 int err;
727 u32 *tmp;
728
729 tmp = kzalloc(mbox->size, GFP_KERNEL);
730 if (!tmp) {
731 err = -ENOMEM;
732 goto out;
733 }
734
735 size = allegro_encode_mail(tmp, msg);
736
737 err = allegro_mbox_write(mbox, tmp, size);
738 kfree(tmp);
739 if (err)
740 goto out;
741
742 allegro_mcu_interrupt(dev);
743
744 out:
745 return err;
746 }
747
748 /**
749 * allegro_mbox_notify() - Notify the mailbox about a new message
750 * @mbox: The allegro_mbox to notify
751 */
allegro_mbox_notify(struct allegro_mbox * mbox)752 static void allegro_mbox_notify(struct allegro_mbox *mbox)
753 {
754 struct allegro_dev *dev = mbox->dev;
755 union mcu_msg_response *msg;
756 ssize_t size;
757 u32 *tmp;
758 int err;
759
760 msg = kmalloc(sizeof(*msg), GFP_KERNEL);
761 if (!msg)
762 return;
763
764 msg->header.version = dev->fw_info->mailbox_version;
765
766 tmp = kmalloc(mbox->size, GFP_KERNEL);
767 if (!tmp)
768 goto out;
769
770 size = allegro_mbox_read(mbox, tmp, mbox->size);
771 if (size < 0)
772 goto out;
773
774 err = allegro_decode_mail(msg, tmp);
775 if (err)
776 goto out;
777
778 allegro_handle_message(dev, msg);
779
780 out:
781 kfree(tmp);
782 kfree(msg);
783 }
784
allegro_mcu_send_init(struct allegro_dev * dev,dma_addr_t suballoc_dma,size_t suballoc_size)785 static void allegro_mcu_send_init(struct allegro_dev *dev,
786 dma_addr_t suballoc_dma, size_t suballoc_size)
787 {
788 struct mcu_msg_init_request msg;
789
790 memset(&msg, 0, sizeof(msg));
791
792 msg.header.type = MCU_MSG_TYPE_INIT;
793 msg.header.version = dev->fw_info->mailbox_version;
794
795 msg.suballoc_dma = to_mcu_addr(dev, suballoc_dma);
796 msg.suballoc_size = to_mcu_size(dev, suballoc_size);
797
798 /* disable L2 cache */
799 msg.l2_cache[0] = -1;
800 msg.l2_cache[1] = -1;
801 msg.l2_cache[2] = -1;
802
803 allegro_mbox_send(dev->mbox_command, &msg);
804 }
805
v4l2_pixelformat_to_mcu_format(u32 pixelformat)806 static u32 v4l2_pixelformat_to_mcu_format(u32 pixelformat)
807 {
808 switch (pixelformat) {
809 case V4L2_PIX_FMT_NV12:
810 /* AL_420_8BITS: 0x100 -> NV12, 0x88 -> 8 bit */
811 return 0x100 | 0x88;
812 default:
813 return -EINVAL;
814 }
815 }
816
v4l2_colorspace_to_mcu_colorspace(enum v4l2_colorspace colorspace)817 static u32 v4l2_colorspace_to_mcu_colorspace(enum v4l2_colorspace colorspace)
818 {
819 switch (colorspace) {
820 case V4L2_COLORSPACE_REC709:
821 return 2;
822 case V4L2_COLORSPACE_SMPTE170M:
823 return 3;
824 case V4L2_COLORSPACE_SMPTE240M:
825 return 4;
826 case V4L2_COLORSPACE_SRGB:
827 return 7;
828 default:
829 /* UNKNOWN */
830 return 0;
831 }
832 }
833
v4l2_profile_to_mcu_profile(enum v4l2_mpeg_video_h264_profile profile)834 static u8 v4l2_profile_to_mcu_profile(enum v4l2_mpeg_video_h264_profile profile)
835 {
836 switch (profile) {
837 case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
838 default:
839 return 66;
840 }
841 }
842
v4l2_level_to_mcu_level(enum v4l2_mpeg_video_h264_level level)843 static u16 v4l2_level_to_mcu_level(enum v4l2_mpeg_video_h264_level level)
844 {
845 switch (level) {
846 case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
847 return 10;
848 case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
849 return 11;
850 case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
851 return 12;
852 case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
853 return 13;
854 case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
855 return 20;
856 case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
857 return 21;
858 case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
859 return 22;
860 case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
861 return 30;
862 case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
863 return 31;
864 case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
865 return 32;
866 case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
867 return 40;
868 case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
869 return 41;
870 case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
871 return 42;
872 case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
873 return 50;
874 case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
875 default:
876 return 51;
877 }
878 }
879
880 static u32
v4l2_bitrate_mode_to_mcu_mode(enum v4l2_mpeg_video_bitrate_mode mode)881 v4l2_bitrate_mode_to_mcu_mode(enum v4l2_mpeg_video_bitrate_mode mode)
882 {
883 switch (mode) {
884 case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR:
885 return 2;
886 case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR:
887 default:
888 return 1;
889 }
890 }
891
v4l2_cpb_size_to_mcu(unsigned int cpb_size,unsigned int bitrate)892 static u32 v4l2_cpb_size_to_mcu(unsigned int cpb_size, unsigned int bitrate)
893 {
894 unsigned int cpb_size_kbit;
895 unsigned int bitrate_kbps;
896
897 /*
898 * The mcu expects the CPB size in units of a 90 kHz clock, but the
899 * channel follows the V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE and stores
900 * the CPB size in kilobytes.
901 */
902 cpb_size_kbit = cpb_size * BITS_PER_BYTE;
903 bitrate_kbps = bitrate / 1000;
904
905 return (cpb_size_kbit * 90000) / bitrate_kbps;
906 }
907
get_qp_delta(int minuend,int subtrahend)908 static s16 get_qp_delta(int minuend, int subtrahend)
909 {
910 if (minuend == subtrahend)
911 return -1;
912 else
913 return minuend - subtrahend;
914 }
915
fill_create_channel_param(struct allegro_channel * channel,struct create_channel_param * param)916 static int fill_create_channel_param(struct allegro_channel *channel,
917 struct create_channel_param *param)
918 {
919 int i_frame_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_i_frame_qp);
920 int p_frame_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_p_frame_qp);
921 int b_frame_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_b_frame_qp);
922 int bitrate_mode = v4l2_ctrl_g_ctrl(channel->mpeg_video_bitrate_mode);
923
924 param->width = channel->width;
925 param->height = channel->height;
926 param->format = v4l2_pixelformat_to_mcu_format(channel->pixelformat);
927 param->colorspace =
928 v4l2_colorspace_to_mcu_colorspace(channel->colorspace);
929 param->src_mode = 0x0;
930 param->profile = v4l2_profile_to_mcu_profile(channel->profile);
931 param->constraint_set_flags = BIT(1);
932 param->codec = channel->codec;
933 param->level = v4l2_level_to_mcu_level(channel->level);
934 param->tier = 0;
935
936 param->log2_max_poc = 10;
937 param->log2_max_frame_num = 4;
938 param->temporal_mvp_enable = 1;
939
940 param->dbf_ovr_en = 1;
941 param->rdo_cost_mode = 1;
942 param->custom_lda = 1;
943 param->lf = 1;
944 param->lf_x_tile = 1;
945 param->lf_x_slice = 1;
946
947 param->src_bit_depth = 8;
948
949 param->beta_offset = -1;
950 param->tc_offset = -1;
951 param->num_slices = 1;
952 param->me_range[0] = 8;
953 param->me_range[1] = 8;
954 param->me_range[2] = 16;
955 param->me_range[3] = 16;
956 param->max_cu_size = ilog2(SIZE_MACROBLOCK);
957 param->min_cu_size = ilog2(8);
958 param->max_tu_size = 2;
959 param->min_tu_size = 2;
960 param->max_transfo_depth_intra = 1;
961 param->max_transfo_depth_inter = 1;
962
963 param->prefetch_auto = 0;
964 param->prefetch_mem_offset = 0;
965 param->prefetch_mem_size = 0;
966
967 param->rate_control_mode = channel->frame_rc_enable ?
968 v4l2_bitrate_mode_to_mcu_mode(bitrate_mode) : 0;
969
970 param->cpb_size = v4l2_cpb_size_to_mcu(channel->cpb_size,
971 channel->bitrate_peak);
972 /* Shall be ]0;cpb_size in 90 kHz units]. Use maximum value. */
973 param->initial_rem_delay = param->cpb_size;
974 param->framerate = DIV_ROUND_UP(channel->framerate.numerator,
975 channel->framerate.denominator);
976 param->clk_ratio = channel->framerate.denominator == 1001 ? 1001 : 1000;
977 param->target_bitrate = channel->bitrate;
978 param->max_bitrate = channel->bitrate_peak;
979 param->initial_qp = i_frame_qp;
980 param->min_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_min_qp);
981 param->max_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_max_qp);
982 param->ip_delta = get_qp_delta(i_frame_qp, p_frame_qp);
983 param->pb_delta = get_qp_delta(p_frame_qp, b_frame_qp);
984 param->golden_ref = 0;
985 param->golden_delta = 2;
986 param->golden_ref_frequency = 10;
987 param->rate_control_option = 0x00000000;
988
989 param->num_pixel = channel->width + channel->height;
990 param->max_psnr = 4200;
991 param->max_pixel_value = 255;
992
993 param->gop_ctrl_mode = 0x00000002;
994 param->freq_idr = channel->gop_size;
995 param->freq_lt = 0;
996 param->gdr_mode = 0x00000000;
997 param->gop_length = channel->gop_size;
998 param->subframe_latency = 0x00000000;
999
1000 param->lda_factors[0] = 51;
1001 param->lda_factors[1] = 90;
1002 param->lda_factors[2] = 151;
1003 param->lda_factors[3] = 151;
1004 param->lda_factors[4] = 151;
1005 param->lda_factors[5] = 151;
1006
1007 param->max_num_merge_cand = 5;
1008
1009 return 0;
1010 }
1011
allegro_mcu_send_create_channel(struct allegro_dev * dev,struct allegro_channel * channel)1012 static int allegro_mcu_send_create_channel(struct allegro_dev *dev,
1013 struct allegro_channel *channel)
1014 {
1015 struct mcu_msg_create_channel msg;
1016 struct allegro_buffer *blob = &channel->config_blob;
1017 struct create_channel_param param;
1018 size_t size;
1019
1020 memset(¶m, 0, sizeof(param));
1021 fill_create_channel_param(channel, ¶m);
1022 allegro_alloc_buffer(dev, blob, sizeof(struct create_channel_param));
1023 param.version = dev->fw_info->mailbox_version;
1024 size = allegro_encode_config_blob(blob->vaddr, ¶m);
1025
1026 memset(&msg, 0, sizeof(msg));
1027
1028 msg.header.type = MCU_MSG_TYPE_CREATE_CHANNEL;
1029 msg.header.version = dev->fw_info->mailbox_version;
1030
1031 msg.user_id = channel->user_id;
1032
1033 msg.blob = blob->vaddr;
1034 msg.blob_size = size;
1035 msg.blob_mcu_addr = to_mcu_addr(dev, blob->paddr);
1036
1037 allegro_mbox_send(dev->mbox_command, &msg);
1038
1039 return 0;
1040 }
1041
allegro_mcu_send_destroy_channel(struct allegro_dev * dev,struct allegro_channel * channel)1042 static int allegro_mcu_send_destroy_channel(struct allegro_dev *dev,
1043 struct allegro_channel *channel)
1044 {
1045 struct mcu_msg_destroy_channel msg;
1046
1047 memset(&msg, 0, sizeof(msg));
1048
1049 msg.header.type = MCU_MSG_TYPE_DESTROY_CHANNEL;
1050 msg.header.version = dev->fw_info->mailbox_version;
1051
1052 msg.channel_id = channel->mcu_channel_id;
1053
1054 allegro_mbox_send(dev->mbox_command, &msg);
1055
1056 return 0;
1057 }
1058
allegro_mcu_send_put_stream_buffer(struct allegro_dev * dev,struct allegro_channel * channel,dma_addr_t paddr,unsigned long size,u64 stream_id)1059 static int allegro_mcu_send_put_stream_buffer(struct allegro_dev *dev,
1060 struct allegro_channel *channel,
1061 dma_addr_t paddr,
1062 unsigned long size,
1063 u64 stream_id)
1064 {
1065 struct mcu_msg_put_stream_buffer msg;
1066
1067 memset(&msg, 0, sizeof(msg));
1068
1069 msg.header.type = MCU_MSG_TYPE_PUT_STREAM_BUFFER;
1070 msg.header.version = dev->fw_info->mailbox_version;
1071
1072 msg.channel_id = channel->mcu_channel_id;
1073 msg.dma_addr = to_codec_addr(dev, paddr);
1074 msg.mcu_addr = to_mcu_addr(dev, paddr);
1075 msg.size = size;
1076 msg.offset = ENCODER_STREAM_OFFSET;
1077 /* copied to mcu_msg_encode_frame_response */
1078 msg.stream_id = stream_id;
1079
1080 allegro_mbox_send(dev->mbox_command, &msg);
1081
1082 return 0;
1083 }
1084
allegro_mcu_send_encode_frame(struct allegro_dev * dev,struct allegro_channel * channel,dma_addr_t src_y,dma_addr_t src_uv,u64 src_handle)1085 static int allegro_mcu_send_encode_frame(struct allegro_dev *dev,
1086 struct allegro_channel *channel,
1087 dma_addr_t src_y, dma_addr_t src_uv,
1088 u64 src_handle)
1089 {
1090 struct mcu_msg_encode_frame msg;
1091
1092 memset(&msg, 0, sizeof(msg));
1093
1094 msg.header.type = MCU_MSG_TYPE_ENCODE_FRAME;
1095 msg.header.version = dev->fw_info->mailbox_version;
1096
1097 msg.channel_id = channel->mcu_channel_id;
1098 msg.encoding_options = AL_OPT_FORCE_LOAD;
1099 msg.pps_qp = 26; /* qp are relative to 26 */
1100 msg.user_param = 0; /* copied to mcu_msg_encode_frame_response */
1101 /* src_handle is copied to mcu_msg_encode_frame_response */
1102 msg.src_handle = src_handle;
1103 msg.src_y = to_codec_addr(dev, src_y);
1104 msg.src_uv = to_codec_addr(dev, src_uv);
1105 msg.stride = channel->stride;
1106 msg.ep2 = 0x0;
1107 msg.ep2_v = to_mcu_addr(dev, msg.ep2);
1108
1109 allegro_mbox_send(dev->mbox_command, &msg);
1110
1111 return 0;
1112 }
1113
allegro_mcu_wait_for_init_timeout(struct allegro_dev * dev,unsigned long timeout_ms)1114 static int allegro_mcu_wait_for_init_timeout(struct allegro_dev *dev,
1115 unsigned long timeout_ms)
1116 {
1117 unsigned long tmo;
1118
1119 tmo = wait_for_completion_timeout(&dev->init_complete,
1120 msecs_to_jiffies(timeout_ms));
1121 if (tmo == 0)
1122 return -ETIMEDOUT;
1123
1124 reinit_completion(&dev->init_complete);
1125 return 0;
1126 }
1127
allegro_mcu_push_buffer_internal(struct allegro_channel * channel,enum mcu_msg_type type)1128 static int allegro_mcu_push_buffer_internal(struct allegro_channel *channel,
1129 enum mcu_msg_type type)
1130 {
1131 struct allegro_dev *dev = channel->dev;
1132 struct mcu_msg_push_buffers_internal *msg;
1133 struct mcu_msg_push_buffers_internal_buffer *buffer;
1134 unsigned int num_buffers = 0;
1135 size_t size;
1136 struct allegro_buffer *al_buffer;
1137 struct list_head *list;
1138 int err;
1139
1140 switch (type) {
1141 case MCU_MSG_TYPE_PUSH_BUFFER_REFERENCE:
1142 list = &channel->buffers_reference;
1143 break;
1144 case MCU_MSG_TYPE_PUSH_BUFFER_INTERMEDIATE:
1145 list = &channel->buffers_intermediate;
1146 break;
1147 default:
1148 return -EINVAL;
1149 }
1150
1151 list_for_each_entry(al_buffer, list, head)
1152 num_buffers++;
1153 size = struct_size(msg, buffer, num_buffers);
1154
1155 msg = kmalloc(size, GFP_KERNEL);
1156 if (!msg)
1157 return -ENOMEM;
1158
1159 msg->header.type = type;
1160 msg->header.version = dev->fw_info->mailbox_version;
1161
1162 msg->channel_id = channel->mcu_channel_id;
1163 msg->num_buffers = num_buffers;
1164
1165 buffer = msg->buffer;
1166 list_for_each_entry(al_buffer, list, head) {
1167 buffer->dma_addr = to_codec_addr(dev, al_buffer->paddr);
1168 buffer->mcu_addr = to_mcu_addr(dev, al_buffer->paddr);
1169 buffer->size = to_mcu_size(dev, al_buffer->size);
1170 buffer++;
1171 }
1172
1173 err = allegro_mbox_send(dev->mbox_command, msg);
1174
1175 kfree(msg);
1176 return err;
1177 }
1178
allegro_mcu_push_buffer_intermediate(struct allegro_channel * channel)1179 static int allegro_mcu_push_buffer_intermediate(struct allegro_channel *channel)
1180 {
1181 enum mcu_msg_type type = MCU_MSG_TYPE_PUSH_BUFFER_INTERMEDIATE;
1182
1183 return allegro_mcu_push_buffer_internal(channel, type);
1184 }
1185
allegro_mcu_push_buffer_reference(struct allegro_channel * channel)1186 static int allegro_mcu_push_buffer_reference(struct allegro_channel *channel)
1187 {
1188 enum mcu_msg_type type = MCU_MSG_TYPE_PUSH_BUFFER_REFERENCE;
1189
1190 return allegro_mcu_push_buffer_internal(channel, type);
1191 }
1192
allocate_buffers_internal(struct allegro_channel * channel,struct list_head * list,size_t n,size_t size)1193 static int allocate_buffers_internal(struct allegro_channel *channel,
1194 struct list_head *list,
1195 size_t n, size_t size)
1196 {
1197 struct allegro_dev *dev = channel->dev;
1198 unsigned int i;
1199 int err;
1200 struct allegro_buffer *buffer, *tmp;
1201
1202 for (i = 0; i < n; i++) {
1203 buffer = kmalloc(sizeof(*buffer), GFP_KERNEL);
1204 if (!buffer) {
1205 err = -ENOMEM;
1206 goto err;
1207 }
1208 INIT_LIST_HEAD(&buffer->head);
1209
1210 err = allegro_alloc_buffer(dev, buffer, size);
1211 if (err)
1212 goto err;
1213 list_add(&buffer->head, list);
1214 }
1215
1216 return 0;
1217
1218 err:
1219 list_for_each_entry_safe(buffer, tmp, list, head) {
1220 list_del(&buffer->head);
1221 allegro_free_buffer(dev, buffer);
1222 kfree(buffer);
1223 }
1224 return err;
1225 }
1226
destroy_buffers_internal(struct allegro_channel * channel,struct list_head * list)1227 static void destroy_buffers_internal(struct allegro_channel *channel,
1228 struct list_head *list)
1229 {
1230 struct allegro_dev *dev = channel->dev;
1231 struct allegro_buffer *buffer, *tmp;
1232
1233 list_for_each_entry_safe(buffer, tmp, list, head) {
1234 list_del(&buffer->head);
1235 allegro_free_buffer(dev, buffer);
1236 kfree(buffer);
1237 }
1238 }
1239
destroy_reference_buffers(struct allegro_channel * channel)1240 static void destroy_reference_buffers(struct allegro_channel *channel)
1241 {
1242 return destroy_buffers_internal(channel, &channel->buffers_reference);
1243 }
1244
destroy_intermediate_buffers(struct allegro_channel * channel)1245 static void destroy_intermediate_buffers(struct allegro_channel *channel)
1246 {
1247 return destroy_buffers_internal(channel,
1248 &channel->buffers_intermediate);
1249 }
1250
allocate_intermediate_buffers(struct allegro_channel * channel,size_t n,size_t size)1251 static int allocate_intermediate_buffers(struct allegro_channel *channel,
1252 size_t n, size_t size)
1253 {
1254 return allocate_buffers_internal(channel,
1255 &channel->buffers_intermediate,
1256 n, size);
1257 }
1258
allocate_reference_buffers(struct allegro_channel * channel,size_t n,size_t size)1259 static int allocate_reference_buffers(struct allegro_channel *channel,
1260 size_t n, size_t size)
1261 {
1262 return allocate_buffers_internal(channel,
1263 &channel->buffers_reference,
1264 n, PAGE_ALIGN(size));
1265 }
1266
allegro_h264_write_sps(struct allegro_channel * channel,void * dest,size_t n)1267 static ssize_t allegro_h264_write_sps(struct allegro_channel *channel,
1268 void *dest, size_t n)
1269 {
1270 struct allegro_dev *dev = channel->dev;
1271 struct nal_h264_sps *sps;
1272 ssize_t size;
1273 unsigned int size_mb = SIZE_MACROBLOCK;
1274 /* Calculation of crop units in Rec. ITU-T H.264 (04/2017) p. 76 */
1275 unsigned int crop_unit_x = 2;
1276 unsigned int crop_unit_y = 2;
1277
1278 sps = kzalloc(sizeof(*sps), GFP_KERNEL);
1279 if (!sps)
1280 return -ENOMEM;
1281
1282 sps->profile_idc = nal_h264_profile_from_v4l2(channel->profile);
1283 sps->constraint_set0_flag = 0;
1284 sps->constraint_set1_flag = 1;
1285 sps->constraint_set2_flag = 0;
1286 sps->constraint_set3_flag = 0;
1287 sps->constraint_set4_flag = 0;
1288 sps->constraint_set5_flag = 0;
1289 sps->level_idc = nal_h264_level_from_v4l2(channel->level);
1290 sps->seq_parameter_set_id = 0;
1291 sps->log2_max_frame_num_minus4 = 0;
1292 sps->pic_order_cnt_type = 0;
1293 sps->log2_max_pic_order_cnt_lsb_minus4 = 6;
1294 sps->max_num_ref_frames = 3;
1295 sps->gaps_in_frame_num_value_allowed_flag = 0;
1296 sps->pic_width_in_mbs_minus1 =
1297 DIV_ROUND_UP(channel->width, size_mb) - 1;
1298 sps->pic_height_in_map_units_minus1 =
1299 DIV_ROUND_UP(channel->height, size_mb) - 1;
1300 sps->frame_mbs_only_flag = 1;
1301 sps->mb_adaptive_frame_field_flag = 0;
1302 sps->direct_8x8_inference_flag = 1;
1303 sps->frame_cropping_flag =
1304 (channel->width % size_mb) || (channel->height % size_mb);
1305 if (sps->frame_cropping_flag) {
1306 sps->crop_left = 0;
1307 sps->crop_right = (round_up(channel->width, size_mb) - channel->width) / crop_unit_x;
1308 sps->crop_top = 0;
1309 sps->crop_bottom = (round_up(channel->height, size_mb) - channel->height) / crop_unit_y;
1310 }
1311 sps->vui_parameters_present_flag = 1;
1312 sps->vui.aspect_ratio_info_present_flag = 0;
1313 sps->vui.overscan_info_present_flag = 0;
1314 sps->vui.video_signal_type_present_flag = 1;
1315 sps->vui.video_format = 1;
1316 sps->vui.video_full_range_flag = 0;
1317 sps->vui.colour_description_present_flag = 1;
1318 sps->vui.colour_primaries = 5;
1319 sps->vui.transfer_characteristics = 5;
1320 sps->vui.matrix_coefficients = 5;
1321 sps->vui.chroma_loc_info_present_flag = 1;
1322 sps->vui.chroma_sample_loc_type_top_field = 0;
1323 sps->vui.chroma_sample_loc_type_bottom_field = 0;
1324
1325 sps->vui.timing_info_present_flag = 1;
1326 sps->vui.num_units_in_tick = channel->framerate.denominator;
1327 sps->vui.time_scale = 2 * channel->framerate.numerator;
1328
1329 sps->vui.fixed_frame_rate_flag = 1;
1330 sps->vui.nal_hrd_parameters_present_flag = 0;
1331 sps->vui.vcl_hrd_parameters_present_flag = 1;
1332 sps->vui.vcl_hrd_parameters.cpb_cnt_minus1 = 0;
1333 sps->vui.vcl_hrd_parameters.bit_rate_scale = 0;
1334 sps->vui.vcl_hrd_parameters.cpb_size_scale = 1;
1335 /* See Rec. ITU-T H.264 (04/2017) p. 410 E-53 */
1336 sps->vui.vcl_hrd_parameters.bit_rate_value_minus1[0] =
1337 channel->bitrate_peak / (1 << (6 + sps->vui.vcl_hrd_parameters.bit_rate_scale)) - 1;
1338 /* See Rec. ITU-T H.264 (04/2017) p. 410 E-54 */
1339 sps->vui.vcl_hrd_parameters.cpb_size_value_minus1[0] =
1340 (channel->cpb_size * 1000) / (1 << (4 + sps->vui.vcl_hrd_parameters.cpb_size_scale)) - 1;
1341 sps->vui.vcl_hrd_parameters.cbr_flag[0] =
1342 !v4l2_ctrl_g_ctrl(channel->mpeg_video_frame_rc_enable);
1343 sps->vui.vcl_hrd_parameters.initial_cpb_removal_delay_length_minus1 = 31;
1344 sps->vui.vcl_hrd_parameters.cpb_removal_delay_length_minus1 = 31;
1345 sps->vui.vcl_hrd_parameters.dpb_output_delay_length_minus1 = 31;
1346 sps->vui.vcl_hrd_parameters.time_offset_length = 0;
1347 sps->vui.low_delay_hrd_flag = 0;
1348 sps->vui.pic_struct_present_flag = 1;
1349 sps->vui.bitstream_restriction_flag = 0;
1350
1351 size = nal_h264_write_sps(&dev->plat_dev->dev, dest, n, sps);
1352
1353 kfree(sps);
1354
1355 return size;
1356 }
1357
allegro_h264_write_pps(struct allegro_channel * channel,void * dest,size_t n)1358 static ssize_t allegro_h264_write_pps(struct allegro_channel *channel,
1359 void *dest, size_t n)
1360 {
1361 struct allegro_dev *dev = channel->dev;
1362 struct nal_h264_pps *pps;
1363 ssize_t size;
1364
1365 pps = kzalloc(sizeof(*pps), GFP_KERNEL);
1366 if (!pps)
1367 return -ENOMEM;
1368
1369 pps->pic_parameter_set_id = 0;
1370 pps->seq_parameter_set_id = 0;
1371 pps->entropy_coding_mode_flag = 0;
1372 pps->bottom_field_pic_order_in_frame_present_flag = 0;
1373 pps->num_slice_groups_minus1 = 0;
1374 pps->num_ref_idx_l0_default_active_minus1 = channel->num_ref_idx_l0 - 1;
1375 pps->num_ref_idx_l1_default_active_minus1 = channel->num_ref_idx_l1 - 1;
1376 pps->weighted_pred_flag = 0;
1377 pps->weighted_bipred_idc = 0;
1378 pps->pic_init_qp_minus26 = 0;
1379 pps->pic_init_qs_minus26 = 0;
1380 pps->chroma_qp_index_offset = 0;
1381 pps->deblocking_filter_control_present_flag = 1;
1382 pps->constrained_intra_pred_flag = 0;
1383 pps->redundant_pic_cnt_present_flag = 0;
1384 pps->transform_8x8_mode_flag = 0;
1385 pps->pic_scaling_matrix_present_flag = 0;
1386 pps->second_chroma_qp_index_offset = 0;
1387
1388 size = nal_h264_write_pps(&dev->plat_dev->dev, dest, n, pps);
1389
1390 kfree(pps);
1391
1392 return size;
1393 }
1394
allegro_channel_is_at_eos(struct allegro_channel * channel)1395 static bool allegro_channel_is_at_eos(struct allegro_channel *channel)
1396 {
1397 bool is_at_eos = false;
1398
1399 switch (allegro_get_state(channel)) {
1400 case ALLEGRO_STATE_STOPPED:
1401 is_at_eos = true;
1402 break;
1403 case ALLEGRO_STATE_DRAIN:
1404 case ALLEGRO_STATE_WAIT_FOR_BUFFER:
1405 mutex_lock(&channel->shadow_list_lock);
1406 if (v4l2_m2m_num_src_bufs_ready(channel->fh.m2m_ctx) == 0 &&
1407 list_empty(&channel->source_shadow_list))
1408 is_at_eos = true;
1409 mutex_unlock(&channel->shadow_list_lock);
1410 break;
1411 default:
1412 break;
1413 }
1414
1415 return is_at_eos;
1416 }
1417
allegro_channel_buf_done(struct allegro_channel * channel,struct vb2_v4l2_buffer * buf,enum vb2_buffer_state state)1418 static void allegro_channel_buf_done(struct allegro_channel *channel,
1419 struct vb2_v4l2_buffer *buf,
1420 enum vb2_buffer_state state)
1421 {
1422 const struct v4l2_event eos_event = {
1423 .type = V4L2_EVENT_EOS
1424 };
1425
1426 if (allegro_channel_is_at_eos(channel)) {
1427 buf->flags |= V4L2_BUF_FLAG_LAST;
1428 v4l2_event_queue_fh(&channel->fh, &eos_event);
1429
1430 allegro_set_state(channel, ALLEGRO_STATE_STOPPED);
1431 }
1432
1433 v4l2_m2m_buf_done(buf, state);
1434 }
1435
allegro_put_buffer(struct allegro_channel * channel,struct list_head * list,struct vb2_v4l2_buffer * buffer)1436 static u64 allegro_put_buffer(struct allegro_channel *channel,
1437 struct list_head *list,
1438 struct vb2_v4l2_buffer *buffer)
1439 {
1440 struct v4l2_m2m_buffer *b = container_of(buffer,
1441 struct v4l2_m2m_buffer, vb);
1442 struct allegro_m2m_buffer *shadow = to_allegro_m2m_buffer(b);
1443
1444 mutex_lock(&channel->shadow_list_lock);
1445 list_add_tail(&shadow->head, list);
1446 mutex_unlock(&channel->shadow_list_lock);
1447
1448 return ptr_to_u64(buffer);
1449 }
1450
1451 static struct vb2_v4l2_buffer *
allegro_get_buffer(struct allegro_channel * channel,struct list_head * list,u64 handle)1452 allegro_get_buffer(struct allegro_channel *channel,
1453 struct list_head *list, u64 handle)
1454 {
1455 struct allegro_m2m_buffer *shadow, *tmp;
1456 struct vb2_v4l2_buffer *buffer = NULL;
1457
1458 mutex_lock(&channel->shadow_list_lock);
1459 list_for_each_entry_safe(shadow, tmp, list, head) {
1460 if (handle == ptr_to_u64(&shadow->buf.vb)) {
1461 buffer = &shadow->buf.vb;
1462 list_del_init(&shadow->head);
1463 break;
1464 }
1465 }
1466 mutex_unlock(&channel->shadow_list_lock);
1467
1468 return buffer;
1469 }
1470
allegro_channel_finish_frame(struct allegro_channel * channel,struct mcu_msg_encode_frame_response * msg)1471 static void allegro_channel_finish_frame(struct allegro_channel *channel,
1472 struct mcu_msg_encode_frame_response *msg)
1473 {
1474 struct allegro_dev *dev = channel->dev;
1475 struct vb2_v4l2_buffer *src_buf;
1476 struct vb2_v4l2_buffer *dst_buf;
1477 struct {
1478 u32 offset;
1479 u32 size;
1480 } *partition;
1481 enum vb2_buffer_state state = VB2_BUF_STATE_ERROR;
1482 char *curr;
1483 ssize_t len;
1484 ssize_t free;
1485
1486 src_buf = allegro_get_buffer(channel, &channel->source_shadow_list,
1487 msg->src_handle);
1488 if (!src_buf)
1489 v4l2_warn(&dev->v4l2_dev,
1490 "channel %d: invalid source buffer\n",
1491 channel->mcu_channel_id);
1492
1493 dst_buf = allegro_get_buffer(channel, &channel->stream_shadow_list,
1494 msg->stream_id);
1495 if (!dst_buf)
1496 v4l2_warn(&dev->v4l2_dev,
1497 "channel %d: invalid stream buffer\n",
1498 channel->mcu_channel_id);
1499
1500 if (!src_buf || !dst_buf)
1501 goto err;
1502
1503 dst_buf->sequence = channel->csequence++;
1504
1505 if (msg->error_code & AL_ERROR) {
1506 v4l2_err(&dev->v4l2_dev,
1507 "channel %d: failed to encode frame: %s (%x)\n",
1508 channel->mcu_channel_id,
1509 allegro_err_to_string(msg->error_code),
1510 msg->error_code);
1511 goto err;
1512 }
1513
1514 if (msg->partition_table_size != 1) {
1515 v4l2_warn(&dev->v4l2_dev,
1516 "channel %d: only handling first partition table entry (%d entries)\n",
1517 channel->mcu_channel_id, msg->partition_table_size);
1518 }
1519
1520 if (msg->partition_table_offset +
1521 msg->partition_table_size * sizeof(*partition) >
1522 vb2_plane_size(&dst_buf->vb2_buf, 0)) {
1523 v4l2_err(&dev->v4l2_dev,
1524 "channel %d: partition table outside of dst_buf\n",
1525 channel->mcu_channel_id);
1526 goto err;
1527 }
1528
1529 partition =
1530 vb2_plane_vaddr(&dst_buf->vb2_buf, 0) + msg->partition_table_offset;
1531 if (partition->offset + partition->size >
1532 vb2_plane_size(&dst_buf->vb2_buf, 0)) {
1533 v4l2_err(&dev->v4l2_dev,
1534 "channel %d: encoded frame is outside of dst_buf (offset 0x%x, size 0x%x)\n",
1535 channel->mcu_channel_id, partition->offset,
1536 partition->size);
1537 goto err;
1538 }
1539
1540 v4l2_dbg(2, debug, &dev->v4l2_dev,
1541 "channel %d: encoded frame of size %d is at offset 0x%x\n",
1542 channel->mcu_channel_id, partition->size, partition->offset);
1543
1544 /*
1545 * The payload must include the data before the partition offset,
1546 * because we will put the sps and pps data there.
1547 */
1548 vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
1549 partition->offset + partition->size);
1550
1551 curr = vb2_plane_vaddr(&dst_buf->vb2_buf, 0);
1552 free = partition->offset;
1553 if (msg->is_idr) {
1554 len = allegro_h264_write_sps(channel, curr, free);
1555 if (len < 0) {
1556 v4l2_err(&dev->v4l2_dev,
1557 "not enough space for sequence parameter set: %zd left\n",
1558 free);
1559 goto err;
1560 }
1561 curr += len;
1562 free -= len;
1563 v4l2_dbg(1, debug, &dev->v4l2_dev,
1564 "channel %d: wrote %zd byte SPS nal unit\n",
1565 channel->mcu_channel_id, len);
1566 }
1567
1568 if (msg->slice_type == AL_ENC_SLICE_TYPE_I) {
1569 len = allegro_h264_write_pps(channel, curr, free);
1570 if (len < 0) {
1571 v4l2_err(&dev->v4l2_dev,
1572 "not enough space for picture parameter set: %zd left\n",
1573 free);
1574 goto err;
1575 }
1576 curr += len;
1577 free -= len;
1578 v4l2_dbg(1, debug, &dev->v4l2_dev,
1579 "channel %d: wrote %zd byte PPS nal unit\n",
1580 channel->mcu_channel_id, len);
1581 }
1582
1583 if (msg->slice_type != AL_ENC_SLICE_TYPE_I && !msg->is_idr) {
1584 dst_buf->vb2_buf.planes[0].data_offset = free;
1585 free = 0;
1586 } else {
1587 len = nal_h264_write_filler(&dev->plat_dev->dev, curr, free);
1588 if (len < 0) {
1589 v4l2_err(&dev->v4l2_dev,
1590 "failed to write %zd filler data\n", free);
1591 goto err;
1592 }
1593 curr += len;
1594 free -= len;
1595 v4l2_dbg(2, debug, &dev->v4l2_dev,
1596 "channel %d: wrote %zd bytes filler nal unit\n",
1597 channel->mcu_channel_id, len);
1598 }
1599
1600 if (free != 0) {
1601 v4l2_err(&dev->v4l2_dev,
1602 "non-VCL NAL units do not fill space until VCL NAL unit: %zd bytes left\n",
1603 free);
1604 goto err;
1605 }
1606
1607 state = VB2_BUF_STATE_DONE;
1608
1609 v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, false);
1610 if (msg->is_idr)
1611 dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
1612 else
1613 dst_buf->flags |= V4L2_BUF_FLAG_PFRAME;
1614
1615 v4l2_dbg(1, debug, &dev->v4l2_dev,
1616 "channel %d: encoded frame #%03d (%s%s, QP %d, %d bytes)\n",
1617 channel->mcu_channel_id,
1618 dst_buf->sequence,
1619 msg->is_idr ? "IDR, " : "",
1620 msg->slice_type == AL_ENC_SLICE_TYPE_I ? "I slice" :
1621 msg->slice_type == AL_ENC_SLICE_TYPE_P ? "P slice" : "unknown",
1622 msg->qp, partition->size);
1623
1624 err:
1625 if (src_buf)
1626 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
1627
1628 if (dst_buf)
1629 allegro_channel_buf_done(channel, dst_buf, state);
1630 }
1631
allegro_handle_init(struct allegro_dev * dev,struct mcu_msg_init_response * msg)1632 static int allegro_handle_init(struct allegro_dev *dev,
1633 struct mcu_msg_init_response *msg)
1634 {
1635 complete(&dev->init_complete);
1636
1637 return 0;
1638 }
1639
1640 static int
allegro_handle_create_channel(struct allegro_dev * dev,struct mcu_msg_create_channel_response * msg)1641 allegro_handle_create_channel(struct allegro_dev *dev,
1642 struct mcu_msg_create_channel_response *msg)
1643 {
1644 struct allegro_channel *channel;
1645 int err = 0;
1646 struct create_channel_param param;
1647
1648 channel = allegro_find_channel_by_user_id(dev, msg->user_id);
1649 if (IS_ERR(channel)) {
1650 v4l2_warn(&dev->v4l2_dev,
1651 "received %s for unknown user %d\n",
1652 msg_type_name(msg->header.type),
1653 msg->user_id);
1654 return -EINVAL;
1655 }
1656
1657 if (msg->error_code) {
1658 v4l2_err(&dev->v4l2_dev,
1659 "user %d: mcu failed to create channel: %s (%x)\n",
1660 channel->user_id,
1661 allegro_err_to_string(msg->error_code),
1662 msg->error_code);
1663 err = -EIO;
1664 goto out;
1665 }
1666
1667 channel->mcu_channel_id = msg->channel_id;
1668 v4l2_dbg(1, debug, &dev->v4l2_dev,
1669 "user %d: channel has channel id %d\n",
1670 channel->user_id, channel->mcu_channel_id);
1671
1672 err = allegro_decode_config_blob(¶m, msg, channel->config_blob.vaddr);
1673 allegro_free_buffer(channel->dev, &channel->config_blob);
1674 if (err)
1675 goto out;
1676
1677 channel->num_ref_idx_l0 = param.num_ref_idx_l0;
1678 channel->num_ref_idx_l1 = param.num_ref_idx_l1;
1679
1680 v4l2_dbg(1, debug, &dev->v4l2_dev,
1681 "channel %d: intermediate buffers: %d x %d bytes\n",
1682 channel->mcu_channel_id,
1683 msg->int_buffers_count, msg->int_buffers_size);
1684 err = allocate_intermediate_buffers(channel, msg->int_buffers_count,
1685 msg->int_buffers_size);
1686 if (err) {
1687 v4l2_err(&dev->v4l2_dev,
1688 "channel %d: failed to allocate intermediate buffers\n",
1689 channel->mcu_channel_id);
1690 goto out;
1691 }
1692 err = allegro_mcu_push_buffer_intermediate(channel);
1693 if (err)
1694 goto out;
1695
1696 v4l2_dbg(1, debug, &dev->v4l2_dev,
1697 "channel %d: reference buffers: %d x %d bytes\n",
1698 channel->mcu_channel_id,
1699 msg->rec_buffers_count, msg->rec_buffers_size);
1700 err = allocate_reference_buffers(channel, msg->rec_buffers_count,
1701 msg->rec_buffers_size);
1702 if (err) {
1703 v4l2_err(&dev->v4l2_dev,
1704 "channel %d: failed to allocate reference buffers\n",
1705 channel->mcu_channel_id);
1706 goto out;
1707 }
1708 err = allegro_mcu_push_buffer_reference(channel);
1709 if (err)
1710 goto out;
1711
1712 out:
1713 channel->error = err;
1714 complete(&channel->completion);
1715
1716 /* Handled successfully, error is passed via channel->error */
1717 return 0;
1718 }
1719
1720 static int
allegro_handle_destroy_channel(struct allegro_dev * dev,struct mcu_msg_destroy_channel_response * msg)1721 allegro_handle_destroy_channel(struct allegro_dev *dev,
1722 struct mcu_msg_destroy_channel_response *msg)
1723 {
1724 struct allegro_channel *channel;
1725
1726 channel = allegro_find_channel_by_channel_id(dev, msg->channel_id);
1727 if (IS_ERR(channel)) {
1728 v4l2_err(&dev->v4l2_dev,
1729 "received %s for unknown channel %d\n",
1730 msg_type_name(msg->header.type),
1731 msg->channel_id);
1732 return -EINVAL;
1733 }
1734
1735 v4l2_dbg(2, debug, &dev->v4l2_dev,
1736 "user %d: vcu destroyed channel %d\n",
1737 channel->user_id, channel->mcu_channel_id);
1738 complete(&channel->completion);
1739
1740 return 0;
1741 }
1742
1743 static int
allegro_handle_encode_frame(struct allegro_dev * dev,struct mcu_msg_encode_frame_response * msg)1744 allegro_handle_encode_frame(struct allegro_dev *dev,
1745 struct mcu_msg_encode_frame_response *msg)
1746 {
1747 struct allegro_channel *channel;
1748
1749 channel = allegro_find_channel_by_channel_id(dev, msg->channel_id);
1750 if (IS_ERR(channel)) {
1751 v4l2_err(&dev->v4l2_dev,
1752 "received %s for unknown channel %d\n",
1753 msg_type_name(msg->header.type),
1754 msg->channel_id);
1755 return -EINVAL;
1756 }
1757
1758 allegro_channel_finish_frame(channel, msg);
1759
1760 return 0;
1761 }
1762
allegro_handle_message(struct allegro_dev * dev,union mcu_msg_response * msg)1763 static void allegro_handle_message(struct allegro_dev *dev,
1764 union mcu_msg_response *msg)
1765 {
1766 switch (msg->header.type) {
1767 case MCU_MSG_TYPE_INIT:
1768 allegro_handle_init(dev, &msg->init);
1769 break;
1770 case MCU_MSG_TYPE_CREATE_CHANNEL:
1771 allegro_handle_create_channel(dev, &msg->create_channel);
1772 break;
1773 case MCU_MSG_TYPE_DESTROY_CHANNEL:
1774 allegro_handle_destroy_channel(dev, &msg->destroy_channel);
1775 break;
1776 case MCU_MSG_TYPE_ENCODE_FRAME:
1777 allegro_handle_encode_frame(dev, &msg->encode_frame);
1778 break;
1779 default:
1780 v4l2_warn(&dev->v4l2_dev,
1781 "%s: unknown message %s\n",
1782 __func__, msg_type_name(msg->header.type));
1783 break;
1784 }
1785 }
1786
allegro_hardirq(int irq,void * data)1787 static irqreturn_t allegro_hardirq(int irq, void *data)
1788 {
1789 struct allegro_dev *dev = data;
1790 unsigned int status;
1791
1792 regmap_read(dev->regmap, AL5_ITC_CPU_IRQ_STA, &status);
1793 if (!(status & AL5_ITC_CPU_IRQ_STA_TRIGGERED))
1794 return IRQ_NONE;
1795
1796 regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_CLR, status);
1797
1798 return IRQ_WAKE_THREAD;
1799 }
1800
allegro_irq_thread(int irq,void * data)1801 static irqreturn_t allegro_irq_thread(int irq, void *data)
1802 {
1803 struct allegro_dev *dev = data;
1804
1805 allegro_mbox_notify(dev->mbox_status);
1806
1807 return IRQ_HANDLED;
1808 }
1809
allegro_copy_firmware(struct allegro_dev * dev,const u8 * const buf,size_t size)1810 static void allegro_copy_firmware(struct allegro_dev *dev,
1811 const u8 * const buf, size_t size)
1812 {
1813 int err = 0;
1814
1815 v4l2_dbg(1, debug, &dev->v4l2_dev,
1816 "copy mcu firmware (%zu B) to SRAM\n", size);
1817 err = regmap_bulk_write(dev->sram, 0x0, buf, size / 4);
1818 if (err)
1819 v4l2_err(&dev->v4l2_dev,
1820 "failed to copy firmware: %d\n", err);
1821 }
1822
allegro_copy_fw_codec(struct allegro_dev * dev,const u8 * const buf,size_t size)1823 static void allegro_copy_fw_codec(struct allegro_dev *dev,
1824 const u8 * const buf, size_t size)
1825 {
1826 int err;
1827 dma_addr_t icache_offset, dcache_offset;
1828
1829 /*
1830 * The downstream allocates 600 KB for the codec firmware to have some
1831 * extra space for "possible extensions." My tests were fine with
1832 * allocating just enough memory for the actual firmware, but I am not
1833 * sure that the firmware really does not use the remaining space.
1834 */
1835 err = allegro_alloc_buffer(dev, &dev->firmware, size);
1836 if (err) {
1837 v4l2_err(&dev->v4l2_dev,
1838 "failed to allocate %zu bytes for firmware\n", size);
1839 return;
1840 }
1841
1842 v4l2_dbg(1, debug, &dev->v4l2_dev,
1843 "copy codec firmware (%zd B) to phys %pad\n",
1844 size, &dev->firmware.paddr);
1845 memcpy(dev->firmware.vaddr, buf, size);
1846
1847 regmap_write(dev->regmap, AXI_ADDR_OFFSET_IP,
1848 upper_32_bits(dev->firmware.paddr));
1849
1850 icache_offset = dev->firmware.paddr - MCU_CACHE_OFFSET;
1851 v4l2_dbg(2, debug, &dev->v4l2_dev,
1852 "icache_offset: msb = 0x%x, lsb = 0x%x\n",
1853 upper_32_bits(icache_offset), lower_32_bits(icache_offset));
1854 regmap_write(dev->regmap, AL5_ICACHE_ADDR_OFFSET_MSB,
1855 upper_32_bits(icache_offset));
1856 regmap_write(dev->regmap, AL5_ICACHE_ADDR_OFFSET_LSB,
1857 lower_32_bits(icache_offset));
1858
1859 dcache_offset =
1860 (dev->firmware.paddr & 0xffffffff00000000ULL) - MCU_CACHE_OFFSET;
1861 v4l2_dbg(2, debug, &dev->v4l2_dev,
1862 "dcache_offset: msb = 0x%x, lsb = 0x%x\n",
1863 upper_32_bits(dcache_offset), lower_32_bits(dcache_offset));
1864 regmap_write(dev->regmap, AL5_DCACHE_ADDR_OFFSET_MSB,
1865 upper_32_bits(dcache_offset));
1866 regmap_write(dev->regmap, AL5_DCACHE_ADDR_OFFSET_LSB,
1867 lower_32_bits(dcache_offset));
1868 }
1869
allegro_free_fw_codec(struct allegro_dev * dev)1870 static void allegro_free_fw_codec(struct allegro_dev *dev)
1871 {
1872 allegro_free_buffer(dev, &dev->firmware);
1873 }
1874
1875 /*
1876 * Control functions for the MCU
1877 */
1878
allegro_mcu_enable_interrupts(struct allegro_dev * dev)1879 static int allegro_mcu_enable_interrupts(struct allegro_dev *dev)
1880 {
1881 return regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_MSK, BIT(0));
1882 }
1883
allegro_mcu_disable_interrupts(struct allegro_dev * dev)1884 static int allegro_mcu_disable_interrupts(struct allegro_dev *dev)
1885 {
1886 return regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_MSK, 0);
1887 }
1888
allegro_mcu_wait_for_sleep(struct allegro_dev * dev)1889 static int allegro_mcu_wait_for_sleep(struct allegro_dev *dev)
1890 {
1891 unsigned long timeout;
1892 unsigned int status;
1893
1894 timeout = jiffies + msecs_to_jiffies(100);
1895 while (regmap_read(dev->regmap, AL5_MCU_STA, &status) == 0 &&
1896 status != AL5_MCU_STA_SLEEP) {
1897 if (time_after(jiffies, timeout))
1898 return -ETIMEDOUT;
1899 cpu_relax();
1900 }
1901
1902 return 0;
1903 }
1904
allegro_mcu_start(struct allegro_dev * dev)1905 static int allegro_mcu_start(struct allegro_dev *dev)
1906 {
1907 unsigned long timeout;
1908 unsigned int status;
1909 int err;
1910
1911 err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, BIT(0));
1912 if (err)
1913 return err;
1914
1915 timeout = jiffies + msecs_to_jiffies(100);
1916 while (regmap_read(dev->regmap, AL5_MCU_STA, &status) == 0 &&
1917 status == AL5_MCU_STA_SLEEP) {
1918 if (time_after(jiffies, timeout))
1919 return -ETIMEDOUT;
1920 cpu_relax();
1921 }
1922
1923 err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, 0);
1924 if (err)
1925 return err;
1926
1927 return 0;
1928 }
1929
allegro_mcu_reset(struct allegro_dev * dev)1930 static int allegro_mcu_reset(struct allegro_dev *dev)
1931 {
1932 int err;
1933
1934 /*
1935 * Ensure that the AL5_MCU_WAKEUP bit is set to 0 otherwise the mcu
1936 * does not go to sleep after the reset.
1937 */
1938 err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, 0);
1939 if (err)
1940 return err;
1941
1942 err = regmap_write(dev->regmap,
1943 AL5_MCU_RESET_MODE, AL5_MCU_RESET_MODE_SLEEP);
1944 if (err < 0)
1945 return err;
1946
1947 err = regmap_write(dev->regmap, AL5_MCU_RESET, AL5_MCU_RESET_SOFT);
1948 if (err < 0)
1949 return err;
1950
1951 return allegro_mcu_wait_for_sleep(dev);
1952 }
1953
allegro_mcu_interrupt(struct allegro_dev * dev)1954 static void allegro_mcu_interrupt(struct allegro_dev *dev)
1955 {
1956 regmap_write(dev->regmap, AL5_MCU_INTERRUPT, BIT(0));
1957 }
1958
allegro_destroy_channel(struct allegro_channel * channel)1959 static void allegro_destroy_channel(struct allegro_channel *channel)
1960 {
1961 struct allegro_dev *dev = channel->dev;
1962 unsigned long timeout;
1963
1964 if (channel_exists(channel)) {
1965 reinit_completion(&channel->completion);
1966 allegro_mcu_send_destroy_channel(dev, channel);
1967 timeout = wait_for_completion_timeout(&channel->completion,
1968 msecs_to_jiffies(5000));
1969 if (timeout == 0)
1970 v4l2_warn(&dev->v4l2_dev,
1971 "channel %d: timeout while destroying\n",
1972 channel->mcu_channel_id);
1973
1974 channel->mcu_channel_id = -1;
1975 }
1976
1977 destroy_intermediate_buffers(channel);
1978 destroy_reference_buffers(channel);
1979
1980 v4l2_ctrl_grab(channel->mpeg_video_h264_profile, false);
1981 v4l2_ctrl_grab(channel->mpeg_video_h264_level, false);
1982 v4l2_ctrl_grab(channel->mpeg_video_h264_i_frame_qp, false);
1983 v4l2_ctrl_grab(channel->mpeg_video_h264_max_qp, false);
1984 v4l2_ctrl_grab(channel->mpeg_video_h264_min_qp, false);
1985 v4l2_ctrl_grab(channel->mpeg_video_h264_p_frame_qp, false);
1986 v4l2_ctrl_grab(channel->mpeg_video_h264_b_frame_qp, false);
1987 v4l2_ctrl_grab(channel->mpeg_video_frame_rc_enable, false);
1988 v4l2_ctrl_grab(channel->mpeg_video_bitrate_mode, false);
1989 v4l2_ctrl_grab(channel->mpeg_video_bitrate, false);
1990 v4l2_ctrl_grab(channel->mpeg_video_bitrate_peak, false);
1991 v4l2_ctrl_grab(channel->mpeg_video_cpb_size, false);
1992 v4l2_ctrl_grab(channel->mpeg_video_gop_size, false);
1993
1994 if (channel->user_id != -1) {
1995 clear_bit(channel->user_id, &dev->channel_user_ids);
1996 channel->user_id = -1;
1997 }
1998 }
1999
2000 /*
2001 * Create the MCU channel
2002 *
2003 * After the channel has been created, the picture size, format, colorspace
2004 * and framerate are fixed. Also the codec, profile, bitrate, etc. cannot be
2005 * changed anymore.
2006 *
2007 * The channel can be created only once. The MCU will accept source buffers
2008 * and stream buffers only after a channel has been created.
2009 */
allegro_create_channel(struct allegro_channel * channel)2010 static int allegro_create_channel(struct allegro_channel *channel)
2011 {
2012 struct allegro_dev *dev = channel->dev;
2013 unsigned long timeout;
2014 enum v4l2_mpeg_video_h264_level min_level;
2015
2016 if (channel_exists(channel)) {
2017 v4l2_warn(&dev->v4l2_dev,
2018 "channel already exists\n");
2019 return 0;
2020 }
2021
2022 channel->user_id = allegro_next_user_id(dev);
2023 if (channel->user_id < 0) {
2024 v4l2_err(&dev->v4l2_dev,
2025 "no free channels available\n");
2026 return -EBUSY;
2027 }
2028 set_bit(channel->user_id, &dev->channel_user_ids);
2029
2030 v4l2_dbg(1, debug, &dev->v4l2_dev,
2031 "user %d: creating channel (%4.4s, %dx%d@%d)\n",
2032 channel->user_id,
2033 (char *)&channel->codec, channel->width, channel->height,
2034 DIV_ROUND_UP(channel->framerate.numerator,
2035 channel->framerate.denominator));
2036
2037 min_level = select_minimum_h264_level(channel->width, channel->height);
2038 if (channel->level < min_level) {
2039 v4l2_warn(&dev->v4l2_dev,
2040 "user %d: selected Level %s too low: increasing to Level %s\n",
2041 channel->user_id,
2042 v4l2_ctrl_get_menu(V4L2_CID_MPEG_VIDEO_H264_LEVEL)[channel->level],
2043 v4l2_ctrl_get_menu(V4L2_CID_MPEG_VIDEO_H264_LEVEL)[min_level]);
2044 channel->level = min_level;
2045 }
2046
2047 v4l2_ctrl_grab(channel->mpeg_video_h264_profile, true);
2048 v4l2_ctrl_grab(channel->mpeg_video_h264_level, true);
2049 v4l2_ctrl_grab(channel->mpeg_video_h264_i_frame_qp, true);
2050 v4l2_ctrl_grab(channel->mpeg_video_h264_max_qp, true);
2051 v4l2_ctrl_grab(channel->mpeg_video_h264_min_qp, true);
2052 v4l2_ctrl_grab(channel->mpeg_video_h264_p_frame_qp, true);
2053 v4l2_ctrl_grab(channel->mpeg_video_h264_b_frame_qp, true);
2054 v4l2_ctrl_grab(channel->mpeg_video_frame_rc_enable, true);
2055 v4l2_ctrl_grab(channel->mpeg_video_bitrate_mode, true);
2056 v4l2_ctrl_grab(channel->mpeg_video_bitrate, true);
2057 v4l2_ctrl_grab(channel->mpeg_video_bitrate_peak, true);
2058 v4l2_ctrl_grab(channel->mpeg_video_cpb_size, true);
2059 v4l2_ctrl_grab(channel->mpeg_video_gop_size, true);
2060
2061 reinit_completion(&channel->completion);
2062 allegro_mcu_send_create_channel(dev, channel);
2063 timeout = wait_for_completion_timeout(&channel->completion,
2064 msecs_to_jiffies(5000));
2065 if (timeout == 0)
2066 channel->error = -ETIMEDOUT;
2067 if (channel->error)
2068 goto err;
2069
2070 v4l2_dbg(1, debug, &dev->v4l2_dev,
2071 "channel %d: accepting buffers\n",
2072 channel->mcu_channel_id);
2073
2074 return 0;
2075
2076 err:
2077 allegro_destroy_channel(channel);
2078
2079 return channel->error;
2080 }
2081
allegro_set_default_params(struct allegro_channel * channel)2082 static void allegro_set_default_params(struct allegro_channel *channel)
2083 {
2084 channel->width = ALLEGRO_WIDTH_DEFAULT;
2085 channel->height = ALLEGRO_HEIGHT_DEFAULT;
2086 channel->stride = round_up(channel->width, 32);
2087 channel->framerate = ALLEGRO_FRAMERATE_DEFAULT;
2088
2089 channel->colorspace = V4L2_COLORSPACE_REC709;
2090 channel->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
2091 channel->quantization = V4L2_QUANTIZATION_DEFAULT;
2092 channel->xfer_func = V4L2_XFER_FUNC_DEFAULT;
2093
2094 channel->pixelformat = V4L2_PIX_FMT_NV12;
2095 channel->sizeimage_raw = channel->stride * channel->height * 3 / 2;
2096
2097 channel->codec = V4L2_PIX_FMT_H264;
2098 channel->profile = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE;
2099 channel->level =
2100 select_minimum_h264_level(channel->width, channel->height);
2101 channel->sizeimage_encoded =
2102 estimate_stream_size(channel->width, channel->height);
2103
2104 channel->bitrate = maximum_bitrate(channel->level);
2105 channel->bitrate_peak = maximum_bitrate(channel->level);
2106 channel->cpb_size = maximum_cpb_size(channel->level);
2107 channel->gop_size = ALLEGRO_GOP_SIZE_DEFAULT;
2108 }
2109
allegro_queue_setup(struct vb2_queue * vq,unsigned int * nbuffers,unsigned int * nplanes,unsigned int sizes[],struct device * alloc_devs[])2110 static int allegro_queue_setup(struct vb2_queue *vq,
2111 unsigned int *nbuffers, unsigned int *nplanes,
2112 unsigned int sizes[],
2113 struct device *alloc_devs[])
2114 {
2115 struct allegro_channel *channel = vb2_get_drv_priv(vq);
2116 struct allegro_dev *dev = channel->dev;
2117
2118 v4l2_dbg(2, debug, &dev->v4l2_dev,
2119 "%s: queue setup[%s]: nplanes = %d\n",
2120 V4L2_TYPE_IS_OUTPUT(vq->type) ? "output" : "capture",
2121 *nplanes == 0 ? "REQBUFS" : "CREATE_BUFS", *nplanes);
2122
2123 if (*nplanes != 0) {
2124 if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
2125 if (sizes[0] < channel->sizeimage_raw)
2126 return -EINVAL;
2127 } else {
2128 if (sizes[0] < channel->sizeimage_encoded)
2129 return -EINVAL;
2130 }
2131 } else {
2132 *nplanes = 1;
2133 if (V4L2_TYPE_IS_OUTPUT(vq->type))
2134 sizes[0] = channel->sizeimage_raw;
2135 else
2136 sizes[0] = channel->sizeimage_encoded;
2137 }
2138
2139 return 0;
2140 }
2141
allegro_buf_prepare(struct vb2_buffer * vb)2142 static int allegro_buf_prepare(struct vb2_buffer *vb)
2143 {
2144 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2145 struct allegro_channel *channel = vb2_get_drv_priv(vb->vb2_queue);
2146 struct allegro_dev *dev = channel->dev;
2147
2148 if (allegro_get_state(channel) == ALLEGRO_STATE_DRAIN &&
2149 V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type))
2150 return -EBUSY;
2151
2152 if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
2153 if (vbuf->field == V4L2_FIELD_ANY)
2154 vbuf->field = V4L2_FIELD_NONE;
2155 if (vbuf->field != V4L2_FIELD_NONE) {
2156 v4l2_err(&dev->v4l2_dev,
2157 "channel %d: unsupported field\n",
2158 channel->mcu_channel_id);
2159 return -EINVAL;
2160 }
2161 }
2162
2163 return 0;
2164 }
2165
allegro_buf_queue(struct vb2_buffer * vb)2166 static void allegro_buf_queue(struct vb2_buffer *vb)
2167 {
2168 struct allegro_channel *channel = vb2_get_drv_priv(vb->vb2_queue);
2169 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2170
2171 if (allegro_get_state(channel) == ALLEGRO_STATE_WAIT_FOR_BUFFER &&
2172 vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
2173 allegro_channel_buf_done(channel, vbuf, VB2_BUF_STATE_DONE);
2174 return;
2175 }
2176
2177 v4l2_m2m_buf_queue(channel->fh.m2m_ctx, vbuf);
2178 }
2179
allegro_start_streaming(struct vb2_queue * q,unsigned int count)2180 static int allegro_start_streaming(struct vb2_queue *q, unsigned int count)
2181 {
2182 struct allegro_channel *channel = vb2_get_drv_priv(q);
2183 struct allegro_dev *dev = channel->dev;
2184
2185 v4l2_dbg(2, debug, &dev->v4l2_dev,
2186 "%s: start streaming\n",
2187 V4L2_TYPE_IS_OUTPUT(q->type) ? "output" : "capture");
2188
2189 if (V4L2_TYPE_IS_OUTPUT(q->type)) {
2190 channel->osequence = 0;
2191 allegro_set_state(channel, ALLEGRO_STATE_ENCODING);
2192 } else if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
2193 channel->csequence = 0;
2194 }
2195
2196 return 0;
2197 }
2198
allegro_stop_streaming(struct vb2_queue * q)2199 static void allegro_stop_streaming(struct vb2_queue *q)
2200 {
2201 struct allegro_channel *channel = vb2_get_drv_priv(q);
2202 struct allegro_dev *dev = channel->dev;
2203 struct vb2_v4l2_buffer *buffer;
2204 struct allegro_m2m_buffer *shadow, *tmp;
2205
2206 v4l2_dbg(2, debug, &dev->v4l2_dev,
2207 "%s: stop streaming\n",
2208 V4L2_TYPE_IS_OUTPUT(q->type) ? "output" : "capture");
2209
2210 if (V4L2_TYPE_IS_OUTPUT(q->type)) {
2211 mutex_lock(&channel->shadow_list_lock);
2212 list_for_each_entry_safe(shadow, tmp,
2213 &channel->source_shadow_list, head) {
2214 list_del(&shadow->head);
2215 v4l2_m2m_buf_done(&shadow->buf.vb, VB2_BUF_STATE_ERROR);
2216 }
2217 mutex_unlock(&channel->shadow_list_lock);
2218
2219 allegro_set_state(channel, ALLEGRO_STATE_STOPPED);
2220 while ((buffer = v4l2_m2m_src_buf_remove(channel->fh.m2m_ctx)))
2221 v4l2_m2m_buf_done(buffer, VB2_BUF_STATE_ERROR);
2222 } else if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
2223 mutex_lock(&channel->shadow_list_lock);
2224 list_for_each_entry_safe(shadow, tmp,
2225 &channel->stream_shadow_list, head) {
2226 list_del(&shadow->head);
2227 v4l2_m2m_buf_done(&shadow->buf.vb, VB2_BUF_STATE_ERROR);
2228 }
2229 mutex_unlock(&channel->shadow_list_lock);
2230
2231 allegro_destroy_channel(channel);
2232 while ((buffer = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx)))
2233 v4l2_m2m_buf_done(buffer, VB2_BUF_STATE_ERROR);
2234 }
2235 }
2236
2237 static const struct vb2_ops allegro_queue_ops = {
2238 .queue_setup = allegro_queue_setup,
2239 .buf_prepare = allegro_buf_prepare,
2240 .buf_queue = allegro_buf_queue,
2241 .start_streaming = allegro_start_streaming,
2242 .stop_streaming = allegro_stop_streaming,
2243 .wait_prepare = vb2_ops_wait_prepare,
2244 .wait_finish = vb2_ops_wait_finish,
2245 };
2246
allegro_queue_init(void * priv,struct vb2_queue * src_vq,struct vb2_queue * dst_vq)2247 static int allegro_queue_init(void *priv,
2248 struct vb2_queue *src_vq,
2249 struct vb2_queue *dst_vq)
2250 {
2251 int err;
2252 struct allegro_channel *channel = priv;
2253
2254 src_vq->dev = &channel->dev->plat_dev->dev;
2255 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
2256 src_vq->io_modes = VB2_DMABUF | VB2_MMAP;
2257 src_vq->mem_ops = &vb2_dma_contig_memops;
2258 src_vq->drv_priv = channel;
2259 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2260 src_vq->ops = &allegro_queue_ops;
2261 src_vq->buf_struct_size = sizeof(struct allegro_m2m_buffer);
2262 src_vq->lock = &channel->dev->lock;
2263 err = vb2_queue_init(src_vq);
2264 if (err)
2265 return err;
2266
2267 dst_vq->dev = &channel->dev->plat_dev->dev;
2268 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2269 dst_vq->io_modes = VB2_DMABUF | VB2_MMAP;
2270 dst_vq->mem_ops = &vb2_dma_contig_memops;
2271 dst_vq->drv_priv = channel;
2272 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2273 dst_vq->ops = &allegro_queue_ops;
2274 dst_vq->buf_struct_size = sizeof(struct allegro_m2m_buffer);
2275 dst_vq->lock = &channel->dev->lock;
2276 err = vb2_queue_init(dst_vq);
2277 if (err)
2278 return err;
2279
2280 return 0;
2281 }
2282
allegro_clamp_qp(struct allegro_channel * channel,struct v4l2_ctrl * ctrl)2283 static int allegro_clamp_qp(struct allegro_channel *channel,
2284 struct v4l2_ctrl *ctrl)
2285 {
2286 struct v4l2_ctrl *next_ctrl;
2287
2288 if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP)
2289 next_ctrl = channel->mpeg_video_h264_p_frame_qp;
2290 else if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP)
2291 next_ctrl = channel->mpeg_video_h264_b_frame_qp;
2292 else
2293 return 0;
2294
2295 /* Modify range automatically updates the value */
2296 __v4l2_ctrl_modify_range(next_ctrl, ctrl->val, 51, 1, ctrl->val);
2297
2298 return allegro_clamp_qp(channel, next_ctrl);
2299 }
2300
allegro_clamp_bitrate(struct allegro_channel * channel,struct v4l2_ctrl * ctrl)2301 static int allegro_clamp_bitrate(struct allegro_channel *channel,
2302 struct v4l2_ctrl *ctrl)
2303 {
2304 struct v4l2_ctrl *ctrl_bitrate = channel->mpeg_video_bitrate;
2305 struct v4l2_ctrl *ctrl_bitrate_peak = channel->mpeg_video_bitrate_peak;
2306
2307 if (ctrl->val == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR &&
2308 ctrl_bitrate_peak->val < ctrl_bitrate->val)
2309 ctrl_bitrate_peak->val = ctrl_bitrate->val;
2310
2311 return 0;
2312 }
2313
allegro_try_ctrl(struct v4l2_ctrl * ctrl)2314 static int allegro_try_ctrl(struct v4l2_ctrl *ctrl)
2315 {
2316 struct allegro_channel *channel = container_of(ctrl->handler,
2317 struct allegro_channel,
2318 ctrl_handler);
2319
2320 switch (ctrl->id) {
2321 case V4L2_CID_MPEG_VIDEO_BITRATE_MODE:
2322 allegro_clamp_bitrate(channel, ctrl);
2323 break;
2324 }
2325
2326 return 0;
2327 }
2328
allegro_s_ctrl(struct v4l2_ctrl * ctrl)2329 static int allegro_s_ctrl(struct v4l2_ctrl *ctrl)
2330 {
2331 struct allegro_channel *channel = container_of(ctrl->handler,
2332 struct allegro_channel,
2333 ctrl_handler);
2334 struct allegro_dev *dev = channel->dev;
2335
2336 v4l2_dbg(1, debug, &dev->v4l2_dev,
2337 "s_ctrl: %s = %d\n", v4l2_ctrl_get_name(ctrl->id), ctrl->val);
2338
2339 switch (ctrl->id) {
2340 case V4L2_CID_MPEG_VIDEO_H264_LEVEL:
2341 channel->level = ctrl->val;
2342 break;
2343 case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE:
2344 channel->frame_rc_enable = ctrl->val;
2345 break;
2346 case V4L2_CID_MPEG_VIDEO_BITRATE_MODE:
2347 channel->bitrate = channel->mpeg_video_bitrate->val;
2348 channel->bitrate_peak = channel->mpeg_video_bitrate_peak->val;
2349 v4l2_ctrl_activate(channel->mpeg_video_bitrate_peak,
2350 ctrl->val == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR);
2351 break;
2352 case V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE:
2353 channel->cpb_size = ctrl->val;
2354 break;
2355 case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
2356 channel->gop_size = ctrl->val;
2357 break;
2358 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
2359 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
2360 case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP:
2361 allegro_clamp_qp(channel, ctrl);
2362 break;
2363 }
2364
2365 return 0;
2366 }
2367
2368 static const struct v4l2_ctrl_ops allegro_ctrl_ops = {
2369 .try_ctrl = allegro_try_ctrl,
2370 .s_ctrl = allegro_s_ctrl,
2371 };
2372
allegro_open(struct file * file)2373 static int allegro_open(struct file *file)
2374 {
2375 struct video_device *vdev = video_devdata(file);
2376 struct allegro_dev *dev = video_get_drvdata(vdev);
2377 struct allegro_channel *channel = NULL;
2378 struct v4l2_ctrl_handler *handler;
2379 u64 mask;
2380 int ret;
2381
2382 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
2383 if (!channel)
2384 return -ENOMEM;
2385
2386 v4l2_fh_init(&channel->fh, vdev);
2387
2388 init_completion(&channel->completion);
2389 INIT_LIST_HEAD(&channel->source_shadow_list);
2390 INIT_LIST_HEAD(&channel->stream_shadow_list);
2391 mutex_init(&channel->shadow_list_lock);
2392
2393 channel->dev = dev;
2394
2395 allegro_set_default_params(channel);
2396
2397 handler = &channel->ctrl_handler;
2398 v4l2_ctrl_handler_init(handler, 0);
2399 channel->mpeg_video_h264_profile = v4l2_ctrl_new_std_menu(handler,
2400 &allegro_ctrl_ops,
2401 V4L2_CID_MPEG_VIDEO_H264_PROFILE,
2402 V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, 0x0,
2403 V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE);
2404 mask = 1 << V4L2_MPEG_VIDEO_H264_LEVEL_1B;
2405 channel->mpeg_video_h264_level = v4l2_ctrl_new_std_menu(handler,
2406 &allegro_ctrl_ops,
2407 V4L2_CID_MPEG_VIDEO_H264_LEVEL,
2408 V4L2_MPEG_VIDEO_H264_LEVEL_5_1, mask,
2409 V4L2_MPEG_VIDEO_H264_LEVEL_5_1);
2410 channel->mpeg_video_h264_i_frame_qp =
2411 v4l2_ctrl_new_std(handler,
2412 &allegro_ctrl_ops,
2413 V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP,
2414 0, 51, 1, 30);
2415 channel->mpeg_video_h264_max_qp =
2416 v4l2_ctrl_new_std(handler,
2417 &allegro_ctrl_ops,
2418 V4L2_CID_MPEG_VIDEO_H264_MAX_QP,
2419 0, 51, 1, 51);
2420 channel->mpeg_video_h264_min_qp =
2421 v4l2_ctrl_new_std(handler,
2422 &allegro_ctrl_ops,
2423 V4L2_CID_MPEG_VIDEO_H264_MIN_QP,
2424 0, 51, 1, 0);
2425 channel->mpeg_video_h264_p_frame_qp =
2426 v4l2_ctrl_new_std(handler,
2427 &allegro_ctrl_ops,
2428 V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP,
2429 0, 51, 1, 30);
2430 channel->mpeg_video_h264_b_frame_qp =
2431 v4l2_ctrl_new_std(handler,
2432 &allegro_ctrl_ops,
2433 V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP,
2434 0, 51, 1, 30);
2435 channel->mpeg_video_frame_rc_enable =
2436 v4l2_ctrl_new_std(handler,
2437 &allegro_ctrl_ops,
2438 V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE,
2439 false, 0x1,
2440 true, false);
2441 channel->mpeg_video_bitrate_mode = v4l2_ctrl_new_std_menu(handler,
2442 &allegro_ctrl_ops,
2443 V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
2444 V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, 0,
2445 V4L2_MPEG_VIDEO_BITRATE_MODE_CBR);
2446 channel->mpeg_video_bitrate = v4l2_ctrl_new_std(handler,
2447 &allegro_ctrl_ops,
2448 V4L2_CID_MPEG_VIDEO_BITRATE,
2449 0, maximum_bitrate(V4L2_MPEG_VIDEO_H264_LEVEL_5_1),
2450 1, channel->bitrate);
2451 channel->mpeg_video_bitrate_peak = v4l2_ctrl_new_std(handler,
2452 &allegro_ctrl_ops,
2453 V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
2454 0, maximum_bitrate(V4L2_MPEG_VIDEO_H264_LEVEL_5_1),
2455 1, channel->bitrate_peak);
2456 channel->mpeg_video_cpb_size = v4l2_ctrl_new_std(handler,
2457 &allegro_ctrl_ops,
2458 V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE,
2459 0, maximum_cpb_size(V4L2_MPEG_VIDEO_H264_LEVEL_5_1),
2460 1, channel->cpb_size);
2461 channel->mpeg_video_gop_size = v4l2_ctrl_new_std(handler,
2462 &allegro_ctrl_ops,
2463 V4L2_CID_MPEG_VIDEO_GOP_SIZE,
2464 0, ALLEGRO_GOP_SIZE_MAX,
2465 1, channel->gop_size);
2466 v4l2_ctrl_new_std(handler,
2467 &allegro_ctrl_ops,
2468 V4L2_CID_MIN_BUFFERS_FOR_OUTPUT,
2469 1, 32,
2470 1, 1);
2471 if (handler->error != 0) {
2472 ret = handler->error;
2473 goto error;
2474 }
2475
2476 channel->fh.ctrl_handler = handler;
2477
2478 v4l2_ctrl_cluster(3, &channel->mpeg_video_bitrate_mode);
2479
2480 channel->mcu_channel_id = -1;
2481 channel->user_id = -1;
2482
2483 INIT_LIST_HEAD(&channel->buffers_reference);
2484 INIT_LIST_HEAD(&channel->buffers_intermediate);
2485
2486 list_add(&channel->list, &dev->channels);
2487
2488 channel->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, channel,
2489 allegro_queue_init);
2490
2491 if (IS_ERR(channel->fh.m2m_ctx)) {
2492 ret = PTR_ERR(channel->fh.m2m_ctx);
2493 goto error;
2494 }
2495
2496 file->private_data = &channel->fh;
2497 v4l2_fh_add(&channel->fh);
2498
2499 return 0;
2500
2501 error:
2502 v4l2_ctrl_handler_free(handler);
2503 kfree(channel);
2504 return ret;
2505 }
2506
allegro_release(struct file * file)2507 static int allegro_release(struct file *file)
2508 {
2509 struct allegro_channel *channel = fh_to_channel(file->private_data);
2510
2511 v4l2_m2m_ctx_release(channel->fh.m2m_ctx);
2512
2513 list_del(&channel->list);
2514
2515 v4l2_ctrl_handler_free(&channel->ctrl_handler);
2516
2517 v4l2_fh_del(&channel->fh);
2518 v4l2_fh_exit(&channel->fh);
2519
2520 kfree(channel);
2521
2522 return 0;
2523 }
2524
allegro_querycap(struct file * file,void * fh,struct v4l2_capability * cap)2525 static int allegro_querycap(struct file *file, void *fh,
2526 struct v4l2_capability *cap)
2527 {
2528 struct video_device *vdev = video_devdata(file);
2529 struct allegro_dev *dev = video_get_drvdata(vdev);
2530
2531 strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver));
2532 strscpy(cap->card, "Allegro DVT Video Encoder", sizeof(cap->card));
2533 snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
2534 dev_name(&dev->plat_dev->dev));
2535
2536 return 0;
2537 }
2538
allegro_enum_fmt_vid(struct file * file,void * fh,struct v4l2_fmtdesc * f)2539 static int allegro_enum_fmt_vid(struct file *file, void *fh,
2540 struct v4l2_fmtdesc *f)
2541 {
2542 if (f->index)
2543 return -EINVAL;
2544 switch (f->type) {
2545 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
2546 f->pixelformat = V4L2_PIX_FMT_NV12;
2547 break;
2548 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
2549 f->pixelformat = V4L2_PIX_FMT_H264;
2550 break;
2551 default:
2552 return -EINVAL;
2553 }
2554 return 0;
2555 }
2556
allegro_g_fmt_vid_cap(struct file * file,void * fh,struct v4l2_format * f)2557 static int allegro_g_fmt_vid_cap(struct file *file, void *fh,
2558 struct v4l2_format *f)
2559 {
2560 struct allegro_channel *channel = fh_to_channel(fh);
2561
2562 f->fmt.pix.field = V4L2_FIELD_NONE;
2563 f->fmt.pix.width = channel->width;
2564 f->fmt.pix.height = channel->height;
2565
2566 f->fmt.pix.colorspace = channel->colorspace;
2567 f->fmt.pix.ycbcr_enc = channel->ycbcr_enc;
2568 f->fmt.pix.quantization = channel->quantization;
2569 f->fmt.pix.xfer_func = channel->xfer_func;
2570
2571 f->fmt.pix.pixelformat = channel->codec;
2572 f->fmt.pix.bytesperline = 0;
2573 f->fmt.pix.sizeimage = channel->sizeimage_encoded;
2574
2575 return 0;
2576 }
2577
allegro_try_fmt_vid_cap(struct file * file,void * fh,struct v4l2_format * f)2578 static int allegro_try_fmt_vid_cap(struct file *file, void *fh,
2579 struct v4l2_format *f)
2580 {
2581 f->fmt.pix.field = V4L2_FIELD_NONE;
2582
2583 f->fmt.pix.width = clamp_t(__u32, f->fmt.pix.width,
2584 ALLEGRO_WIDTH_MIN, ALLEGRO_WIDTH_MAX);
2585 f->fmt.pix.height = clamp_t(__u32, f->fmt.pix.height,
2586 ALLEGRO_HEIGHT_MIN, ALLEGRO_HEIGHT_MAX);
2587
2588 f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
2589 f->fmt.pix.bytesperline = 0;
2590 f->fmt.pix.sizeimage =
2591 estimate_stream_size(f->fmt.pix.width, f->fmt.pix.height);
2592
2593 return 0;
2594 }
2595
allegro_g_fmt_vid_out(struct file * file,void * fh,struct v4l2_format * f)2596 static int allegro_g_fmt_vid_out(struct file *file, void *fh,
2597 struct v4l2_format *f)
2598 {
2599 struct allegro_channel *channel = fh_to_channel(fh);
2600
2601 f->fmt.pix.field = V4L2_FIELD_NONE;
2602
2603 f->fmt.pix.width = channel->width;
2604 f->fmt.pix.height = channel->height;
2605
2606 f->fmt.pix.colorspace = channel->colorspace;
2607 f->fmt.pix.ycbcr_enc = channel->ycbcr_enc;
2608 f->fmt.pix.quantization = channel->quantization;
2609 f->fmt.pix.xfer_func = channel->xfer_func;
2610
2611 f->fmt.pix.pixelformat = channel->pixelformat;
2612 f->fmt.pix.bytesperline = channel->stride;
2613 f->fmt.pix.sizeimage = channel->sizeimage_raw;
2614
2615 return 0;
2616 }
2617
allegro_try_fmt_vid_out(struct file * file,void * fh,struct v4l2_format * f)2618 static int allegro_try_fmt_vid_out(struct file *file, void *fh,
2619 struct v4l2_format *f)
2620 {
2621 f->fmt.pix.field = V4L2_FIELD_NONE;
2622
2623 /*
2624 * The firmware of the Allegro codec handles the padding internally
2625 * and expects the visual frame size when configuring a channel.
2626 * Therefore, unlike other encoder drivers, this driver does not round
2627 * up the width and height to macroblock alignment and does not
2628 * implement the selection api.
2629 */
2630 f->fmt.pix.width = clamp_t(__u32, f->fmt.pix.width,
2631 ALLEGRO_WIDTH_MIN, ALLEGRO_WIDTH_MAX);
2632 f->fmt.pix.height = clamp_t(__u32, f->fmt.pix.height,
2633 ALLEGRO_HEIGHT_MIN, ALLEGRO_HEIGHT_MAX);
2634
2635 f->fmt.pix.pixelformat = V4L2_PIX_FMT_NV12;
2636 f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 32);
2637 f->fmt.pix.sizeimage =
2638 f->fmt.pix.bytesperline * f->fmt.pix.height * 3 / 2;
2639
2640 return 0;
2641 }
2642
allegro_s_fmt_vid_out(struct file * file,void * fh,struct v4l2_format * f)2643 static int allegro_s_fmt_vid_out(struct file *file, void *fh,
2644 struct v4l2_format *f)
2645 {
2646 struct allegro_channel *channel = fh_to_channel(fh);
2647 int err;
2648
2649 err = allegro_try_fmt_vid_out(file, fh, f);
2650 if (err)
2651 return err;
2652
2653 channel->width = f->fmt.pix.width;
2654 channel->height = f->fmt.pix.height;
2655 channel->stride = f->fmt.pix.bytesperline;
2656 channel->sizeimage_raw = f->fmt.pix.sizeimage;
2657
2658 channel->colorspace = f->fmt.pix.colorspace;
2659 channel->ycbcr_enc = f->fmt.pix.ycbcr_enc;
2660 channel->quantization = f->fmt.pix.quantization;
2661 channel->xfer_func = f->fmt.pix.xfer_func;
2662
2663 channel->level =
2664 select_minimum_h264_level(channel->width, channel->height);
2665 channel->sizeimage_encoded =
2666 estimate_stream_size(channel->width, channel->height);
2667
2668 return 0;
2669 }
2670
allegro_channel_cmd_stop(struct allegro_channel * channel)2671 static int allegro_channel_cmd_stop(struct allegro_channel *channel)
2672 {
2673 struct allegro_dev *dev = channel->dev;
2674 struct vb2_v4l2_buffer *dst_buf;
2675
2676 switch (allegro_get_state(channel)) {
2677 case ALLEGRO_STATE_DRAIN:
2678 case ALLEGRO_STATE_WAIT_FOR_BUFFER:
2679 return -EBUSY;
2680 case ALLEGRO_STATE_ENCODING:
2681 allegro_set_state(channel, ALLEGRO_STATE_DRAIN);
2682 break;
2683 default:
2684 return 0;
2685 }
2686
2687 /* If there are output buffers, they must be encoded */
2688 if (v4l2_m2m_num_src_bufs_ready(channel->fh.m2m_ctx) != 0) {
2689 v4l2_dbg(1, debug, &dev->v4l2_dev,
2690 "channel %d: CMD_STOP: continue encoding src buffers\n",
2691 channel->mcu_channel_id);
2692 return 0;
2693 }
2694
2695 /* If there are capture buffers, use it to signal EOS */
2696 dst_buf = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx);
2697 if (dst_buf) {
2698 v4l2_dbg(1, debug, &dev->v4l2_dev,
2699 "channel %d: CMD_STOP: signaling EOS\n",
2700 channel->mcu_channel_id);
2701 allegro_channel_buf_done(channel, dst_buf, VB2_BUF_STATE_DONE);
2702 return 0;
2703 }
2704
2705 /*
2706 * If there are no capture buffers, we need to wait for the next
2707 * buffer to signal EOS.
2708 */
2709 v4l2_dbg(1, debug, &dev->v4l2_dev,
2710 "channel %d: CMD_STOP: wait for CAPTURE buffer to signal EOS\n",
2711 channel->mcu_channel_id);
2712 allegro_set_state(channel, ALLEGRO_STATE_WAIT_FOR_BUFFER);
2713
2714 return 0;
2715 }
2716
allegro_channel_cmd_start(struct allegro_channel * channel)2717 static int allegro_channel_cmd_start(struct allegro_channel *channel)
2718 {
2719 switch (allegro_get_state(channel)) {
2720 case ALLEGRO_STATE_DRAIN:
2721 case ALLEGRO_STATE_WAIT_FOR_BUFFER:
2722 return -EBUSY;
2723 case ALLEGRO_STATE_STOPPED:
2724 allegro_set_state(channel, ALLEGRO_STATE_ENCODING);
2725 break;
2726 default:
2727 return 0;
2728 }
2729
2730 return 0;
2731 }
2732
allegro_encoder_cmd(struct file * file,void * fh,struct v4l2_encoder_cmd * cmd)2733 static int allegro_encoder_cmd(struct file *file, void *fh,
2734 struct v4l2_encoder_cmd *cmd)
2735 {
2736 struct allegro_channel *channel = fh_to_channel(fh);
2737 int err;
2738
2739 err = v4l2_m2m_ioctl_try_encoder_cmd(file, fh, cmd);
2740 if (err)
2741 return err;
2742
2743 switch (cmd->cmd) {
2744 case V4L2_ENC_CMD_STOP:
2745 err = allegro_channel_cmd_stop(channel);
2746 break;
2747 case V4L2_ENC_CMD_START:
2748 err = allegro_channel_cmd_start(channel);
2749 break;
2750 default:
2751 err = -EINVAL;
2752 break;
2753 }
2754
2755 return err;
2756 }
2757
allegro_enum_framesizes(struct file * file,void * fh,struct v4l2_frmsizeenum * fsize)2758 static int allegro_enum_framesizes(struct file *file, void *fh,
2759 struct v4l2_frmsizeenum *fsize)
2760 {
2761 switch (fsize->pixel_format) {
2762 case V4L2_PIX_FMT_H264:
2763 case V4L2_PIX_FMT_NV12:
2764 break;
2765 default:
2766 return -EINVAL;
2767 }
2768
2769 if (fsize->index)
2770 return -EINVAL;
2771
2772 fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
2773 fsize->stepwise.min_width = ALLEGRO_WIDTH_MIN;
2774 fsize->stepwise.max_width = ALLEGRO_WIDTH_MAX;
2775 fsize->stepwise.step_width = 1;
2776 fsize->stepwise.min_height = ALLEGRO_HEIGHT_MIN;
2777 fsize->stepwise.max_height = ALLEGRO_HEIGHT_MAX;
2778 fsize->stepwise.step_height = 1;
2779
2780 return 0;
2781 }
2782
allegro_ioctl_streamon(struct file * file,void * priv,enum v4l2_buf_type type)2783 static int allegro_ioctl_streamon(struct file *file, void *priv,
2784 enum v4l2_buf_type type)
2785 {
2786 struct v4l2_fh *fh = file->private_data;
2787 struct allegro_channel *channel = fh_to_channel(fh);
2788 int err;
2789
2790 if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
2791 err = allegro_create_channel(channel);
2792 if (err)
2793 return err;
2794 }
2795
2796 return v4l2_m2m_streamon(file, fh->m2m_ctx, type);
2797 }
2798
allegro_g_parm(struct file * file,void * fh,struct v4l2_streamparm * a)2799 static int allegro_g_parm(struct file *file, void *fh,
2800 struct v4l2_streamparm *a)
2801 {
2802 struct allegro_channel *channel = fh_to_channel(fh);
2803 struct v4l2_fract *timeperframe;
2804
2805 if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
2806 return -EINVAL;
2807
2808 a->parm.output.capability = V4L2_CAP_TIMEPERFRAME;
2809 timeperframe = &a->parm.output.timeperframe;
2810 timeperframe->numerator = channel->framerate.denominator;
2811 timeperframe->denominator = channel->framerate.numerator;
2812
2813 return 0;
2814 }
2815
allegro_s_parm(struct file * file,void * fh,struct v4l2_streamparm * a)2816 static int allegro_s_parm(struct file *file, void *fh,
2817 struct v4l2_streamparm *a)
2818 {
2819 struct allegro_channel *channel = fh_to_channel(fh);
2820 struct v4l2_fract *timeperframe;
2821 int div;
2822
2823 if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
2824 return -EINVAL;
2825
2826 a->parm.output.capability = V4L2_CAP_TIMEPERFRAME;
2827 timeperframe = &a->parm.output.timeperframe;
2828
2829 if (timeperframe->numerator == 0 || timeperframe->denominator == 0)
2830 return allegro_g_parm(file, fh, a);
2831
2832 div = gcd(timeperframe->denominator, timeperframe->numerator);
2833 channel->framerate.numerator = timeperframe->denominator / div;
2834 channel->framerate.denominator = timeperframe->numerator / div;
2835
2836 return 0;
2837 }
2838
allegro_subscribe_event(struct v4l2_fh * fh,const struct v4l2_event_subscription * sub)2839 static int allegro_subscribe_event(struct v4l2_fh *fh,
2840 const struct v4l2_event_subscription *sub)
2841 {
2842 switch (sub->type) {
2843 case V4L2_EVENT_EOS:
2844 return v4l2_event_subscribe(fh, sub, 0, NULL);
2845 default:
2846 return v4l2_ctrl_subscribe_event(fh, sub);
2847 }
2848 }
2849
2850 static const struct v4l2_ioctl_ops allegro_ioctl_ops = {
2851 .vidioc_querycap = allegro_querycap,
2852 .vidioc_enum_fmt_vid_cap = allegro_enum_fmt_vid,
2853 .vidioc_enum_fmt_vid_out = allegro_enum_fmt_vid,
2854 .vidioc_g_fmt_vid_cap = allegro_g_fmt_vid_cap,
2855 .vidioc_try_fmt_vid_cap = allegro_try_fmt_vid_cap,
2856 .vidioc_s_fmt_vid_cap = allegro_try_fmt_vid_cap,
2857 .vidioc_g_fmt_vid_out = allegro_g_fmt_vid_out,
2858 .vidioc_try_fmt_vid_out = allegro_try_fmt_vid_out,
2859 .vidioc_s_fmt_vid_out = allegro_s_fmt_vid_out,
2860
2861 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
2862 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
2863
2864 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
2865 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
2866 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
2867 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
2868 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
2869
2870 .vidioc_streamon = allegro_ioctl_streamon,
2871 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
2872
2873 .vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd,
2874 .vidioc_encoder_cmd = allegro_encoder_cmd,
2875 .vidioc_enum_framesizes = allegro_enum_framesizes,
2876
2877 .vidioc_g_parm = allegro_g_parm,
2878 .vidioc_s_parm = allegro_s_parm,
2879
2880 .vidioc_subscribe_event = allegro_subscribe_event,
2881 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
2882 };
2883
2884 static const struct v4l2_file_operations allegro_fops = {
2885 .owner = THIS_MODULE,
2886 .open = allegro_open,
2887 .release = allegro_release,
2888 .poll = v4l2_m2m_fop_poll,
2889 .unlocked_ioctl = video_ioctl2,
2890 .mmap = v4l2_m2m_fop_mmap,
2891 };
2892
allegro_register_device(struct allegro_dev * dev)2893 static int allegro_register_device(struct allegro_dev *dev)
2894 {
2895 struct video_device *video_dev = &dev->video_dev;
2896
2897 strscpy(video_dev->name, "allegro", sizeof(video_dev->name));
2898 video_dev->fops = &allegro_fops;
2899 video_dev->ioctl_ops = &allegro_ioctl_ops;
2900 video_dev->release = video_device_release_empty;
2901 video_dev->lock = &dev->lock;
2902 video_dev->v4l2_dev = &dev->v4l2_dev;
2903 video_dev->vfl_dir = VFL_DIR_M2M;
2904 video_dev->device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
2905 video_set_drvdata(video_dev, dev);
2906
2907 return video_register_device(video_dev, VFL_TYPE_VIDEO, 0);
2908 }
2909
allegro_device_run(void * priv)2910 static void allegro_device_run(void *priv)
2911 {
2912 struct allegro_channel *channel = priv;
2913 struct allegro_dev *dev = channel->dev;
2914 struct vb2_v4l2_buffer *src_buf;
2915 struct vb2_v4l2_buffer *dst_buf;
2916 dma_addr_t src_y;
2917 dma_addr_t src_uv;
2918 dma_addr_t dst_addr;
2919 unsigned long dst_size;
2920 u64 src_handle;
2921 u64 dst_handle;
2922
2923 dst_buf = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx);
2924 dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
2925 dst_size = vb2_plane_size(&dst_buf->vb2_buf, 0);
2926 dst_handle = allegro_put_buffer(channel, &channel->stream_shadow_list,
2927 dst_buf);
2928 allegro_mcu_send_put_stream_buffer(dev, channel, dst_addr, dst_size,
2929 dst_handle);
2930
2931 src_buf = v4l2_m2m_src_buf_remove(channel->fh.m2m_ctx);
2932 src_buf->sequence = channel->osequence++;
2933 src_y = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
2934 src_uv = src_y + (channel->stride * channel->height);
2935 src_handle = allegro_put_buffer(channel, &channel->source_shadow_list,
2936 src_buf);
2937 allegro_mcu_send_encode_frame(dev, channel, src_y, src_uv, src_handle);
2938
2939 v4l2_m2m_job_finish(dev->m2m_dev, channel->fh.m2m_ctx);
2940 }
2941
2942 static const struct v4l2_m2m_ops allegro_m2m_ops = {
2943 .device_run = allegro_device_run,
2944 };
2945
allegro_mcu_hw_init(struct allegro_dev * dev,const struct fw_info * info)2946 static int allegro_mcu_hw_init(struct allegro_dev *dev,
2947 const struct fw_info *info)
2948 {
2949 int err;
2950
2951 dev->mbox_command = allegro_mbox_init(dev, info->mailbox_cmd,
2952 info->mailbox_size);
2953 dev->mbox_status = allegro_mbox_init(dev, info->mailbox_status,
2954 info->mailbox_size);
2955 if (IS_ERR(dev->mbox_command) || IS_ERR(dev->mbox_status)) {
2956 v4l2_err(&dev->v4l2_dev,
2957 "failed to initialize mailboxes\n");
2958 return -EIO;
2959 }
2960
2961 allegro_mcu_enable_interrupts(dev);
2962
2963 /* The mcu sends INIT after reset. */
2964 allegro_mcu_start(dev);
2965 err = allegro_mcu_wait_for_init_timeout(dev, 5000);
2966 if (err < 0) {
2967 v4l2_err(&dev->v4l2_dev,
2968 "mcu did not send INIT after reset\n");
2969 err = -EIO;
2970 goto err_disable_interrupts;
2971 }
2972
2973 err = allegro_alloc_buffer(dev, &dev->suballocator,
2974 info->suballocator_size);
2975 if (err) {
2976 v4l2_err(&dev->v4l2_dev,
2977 "failed to allocate %zu bytes for suballocator\n",
2978 info->suballocator_size);
2979 goto err_reset_mcu;
2980 }
2981
2982 allegro_mcu_send_init(dev, dev->suballocator.paddr,
2983 dev->suballocator.size);
2984 err = allegro_mcu_wait_for_init_timeout(dev, 5000);
2985 if (err < 0) {
2986 v4l2_err(&dev->v4l2_dev,
2987 "mcu failed to configure sub-allocator\n");
2988 err = -EIO;
2989 goto err_free_suballocator;
2990 }
2991
2992 return 0;
2993
2994 err_free_suballocator:
2995 allegro_free_buffer(dev, &dev->suballocator);
2996 err_reset_mcu:
2997 allegro_mcu_reset(dev);
2998 err_disable_interrupts:
2999 allegro_mcu_disable_interrupts(dev);
3000
3001 return err;
3002 }
3003
allegro_mcu_hw_deinit(struct allegro_dev * dev)3004 static int allegro_mcu_hw_deinit(struct allegro_dev *dev)
3005 {
3006 int err;
3007
3008 err = allegro_mcu_reset(dev);
3009 if (err)
3010 v4l2_warn(&dev->v4l2_dev,
3011 "mcu failed to enter sleep state\n");
3012
3013 err = allegro_mcu_disable_interrupts(dev);
3014 if (err)
3015 v4l2_warn(&dev->v4l2_dev,
3016 "failed to disable interrupts\n");
3017
3018 allegro_free_buffer(dev, &dev->suballocator);
3019
3020 return 0;
3021 }
3022
allegro_fw_callback(const struct firmware * fw,void * context)3023 static void allegro_fw_callback(const struct firmware *fw, void *context)
3024 {
3025 struct allegro_dev *dev = context;
3026 const char *fw_codec_name = "al5e.fw";
3027 const struct firmware *fw_codec;
3028 int err;
3029
3030 if (!fw)
3031 return;
3032
3033 v4l2_dbg(1, debug, &dev->v4l2_dev,
3034 "requesting codec firmware '%s'\n", fw_codec_name);
3035 err = request_firmware(&fw_codec, fw_codec_name, &dev->plat_dev->dev);
3036 if (err)
3037 goto err_release_firmware;
3038
3039 dev->fw_info = allegro_get_firmware_info(dev, fw, fw_codec);
3040 if (!dev->fw_info) {
3041 v4l2_err(&dev->v4l2_dev, "firmware is not supported\n");
3042 goto err_release_firmware_codec;
3043 }
3044
3045 v4l2_info(&dev->v4l2_dev,
3046 "using mcu firmware version '%s'\n", dev->fw_info->version);
3047
3048 /* Ensure that the mcu is sleeping at the reset vector */
3049 err = allegro_mcu_reset(dev);
3050 if (err) {
3051 v4l2_err(&dev->v4l2_dev, "failed to reset mcu\n");
3052 goto err_release_firmware_codec;
3053 }
3054
3055 allegro_copy_firmware(dev, fw->data, fw->size);
3056 allegro_copy_fw_codec(dev, fw_codec->data, fw_codec->size);
3057
3058 err = allegro_mcu_hw_init(dev, dev->fw_info);
3059 if (err) {
3060 v4l2_err(&dev->v4l2_dev, "failed to initialize mcu\n");
3061 goto err_free_fw_codec;
3062 }
3063
3064 dev->m2m_dev = v4l2_m2m_init(&allegro_m2m_ops);
3065 if (IS_ERR(dev->m2m_dev)) {
3066 v4l2_err(&dev->v4l2_dev, "failed to init mem2mem device\n");
3067 goto err_mcu_hw_deinit;
3068 }
3069
3070 err = allegro_register_device(dev);
3071 if (err) {
3072 v4l2_err(&dev->v4l2_dev, "failed to register video device\n");
3073 goto err_m2m_release;
3074 }
3075
3076 v4l2_dbg(1, debug, &dev->v4l2_dev,
3077 "allegro codec registered as /dev/video%d\n",
3078 dev->video_dev.num);
3079
3080 release_firmware(fw_codec);
3081 release_firmware(fw);
3082
3083 return;
3084
3085 err_m2m_release:
3086 v4l2_m2m_release(dev->m2m_dev);
3087 dev->m2m_dev = NULL;
3088 err_mcu_hw_deinit:
3089 allegro_mcu_hw_deinit(dev);
3090 err_free_fw_codec:
3091 allegro_free_fw_codec(dev);
3092 err_release_firmware_codec:
3093 release_firmware(fw_codec);
3094 err_release_firmware:
3095 release_firmware(fw);
3096 }
3097
allegro_firmware_request_nowait(struct allegro_dev * dev)3098 static int allegro_firmware_request_nowait(struct allegro_dev *dev)
3099 {
3100 const char *fw = "al5e_b.fw";
3101
3102 v4l2_dbg(1, debug, &dev->v4l2_dev,
3103 "requesting firmware '%s'\n", fw);
3104 return request_firmware_nowait(THIS_MODULE, true, fw,
3105 &dev->plat_dev->dev, GFP_KERNEL, dev,
3106 allegro_fw_callback);
3107 }
3108
allegro_probe(struct platform_device * pdev)3109 static int allegro_probe(struct platform_device *pdev)
3110 {
3111 struct allegro_dev *dev;
3112 struct resource *res, *sram_res;
3113 int ret;
3114 int irq;
3115 void __iomem *regs, *sram_regs;
3116
3117 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
3118 if (!dev)
3119 return -ENOMEM;
3120 dev->plat_dev = pdev;
3121 init_completion(&dev->init_complete);
3122 INIT_LIST_HEAD(&dev->channels);
3123
3124 mutex_init(&dev->lock);
3125
3126 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
3127 if (!res) {
3128 dev_err(&pdev->dev,
3129 "regs resource missing from device tree\n");
3130 return -EINVAL;
3131 }
3132 regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3133 if (!regs) {
3134 dev_err(&pdev->dev, "failed to map registers\n");
3135 return -ENOMEM;
3136 }
3137 dev->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
3138 &allegro_regmap_config);
3139 if (IS_ERR(dev->regmap)) {
3140 dev_err(&pdev->dev, "failed to init regmap\n");
3141 return PTR_ERR(dev->regmap);
3142 }
3143
3144 sram_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
3145 if (!sram_res) {
3146 dev_err(&pdev->dev,
3147 "sram resource missing from device tree\n");
3148 return -EINVAL;
3149 }
3150 sram_regs = devm_ioremap(&pdev->dev,
3151 sram_res->start,
3152 resource_size(sram_res));
3153 if (!sram_regs) {
3154 dev_err(&pdev->dev, "failed to map sram\n");
3155 return -ENOMEM;
3156 }
3157 dev->sram = devm_regmap_init_mmio(&pdev->dev, sram_regs,
3158 &allegro_sram_config);
3159 if (IS_ERR(dev->sram)) {
3160 dev_err(&pdev->dev, "failed to init sram\n");
3161 return PTR_ERR(dev->sram);
3162 }
3163
3164 irq = platform_get_irq(pdev, 0);
3165 if (irq < 0)
3166 return irq;
3167 ret = devm_request_threaded_irq(&pdev->dev, irq,
3168 allegro_hardirq,
3169 allegro_irq_thread,
3170 IRQF_SHARED, dev_name(&pdev->dev), dev);
3171 if (ret < 0) {
3172 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
3173 return ret;
3174 }
3175
3176 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
3177 if (ret)
3178 return ret;
3179
3180 platform_set_drvdata(pdev, dev);
3181
3182 ret = allegro_firmware_request_nowait(dev);
3183 if (ret < 0) {
3184 v4l2_err(&dev->v4l2_dev,
3185 "failed to request firmware: %d\n", ret);
3186 return ret;
3187 }
3188
3189 return 0;
3190 }
3191
allegro_remove(struct platform_device * pdev)3192 static int allegro_remove(struct platform_device *pdev)
3193 {
3194 struct allegro_dev *dev = platform_get_drvdata(pdev);
3195
3196 video_unregister_device(&dev->video_dev);
3197 if (dev->m2m_dev)
3198 v4l2_m2m_release(dev->m2m_dev);
3199 allegro_mcu_hw_deinit(dev);
3200 allegro_free_fw_codec(dev);
3201
3202 v4l2_device_unregister(&dev->v4l2_dev);
3203
3204 return 0;
3205 }
3206
3207 static const struct of_device_id allegro_dt_ids[] = {
3208 { .compatible = "allegro,al5e-1.1" },
3209 { /* sentinel */ }
3210 };
3211
3212 MODULE_DEVICE_TABLE(of, allegro_dt_ids);
3213
3214 static struct platform_driver allegro_driver = {
3215 .probe = allegro_probe,
3216 .remove = allegro_remove,
3217 .driver = {
3218 .name = "allegro",
3219 .of_match_table = of_match_ptr(allegro_dt_ids),
3220 },
3221 };
3222
3223 module_platform_driver(allegro_driver);
3224
3225 MODULE_LICENSE("GPL");
3226 MODULE_AUTHOR("Michael Tretter <kernel@pengutronix.de>");
3227 MODULE_DESCRIPTION("Allegro DVT encoder driver");
3228