1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for CPM (SCC/SMC) serial ports; core driver
4 *
5 * Based on arch/ppc/cpm2_io/uart.c by Dan Malek
6 * Based on ppc8xx.c by Thomas Gleixner
7 * Based on drivers/serial/amba.c by Russell King
8 *
9 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
10 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
11 *
12 * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc.
13 * (C) 2004 Intracom, S.A.
14 * (C) 2005-2006 MontaVista Software, Inc.
15 * Vitaly Bordug <vbordug@ru.mvista.com>
16 */
17
18 #include <linux/module.h>
19 #include <linux/tty.h>
20 #include <linux/tty_flip.h>
21 #include <linux/ioport.h>
22 #include <linux/init.h>
23 #include <linux/serial.h>
24 #include <linux/console.h>
25 #include <linux/sysrq.h>
26 #include <linux/device.h>
27 #include <linux/memblock.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/fs_uart_pd.h>
30 #include <linux/of_address.h>
31 #include <linux/of_irq.h>
32 #include <linux/of_platform.h>
33 #include <linux/gpio.h>
34 #include <linux/of_gpio.h>
35 #include <linux/clk.h>
36
37 #include <asm/io.h>
38 #include <asm/irq.h>
39 #include <asm/delay.h>
40 #include <asm/fs_pd.h>
41 #include <asm/udbg.h>
42
43 #if defined(CONFIG_SERIAL_CPM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
44 #define SUPPORT_SYSRQ
45 #endif
46
47 #include <linux/serial_core.h>
48 #include <linux/kernel.h>
49
50 #include "cpm_uart.h"
51
52
53 /**************************************************************/
54
55 static int cpm_uart_tx_pump(struct uart_port *port);
56 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo);
57 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo);
58 static void cpm_uart_initbd(struct uart_cpm_port *pinfo);
59
60 /**************************************************************/
61
62 #define HW_BUF_SPD_THRESHOLD 2400
63
64 /*
65 * Check, if transmit buffers are processed
66 */
cpm_uart_tx_empty(struct uart_port * port)67 static unsigned int cpm_uart_tx_empty(struct uart_port *port)
68 {
69 struct uart_cpm_port *pinfo =
70 container_of(port, struct uart_cpm_port, port);
71 cbd_t __iomem *bdp = pinfo->tx_bd_base;
72 int ret = 0;
73
74 while (1) {
75 if (in_be16(&bdp->cbd_sc) & BD_SC_READY)
76 break;
77
78 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) {
79 ret = TIOCSER_TEMT;
80 break;
81 }
82 bdp++;
83 }
84
85 pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret);
86
87 return ret;
88 }
89
cpm_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)90 static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
91 {
92 struct uart_cpm_port *pinfo =
93 container_of(port, struct uart_cpm_port, port);
94
95 if (pinfo->gpios[GPIO_RTS] >= 0)
96 gpio_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS));
97
98 if (pinfo->gpios[GPIO_DTR] >= 0)
99 gpio_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR));
100 }
101
cpm_uart_get_mctrl(struct uart_port * port)102 static unsigned int cpm_uart_get_mctrl(struct uart_port *port)
103 {
104 struct uart_cpm_port *pinfo =
105 container_of(port, struct uart_cpm_port, port);
106 unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
107
108 if (pinfo->gpios[GPIO_CTS] >= 0) {
109 if (gpio_get_value(pinfo->gpios[GPIO_CTS]))
110 mctrl &= ~TIOCM_CTS;
111 }
112
113 if (pinfo->gpios[GPIO_DSR] >= 0) {
114 if (gpio_get_value(pinfo->gpios[GPIO_DSR]))
115 mctrl &= ~TIOCM_DSR;
116 }
117
118 if (pinfo->gpios[GPIO_DCD] >= 0) {
119 if (gpio_get_value(pinfo->gpios[GPIO_DCD]))
120 mctrl &= ~TIOCM_CAR;
121 }
122
123 if (pinfo->gpios[GPIO_RI] >= 0) {
124 if (!gpio_get_value(pinfo->gpios[GPIO_RI]))
125 mctrl |= TIOCM_RNG;
126 }
127
128 return mctrl;
129 }
130
131 /*
132 * Stop transmitter
133 */
cpm_uart_stop_tx(struct uart_port * port)134 static void cpm_uart_stop_tx(struct uart_port *port)
135 {
136 struct uart_cpm_port *pinfo =
137 container_of(port, struct uart_cpm_port, port);
138 smc_t __iomem *smcp = pinfo->smcp;
139 scc_t __iomem *sccp = pinfo->sccp;
140
141 pr_debug("CPM uart[%d]:stop tx\n", port->line);
142
143 if (IS_SMC(pinfo))
144 clrbits8(&smcp->smc_smcm, SMCM_TX);
145 else
146 clrbits16(&sccp->scc_sccm, UART_SCCM_TX);
147 }
148
149 /*
150 * Start transmitter
151 */
cpm_uart_start_tx(struct uart_port * port)152 static void cpm_uart_start_tx(struct uart_port *port)
153 {
154 struct uart_cpm_port *pinfo =
155 container_of(port, struct uart_cpm_port, port);
156 smc_t __iomem *smcp = pinfo->smcp;
157 scc_t __iomem *sccp = pinfo->sccp;
158
159 pr_debug("CPM uart[%d]:start tx\n", port->line);
160
161 if (IS_SMC(pinfo)) {
162 if (in_8(&smcp->smc_smcm) & SMCM_TX)
163 return;
164 } else {
165 if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX)
166 return;
167 }
168
169 if (cpm_uart_tx_pump(port) != 0) {
170 if (IS_SMC(pinfo)) {
171 setbits8(&smcp->smc_smcm, SMCM_TX);
172 } else {
173 setbits16(&sccp->scc_sccm, UART_SCCM_TX);
174 }
175 }
176 }
177
178 /*
179 * Stop receiver
180 */
cpm_uart_stop_rx(struct uart_port * port)181 static void cpm_uart_stop_rx(struct uart_port *port)
182 {
183 struct uart_cpm_port *pinfo =
184 container_of(port, struct uart_cpm_port, port);
185 smc_t __iomem *smcp = pinfo->smcp;
186 scc_t __iomem *sccp = pinfo->sccp;
187
188 pr_debug("CPM uart[%d]:stop rx\n", port->line);
189
190 if (IS_SMC(pinfo))
191 clrbits8(&smcp->smc_smcm, SMCM_RX);
192 else
193 clrbits16(&sccp->scc_sccm, UART_SCCM_RX);
194 }
195
196 /*
197 * Generate a break.
198 */
cpm_uart_break_ctl(struct uart_port * port,int break_state)199 static void cpm_uart_break_ctl(struct uart_port *port, int break_state)
200 {
201 struct uart_cpm_port *pinfo =
202 container_of(port, struct uart_cpm_port, port);
203
204 pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line,
205 break_state);
206
207 if (break_state)
208 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
209 else
210 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
211 }
212
213 /*
214 * Transmit characters, refill buffer descriptor, if possible
215 */
cpm_uart_int_tx(struct uart_port * port)216 static void cpm_uart_int_tx(struct uart_port *port)
217 {
218 pr_debug("CPM uart[%d]:TX INT\n", port->line);
219
220 cpm_uart_tx_pump(port);
221 }
222
223 #ifdef CONFIG_CONSOLE_POLL
224 static int serial_polled;
225 #endif
226
227 /*
228 * Receive characters
229 */
cpm_uart_int_rx(struct uart_port * port)230 static void cpm_uart_int_rx(struct uart_port *port)
231 {
232 int i;
233 unsigned char ch;
234 u8 *cp;
235 struct tty_port *tport = &port->state->port;
236 struct uart_cpm_port *pinfo =
237 container_of(port, struct uart_cpm_port, port);
238 cbd_t __iomem *bdp;
239 u16 status;
240 unsigned int flg;
241
242 pr_debug("CPM uart[%d]:RX INT\n", port->line);
243
244 /* Just loop through the closed BDs and copy the characters into
245 * the buffer.
246 */
247 bdp = pinfo->rx_cur;
248 for (;;) {
249 #ifdef CONFIG_CONSOLE_POLL
250 if (unlikely(serial_polled)) {
251 serial_polled = 0;
252 return;
253 }
254 #endif
255 /* get status */
256 status = in_be16(&bdp->cbd_sc);
257 /* If this one is empty, return happy */
258 if (status & BD_SC_EMPTY)
259 break;
260
261 /* get number of characters, and check spce in flip-buffer */
262 i = in_be16(&bdp->cbd_datlen);
263
264 /* If we have not enough room in tty flip buffer, then we try
265 * later, which will be the next rx-interrupt or a timeout
266 */
267 if (tty_buffer_request_room(tport, i) < i) {
268 printk(KERN_WARNING "No room in flip buffer\n");
269 return;
270 }
271
272 /* get pointer */
273 cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
274
275 /* loop through the buffer */
276 while (i-- > 0) {
277 ch = *cp++;
278 port->icount.rx++;
279 flg = TTY_NORMAL;
280
281 if (status &
282 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
283 goto handle_error;
284 if (uart_handle_sysrq_char(port, ch))
285 continue;
286 #ifdef CONFIG_CONSOLE_POLL
287 if (unlikely(serial_polled)) {
288 serial_polled = 0;
289 return;
290 }
291 #endif
292 error_return:
293 tty_insert_flip_char(tport, ch, flg);
294
295 } /* End while (i--) */
296
297 /* This BD is ready to be used again. Clear status. get next */
298 clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR |
299 BD_SC_OV | BD_SC_ID);
300 setbits16(&bdp->cbd_sc, BD_SC_EMPTY);
301
302 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
303 bdp = pinfo->rx_bd_base;
304 else
305 bdp++;
306
307 } /* End for (;;) */
308
309 /* Write back buffer pointer */
310 pinfo->rx_cur = bdp;
311
312 /* activate BH processing */
313 tty_flip_buffer_push(tport);
314
315 return;
316
317 /* Error processing */
318
319 handle_error:
320 /* Statistics */
321 if (status & BD_SC_BR)
322 port->icount.brk++;
323 if (status & BD_SC_PR)
324 port->icount.parity++;
325 if (status & BD_SC_FR)
326 port->icount.frame++;
327 if (status & BD_SC_OV)
328 port->icount.overrun++;
329
330 /* Mask out ignored conditions */
331 status &= port->read_status_mask;
332
333 /* Handle the remaining ones */
334 if (status & BD_SC_BR)
335 flg = TTY_BREAK;
336 else if (status & BD_SC_PR)
337 flg = TTY_PARITY;
338 else if (status & BD_SC_FR)
339 flg = TTY_FRAME;
340
341 /* overrun does not affect the current character ! */
342 if (status & BD_SC_OV) {
343 ch = 0;
344 flg = TTY_OVERRUN;
345 /* We skip this buffer */
346 /* CHECK: Is really nothing senseful there */
347 /* ASSUMPTION: it contains nothing valid */
348 i = 0;
349 }
350 #ifdef SUPPORT_SYSRQ
351 port->sysrq = 0;
352 #endif
353 goto error_return;
354 }
355
356 /*
357 * Asynchron mode interrupt handler
358 */
cpm_uart_int(int irq,void * data)359 static irqreturn_t cpm_uart_int(int irq, void *data)
360 {
361 u8 events;
362 struct uart_port *port = data;
363 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
364 smc_t __iomem *smcp = pinfo->smcp;
365 scc_t __iomem *sccp = pinfo->sccp;
366
367 pr_debug("CPM uart[%d]:IRQ\n", port->line);
368
369 if (IS_SMC(pinfo)) {
370 events = in_8(&smcp->smc_smce);
371 out_8(&smcp->smc_smce, events);
372 if (events & SMCM_BRKE)
373 uart_handle_break(port);
374 if (events & SMCM_RX)
375 cpm_uart_int_rx(port);
376 if (events & SMCM_TX)
377 cpm_uart_int_tx(port);
378 } else {
379 events = in_be16(&sccp->scc_scce);
380 out_be16(&sccp->scc_scce, events);
381 if (events & UART_SCCM_BRKE)
382 uart_handle_break(port);
383 if (events & UART_SCCM_RX)
384 cpm_uart_int_rx(port);
385 if (events & UART_SCCM_TX)
386 cpm_uart_int_tx(port);
387 }
388 return (events) ? IRQ_HANDLED : IRQ_NONE;
389 }
390
cpm_uart_startup(struct uart_port * port)391 static int cpm_uart_startup(struct uart_port *port)
392 {
393 int retval;
394 struct uart_cpm_port *pinfo =
395 container_of(port, struct uart_cpm_port, port);
396
397 pr_debug("CPM uart[%d]:startup\n", port->line);
398
399 /* If the port is not the console, make sure rx is disabled. */
400 if (!(pinfo->flags & FLAG_CONSOLE)) {
401 /* Disable UART rx */
402 if (IS_SMC(pinfo)) {
403 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN);
404 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
405 } else {
406 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR);
407 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
408 }
409 cpm_uart_initbd(pinfo);
410 if (IS_SMC(pinfo)) {
411 out_be32(&pinfo->smcup->smc_rstate, 0);
412 out_be32(&pinfo->smcup->smc_tstate, 0);
413 out_be16(&pinfo->smcup->smc_rbptr,
414 in_be16(&pinfo->smcup->smc_rbase));
415 out_be16(&pinfo->smcup->smc_tbptr,
416 in_be16(&pinfo->smcup->smc_tbase));
417 } else {
418 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
419 }
420 }
421 /* Install interrupt handler. */
422 retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port);
423 if (retval)
424 return retval;
425
426 /* Startup rx-int */
427 if (IS_SMC(pinfo)) {
428 setbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
429 setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN));
430 } else {
431 setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
432 setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT));
433 }
434
435 return 0;
436 }
437
cpm_uart_wait_until_send(struct uart_cpm_port * pinfo)438 inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo)
439 {
440 set_current_state(TASK_UNINTERRUPTIBLE);
441 schedule_timeout(pinfo->wait_closing);
442 }
443
444 /*
445 * Shutdown the uart
446 */
cpm_uart_shutdown(struct uart_port * port)447 static void cpm_uart_shutdown(struct uart_port *port)
448 {
449 struct uart_cpm_port *pinfo =
450 container_of(port, struct uart_cpm_port, port);
451
452 pr_debug("CPM uart[%d]:shutdown\n", port->line);
453
454 /* free interrupt handler */
455 free_irq(port->irq, port);
456
457 /* If the port is not the console, disable Rx and Tx. */
458 if (!(pinfo->flags & FLAG_CONSOLE)) {
459 /* Wait for all the BDs marked sent */
460 while(!cpm_uart_tx_empty(port)) {
461 set_current_state(TASK_UNINTERRUPTIBLE);
462 schedule_timeout(2);
463 }
464
465 if (pinfo->wait_closing)
466 cpm_uart_wait_until_send(pinfo);
467
468 /* Stop uarts */
469 if (IS_SMC(pinfo)) {
470 smc_t __iomem *smcp = pinfo->smcp;
471 clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
472 clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX);
473 } else {
474 scc_t __iomem *sccp = pinfo->sccp;
475 clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
476 clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
477 }
478
479 /* Shut them really down and reinit buffer descriptors */
480 if (IS_SMC(pinfo)) {
481 out_be16(&pinfo->smcup->smc_brkcr, 0);
482 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
483 } else {
484 out_be16(&pinfo->sccup->scc_brkcr, 0);
485 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
486 }
487
488 cpm_uart_initbd(pinfo);
489 }
490 }
491
cpm_uart_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)492 static void cpm_uart_set_termios(struct uart_port *port,
493 struct ktermios *termios,
494 struct ktermios *old)
495 {
496 int baud;
497 unsigned long flags;
498 u16 cval, scval, prev_mode;
499 int bits, sbits;
500 struct uart_cpm_port *pinfo =
501 container_of(port, struct uart_cpm_port, port);
502 smc_t __iomem *smcp = pinfo->smcp;
503 scc_t __iomem *sccp = pinfo->sccp;
504 int maxidl;
505
506 pr_debug("CPM uart[%d]:set_termios\n", port->line);
507
508 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
509 if (baud < HW_BUF_SPD_THRESHOLD ||
510 (pinfo->port.state && pinfo->port.state->port.low_latency))
511 pinfo->rx_fifosize = 1;
512 else
513 pinfo->rx_fifosize = RX_BUF_SIZE;
514
515 /* MAXIDL is the timeout after which a receive buffer is closed
516 * when not full if no more characters are received.
517 * We calculate it from the baudrate so that the duration is
518 * always the same at standard rates: about 4ms.
519 */
520 maxidl = baud / 2400;
521 if (maxidl < 1)
522 maxidl = 1;
523 if (maxidl > 0x10)
524 maxidl = 0x10;
525
526 /* Character length programmed into the mode register is the
527 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
528 * 1 or 2 stop bits, minus 1.
529 * The value 'bits' counts this for us.
530 */
531 cval = 0;
532 scval = 0;
533
534 /* byte size */
535 switch (termios->c_cflag & CSIZE) {
536 case CS5:
537 bits = 5;
538 break;
539 case CS6:
540 bits = 6;
541 break;
542 case CS7:
543 bits = 7;
544 break;
545 case CS8:
546 bits = 8;
547 break;
548 /* Never happens, but GCC is too dumb to figure it out */
549 default:
550 bits = 8;
551 break;
552 }
553 sbits = bits - 5;
554
555 if (termios->c_cflag & CSTOPB) {
556 cval |= SMCMR_SL; /* Two stops */
557 scval |= SCU_PSMR_SL;
558 bits++;
559 }
560
561 if (termios->c_cflag & PARENB) {
562 cval |= SMCMR_PEN;
563 scval |= SCU_PSMR_PEN;
564 bits++;
565 if (!(termios->c_cflag & PARODD)) {
566 cval |= SMCMR_PM_EVEN;
567 scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP);
568 }
569 }
570
571 /*
572 * Update the timeout
573 */
574 uart_update_timeout(port, termios->c_cflag, baud);
575
576 /*
577 * Set up parity check flag
578 */
579 port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV);
580 if (termios->c_iflag & INPCK)
581 port->read_status_mask |= BD_SC_FR | BD_SC_PR;
582 if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK))
583 port->read_status_mask |= BD_SC_BR;
584
585 /*
586 * Characters to ignore
587 */
588 port->ignore_status_mask = 0;
589 if (termios->c_iflag & IGNPAR)
590 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
591 if (termios->c_iflag & IGNBRK) {
592 port->ignore_status_mask |= BD_SC_BR;
593 /*
594 * If we're ignore parity and break indicators, ignore
595 * overruns too. (For real raw support).
596 */
597 if (termios->c_iflag & IGNPAR)
598 port->ignore_status_mask |= BD_SC_OV;
599 }
600 /*
601 * !!! ignore all characters if CREAD is not set
602 */
603 if ((termios->c_cflag & CREAD) == 0)
604 port->read_status_mask &= ~BD_SC_EMPTY;
605
606 spin_lock_irqsave(&port->lock, flags);
607
608 /* Start bit has not been added (so don't, because we would just
609 * subtract it later), and we need to add one for the number of
610 * stops bits (there is always at least one).
611 */
612 bits++;
613 if (IS_SMC(pinfo)) {
614 /*
615 * MRBLR can be changed while an SMC/SCC is operating only
616 * if it is done in a single bus cycle with one 16-bit move
617 * (not two 8-bit bus cycles back-to-back). This occurs when
618 * the cp shifts control to the next RxBD, so the change does
619 * not take effect immediately. To guarantee the exact RxBD
620 * on which the change occurs, change MRBLR only while the
621 * SMC/SCC receiver is disabled.
622 */
623 out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize);
624 out_be16(&pinfo->smcup->smc_maxidl, maxidl);
625
626 /* Set the mode register. We want to keep a copy of the
627 * enables, because we want to put them back if they were
628 * present.
629 */
630 prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN);
631 /* Output in *one* operation, so we don't interrupt RX/TX if they
632 * were already enabled. */
633 out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval |
634 SMCMR_SM_UART | prev_mode);
635 } else {
636 out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
637 out_be16(&pinfo->sccup->scc_maxidl, maxidl);
638 out_be16(&sccp->scc_psmr, (sbits << 12) | scval);
639 }
640
641 if (pinfo->clk)
642 clk_set_rate(pinfo->clk, baud);
643 else
644 cpm_set_brg(pinfo->brg - 1, baud);
645 spin_unlock_irqrestore(&port->lock, flags);
646 }
647
cpm_uart_type(struct uart_port * port)648 static const char *cpm_uart_type(struct uart_port *port)
649 {
650 pr_debug("CPM uart[%d]:uart_type\n", port->line);
651
652 return port->type == PORT_CPM ? "CPM UART" : NULL;
653 }
654
655 /*
656 * verify the new serial_struct (for TIOCSSERIAL).
657 */
cpm_uart_verify_port(struct uart_port * port,struct serial_struct * ser)658 static int cpm_uart_verify_port(struct uart_port *port,
659 struct serial_struct *ser)
660 {
661 int ret = 0;
662
663 pr_debug("CPM uart[%d]:verify_port\n", port->line);
664
665 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
666 ret = -EINVAL;
667 if (ser->irq < 0 || ser->irq >= nr_irqs)
668 ret = -EINVAL;
669 if (ser->baud_base < 9600)
670 ret = -EINVAL;
671 return ret;
672 }
673
674 /*
675 * Transmit characters, refill buffer descriptor, if possible
676 */
cpm_uart_tx_pump(struct uart_port * port)677 static int cpm_uart_tx_pump(struct uart_port *port)
678 {
679 cbd_t __iomem *bdp;
680 u8 *p;
681 int count;
682 struct uart_cpm_port *pinfo =
683 container_of(port, struct uart_cpm_port, port);
684 struct circ_buf *xmit = &port->state->xmit;
685
686 /* Handle xon/xoff */
687 if (port->x_char) {
688 /* Pick next descriptor and fill from buffer */
689 bdp = pinfo->tx_cur;
690
691 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
692
693 *p++ = port->x_char;
694
695 out_be16(&bdp->cbd_datlen, 1);
696 setbits16(&bdp->cbd_sc, BD_SC_READY);
697 /* Get next BD. */
698 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
699 bdp = pinfo->tx_bd_base;
700 else
701 bdp++;
702 pinfo->tx_cur = bdp;
703
704 port->icount.tx++;
705 port->x_char = 0;
706 return 1;
707 }
708
709 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
710 cpm_uart_stop_tx(port);
711 return 0;
712 }
713
714 /* Pick next descriptor and fill from buffer */
715 bdp = pinfo->tx_cur;
716
717 while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) &&
718 xmit->tail != xmit->head) {
719 count = 0;
720 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
721 while (count < pinfo->tx_fifosize) {
722 *p++ = xmit->buf[xmit->tail];
723 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
724 port->icount.tx++;
725 count++;
726 if (xmit->head == xmit->tail)
727 break;
728 }
729 out_be16(&bdp->cbd_datlen, count);
730 setbits16(&bdp->cbd_sc, BD_SC_READY);
731 /* Get next BD. */
732 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
733 bdp = pinfo->tx_bd_base;
734 else
735 bdp++;
736 }
737 pinfo->tx_cur = bdp;
738
739 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
740 uart_write_wakeup(port);
741
742 if (uart_circ_empty(xmit)) {
743 cpm_uart_stop_tx(port);
744 return 0;
745 }
746
747 return 1;
748 }
749
750 /*
751 * init buffer descriptors
752 */
cpm_uart_initbd(struct uart_cpm_port * pinfo)753 static void cpm_uart_initbd(struct uart_cpm_port *pinfo)
754 {
755 int i;
756 u8 *mem_addr;
757 cbd_t __iomem *bdp;
758
759 pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line);
760
761 /* Set the physical address of the host memory
762 * buffers in the buffer descriptors, and the
763 * virtual address for us to work with.
764 */
765 mem_addr = pinfo->mem_addr;
766 bdp = pinfo->rx_cur = pinfo->rx_bd_base;
767 for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) {
768 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
769 out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
770 mem_addr += pinfo->rx_fifosize;
771 }
772
773 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
774 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
775
776 /* Set the physical address of the host memory
777 * buffers in the buffer descriptors, and the
778 * virtual address for us to work with.
779 */
780 mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize);
781 bdp = pinfo->tx_cur = pinfo->tx_bd_base;
782 for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) {
783 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
784 out_be16(&bdp->cbd_sc, BD_SC_INTRPT);
785 mem_addr += pinfo->tx_fifosize;
786 }
787
788 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
789 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT);
790 }
791
cpm_uart_init_scc(struct uart_cpm_port * pinfo)792 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo)
793 {
794 scc_t __iomem *scp;
795 scc_uart_t __iomem *sup;
796
797 pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line);
798
799 scp = pinfo->sccp;
800 sup = pinfo->sccup;
801
802 /* Store address */
803 out_be16(&pinfo->sccup->scc_genscc.scc_rbase,
804 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
805 out_be16(&pinfo->sccup->scc_genscc.scc_tbase,
806 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
807
808 /* Set up the uart parameters in the
809 * parameter ram.
810 */
811
812 cpm_set_scc_fcr(sup);
813
814 out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
815 out_be16(&sup->scc_maxidl, 0x10);
816 out_be16(&sup->scc_brkcr, 1);
817 out_be16(&sup->scc_parec, 0);
818 out_be16(&sup->scc_frmec, 0);
819 out_be16(&sup->scc_nosec, 0);
820 out_be16(&sup->scc_brkec, 0);
821 out_be16(&sup->scc_uaddr1, 0);
822 out_be16(&sup->scc_uaddr2, 0);
823 out_be16(&sup->scc_toseq, 0);
824 out_be16(&sup->scc_char1, 0x8000);
825 out_be16(&sup->scc_char2, 0x8000);
826 out_be16(&sup->scc_char3, 0x8000);
827 out_be16(&sup->scc_char4, 0x8000);
828 out_be16(&sup->scc_char5, 0x8000);
829 out_be16(&sup->scc_char6, 0x8000);
830 out_be16(&sup->scc_char7, 0x8000);
831 out_be16(&sup->scc_char8, 0x8000);
832 out_be16(&sup->scc_rccm, 0xc0ff);
833
834 /* Send the CPM an initialize command.
835 */
836 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
837
838 /* Set UART mode, 8 bit, no parity, one stop.
839 * Enable receive and transmit.
840 */
841 out_be32(&scp->scc_gsmrh, 0);
842 out_be32(&scp->scc_gsmrl,
843 SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
844
845 /* Enable rx interrupts and clear all pending events. */
846 out_be16(&scp->scc_sccm, 0);
847 out_be16(&scp->scc_scce, 0xffff);
848 out_be16(&scp->scc_dsr, 0x7e7e);
849 out_be16(&scp->scc_psmr, 0x3000);
850
851 setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
852 }
853
cpm_uart_init_smc(struct uart_cpm_port * pinfo)854 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo)
855 {
856 smc_t __iomem *sp;
857 smc_uart_t __iomem *up;
858
859 pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line);
860
861 sp = pinfo->smcp;
862 up = pinfo->smcup;
863
864 /* Store address */
865 out_be16(&pinfo->smcup->smc_rbase,
866 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
867 out_be16(&pinfo->smcup->smc_tbase,
868 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
869
870 /*
871 * In case SMC is being relocated...
872 */
873 out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase));
874 out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase));
875 out_be32(&up->smc_rstate, 0);
876 out_be32(&up->smc_tstate, 0);
877 out_be16(&up->smc_brkcr, 1); /* number of break chars */
878 out_be16(&up->smc_brkec, 0);
879
880 /* Set up the uart parameters in the
881 * parameter ram.
882 */
883 cpm_set_smc_fcr(up);
884
885 /* Using idle character time requires some additional tuning. */
886 out_be16(&up->smc_mrblr, pinfo->rx_fifosize);
887 out_be16(&up->smc_maxidl, 0x10);
888 out_be16(&up->smc_brklen, 0);
889 out_be16(&up->smc_brkec, 0);
890 out_be16(&up->smc_brkcr, 1);
891
892 /* Set UART mode, 8 bit, no parity, one stop.
893 * Enable receive and transmit.
894 */
895 out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);
896
897 /* Enable only rx interrupts clear all pending events. */
898 out_8(&sp->smc_smcm, 0);
899 out_8(&sp->smc_smce, 0xff);
900
901 setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
902 }
903
904 /*
905 * Initialize port. This is called from early_console stuff
906 * so we have to be careful here !
907 */
cpm_uart_request_port(struct uart_port * port)908 static int cpm_uart_request_port(struct uart_port *port)
909 {
910 struct uart_cpm_port *pinfo =
911 container_of(port, struct uart_cpm_port, port);
912 int ret;
913
914 pr_debug("CPM uart[%d]:request port\n", port->line);
915
916 if (pinfo->flags & FLAG_CONSOLE)
917 return 0;
918
919 if (IS_SMC(pinfo)) {
920 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
921 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
922 } else {
923 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
924 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
925 }
926
927 ret = cpm_uart_allocbuf(pinfo, 0);
928
929 if (ret)
930 return ret;
931
932 cpm_uart_initbd(pinfo);
933 if (IS_SMC(pinfo))
934 cpm_uart_init_smc(pinfo);
935 else
936 cpm_uart_init_scc(pinfo);
937
938 return 0;
939 }
940
cpm_uart_release_port(struct uart_port * port)941 static void cpm_uart_release_port(struct uart_port *port)
942 {
943 struct uart_cpm_port *pinfo =
944 container_of(port, struct uart_cpm_port, port);
945
946 if (!(pinfo->flags & FLAG_CONSOLE))
947 cpm_uart_freebuf(pinfo);
948 }
949
950 /*
951 * Configure/autoconfigure the port.
952 */
cpm_uart_config_port(struct uart_port * port,int flags)953 static void cpm_uart_config_port(struct uart_port *port, int flags)
954 {
955 pr_debug("CPM uart[%d]:config_port\n", port->line);
956
957 if (flags & UART_CONFIG_TYPE) {
958 port->type = PORT_CPM;
959 cpm_uart_request_port(port);
960 }
961 }
962
963 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE)
964 /*
965 * Write a string to the serial port
966 * Note that this is called with interrupts already disabled
967 */
cpm_uart_early_write(struct uart_cpm_port * pinfo,const char * string,u_int count,bool handle_linefeed)968 static void cpm_uart_early_write(struct uart_cpm_port *pinfo,
969 const char *string, u_int count, bool handle_linefeed)
970 {
971 unsigned int i;
972 cbd_t __iomem *bdp, *bdbase;
973 unsigned char *cpm_outp_addr;
974
975 /* Get the address of the host memory buffer.
976 */
977 bdp = pinfo->tx_cur;
978 bdbase = pinfo->tx_bd_base;
979
980 /*
981 * Now, do each character. This is not as bad as it looks
982 * since this is a holding FIFO and not a transmitting FIFO.
983 * We could add the complexity of filling the entire transmit
984 * buffer, but we would just wait longer between accesses......
985 */
986 for (i = 0; i < count; i++, string++) {
987 /* Wait for transmitter fifo to empty.
988 * Ready indicates output is ready, and xmt is doing
989 * that, not that it is ready for us to send.
990 */
991 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
992 ;
993
994 /* Send the character out.
995 * If the buffer address is in the CPM DPRAM, don't
996 * convert it.
997 */
998 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
999 pinfo);
1000 *cpm_outp_addr = *string;
1001
1002 out_be16(&bdp->cbd_datlen, 1);
1003 setbits16(&bdp->cbd_sc, BD_SC_READY);
1004
1005 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
1006 bdp = bdbase;
1007 else
1008 bdp++;
1009
1010 /* if a LF, also do CR... */
1011 if (handle_linefeed && *string == 10) {
1012 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
1013 ;
1014
1015 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
1016 pinfo);
1017 *cpm_outp_addr = 13;
1018
1019 out_be16(&bdp->cbd_datlen, 1);
1020 setbits16(&bdp->cbd_sc, BD_SC_READY);
1021
1022 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
1023 bdp = bdbase;
1024 else
1025 bdp++;
1026 }
1027 }
1028
1029 /*
1030 * Finally, Wait for transmitter & holding register to empty
1031 * and restore the IER
1032 */
1033 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
1034 ;
1035
1036 pinfo->tx_cur = bdp;
1037 }
1038 #endif
1039
1040 #ifdef CONFIG_CONSOLE_POLL
1041 /* Serial polling routines for writing and reading from the uart while
1042 * in an interrupt or debug context.
1043 */
1044
1045 #define GDB_BUF_SIZE 512 /* power of 2, please */
1046
1047 static char poll_buf[GDB_BUF_SIZE];
1048 static char *pollp;
1049 static int poll_chars;
1050
poll_wait_key(char * obuf,struct uart_cpm_port * pinfo)1051 static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo)
1052 {
1053 u_char c, *cp;
1054 volatile cbd_t *bdp;
1055 int i;
1056
1057 /* Get the address of the host memory buffer.
1058 */
1059 bdp = pinfo->rx_cur;
1060 if (bdp->cbd_sc & BD_SC_EMPTY)
1061 return NO_POLL_CHAR;
1062
1063 /* If the buffer address is in the CPM DPRAM, don't
1064 * convert it.
1065 */
1066 cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo);
1067
1068 if (obuf) {
1069 i = c = bdp->cbd_datlen;
1070 while (i-- > 0)
1071 *obuf++ = *cp++;
1072 } else
1073 c = *cp;
1074 bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID);
1075 bdp->cbd_sc |= BD_SC_EMPTY;
1076
1077 if (bdp->cbd_sc & BD_SC_WRAP)
1078 bdp = pinfo->rx_bd_base;
1079 else
1080 bdp++;
1081 pinfo->rx_cur = (cbd_t *)bdp;
1082
1083 return (int)c;
1084 }
1085
cpm_get_poll_char(struct uart_port * port)1086 static int cpm_get_poll_char(struct uart_port *port)
1087 {
1088 struct uart_cpm_port *pinfo =
1089 container_of(port, struct uart_cpm_port, port);
1090
1091 if (!serial_polled) {
1092 serial_polled = 1;
1093 poll_chars = 0;
1094 }
1095 if (poll_chars <= 0) {
1096 int ret = poll_wait_key(poll_buf, pinfo);
1097
1098 if (ret == NO_POLL_CHAR)
1099 return ret;
1100 poll_chars = ret;
1101 pollp = poll_buf;
1102 }
1103 poll_chars--;
1104 return *pollp++;
1105 }
1106
cpm_put_poll_char(struct uart_port * port,unsigned char c)1107 static void cpm_put_poll_char(struct uart_port *port,
1108 unsigned char c)
1109 {
1110 struct uart_cpm_port *pinfo =
1111 container_of(port, struct uart_cpm_port, port);
1112 static char ch[2];
1113
1114 ch[0] = (char)c;
1115 cpm_uart_early_write(pinfo, ch, 1, false);
1116 }
1117 #endif /* CONFIG_CONSOLE_POLL */
1118
1119 static const struct uart_ops cpm_uart_pops = {
1120 .tx_empty = cpm_uart_tx_empty,
1121 .set_mctrl = cpm_uart_set_mctrl,
1122 .get_mctrl = cpm_uart_get_mctrl,
1123 .stop_tx = cpm_uart_stop_tx,
1124 .start_tx = cpm_uart_start_tx,
1125 .stop_rx = cpm_uart_stop_rx,
1126 .break_ctl = cpm_uart_break_ctl,
1127 .startup = cpm_uart_startup,
1128 .shutdown = cpm_uart_shutdown,
1129 .set_termios = cpm_uart_set_termios,
1130 .type = cpm_uart_type,
1131 .release_port = cpm_uart_release_port,
1132 .request_port = cpm_uart_request_port,
1133 .config_port = cpm_uart_config_port,
1134 .verify_port = cpm_uart_verify_port,
1135 #ifdef CONFIG_CONSOLE_POLL
1136 .poll_get_char = cpm_get_poll_char,
1137 .poll_put_char = cpm_put_poll_char,
1138 #endif
1139 };
1140
1141 struct uart_cpm_port cpm_uart_ports[UART_NR];
1142
cpm_uart_init_port(struct device_node * np,struct uart_cpm_port * pinfo)1143 static int cpm_uart_init_port(struct device_node *np,
1144 struct uart_cpm_port *pinfo)
1145 {
1146 const u32 *data;
1147 void __iomem *mem, *pram;
1148 int len;
1149 int ret;
1150 int i;
1151
1152 data = of_get_property(np, "clock", NULL);
1153 if (data) {
1154 struct clk *clk = clk_get(NULL, (const char*)data);
1155 if (!IS_ERR(clk))
1156 pinfo->clk = clk;
1157 }
1158 if (!pinfo->clk) {
1159 data = of_get_property(np, "fsl,cpm-brg", &len);
1160 if (!data || len != 4) {
1161 printk(KERN_ERR "CPM UART %pOFn has no/invalid "
1162 "fsl,cpm-brg property.\n", np);
1163 return -EINVAL;
1164 }
1165 pinfo->brg = *data;
1166 }
1167
1168 data = of_get_property(np, "fsl,cpm-command", &len);
1169 if (!data || len != 4) {
1170 printk(KERN_ERR "CPM UART %pOFn has no/invalid "
1171 "fsl,cpm-command property.\n", np);
1172 return -EINVAL;
1173 }
1174 pinfo->command = *data;
1175
1176 mem = of_iomap(np, 0);
1177 if (!mem)
1178 return -ENOMEM;
1179
1180 if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") ||
1181 of_device_is_compatible(np, "fsl,cpm2-scc-uart")) {
1182 pinfo->sccp = mem;
1183 pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np);
1184 } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") ||
1185 of_device_is_compatible(np, "fsl,cpm2-smc-uart")) {
1186 pinfo->flags |= FLAG_SMC;
1187 pinfo->smcp = mem;
1188 pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np);
1189 } else {
1190 ret = -ENODEV;
1191 goto out_mem;
1192 }
1193
1194 if (!pram) {
1195 ret = -ENOMEM;
1196 goto out_mem;
1197 }
1198
1199 pinfo->tx_nrfifos = TX_NUM_FIFO;
1200 pinfo->tx_fifosize = TX_BUF_SIZE;
1201 pinfo->rx_nrfifos = RX_NUM_FIFO;
1202 pinfo->rx_fifosize = RX_BUF_SIZE;
1203
1204 pinfo->port.uartclk = ppc_proc_freq;
1205 pinfo->port.mapbase = (unsigned long)mem;
1206 pinfo->port.type = PORT_CPM;
1207 pinfo->port.ops = &cpm_uart_pops,
1208 pinfo->port.iotype = UPIO_MEM;
1209 pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize;
1210 spin_lock_init(&pinfo->port.lock);
1211
1212 pinfo->port.irq = irq_of_parse_and_map(np, 0);
1213 if (pinfo->port.irq == NO_IRQ) {
1214 ret = -EINVAL;
1215 goto out_pram;
1216 }
1217
1218 for (i = 0; i < NUM_GPIOS; i++) {
1219 int gpio;
1220
1221 pinfo->gpios[i] = -1;
1222
1223 gpio = of_get_gpio(np, i);
1224
1225 if (gpio_is_valid(gpio)) {
1226 ret = gpio_request(gpio, "cpm_uart");
1227 if (ret) {
1228 pr_err("can't request gpio #%d: %d\n", i, ret);
1229 continue;
1230 }
1231 if (i == GPIO_RTS || i == GPIO_DTR)
1232 ret = gpio_direction_output(gpio, 0);
1233 else
1234 ret = gpio_direction_input(gpio);
1235 if (ret) {
1236 pr_err("can't set direction for gpio #%d: %d\n",
1237 i, ret);
1238 gpio_free(gpio);
1239 continue;
1240 }
1241 pinfo->gpios[i] = gpio;
1242 }
1243 }
1244
1245 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1246 udbg_putc = NULL;
1247 #endif
1248
1249 return cpm_uart_request_port(&pinfo->port);
1250
1251 out_pram:
1252 cpm_uart_unmap_pram(pinfo, pram);
1253 out_mem:
1254 iounmap(mem);
1255 return ret;
1256 }
1257
1258 #ifdef CONFIG_SERIAL_CPM_CONSOLE
1259 /*
1260 * Print a string to the serial port trying not to disturb
1261 * any possible real use of the port...
1262 *
1263 * Note that this is called with interrupts already disabled
1264 */
cpm_uart_console_write(struct console * co,const char * s,u_int count)1265 static void cpm_uart_console_write(struct console *co, const char *s,
1266 u_int count)
1267 {
1268 struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index];
1269 unsigned long flags;
1270 int nolock = oops_in_progress;
1271
1272 if (unlikely(nolock)) {
1273 local_irq_save(flags);
1274 } else {
1275 spin_lock_irqsave(&pinfo->port.lock, flags);
1276 }
1277
1278 cpm_uart_early_write(pinfo, s, count, true);
1279
1280 if (unlikely(nolock)) {
1281 local_irq_restore(flags);
1282 } else {
1283 spin_unlock_irqrestore(&pinfo->port.lock, flags);
1284 }
1285 }
1286
1287
cpm_uart_console_setup(struct console * co,char * options)1288 static int __init cpm_uart_console_setup(struct console *co, char *options)
1289 {
1290 int baud = 38400;
1291 int bits = 8;
1292 int parity = 'n';
1293 int flow = 'n';
1294 int ret;
1295 struct uart_cpm_port *pinfo;
1296 struct uart_port *port;
1297
1298 struct device_node *np;
1299 int i = 0;
1300
1301 if (co->index >= UART_NR) {
1302 printk(KERN_ERR "cpm_uart: console index %d too high\n",
1303 co->index);
1304 return -ENODEV;
1305 }
1306
1307 for_each_node_by_type(np, "serial") {
1308 if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") &&
1309 !of_device_is_compatible(np, "fsl,cpm1-scc-uart") &&
1310 !of_device_is_compatible(np, "fsl,cpm2-smc-uart") &&
1311 !of_device_is_compatible(np, "fsl,cpm2-scc-uart"))
1312 continue;
1313
1314 if (i++ == co->index)
1315 break;
1316 }
1317
1318 if (!np)
1319 return -ENODEV;
1320
1321 pinfo = &cpm_uart_ports[co->index];
1322
1323 pinfo->flags |= FLAG_CONSOLE;
1324 port = &pinfo->port;
1325
1326 ret = cpm_uart_init_port(np, pinfo);
1327 of_node_put(np);
1328 if (ret)
1329 return ret;
1330
1331 if (options) {
1332 uart_parse_options(options, &baud, &parity, &bits, &flow);
1333 } else {
1334 if ((baud = uart_baudrate()) == -1)
1335 baud = 9600;
1336 }
1337
1338 if (IS_SMC(pinfo)) {
1339 out_be16(&pinfo->smcup->smc_brkcr, 0);
1340 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
1341 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
1342 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
1343 } else {
1344 out_be16(&pinfo->sccup->scc_brkcr, 0);
1345 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
1346 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
1347 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
1348 }
1349
1350 ret = cpm_uart_allocbuf(pinfo, 1);
1351
1352 if (ret)
1353 return ret;
1354
1355 cpm_uart_initbd(pinfo);
1356
1357 if (IS_SMC(pinfo))
1358 cpm_uart_init_smc(pinfo);
1359 else
1360 cpm_uart_init_scc(pinfo);
1361
1362 uart_set_options(port, co, baud, parity, bits, flow);
1363 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
1364
1365 return 0;
1366 }
1367
1368 static struct uart_driver cpm_reg;
1369 static struct console cpm_scc_uart_console = {
1370 .name = "ttyCPM",
1371 .write = cpm_uart_console_write,
1372 .device = uart_console_device,
1373 .setup = cpm_uart_console_setup,
1374 .flags = CON_PRINTBUFFER,
1375 .index = -1,
1376 .data = &cpm_reg,
1377 };
1378
cpm_uart_console_init(void)1379 static int __init cpm_uart_console_init(void)
1380 {
1381 register_console(&cpm_scc_uart_console);
1382 return 0;
1383 }
1384
1385 console_initcall(cpm_uart_console_init);
1386
1387 #define CPM_UART_CONSOLE &cpm_scc_uart_console
1388 #else
1389 #define CPM_UART_CONSOLE NULL
1390 #endif
1391
1392 static struct uart_driver cpm_reg = {
1393 .owner = THIS_MODULE,
1394 .driver_name = "ttyCPM",
1395 .dev_name = "ttyCPM",
1396 .major = SERIAL_CPM_MAJOR,
1397 .minor = SERIAL_CPM_MINOR,
1398 .cons = CPM_UART_CONSOLE,
1399 .nr = UART_NR,
1400 };
1401
1402 static int probe_index;
1403
cpm_uart_probe(struct platform_device * ofdev)1404 static int cpm_uart_probe(struct platform_device *ofdev)
1405 {
1406 int index = probe_index++;
1407 struct uart_cpm_port *pinfo = &cpm_uart_ports[index];
1408 int ret;
1409
1410 pinfo->port.line = index;
1411
1412 if (index >= UART_NR)
1413 return -ENODEV;
1414
1415 platform_set_drvdata(ofdev, pinfo);
1416
1417 /* initialize the device pointer for the port */
1418 pinfo->port.dev = &ofdev->dev;
1419
1420 ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo);
1421 if (ret)
1422 return ret;
1423
1424 return uart_add_one_port(&cpm_reg, &pinfo->port);
1425 }
1426
cpm_uart_remove(struct platform_device * ofdev)1427 static int cpm_uart_remove(struct platform_device *ofdev)
1428 {
1429 struct uart_cpm_port *pinfo = platform_get_drvdata(ofdev);
1430 return uart_remove_one_port(&cpm_reg, &pinfo->port);
1431 }
1432
1433 static const struct of_device_id cpm_uart_match[] = {
1434 {
1435 .compatible = "fsl,cpm1-smc-uart",
1436 },
1437 {
1438 .compatible = "fsl,cpm1-scc-uart",
1439 },
1440 {
1441 .compatible = "fsl,cpm2-smc-uart",
1442 },
1443 {
1444 .compatible = "fsl,cpm2-scc-uart",
1445 },
1446 {}
1447 };
1448 MODULE_DEVICE_TABLE(of, cpm_uart_match);
1449
1450 static struct platform_driver cpm_uart_driver = {
1451 .driver = {
1452 .name = "cpm_uart",
1453 .of_match_table = cpm_uart_match,
1454 },
1455 .probe = cpm_uart_probe,
1456 .remove = cpm_uart_remove,
1457 };
1458
cpm_uart_init(void)1459 static int __init cpm_uart_init(void)
1460 {
1461 int ret = uart_register_driver(&cpm_reg);
1462 if (ret)
1463 return ret;
1464
1465 ret = platform_driver_register(&cpm_uart_driver);
1466 if (ret)
1467 uart_unregister_driver(&cpm_reg);
1468
1469 return ret;
1470 }
1471
cpm_uart_exit(void)1472 static void __exit cpm_uart_exit(void)
1473 {
1474 platform_driver_unregister(&cpm_uart_driver);
1475 uart_unregister_driver(&cpm_reg);
1476 }
1477
1478 module_init(cpm_uart_init);
1479 module_exit(cpm_uart_exit);
1480
1481 MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis");
1482 MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $");
1483 MODULE_LICENSE("GPL");
1484 MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR);
1485
