1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
5 */
6
7 #include <linux/auxiliary_bus.h>
8 #include <linux/bits.h>
9 #include <linux/clk.h>
10 #include <linux/debugfs.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/i2c.h>
14 #include <linux/iopoll.h>
15 #include <linux/module.h>
16 #include <linux/of_graph.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regmap.h>
19 #include <linux/regulator/consumer.h>
20
21 #include <asm/unaligned.h>
22
23 #include <drm/drm_atomic.h>
24 #include <drm/drm_atomic_helper.h>
25 #include <drm/drm_bridge.h>
26 #include <drm/drm_dp_aux_bus.h>
27 #include <drm/drm_dp_helper.h>
28 #include <drm/drm_mipi_dsi.h>
29 #include <drm/drm_of.h>
30 #include <drm/drm_panel.h>
31 #include <drm/drm_print.h>
32 #include <drm/drm_probe_helper.h>
33
34 #define SN_DEVICE_REV_REG 0x08
35 #define SN_DPPLL_SRC_REG 0x0A
36 #define DPPLL_CLK_SRC_DSICLK BIT(0)
37 #define REFCLK_FREQ_MASK GENMASK(3, 1)
38 #define REFCLK_FREQ(x) ((x) << 1)
39 #define DPPLL_SRC_DP_PLL_LOCK BIT(7)
40 #define SN_PLL_ENABLE_REG 0x0D
41 #define SN_DSI_LANES_REG 0x10
42 #define CHA_DSI_LANES_MASK GENMASK(4, 3)
43 #define CHA_DSI_LANES(x) ((x) << 3)
44 #define SN_DSIA_CLK_FREQ_REG 0x12
45 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
46 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
47 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
48 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
49 #define CHA_HSYNC_POLARITY BIT(7)
50 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
51 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
52 #define CHA_VSYNC_POLARITY BIT(7)
53 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
54 #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
55 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
56 #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
57 #define SN_LN_ASSIGN_REG 0x59
58 #define LN_ASSIGN_WIDTH 2
59 #define SN_ENH_FRAME_REG 0x5A
60 #define VSTREAM_ENABLE BIT(3)
61 #define LN_POLRS_OFFSET 4
62 #define LN_POLRS_MASK 0xf0
63 #define SN_DATA_FORMAT_REG 0x5B
64 #define BPP_18_RGB BIT(0)
65 #define SN_HPD_DISABLE_REG 0x5C
66 #define HPD_DISABLE BIT(0)
67 #define SN_GPIO_IO_REG 0x5E
68 #define SN_GPIO_INPUT_SHIFT 4
69 #define SN_GPIO_OUTPUT_SHIFT 0
70 #define SN_GPIO_CTRL_REG 0x5F
71 #define SN_GPIO_MUX_INPUT 0
72 #define SN_GPIO_MUX_OUTPUT 1
73 #define SN_GPIO_MUX_SPECIAL 2
74 #define SN_GPIO_MUX_MASK 0x3
75 #define SN_AUX_WDATA_REG(x) (0x64 + (x))
76 #define SN_AUX_ADDR_19_16_REG 0x74
77 #define SN_AUX_ADDR_15_8_REG 0x75
78 #define SN_AUX_ADDR_7_0_REG 0x76
79 #define SN_AUX_ADDR_MASK GENMASK(19, 0)
80 #define SN_AUX_LENGTH_REG 0x77
81 #define SN_AUX_CMD_REG 0x78
82 #define AUX_CMD_SEND BIT(0)
83 #define AUX_CMD_REQ(x) ((x) << 4)
84 #define SN_AUX_RDATA_REG(x) (0x79 + (x))
85 #define SN_SSC_CONFIG_REG 0x93
86 #define DP_NUM_LANES_MASK GENMASK(5, 4)
87 #define DP_NUM_LANES(x) ((x) << 4)
88 #define SN_DATARATE_CONFIG_REG 0x94
89 #define DP_DATARATE_MASK GENMASK(7, 5)
90 #define DP_DATARATE(x) ((x) << 5)
91 #define SN_ML_TX_MODE_REG 0x96
92 #define ML_TX_MAIN_LINK_OFF 0
93 #define ML_TX_NORMAL_MODE BIT(0)
94 #define SN_AUX_CMD_STATUS_REG 0xF4
95 #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3)
96 #define AUX_IRQ_STATUS_AUX_SHORT BIT(5)
97 #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6)
98
99 #define MIN_DSI_CLK_FREQ_MHZ 40
100
101 /* fudge factor required to account for 8b/10b encoding */
102 #define DP_CLK_FUDGE_NUM 10
103 #define DP_CLK_FUDGE_DEN 8
104
105 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
106 #define SN_AUX_MAX_PAYLOAD_BYTES 16
107
108 #define SN_REGULATOR_SUPPLY_NUM 4
109
110 #define SN_MAX_DP_LANES 4
111 #define SN_NUM_GPIOS 4
112 #define SN_GPIO_PHYSICAL_OFFSET 1
113
114 #define SN_LINK_TRAINING_TRIES 10
115
116 /**
117 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
118 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
119 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
120 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
121 *
122 * @dev: Pointer to the top level (i2c) device.
123 * @regmap: Regmap for accessing i2c.
124 * @aux: Our aux channel.
125 * @bridge: Our bridge.
126 * @connector: Our connector.
127 * @host_node: Remote DSI node.
128 * @dsi: Our MIPI DSI source.
129 * @refclk: Our reference clock.
130 * @next_bridge: The bridge on the eDP side.
131 * @enable_gpio: The GPIO we toggle to enable the bridge.
132 * @supplies: Data for bulk enabling/disabling our regulators.
133 * @dp_lanes: Count of dp_lanes we're using.
134 * @ln_assign: Value to program to the LN_ASSIGN register.
135 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
136 * @comms_enabled: If true then communication over the aux channel is enabled.
137 * @comms_mutex: Protects modification of comms_enabled.
138 *
139 * @gchip: If we expose our GPIOs, this is used.
140 * @gchip_output: A cache of whether we've set GPIOs to output. This
141 * serves double-duty of keeping track of the direction and
142 * also keeping track of whether we've incremented the
143 * pm_runtime reference count for this pin, which we do
144 * whenever a pin is configured as an output. This is a
145 * bitmap so we can do atomic ops on it without an extra
146 * lock so concurrent users of our 4 GPIOs don't stomp on
147 * each other's read-modify-write.
148 */
149 struct ti_sn65dsi86 {
150 struct auxiliary_device bridge_aux;
151 struct auxiliary_device gpio_aux;
152 struct auxiliary_device aux_aux;
153
154 struct device *dev;
155 struct regmap *regmap;
156 struct drm_dp_aux aux;
157 struct drm_bridge bridge;
158 struct drm_connector connector;
159 struct device_node *host_node;
160 struct mipi_dsi_device *dsi;
161 struct clk *refclk;
162 struct drm_bridge *next_bridge;
163 struct gpio_desc *enable_gpio;
164 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM];
165 int dp_lanes;
166 u8 ln_assign;
167 u8 ln_polrs;
168 bool comms_enabled;
169 struct mutex comms_mutex;
170
171 #if defined(CONFIG_OF_GPIO)
172 struct gpio_chip gchip;
173 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS);
174 #endif
175 };
176
177 static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = {
178 { .range_min = 0, .range_max = 0xFF },
179 };
180
181 static const struct regmap_access_table ti_sn_bridge_volatile_table = {
182 .yes_ranges = ti_sn65dsi86_volatile_ranges,
183 .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges),
184 };
185
186 static const struct regmap_config ti_sn65dsi86_regmap_config = {
187 .reg_bits = 8,
188 .val_bits = 8,
189 .volatile_table = &ti_sn_bridge_volatile_table,
190 .cache_type = REGCACHE_NONE,
191 };
192
ti_sn65dsi86_write_u16(struct ti_sn65dsi86 * pdata,unsigned int reg,u16 val)193 static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata,
194 unsigned int reg, u16 val)
195 {
196 regmap_write(pdata->regmap, reg, val & 0xFF);
197 regmap_write(pdata->regmap, reg + 1, val >> 8);
198 }
199
ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 * pdata)200 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata)
201 {
202 u32 bit_rate_khz, clk_freq_khz;
203 struct drm_display_mode *mode =
204 &pdata->bridge.encoder->crtc->state->adjusted_mode;
205
206 bit_rate_khz = mode->clock *
207 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
208 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
209
210 return clk_freq_khz;
211 }
212
213 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
214 static const u32 ti_sn_bridge_refclk_lut[] = {
215 12000000,
216 19200000,
217 26000000,
218 27000000,
219 38400000,
220 };
221
222 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
223 static const u32 ti_sn_bridge_dsiclk_lut[] = {
224 468000000,
225 384000000,
226 416000000,
227 486000000,
228 460800000,
229 };
230
ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 * pdata)231 static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata)
232 {
233 int i;
234 u32 refclk_rate;
235 const u32 *refclk_lut;
236 size_t refclk_lut_size;
237
238 if (pdata->refclk) {
239 refclk_rate = clk_get_rate(pdata->refclk);
240 refclk_lut = ti_sn_bridge_refclk_lut;
241 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
242 clk_prepare_enable(pdata->refclk);
243 } else {
244 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
245 refclk_lut = ti_sn_bridge_dsiclk_lut;
246 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
247 }
248
249 /* for i equals to refclk_lut_size means default frequency */
250 for (i = 0; i < refclk_lut_size; i++)
251 if (refclk_lut[i] == refclk_rate)
252 break;
253
254 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
255 REFCLK_FREQ(i));
256 }
257
ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 * pdata)258 static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata)
259 {
260 mutex_lock(&pdata->comms_mutex);
261
262 /* configure bridge ref_clk */
263 ti_sn_bridge_set_refclk_freq(pdata);
264
265 /*
266 * HPD on this bridge chip is a bit useless. This is an eDP bridge
267 * so the HPD is an internal signal that's only there to signal that
268 * the panel is done powering up. ...but the bridge chip debounces
269 * this signal by between 100 ms and 400 ms (depending on process,
270 * voltage, and temperate--I measured it at about 200 ms). One
271 * particular panel asserted HPD 84 ms after it was powered on meaning
272 * that we saw HPD 284 ms after power on. ...but the same panel said
273 * that instead of looking at HPD you could just hardcode a delay of
274 * 200 ms. We'll assume that the panel driver will have the hardcoded
275 * delay in its prepare and always disable HPD.
276 *
277 * If HPD somehow makes sense on some future panel we'll have to
278 * change this to be conditional on someone specifying that HPD should
279 * be used.
280 */
281 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
282 HPD_DISABLE);
283
284 pdata->comms_enabled = true;
285
286 mutex_unlock(&pdata->comms_mutex);
287 }
288
ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 * pdata)289 static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata)
290 {
291 mutex_lock(&pdata->comms_mutex);
292
293 pdata->comms_enabled = false;
294 clk_disable_unprepare(pdata->refclk);
295
296 mutex_unlock(&pdata->comms_mutex);
297 }
298
ti_sn65dsi86_resume(struct device * dev)299 static int __maybe_unused ti_sn65dsi86_resume(struct device *dev)
300 {
301 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
302 int ret;
303
304 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
305 if (ret) {
306 DRM_ERROR("failed to enable supplies %d\n", ret);
307 return ret;
308 }
309
310 /* td2: min 100 us after regulators before enabling the GPIO */
311 usleep_range(100, 110);
312
313 gpiod_set_value(pdata->enable_gpio, 1);
314
315 /*
316 * If we have a reference clock we can enable communication w/ the
317 * panel (including the aux channel) w/out any need for an input clock
318 * so we can do it in resume which lets us read the EDID before
319 * pre_enable(). Without a reference clock we need the MIPI reference
320 * clock so reading early doesn't work.
321 */
322 if (pdata->refclk)
323 ti_sn65dsi86_enable_comms(pdata);
324
325 return ret;
326 }
327
ti_sn65dsi86_suspend(struct device * dev)328 static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev)
329 {
330 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
331 int ret;
332
333 if (pdata->refclk)
334 ti_sn65dsi86_disable_comms(pdata);
335
336 gpiod_set_value(pdata->enable_gpio, 0);
337
338 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
339 if (ret)
340 DRM_ERROR("failed to disable supplies %d\n", ret);
341
342 return ret;
343 }
344
345 static const struct dev_pm_ops ti_sn65dsi86_pm_ops = {
346 SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL)
347 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
348 pm_runtime_force_resume)
349 };
350
status_show(struct seq_file * s,void * data)351 static int status_show(struct seq_file *s, void *data)
352 {
353 struct ti_sn65dsi86 *pdata = s->private;
354 unsigned int reg, val;
355
356 seq_puts(s, "STATUS REGISTERS:\n");
357
358 pm_runtime_get_sync(pdata->dev);
359
360 /* IRQ Status Registers, see Table 31 in datasheet */
361 for (reg = 0xf0; reg <= 0xf8; reg++) {
362 regmap_read(pdata->regmap, reg, &val);
363 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
364 }
365
366 pm_runtime_put_autosuspend(pdata->dev);
367
368 return 0;
369 }
370
371 DEFINE_SHOW_ATTRIBUTE(status);
372
ti_sn65dsi86_debugfs_remove(void * data)373 static void ti_sn65dsi86_debugfs_remove(void *data)
374 {
375 debugfs_remove_recursive(data);
376 }
377
ti_sn65dsi86_debugfs_init(struct ti_sn65dsi86 * pdata)378 static void ti_sn65dsi86_debugfs_init(struct ti_sn65dsi86 *pdata)
379 {
380 struct device *dev = pdata->dev;
381 struct dentry *debugfs;
382 int ret;
383
384 debugfs = debugfs_create_dir(dev_name(dev), NULL);
385
386 /*
387 * We might get an error back if debugfs wasn't enabled in the kernel
388 * so let's just silently return upon failure.
389 */
390 if (IS_ERR_OR_NULL(debugfs))
391 return;
392
393 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_debugfs_remove, debugfs);
394 if (ret)
395 return;
396
397 debugfs_create_file("status", 0600, debugfs, pdata, &status_fops);
398 }
399
400 /* -----------------------------------------------------------------------------
401 * Auxiliary Devices (*not* AUX)
402 */
403
ti_sn65dsi86_uninit_aux(void * data)404 static void ti_sn65dsi86_uninit_aux(void *data)
405 {
406 auxiliary_device_uninit(data);
407 }
408
ti_sn65dsi86_delete_aux(void * data)409 static void ti_sn65dsi86_delete_aux(void *data)
410 {
411 auxiliary_device_delete(data);
412 }
413
414 /*
415 * AUX bus docs say that a non-NULL release is mandatory, but it makes no
416 * sense for the model used here where all of the aux devices are allocated
417 * in the single shared structure. We'll use this noop as a workaround.
418 */
ti_sn65dsi86_noop(struct device * dev)419 static void ti_sn65dsi86_noop(struct device *dev) {}
420
ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 * pdata,struct auxiliary_device * aux,const char * name)421 static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata,
422 struct auxiliary_device *aux,
423 const char *name)
424 {
425 struct device *dev = pdata->dev;
426 int ret;
427
428 aux->name = name;
429 aux->dev.parent = dev;
430 aux->dev.release = ti_sn65dsi86_noop;
431 device_set_of_node_from_dev(&aux->dev, dev);
432 ret = auxiliary_device_init(aux);
433 if (ret)
434 return ret;
435 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_uninit_aux, aux);
436 if (ret)
437 return ret;
438
439 ret = auxiliary_device_add(aux);
440 if (ret)
441 return ret;
442 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_delete_aux, aux);
443
444 return ret;
445 }
446
447 /* -----------------------------------------------------------------------------
448 * AUX Adapter
449 */
450
aux_to_ti_sn65dsi86(struct drm_dp_aux * aux)451 static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux)
452 {
453 return container_of(aux, struct ti_sn65dsi86, aux);
454 }
455
ti_sn_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)456 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
457 struct drm_dp_aux_msg *msg)
458 {
459 struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux);
460 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
461 u32 request_val = AUX_CMD_REQ(msg->request);
462 u8 *buf = msg->buffer;
463 unsigned int len = msg->size;
464 unsigned int val;
465 int ret;
466 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG];
467
468 if (len > SN_AUX_MAX_PAYLOAD_BYTES)
469 return -EINVAL;
470
471 pm_runtime_get_sync(pdata->dev);
472 mutex_lock(&pdata->comms_mutex);
473
474 /*
475 * If someone tries to do a DDC over AUX transaction before pre_enable()
476 * on a device without a dedicated reference clock then we just can't
477 * do it. Fail right away. This prevents non-refclk users from reading
478 * the EDID before enabling the panel but such is life.
479 */
480 if (!pdata->comms_enabled) {
481 ret = -EIO;
482 goto exit;
483 }
484
485 switch (request) {
486 case DP_AUX_NATIVE_WRITE:
487 case DP_AUX_I2C_WRITE:
488 case DP_AUX_NATIVE_READ:
489 case DP_AUX_I2C_READ:
490 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
491 /* Assume it's good */
492 msg->reply = 0;
493 break;
494 default:
495 ret = -EINVAL;
496 goto exit;
497 }
498
499 BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32));
500 put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len,
501 addr_len);
502 regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len,
503 ARRAY_SIZE(addr_len));
504
505 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
506 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len);
507
508 /* Clear old status bits before start so we don't get confused */
509 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG,
510 AUX_IRQ_STATUS_NAT_I2C_FAIL |
511 AUX_IRQ_STATUS_AUX_RPLY_TOUT |
512 AUX_IRQ_STATUS_AUX_SHORT);
513
514 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
515
516 /* Zero delay loop because i2c transactions are slow already */
517 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
518 !(val & AUX_CMD_SEND), 0, 50 * 1000);
519 if (ret)
520 goto exit;
521
522 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
523 if (ret)
524 goto exit;
525
526 if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) {
527 /*
528 * The hardware tried the message seven times per the DP spec
529 * but it hit a timeout. We ignore defers here because they're
530 * handled in hardware.
531 */
532 ret = -ETIMEDOUT;
533 goto exit;
534 }
535
536 if (val & AUX_IRQ_STATUS_AUX_SHORT) {
537 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &len);
538 if (ret)
539 goto exit;
540 } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) {
541 switch (request) {
542 case DP_AUX_I2C_WRITE:
543 case DP_AUX_I2C_READ:
544 msg->reply |= DP_AUX_I2C_REPLY_NACK;
545 break;
546 case DP_AUX_NATIVE_READ:
547 case DP_AUX_NATIVE_WRITE:
548 msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
549 break;
550 }
551 len = 0;
552 goto exit;
553 }
554
555 if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0)
556 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len);
557
558 exit:
559 mutex_unlock(&pdata->comms_mutex);
560 pm_runtime_mark_last_busy(pdata->dev);
561 pm_runtime_put_autosuspend(pdata->dev);
562
563 if (ret)
564 return ret;
565 return len;
566 }
567
ti_sn_aux_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)568 static int ti_sn_aux_probe(struct auxiliary_device *adev,
569 const struct auxiliary_device_id *id)
570 {
571 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
572 int ret;
573
574 pdata->aux.name = "ti-sn65dsi86-aux";
575 pdata->aux.dev = &adev->dev;
576 pdata->aux.transfer = ti_sn_aux_transfer;
577 drm_dp_aux_init(&pdata->aux);
578
579 ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux);
580 if (ret)
581 return ret;
582
583 /*
584 * The eDP to MIPI bridge parts don't work until the AUX channel is
585 * setup so we don't add it in the main driver probe, we add it now.
586 */
587 return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge");
588 }
589
590 static const struct auxiliary_device_id ti_sn_aux_id_table[] = {
591 { .name = "ti_sn65dsi86.aux", },
592 {},
593 };
594
595 static struct auxiliary_driver ti_sn_aux_driver = {
596 .name = "aux",
597 .probe = ti_sn_aux_probe,
598 .id_table = ti_sn_aux_id_table,
599 };
600
601 /* -----------------------------------------------------------------------------
602 * DRM Connector Operations
603 */
604
605 static struct ti_sn65dsi86 *
connector_to_ti_sn65dsi86(struct drm_connector * connector)606 connector_to_ti_sn65dsi86(struct drm_connector *connector)
607 {
608 return container_of(connector, struct ti_sn65dsi86, connector);
609 }
610
ti_sn_bridge_connector_get_modes(struct drm_connector * connector)611 static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector)
612 {
613 struct ti_sn65dsi86 *pdata = connector_to_ti_sn65dsi86(connector);
614
615 return drm_bridge_get_modes(pdata->next_bridge, connector);
616 }
617
618 static enum drm_mode_status
ti_sn_bridge_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)619 ti_sn_bridge_connector_mode_valid(struct drm_connector *connector,
620 struct drm_display_mode *mode)
621 {
622 /* maximum supported resolution is 4K at 60 fps */
623 if (mode->clock > 594000)
624 return MODE_CLOCK_HIGH;
625
626 return MODE_OK;
627 }
628
629 static struct drm_connector_helper_funcs ti_sn_bridge_connector_helper_funcs = {
630 .get_modes = ti_sn_bridge_connector_get_modes,
631 .mode_valid = ti_sn_bridge_connector_mode_valid,
632 };
633
634 static const struct drm_connector_funcs ti_sn_bridge_connector_funcs = {
635 .fill_modes = drm_helper_probe_single_connector_modes,
636 .destroy = drm_connector_cleanup,
637 .reset = drm_atomic_helper_connector_reset,
638 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
639 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
640 };
641
ti_sn_bridge_connector_init(struct ti_sn65dsi86 * pdata)642 static int ti_sn_bridge_connector_init(struct ti_sn65dsi86 *pdata)
643 {
644 int ret;
645
646 ret = drm_connector_init(pdata->bridge.dev, &pdata->connector,
647 &ti_sn_bridge_connector_funcs,
648 DRM_MODE_CONNECTOR_eDP);
649 if (ret) {
650 DRM_ERROR("Failed to initialize connector with drm\n");
651 return ret;
652 }
653
654 drm_connector_helper_add(&pdata->connector,
655 &ti_sn_bridge_connector_helper_funcs);
656 drm_connector_attach_encoder(&pdata->connector, pdata->bridge.encoder);
657
658 return 0;
659 }
660
661 /*------------------------------------------------------------------------------
662 * DRM Bridge
663 */
664
bridge_to_ti_sn65dsi86(struct drm_bridge * bridge)665 static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge)
666 {
667 return container_of(bridge, struct ti_sn65dsi86, bridge);
668 }
669
ti_sn_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)670 static int ti_sn_bridge_attach(struct drm_bridge *bridge,
671 enum drm_bridge_attach_flags flags)
672 {
673 int ret, val;
674 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
675 struct mipi_dsi_host *host;
676 struct mipi_dsi_device *dsi;
677 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
678 .channel = 0,
679 .node = NULL,
680 };
681
682 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
683 DRM_ERROR("Fix bridge driver to make connector optional!");
684 return -EINVAL;
685 }
686
687 pdata->aux.drm_dev = bridge->dev;
688 ret = drm_dp_aux_register(&pdata->aux);
689 if (ret < 0) {
690 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret);
691 return ret;
692 }
693
694 ret = ti_sn_bridge_connector_init(pdata);
695 if (ret < 0)
696 goto err_conn_init;
697
698 /*
699 * TODO: ideally finding host resource and dsi dev registration needs
700 * to be done in bridge probe. But some existing DSI host drivers will
701 * wait for any of the drm_bridge/drm_panel to get added to the global
702 * bridge/panel list, before completing their probe. So if we do the
703 * dsi dev registration part in bridge probe, before populating in
704 * the global bridge list, then it will cause deadlock as dsi host probe
705 * will never complete, neither our bridge probe. So keeping it here
706 * will satisfy most of the existing host drivers. Once the host driver
707 * is fixed we can move the below code to bridge probe safely.
708 */
709 host = of_find_mipi_dsi_host_by_node(pdata->host_node);
710 if (!host) {
711 DRM_ERROR("failed to find dsi host\n");
712 ret = -ENODEV;
713 goto err_dsi_host;
714 }
715
716 dsi = mipi_dsi_device_register_full(host, &info);
717 if (IS_ERR(dsi)) {
718 DRM_ERROR("failed to create dsi device\n");
719 ret = PTR_ERR(dsi);
720 goto err_dsi_host;
721 }
722
723 /* TODO: setting to 4 MIPI lanes always for now */
724 dsi->lanes = 4;
725 dsi->format = MIPI_DSI_FMT_RGB888;
726 dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
727
728 /* check if continuous dsi clock is required or not */
729 pm_runtime_get_sync(pdata->dev);
730 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
731 pm_runtime_put_autosuspend(pdata->dev);
732 if (!(val & DPPLL_CLK_SRC_DSICLK))
733 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
734
735 ret = mipi_dsi_attach(dsi);
736 if (ret < 0) {
737 DRM_ERROR("failed to attach dsi to host\n");
738 goto err_dsi_attach;
739 }
740 pdata->dsi = dsi;
741
742 /* We never want the next bridge to *also* create a connector: */
743 flags |= DRM_BRIDGE_ATTACH_NO_CONNECTOR;
744
745 /* Attach the next bridge */
746 ret = drm_bridge_attach(bridge->encoder, pdata->next_bridge,
747 &pdata->bridge, flags);
748 if (ret < 0)
749 goto err_dsi_detach;
750
751 return 0;
752
753 err_dsi_detach:
754 mipi_dsi_detach(dsi);
755 err_dsi_attach:
756 mipi_dsi_device_unregister(dsi);
757 err_dsi_host:
758 drm_connector_cleanup(&pdata->connector);
759 err_conn_init:
760 drm_dp_aux_unregister(&pdata->aux);
761 return ret;
762 }
763
ti_sn_bridge_detach(struct drm_bridge * bridge)764 static void ti_sn_bridge_detach(struct drm_bridge *bridge)
765 {
766 drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux);
767 }
768
ti_sn_bridge_disable(struct drm_bridge * bridge)769 static void ti_sn_bridge_disable(struct drm_bridge *bridge)
770 {
771 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
772
773 /* disable video stream */
774 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
775 }
776
ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 * pdata)777 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata)
778 {
779 unsigned int bit_rate_mhz, clk_freq_mhz;
780 unsigned int val;
781 struct drm_display_mode *mode =
782 &pdata->bridge.encoder->crtc->state->adjusted_mode;
783
784 /* set DSIA clk frequency */
785 bit_rate_mhz = (mode->clock / 1000) *
786 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
787 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
788
789 /* for each increment in val, frequency increases by 5MHz */
790 val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
791 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
792 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
793 }
794
ti_sn_bridge_get_bpp(struct ti_sn65dsi86 * pdata)795 static unsigned int ti_sn_bridge_get_bpp(struct ti_sn65dsi86 *pdata)
796 {
797 if (pdata->connector.display_info.bpc <= 6)
798 return 18;
799 else
800 return 24;
801 }
802
803 /*
804 * LUT index corresponds to register value and
805 * LUT values corresponds to dp data rate supported
806 * by the bridge in Mbps unit.
807 */
808 static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
809 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
810 };
811
ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 * pdata)812 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata)
813 {
814 unsigned int bit_rate_khz, dp_rate_mhz;
815 unsigned int i;
816 struct drm_display_mode *mode =
817 &pdata->bridge.encoder->crtc->state->adjusted_mode;
818
819 /* Calculate minimum bit rate based on our pixel clock. */
820 bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata);
821
822 /* Calculate minimum DP data rate, taking 80% as per DP spec */
823 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
824 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
825
826 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
827 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz)
828 break;
829
830 return i;
831 }
832
ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 * pdata)833 static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata)
834 {
835 unsigned int valid_rates = 0;
836 unsigned int rate_per_200khz;
837 unsigned int rate_mhz;
838 u8 dpcd_val;
839 int ret;
840 int i, j;
841
842 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val);
843 if (ret != 1) {
844 DRM_DEV_ERROR(pdata->dev,
845 "Can't read eDP rev (%d), assuming 1.1\n", ret);
846 dpcd_val = DP_EDP_11;
847 }
848
849 if (dpcd_val >= DP_EDP_14) {
850 /* eDP 1.4 devices must provide a custom table */
851 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
852
853 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES,
854 sink_rates, sizeof(sink_rates));
855
856 if (ret != sizeof(sink_rates)) {
857 DRM_DEV_ERROR(pdata->dev,
858 "Can't read supported rate table (%d)\n", ret);
859
860 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */
861 memset(sink_rates, 0, sizeof(sink_rates));
862 }
863
864 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
865 rate_per_200khz = le16_to_cpu(sink_rates[i]);
866
867 if (!rate_per_200khz)
868 break;
869
870 rate_mhz = rate_per_200khz * 200 / 1000;
871 for (j = 0;
872 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
873 j++) {
874 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz)
875 valid_rates |= BIT(j);
876 }
877 }
878
879 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) {
880 if (valid_rates & BIT(i))
881 return valid_rates;
882 }
883 DRM_DEV_ERROR(pdata->dev,
884 "No matching eDP rates in table; falling back\n");
885 }
886
887 /* On older versions best we can do is use DP_MAX_LINK_RATE */
888 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val);
889 if (ret != 1) {
890 DRM_DEV_ERROR(pdata->dev,
891 "Can't read max rate (%d); assuming 5.4 GHz\n",
892 ret);
893 dpcd_val = DP_LINK_BW_5_4;
894 }
895
896 switch (dpcd_val) {
897 default:
898 DRM_DEV_ERROR(pdata->dev,
899 "Unexpected max rate (%#x); assuming 5.4 GHz\n",
900 (int)dpcd_val);
901 fallthrough;
902 case DP_LINK_BW_5_4:
903 valid_rates |= BIT(7);
904 fallthrough;
905 case DP_LINK_BW_2_7:
906 valid_rates |= BIT(4);
907 fallthrough;
908 case DP_LINK_BW_1_62:
909 valid_rates |= BIT(1);
910 break;
911 }
912
913 return valid_rates;
914 }
915
ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 * pdata)916 static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata)
917 {
918 struct drm_display_mode *mode =
919 &pdata->bridge.encoder->crtc->state->adjusted_mode;
920 u8 hsync_polarity = 0, vsync_polarity = 0;
921
922 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
923 hsync_polarity = CHA_HSYNC_POLARITY;
924 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
925 vsync_polarity = CHA_VSYNC_POLARITY;
926
927 ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
928 mode->hdisplay);
929 ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
930 mode->vdisplay);
931 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
932 (mode->hsync_end - mode->hsync_start) & 0xFF);
933 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
934 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
935 hsync_polarity);
936 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
937 (mode->vsync_end - mode->vsync_start) & 0xFF);
938 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
939 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
940 vsync_polarity);
941
942 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
943 (mode->htotal - mode->hsync_end) & 0xFF);
944 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
945 (mode->vtotal - mode->vsync_end) & 0xFF);
946
947 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
948 (mode->hsync_start - mode->hdisplay) & 0xFF);
949 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
950 (mode->vsync_start - mode->vdisplay) & 0xFF);
951
952 usleep_range(10000, 10500); /* 10ms delay recommended by spec */
953 }
954
ti_sn_get_max_lanes(struct ti_sn65dsi86 * pdata)955 static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata)
956 {
957 u8 data;
958 int ret;
959
960 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);
961 if (ret != 1) {
962 DRM_DEV_ERROR(pdata->dev,
963 "Can't read lane count (%d); assuming 4\n", ret);
964 return 4;
965 }
966
967 return data & DP_LANE_COUNT_MASK;
968 }
969
ti_sn_link_training(struct ti_sn65dsi86 * pdata,int dp_rate_idx,const char ** last_err_str)970 static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx,
971 const char **last_err_str)
972 {
973 unsigned int val;
974 int ret;
975 int i;
976
977 /* set dp clk frequency value */
978 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
979 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));
980
981 /* enable DP PLL */
982 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
983
984 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
985 val & DPPLL_SRC_DP_PLL_LOCK, 1000,
986 50 * 1000);
987 if (ret) {
988 *last_err_str = "DP_PLL_LOCK polling failed";
989 goto exit;
990 }
991
992 /*
993 * We'll try to link train several times. As part of link training
994 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If
995 * the panel isn't ready quite it might respond NAK here which means
996 * we need to try again.
997 */
998 for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) {
999 /* Semi auto link training mode */
1000 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
1001 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
1002 val == ML_TX_MAIN_LINK_OFF ||
1003 val == ML_TX_NORMAL_MODE, 1000,
1004 500 * 1000);
1005 if (ret) {
1006 *last_err_str = "Training complete polling failed";
1007 } else if (val == ML_TX_MAIN_LINK_OFF) {
1008 *last_err_str = "Link training failed, link is off";
1009 ret = -EIO;
1010 continue;
1011 }
1012
1013 break;
1014 }
1015
1016 /* If we saw quite a few retries, add a note about it */
1017 if (!ret && i > SN_LINK_TRAINING_TRIES / 2)
1018 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i);
1019
1020 exit:
1021 /* Disable the PLL if we failed */
1022 if (ret)
1023 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1024
1025 return ret;
1026 }
1027
ti_sn_bridge_enable(struct drm_bridge * bridge)1028 static void ti_sn_bridge_enable(struct drm_bridge *bridge)
1029 {
1030 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1031 const char *last_err_str = "No supported DP rate";
1032 unsigned int valid_rates;
1033 int dp_rate_idx;
1034 unsigned int val;
1035 int ret = -EINVAL;
1036 int max_dp_lanes;
1037
1038 max_dp_lanes = ti_sn_get_max_lanes(pdata);
1039 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
1040
1041 /* DSI_A lane config */
1042 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes);
1043 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
1044 CHA_DSI_LANES_MASK, val);
1045
1046 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign);
1047 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK,
1048 pdata->ln_polrs << LN_POLRS_OFFSET);
1049
1050 /* set dsi clk frequency value */
1051 ti_sn_bridge_set_dsi_rate(pdata);
1052
1053 /*
1054 * The SN65DSI86 only supports ASSR Display Authentication method and
1055 * this method is enabled by default. An eDP panel must support this
1056 * authentication method. We need to enable this method in the eDP panel
1057 * at DisplayPort address 0x0010A prior to link training.
1058 */
1059 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
1060 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
1061
1062 /* Set the DP output format (18 bpp or 24 bpp) */
1063 val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0;
1064 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
1065
1066 /* DP lane config */
1067 val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
1068 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
1069 val);
1070
1071 valid_rates = ti_sn_bridge_read_valid_rates(pdata);
1072
1073 /* Train until we run out of rates */
1074 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata);
1075 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
1076 dp_rate_idx++) {
1077 if (!(valid_rates & BIT(dp_rate_idx)))
1078 continue;
1079
1080 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str);
1081 if (!ret)
1082 break;
1083 }
1084 if (ret) {
1085 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret);
1086 return;
1087 }
1088
1089 /* config video parameters */
1090 ti_sn_bridge_set_video_timings(pdata);
1091
1092 /* enable video stream */
1093 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
1094 VSTREAM_ENABLE);
1095 }
1096
ti_sn_bridge_pre_enable(struct drm_bridge * bridge)1097 static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
1098 {
1099 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1100
1101 pm_runtime_get_sync(pdata->dev);
1102
1103 if (!pdata->refclk)
1104 ti_sn65dsi86_enable_comms(pdata);
1105
1106 /* td7: min 100 us after enable before DSI data */
1107 usleep_range(100, 110);
1108 }
1109
ti_sn_bridge_post_disable(struct drm_bridge * bridge)1110 static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
1111 {
1112 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1113
1114 /* semi auto link training mode OFF */
1115 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
1116 /* Num lanes to 0 as per power sequencing in data sheet */
1117 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0);
1118 /* disable DP PLL */
1119 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1120
1121 if (!pdata->refclk)
1122 ti_sn65dsi86_disable_comms(pdata);
1123
1124 pm_runtime_put_sync(pdata->dev);
1125 }
1126
1127 static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
1128 .attach = ti_sn_bridge_attach,
1129 .detach = ti_sn_bridge_detach,
1130 .pre_enable = ti_sn_bridge_pre_enable,
1131 .enable = ti_sn_bridge_enable,
1132 .disable = ti_sn_bridge_disable,
1133 .post_disable = ti_sn_bridge_post_disable,
1134 };
1135
ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 * pdata,struct device_node * np)1136 static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata,
1137 struct device_node *np)
1138 {
1139 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 };
1140 u32 lane_polarities[SN_MAX_DP_LANES] = { };
1141 struct device_node *endpoint;
1142 u8 ln_assign = 0;
1143 u8 ln_polrs = 0;
1144 int dp_lanes;
1145 int i;
1146
1147 /*
1148 * Read config from the device tree about lane remapping and lane
1149 * polarities. These are optional and we assume identity map and
1150 * normal polarity if nothing is specified. It's OK to specify just
1151 * data-lanes but not lane-polarities but not vice versa.
1152 *
1153 * Error checking is light (we just make sure we don't crash or
1154 * buffer overrun) and we assume dts is well formed and specifying
1155 * mappings that the hardware supports.
1156 */
1157 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1158 dp_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
1159 if (dp_lanes > 0 && dp_lanes <= SN_MAX_DP_LANES) {
1160 of_property_read_u32_array(endpoint, "data-lanes",
1161 lane_assignments, dp_lanes);
1162 of_property_read_u32_array(endpoint, "lane-polarities",
1163 lane_polarities, dp_lanes);
1164 } else {
1165 dp_lanes = SN_MAX_DP_LANES;
1166 }
1167 of_node_put(endpoint);
1168
1169 /*
1170 * Convert into register format. Loop over all lanes even if
1171 * data-lanes had fewer elements so that we nicely initialize
1172 * the LN_ASSIGN register.
1173 */
1174 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) {
1175 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i];
1176 ln_polrs = ln_polrs << 1 | lane_polarities[i];
1177 }
1178
1179 /* Stash in our struct for when we power on */
1180 pdata->dp_lanes = dp_lanes;
1181 pdata->ln_assign = ln_assign;
1182 pdata->ln_polrs = ln_polrs;
1183 }
1184
ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 * pdata)1185 static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata)
1186 {
1187 struct device_node *np = pdata->dev->of_node;
1188
1189 pdata->host_node = of_graph_get_remote_node(np, 0, 0);
1190
1191 if (!pdata->host_node) {
1192 DRM_ERROR("remote dsi host node not found\n");
1193 return -ENODEV;
1194 }
1195
1196 return 0;
1197 }
1198
ti_sn_bridge_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)1199 static int ti_sn_bridge_probe(struct auxiliary_device *adev,
1200 const struct auxiliary_device_id *id)
1201 {
1202 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1203 struct device_node *np = pdata->dev->of_node;
1204 struct drm_panel *panel;
1205 int ret;
1206
1207 ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL);
1208 if (ret)
1209 return dev_err_probe(&adev->dev, ret,
1210 "could not find any panel node\n");
1211
1212 pdata->next_bridge = devm_drm_panel_bridge_add(pdata->dev, panel);
1213 if (IS_ERR(pdata->next_bridge)) {
1214 DRM_ERROR("failed to create panel bridge\n");
1215 return PTR_ERR(pdata->next_bridge);
1216 }
1217
1218 ti_sn_bridge_parse_lanes(pdata, np);
1219
1220 ret = ti_sn_bridge_parse_dsi_host(pdata);
1221 if (ret)
1222 return ret;
1223
1224 pdata->bridge.funcs = &ti_sn_bridge_funcs;
1225 pdata->bridge.of_node = np;
1226
1227 drm_bridge_add(&pdata->bridge);
1228
1229 return 0;
1230 }
1231
ti_sn_bridge_remove(struct auxiliary_device * adev)1232 static void ti_sn_bridge_remove(struct auxiliary_device *adev)
1233 {
1234 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1235
1236 if (!pdata)
1237 return;
1238
1239 if (pdata->dsi) {
1240 mipi_dsi_detach(pdata->dsi);
1241 mipi_dsi_device_unregister(pdata->dsi);
1242 }
1243
1244 drm_bridge_remove(&pdata->bridge);
1245
1246 of_node_put(pdata->host_node);
1247 }
1248
1249 static const struct auxiliary_device_id ti_sn_bridge_id_table[] = {
1250 { .name = "ti_sn65dsi86.bridge", },
1251 {},
1252 };
1253
1254 static struct auxiliary_driver ti_sn_bridge_driver = {
1255 .name = "bridge",
1256 .probe = ti_sn_bridge_probe,
1257 .remove = ti_sn_bridge_remove,
1258 .id_table = ti_sn_bridge_id_table,
1259 };
1260
1261 /* -----------------------------------------------------------------------------
1262 * GPIO Controller
1263 */
1264
1265 #if defined(CONFIG_OF_GPIO)
1266
tn_sn_bridge_of_xlate(struct gpio_chip * chip,const struct of_phandle_args * gpiospec,u32 * flags)1267 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip,
1268 const struct of_phandle_args *gpiospec,
1269 u32 *flags)
1270 {
1271 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells))
1272 return -EINVAL;
1273
1274 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1)
1275 return -EINVAL;
1276
1277 if (flags)
1278 *flags = gpiospec->args[1];
1279
1280 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET;
1281 }
1282
ti_sn_bridge_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)1283 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip,
1284 unsigned int offset)
1285 {
1286 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1287
1288 /*
1289 * We already have to keep track of the direction because we use
1290 * that to figure out whether we've powered the device. We can
1291 * just return that rather than (maybe) powering up the device
1292 * to ask its direction.
1293 */
1294 return test_bit(offset, pdata->gchip_output) ?
1295 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1296 }
1297
ti_sn_bridge_gpio_get(struct gpio_chip * chip,unsigned int offset)1298 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset)
1299 {
1300 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1301 unsigned int val;
1302 int ret;
1303
1304 /*
1305 * When the pin is an input we don't forcibly keep the bridge
1306 * powered--we just power it on to read the pin. NOTE: part of
1307 * the reason this works is that the bridge defaults (when
1308 * powered back on) to all 4 GPIOs being configured as GPIO input.
1309 * Also note that if something else is keeping the chip powered the
1310 * pm_runtime functions are lightweight increments of a refcount.
1311 */
1312 pm_runtime_get_sync(pdata->dev);
1313 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val);
1314 pm_runtime_put_autosuspend(pdata->dev);
1315
1316 if (ret)
1317 return ret;
1318
1319 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset));
1320 }
1321
ti_sn_bridge_gpio_set(struct gpio_chip * chip,unsigned int offset,int val)1322 static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset,
1323 int val)
1324 {
1325 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1326 int ret;
1327
1328 if (!test_bit(offset, pdata->gchip_output)) {
1329 dev_err(pdata->dev, "Ignoring GPIO set while input\n");
1330 return;
1331 }
1332
1333 val &= 1;
1334 ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG,
1335 BIT(SN_GPIO_OUTPUT_SHIFT + offset),
1336 val << (SN_GPIO_OUTPUT_SHIFT + offset));
1337 if (ret)
1338 dev_warn(pdata->dev,
1339 "Failed to set bridge GPIO %u: %d\n", offset, ret);
1340 }
1341
ti_sn_bridge_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)1342 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip,
1343 unsigned int offset)
1344 {
1345 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1346 int shift = offset * 2;
1347 int ret;
1348
1349 if (!test_and_clear_bit(offset, pdata->gchip_output))
1350 return 0;
1351
1352 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1353 SN_GPIO_MUX_MASK << shift,
1354 SN_GPIO_MUX_INPUT << shift);
1355 if (ret) {
1356 set_bit(offset, pdata->gchip_output);
1357 return ret;
1358 }
1359
1360 /*
1361 * NOTE: if nobody else is powering the device this may fully power
1362 * it off and when it comes back it will have lost all state, but
1363 * that's OK because the default is input and we're now an input.
1364 */
1365 pm_runtime_put_autosuspend(pdata->dev);
1366
1367 return 0;
1368 }
1369
ti_sn_bridge_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int val)1370 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip,
1371 unsigned int offset, int val)
1372 {
1373 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1374 int shift = offset * 2;
1375 int ret;
1376
1377 if (test_and_set_bit(offset, pdata->gchip_output))
1378 return 0;
1379
1380 pm_runtime_get_sync(pdata->dev);
1381
1382 /* Set value first to avoid glitching */
1383 ti_sn_bridge_gpio_set(chip, offset, val);
1384
1385 /* Set direction */
1386 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1387 SN_GPIO_MUX_MASK << shift,
1388 SN_GPIO_MUX_OUTPUT << shift);
1389 if (ret) {
1390 clear_bit(offset, pdata->gchip_output);
1391 pm_runtime_put_autosuspend(pdata->dev);
1392 }
1393
1394 return ret;
1395 }
1396
ti_sn_bridge_gpio_free(struct gpio_chip * chip,unsigned int offset)1397 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset)
1398 {
1399 /* We won't keep pm_runtime if we're input, so switch there on free */
1400 ti_sn_bridge_gpio_direction_input(chip, offset);
1401 }
1402
1403 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = {
1404 "GPIO1", "GPIO2", "GPIO3", "GPIO4"
1405 };
1406
ti_sn_gpio_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)1407 static int ti_sn_gpio_probe(struct auxiliary_device *adev,
1408 const struct auxiliary_device_id *id)
1409 {
1410 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1411 int ret;
1412
1413 /* Only init if someone is going to use us as a GPIO controller */
1414 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller"))
1415 return 0;
1416
1417 pdata->gchip.label = dev_name(pdata->dev);
1418 pdata->gchip.parent = pdata->dev;
1419 pdata->gchip.owner = THIS_MODULE;
1420 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate;
1421 pdata->gchip.of_gpio_n_cells = 2;
1422 pdata->gchip.free = ti_sn_bridge_gpio_free;
1423 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction;
1424 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input;
1425 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output;
1426 pdata->gchip.get = ti_sn_bridge_gpio_get;
1427 pdata->gchip.set = ti_sn_bridge_gpio_set;
1428 pdata->gchip.can_sleep = true;
1429 pdata->gchip.names = ti_sn_bridge_gpio_names;
1430 pdata->gchip.ngpio = SN_NUM_GPIOS;
1431 pdata->gchip.base = -1;
1432 ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata);
1433 if (ret)
1434 dev_err(pdata->dev, "can't add gpio chip\n");
1435
1436 return ret;
1437 }
1438
1439 static const struct auxiliary_device_id ti_sn_gpio_id_table[] = {
1440 { .name = "ti_sn65dsi86.gpio", },
1441 {},
1442 };
1443
1444 MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table);
1445
1446 static struct auxiliary_driver ti_sn_gpio_driver = {
1447 .name = "gpio",
1448 .probe = ti_sn_gpio_probe,
1449 .id_table = ti_sn_gpio_id_table,
1450 };
1451
ti_sn_gpio_register(void)1452 static int __init ti_sn_gpio_register(void)
1453 {
1454 return auxiliary_driver_register(&ti_sn_gpio_driver);
1455 }
1456
ti_sn_gpio_unregister(void)1457 static void ti_sn_gpio_unregister(void)
1458 {
1459 auxiliary_driver_unregister(&ti_sn_gpio_driver);
1460 }
1461
1462 #else
1463
ti_sn_gpio_register(void)1464 static inline int ti_sn_gpio_register(void) { return 0; }
ti_sn_gpio_unregister(void)1465 static inline void ti_sn_gpio_unregister(void) {}
1466
1467 #endif
1468
1469 /* -----------------------------------------------------------------------------
1470 * Probe & Remove
1471 */
1472
ti_sn65dsi86_runtime_disable(void * data)1473 static void ti_sn65dsi86_runtime_disable(void *data)
1474 {
1475 pm_runtime_disable(data);
1476 }
1477
ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 * pdata)1478 static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata)
1479 {
1480 unsigned int i;
1481 const char * const ti_sn_bridge_supply_names[] = {
1482 "vcca", "vcc", "vccio", "vpll",
1483 };
1484
1485 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
1486 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
1487
1488 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
1489 pdata->supplies);
1490 }
1491
ti_sn65dsi86_probe(struct i2c_client * client,const struct i2c_device_id * id)1492 static int ti_sn65dsi86_probe(struct i2c_client *client,
1493 const struct i2c_device_id *id)
1494 {
1495 struct device *dev = &client->dev;
1496 struct ti_sn65dsi86 *pdata;
1497 int ret;
1498
1499 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1500 DRM_ERROR("device doesn't support I2C\n");
1501 return -ENODEV;
1502 }
1503
1504 pdata = devm_kzalloc(dev, sizeof(struct ti_sn65dsi86), GFP_KERNEL);
1505 if (!pdata)
1506 return -ENOMEM;
1507 dev_set_drvdata(dev, pdata);
1508 pdata->dev = dev;
1509
1510 mutex_init(&pdata->comms_mutex);
1511
1512 pdata->regmap = devm_regmap_init_i2c(client,
1513 &ti_sn65dsi86_regmap_config);
1514 if (IS_ERR(pdata->regmap))
1515 return dev_err_probe(dev, PTR_ERR(pdata->regmap),
1516 "regmap i2c init failed\n");
1517
1518 pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable",
1519 GPIOD_OUT_LOW);
1520 if (IS_ERR(pdata->enable_gpio))
1521 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio),
1522 "failed to get enable gpio from DT\n");
1523
1524 ret = ti_sn65dsi86_parse_regulators(pdata);
1525 if (ret)
1526 return dev_err_probe(dev, ret, "failed to parse regulators\n");
1527
1528 pdata->refclk = devm_clk_get_optional(dev, "refclk");
1529 if (IS_ERR(pdata->refclk))
1530 return dev_err_probe(dev, PTR_ERR(pdata->refclk),
1531 "failed to get reference clock\n");
1532
1533 pm_runtime_enable(dev);
1534 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev);
1535 if (ret)
1536 return ret;
1537 pm_runtime_set_autosuspend_delay(pdata->dev, 500);
1538 pm_runtime_use_autosuspend(pdata->dev);
1539
1540 ti_sn65dsi86_debugfs_init(pdata);
1541
1542 /*
1543 * Break ourselves up into a collection of aux devices. The only real
1544 * motiviation here is to solve the chicken-and-egg problem of probe
1545 * ordering. The bridge wants the panel to be there when it probes.
1546 * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards)
1547 * when it probes. The panel and maybe backlight might want the DDC
1548 * bus. Soon the PWM provided by the bridge chip will have the same
1549 * problem. Having sub-devices allows the some sub devices to finish
1550 * probing even if others return -EPROBE_DEFER and gets us around the
1551 * problems.
1552 */
1553
1554 if (IS_ENABLED(CONFIG_OF_GPIO)) {
1555 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio");
1556 if (ret)
1557 return ret;
1558 }
1559
1560 /*
1561 * NOTE: At the end of the AUX channel probe we'll add the aux device
1562 * for the bridge. This is because the bridge can't be used until the
1563 * AUX channel is there and this is a very simple solution to the
1564 * dependency problem.
1565 */
1566 return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux");
1567 }
1568
1569 static struct i2c_device_id ti_sn65dsi86_id[] = {
1570 { "ti,sn65dsi86", 0},
1571 {},
1572 };
1573 MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id);
1574
1575 static const struct of_device_id ti_sn65dsi86_match_table[] = {
1576 {.compatible = "ti,sn65dsi86"},
1577 {},
1578 };
1579 MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table);
1580
1581 static struct i2c_driver ti_sn65dsi86_driver = {
1582 .driver = {
1583 .name = "ti_sn65dsi86",
1584 .of_match_table = ti_sn65dsi86_match_table,
1585 .pm = &ti_sn65dsi86_pm_ops,
1586 },
1587 .probe = ti_sn65dsi86_probe,
1588 .id_table = ti_sn65dsi86_id,
1589 };
1590
ti_sn65dsi86_init(void)1591 static int __init ti_sn65dsi86_init(void)
1592 {
1593 int ret;
1594
1595 ret = i2c_add_driver(&ti_sn65dsi86_driver);
1596 if (ret)
1597 return ret;
1598
1599 ret = ti_sn_gpio_register();
1600 if (ret)
1601 goto err_main_was_registered;
1602
1603 ret = auxiliary_driver_register(&ti_sn_aux_driver);
1604 if (ret)
1605 goto err_gpio_was_registered;
1606
1607 ret = auxiliary_driver_register(&ti_sn_bridge_driver);
1608 if (ret)
1609 goto err_aux_was_registered;
1610
1611 return 0;
1612
1613 err_aux_was_registered:
1614 auxiliary_driver_unregister(&ti_sn_aux_driver);
1615 err_gpio_was_registered:
1616 ti_sn_gpio_unregister();
1617 err_main_was_registered:
1618 i2c_del_driver(&ti_sn65dsi86_driver);
1619
1620 return ret;
1621 }
1622 module_init(ti_sn65dsi86_init);
1623
ti_sn65dsi86_exit(void)1624 static void __exit ti_sn65dsi86_exit(void)
1625 {
1626 auxiliary_driver_unregister(&ti_sn_bridge_driver);
1627 auxiliary_driver_unregister(&ti_sn_aux_driver);
1628 ti_sn_gpio_unregister();
1629 i2c_del_driver(&ti_sn65dsi86_driver);
1630 }
1631 module_exit(ti_sn65dsi86_exit);
1632
1633 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
1634 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
1635 MODULE_LICENSE("GPL v2");
1636
