1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Real Time Clock (RTC) Driver for i.MX53
4 * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
5 * Copyright (c) 2017 Beckhoff Automation GmbH & Co. KG
6 */
7
8 #include <linux/clk.h>
9 #include <linux/io.h>
10 #include <linux/module.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_wakeirq.h>
14 #include <linux/rtc.h>
15
16 #define SRTC_LPPDR_INIT 0x41736166 /* init for glitch detect */
17
18 #define SRTC_LPCR_EN_LP BIT(3) /* lp enable */
19 #define SRTC_LPCR_WAE BIT(4) /* lp wakeup alarm enable */
20 #define SRTC_LPCR_ALP BIT(7) /* lp alarm flag */
21 #define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
22 #define SRTC_LPCR_NVE BIT(14) /* lp non valid state exit bit */
23 #define SRTC_LPCR_IE BIT(15) /* lp init state exit bit */
24
25 #define SRTC_LPSR_ALP BIT(3) /* lp alarm flag */
26 #define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
27 #define SRTC_LPSR_IES BIT(15) /* lp init state exit status */
28
29 #define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
30 #define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
31 #define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
32 #define SRTC_LPCR 0x10 /* LP Control Reg */
33 #define SRTC_LPSR 0x14 /* LP Status Reg */
34 #define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */
35
36 /* max. number of retries to read registers, 120 was max during test */
37 #define REG_READ_TIMEOUT 2000
38
39 struct mxc_rtc_data {
40 struct rtc_device *rtc;
41 void __iomem *ioaddr;
42 struct clk *clk;
43 spinlock_t lock; /* protects register access */
44 int irq;
45 };
46
47 /*
48 * This function does write synchronization for writes to the lp srtc block.
49 * To take care of the asynchronous CKIL clock, all writes from the IP domain
50 * will be synchronized to the CKIL domain.
51 * The caller should hold the pdata->lock
52 */
mxc_rtc_sync_lp_locked(struct device * dev,void __iomem * ioaddr)53 static void mxc_rtc_sync_lp_locked(struct device *dev, void __iomem *ioaddr)
54 {
55 unsigned int i;
56
57 /* Wait for 3 CKIL cycles */
58 for (i = 0; i < 3; i++) {
59 const u32 count = readl(ioaddr + SRTC_LPSCLR);
60 unsigned int timeout = REG_READ_TIMEOUT;
61
62 while ((readl(ioaddr + SRTC_LPSCLR)) == count) {
63 if (!--timeout) {
64 dev_err_once(dev, "SRTC_LPSCLR stuck! Check your hw.\n");
65 return;
66 }
67 }
68 }
69 }
70
71 /* This function is the RTC interrupt service routine. */
mxc_rtc_interrupt(int irq,void * dev_id)72 static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
73 {
74 struct device *dev = dev_id;
75 struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
76 void __iomem *ioaddr = pdata->ioaddr;
77 u32 lp_status;
78 u32 lp_cr;
79
80 spin_lock(&pdata->lock);
81 if (clk_enable(pdata->clk)) {
82 spin_unlock(&pdata->lock);
83 return IRQ_NONE;
84 }
85
86 lp_status = readl(ioaddr + SRTC_LPSR);
87 lp_cr = readl(ioaddr + SRTC_LPCR);
88
89 /* update irq data & counter */
90 if (lp_status & SRTC_LPSR_ALP) {
91 if (lp_cr & SRTC_LPCR_ALP)
92 rtc_update_irq(pdata->rtc, 1, RTC_AF | RTC_IRQF);
93
94 /* disable further lp alarm interrupts */
95 lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
96 }
97
98 /* Update interrupt enables */
99 writel(lp_cr, ioaddr + SRTC_LPCR);
100
101 /* clear interrupt status */
102 writel(lp_status, ioaddr + SRTC_LPSR);
103
104 mxc_rtc_sync_lp_locked(dev, ioaddr);
105 clk_disable(pdata->clk);
106 spin_unlock(&pdata->lock);
107 return IRQ_HANDLED;
108 }
109
110 /*
111 * Enable clk and aquire spinlock
112 * @return 0 if successful; non-zero otherwise.
113 */
mxc_rtc_lock(struct mxc_rtc_data * const pdata)114 static int mxc_rtc_lock(struct mxc_rtc_data *const pdata)
115 {
116 int ret;
117
118 spin_lock_irq(&pdata->lock);
119 ret = clk_enable(pdata->clk);
120 if (ret) {
121 spin_unlock_irq(&pdata->lock);
122 return ret;
123 }
124 return 0;
125 }
126
mxc_rtc_unlock(struct mxc_rtc_data * const pdata)127 static int mxc_rtc_unlock(struct mxc_rtc_data *const pdata)
128 {
129 clk_disable(pdata->clk);
130 spin_unlock_irq(&pdata->lock);
131 return 0;
132 }
133
134 /*
135 * This function reads the current RTC time into tm in Gregorian date.
136 *
137 * @param tm contains the RTC time value upon return
138 *
139 * @return 0 if successful; non-zero otherwise.
140 */
mxc_rtc_read_time(struct device * dev,struct rtc_time * tm)141 static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
142 {
143 struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
144 const int clk_failed = clk_enable(pdata->clk);
145
146 if (!clk_failed) {
147 const time64_t now = readl(pdata->ioaddr + SRTC_LPSCMR);
148
149 rtc_time64_to_tm(now, tm);
150 clk_disable(pdata->clk);
151 return 0;
152 }
153 return clk_failed;
154 }
155
156 /*
157 * This function sets the internal RTC time based on tm in Gregorian date.
158 *
159 * @param tm the time value to be set in the RTC
160 *
161 * @return 0 if successful; non-zero otherwise.
162 */
mxc_rtc_set_time(struct device * dev,struct rtc_time * tm)163 static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
164 {
165 struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
166 time64_t time = rtc_tm_to_time64(tm);
167 int ret;
168
169 ret = mxc_rtc_lock(pdata);
170 if (ret)
171 return ret;
172
173 writel(time, pdata->ioaddr + SRTC_LPSCMR);
174 mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
175 return mxc_rtc_unlock(pdata);
176 }
177
178 /*
179 * This function reads the current alarm value into the passed in \b alrm
180 * argument. It updates the \b alrm's pending field value based on the whether
181 * an alarm interrupt occurs or not.
182 *
183 * @param alrm contains the RTC alarm value upon return
184 *
185 * @return 0 if successful; non-zero otherwise.
186 */
mxc_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)187 static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
188 {
189 struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
190 void __iomem *ioaddr = pdata->ioaddr;
191 int ret;
192
193 ret = mxc_rtc_lock(pdata);
194 if (ret)
195 return ret;
196
197 rtc_time64_to_tm(readl(ioaddr + SRTC_LPSAR), &alrm->time);
198 alrm->pending = !!(readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_ALP);
199 return mxc_rtc_unlock(pdata);
200 }
201
202 /*
203 * Enable/Disable alarm interrupt
204 * The caller should hold the pdata->lock
205 */
mxc_rtc_alarm_irq_enable_locked(struct mxc_rtc_data * pdata,unsigned int enable)206 static void mxc_rtc_alarm_irq_enable_locked(struct mxc_rtc_data *pdata,
207 unsigned int enable)
208 {
209 u32 lp_cr = readl(pdata->ioaddr + SRTC_LPCR);
210
211 if (enable)
212 lp_cr |= (SRTC_LPCR_ALP | SRTC_LPCR_WAE);
213 else
214 lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
215
216 writel(lp_cr, pdata->ioaddr + SRTC_LPCR);
217 }
218
mxc_rtc_alarm_irq_enable(struct device * dev,unsigned int enable)219 static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
220 {
221 struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
222 int ret = mxc_rtc_lock(pdata);
223
224 if (ret)
225 return ret;
226
227 mxc_rtc_alarm_irq_enable_locked(pdata, enable);
228 return mxc_rtc_unlock(pdata);
229 }
230
231 /*
232 * This function sets the RTC alarm based on passed in alrm.
233 *
234 * @param alrm the alarm value to be set in the RTC
235 *
236 * @return 0 if successful; non-zero otherwise.
237 */
mxc_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)238 static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
239 {
240 const time64_t time = rtc_tm_to_time64(&alrm->time);
241 struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
242 int ret = mxc_rtc_lock(pdata);
243
244 if (ret)
245 return ret;
246
247 writel((u32)time, pdata->ioaddr + SRTC_LPSAR);
248
249 /* clear alarm interrupt status bit */
250 writel(SRTC_LPSR_ALP, pdata->ioaddr + SRTC_LPSR);
251 mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
252
253 mxc_rtc_alarm_irq_enable_locked(pdata, alrm->enabled);
254 mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
255 mxc_rtc_unlock(pdata);
256 return ret;
257 }
258
259 static const struct rtc_class_ops mxc_rtc_ops = {
260 .read_time = mxc_rtc_read_time,
261 .set_time = mxc_rtc_set_time,
262 .read_alarm = mxc_rtc_read_alarm,
263 .set_alarm = mxc_rtc_set_alarm,
264 .alarm_irq_enable = mxc_rtc_alarm_irq_enable,
265 };
266
mxc_rtc_wait_for_flag(void __iomem * ioaddr,int flag)267 static int mxc_rtc_wait_for_flag(void __iomem *ioaddr, int flag)
268 {
269 unsigned int timeout = REG_READ_TIMEOUT;
270
271 while (!(readl(ioaddr) & flag)) {
272 if (!--timeout)
273 return -EBUSY;
274 }
275 return 0;
276 }
277
mxc_rtc_probe(struct platform_device * pdev)278 static int mxc_rtc_probe(struct platform_device *pdev)
279 {
280 struct mxc_rtc_data *pdata;
281 void __iomem *ioaddr;
282 int ret = 0;
283
284 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
285 if (!pdata)
286 return -ENOMEM;
287
288 pdata->ioaddr = devm_platform_ioremap_resource(pdev, 0);
289 if (IS_ERR(pdata->ioaddr))
290 return PTR_ERR(pdata->ioaddr);
291
292 ioaddr = pdata->ioaddr;
293
294 pdata->clk = devm_clk_get(&pdev->dev, NULL);
295 if (IS_ERR(pdata->clk)) {
296 dev_err(&pdev->dev, "unable to get rtc clock!\n");
297 return PTR_ERR(pdata->clk);
298 }
299
300 spin_lock_init(&pdata->lock);
301 pdata->irq = platform_get_irq(pdev, 0);
302 if (pdata->irq < 0)
303 return pdata->irq;
304
305 device_init_wakeup(&pdev->dev, 1);
306 ret = dev_pm_set_wake_irq(&pdev->dev, pdata->irq);
307 if (ret)
308 dev_err(&pdev->dev, "failed to enable irq wake\n");
309
310 ret = clk_prepare_enable(pdata->clk);
311 if (ret)
312 return ret;
313 /* initialize glitch detect */
314 writel(SRTC_LPPDR_INIT, ioaddr + SRTC_LPPDR);
315
316 /* clear lp interrupt status */
317 writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
318
319 /* move out of init state */
320 writel((SRTC_LPCR_IE | SRTC_LPCR_NSA), ioaddr + SRTC_LPCR);
321 ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_IES);
322 if (ret) {
323 dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_IES\n");
324 clk_disable_unprepare(pdata->clk);
325 return ret;
326 }
327
328 /* move out of non-valid state */
329 writel((SRTC_LPCR_IE | SRTC_LPCR_NVE | SRTC_LPCR_NSA |
330 SRTC_LPCR_EN_LP), ioaddr + SRTC_LPCR);
331 ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_NVES);
332 if (ret) {
333 dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_NVES\n");
334 clk_disable_unprepare(pdata->clk);
335 return ret;
336 }
337
338 pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
339 if (IS_ERR(pdata->rtc)) {
340 clk_disable_unprepare(pdata->clk);
341 return PTR_ERR(pdata->rtc);
342 }
343
344 pdata->rtc->ops = &mxc_rtc_ops;
345 pdata->rtc->range_max = U32_MAX;
346
347 clk_disable(pdata->clk);
348 platform_set_drvdata(pdev, pdata);
349 ret =
350 devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt, 0,
351 pdev->name, &pdev->dev);
352 if (ret < 0) {
353 dev_err(&pdev->dev, "interrupt not available.\n");
354 clk_unprepare(pdata->clk);
355 return ret;
356 }
357
358 ret = devm_rtc_register_device(pdata->rtc);
359 if (ret < 0)
360 clk_unprepare(pdata->clk);
361
362 return ret;
363 }
364
mxc_rtc_remove(struct platform_device * pdev)365 static void mxc_rtc_remove(struct platform_device *pdev)
366 {
367 struct mxc_rtc_data *pdata = platform_get_drvdata(pdev);
368
369 clk_disable_unprepare(pdata->clk);
370 }
371
372 static const struct of_device_id mxc_ids[] = {
373 { .compatible = "fsl,imx53-rtc", },
374 {}
375 };
376 MODULE_DEVICE_TABLE(of, mxc_ids);
377
378 static struct platform_driver mxc_rtc_driver = {
379 .driver = {
380 .name = "mxc_rtc_v2",
381 .of_match_table = mxc_ids,
382 },
383 .probe = mxc_rtc_probe,
384 .remove_new = mxc_rtc_remove,
385 };
386
387 module_platform_driver(mxc_rtc_driver);
388
389 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
390 MODULE_DESCRIPTION("Real Time Clock (RTC) Driver for i.MX53");
391 MODULE_LICENSE("GPL");
392
