1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 1999 - 2010 Intel Corporation.
4 * Copyright (C) 2010 LAPIS SEMICONDUCTOR CO., LTD.
5 */
6
7 #include <linux/interrupt.h>
8 #include <linux/delay.h>
9 #include <linux/ethtool.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/sched.h>
13 #include <linux/pci.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/errno.h>
17 #include <linux/netdevice.h>
18 #include <linux/skbuff.h>
19 #include <linux/can.h>
20 #include <linux/can/dev.h>
21 #include <linux/can/error.h>
22
23 #define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */
24 #define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */
25 #define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1))
26 #define PCH_CTRL_CCE BIT(6)
27 #define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */
28 #define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */
29 #define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */
30
31 #define PCH_CMASK_RX_TX_SET 0x00f3
32 #define PCH_CMASK_RX_TX_GET 0x0073
33 #define PCH_CMASK_ALL 0xff
34 #define PCH_CMASK_NEWDAT BIT(2)
35 #define PCH_CMASK_CLRINTPND BIT(3)
36 #define PCH_CMASK_CTRL BIT(4)
37 #define PCH_CMASK_ARB BIT(5)
38 #define PCH_CMASK_MASK BIT(6)
39 #define PCH_CMASK_RDWR BIT(7)
40 #define PCH_IF_MCONT_NEWDAT BIT(15)
41 #define PCH_IF_MCONT_MSGLOST BIT(14)
42 #define PCH_IF_MCONT_INTPND BIT(13)
43 #define PCH_IF_MCONT_UMASK BIT(12)
44 #define PCH_IF_MCONT_TXIE BIT(11)
45 #define PCH_IF_MCONT_RXIE BIT(10)
46 #define PCH_IF_MCONT_RMTEN BIT(9)
47 #define PCH_IF_MCONT_TXRQXT BIT(8)
48 #define PCH_IF_MCONT_EOB BIT(7)
49 #define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3))
50 #define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15))
51 #define PCH_ID2_DIR BIT(13)
52 #define PCH_ID2_XTD BIT(14)
53 #define PCH_ID_MSGVAL BIT(15)
54 #define PCH_IF_CREQ_BUSY BIT(15)
55
56 #define PCH_STATUS_INT 0x8000
57 #define PCH_RP 0x00008000
58 #define PCH_REC 0x00007f00
59 #define PCH_TEC 0x000000ff
60
61 #define PCH_TX_OK BIT(3)
62 #define PCH_RX_OK BIT(4)
63 #define PCH_EPASSIV BIT(5)
64 #define PCH_EWARN BIT(6)
65 #define PCH_BUS_OFF BIT(7)
66
67 /* bit position of certain controller bits. */
68 #define PCH_BIT_BRP_SHIFT 0
69 #define PCH_BIT_SJW_SHIFT 6
70 #define PCH_BIT_TSEG1_SHIFT 8
71 #define PCH_BIT_TSEG2_SHIFT 12
72 #define PCH_BIT_BRPE_BRPE_SHIFT 6
73
74 #define PCH_MSK_BITT_BRP 0x3f
75 #define PCH_MSK_BRPE_BRPE 0x3c0
76 #define PCH_MSK_CTRL_IE_SIE_EIE 0x07
77 #define PCH_COUNTER_LIMIT 10
78
79 #define PCH_CAN_CLK 50000000 /* 50MHz */
80
81 /*
82 * Define the number of message object.
83 * PCH CAN communications are done via Message RAM.
84 * The Message RAM consists of 32 message objects.
85 */
86 #define PCH_RX_OBJ_NUM 26
87 #define PCH_TX_OBJ_NUM 6
88 #define PCH_RX_OBJ_START 1
89 #define PCH_RX_OBJ_END PCH_RX_OBJ_NUM
90 #define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1)
91 #define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM)
92
93 #define PCH_FIFO_THRESH 16
94
95 /* TxRqst2 show status of MsgObjNo.17~32 */
96 #define PCH_TREQ2_TX_MASK (((1 << PCH_TX_OBJ_NUM) - 1) <<\
97 (PCH_RX_OBJ_END - 16))
98
99 enum pch_ifreg {
100 PCH_RX_IFREG,
101 PCH_TX_IFREG,
102 };
103
104 enum pch_can_err {
105 PCH_STUF_ERR = 1,
106 PCH_FORM_ERR,
107 PCH_ACK_ERR,
108 PCH_BIT1_ERR,
109 PCH_BIT0_ERR,
110 PCH_CRC_ERR,
111 PCH_LEC_ALL,
112 };
113
114 enum pch_can_mode {
115 PCH_CAN_ENABLE,
116 PCH_CAN_DISABLE,
117 PCH_CAN_ALL,
118 PCH_CAN_NONE,
119 PCH_CAN_STOP,
120 PCH_CAN_RUN,
121 };
122
123 struct pch_can_if_regs {
124 u32 creq;
125 u32 cmask;
126 u32 mask1;
127 u32 mask2;
128 u32 id1;
129 u32 id2;
130 u32 mcont;
131 u32 data[4];
132 u32 rsv[13];
133 };
134
135 struct pch_can_regs {
136 u32 cont;
137 u32 stat;
138 u32 errc;
139 u32 bitt;
140 u32 intr;
141 u32 opt;
142 u32 brpe;
143 u32 reserve;
144 struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */
145 u32 reserve1[8];
146 u32 treq1;
147 u32 treq2;
148 u32 reserve2[6];
149 u32 data1;
150 u32 data2;
151 u32 reserve3[6];
152 u32 canipend1;
153 u32 canipend2;
154 u32 reserve4[6];
155 u32 canmval1;
156 u32 canmval2;
157 u32 reserve5[37];
158 u32 srst;
159 };
160
161 struct pch_can_priv {
162 struct can_priv can;
163 struct pci_dev *dev;
164 u32 tx_enable[PCH_TX_OBJ_END];
165 u32 rx_enable[PCH_TX_OBJ_END];
166 u32 rx_link[PCH_TX_OBJ_END];
167 u32 int_enables;
168 struct net_device *ndev;
169 struct pch_can_regs __iomem *regs;
170 struct napi_struct napi;
171 int tx_obj; /* Point next Tx Obj index */
172 int use_msi;
173 };
174
175 static const struct can_bittiming_const pch_can_bittiming_const = {
176 .name = KBUILD_MODNAME,
177 .tseg1_min = 2,
178 .tseg1_max = 16,
179 .tseg2_min = 1,
180 .tseg2_max = 8,
181 .sjw_max = 4,
182 .brp_min = 1,
183 .brp_max = 1024, /* 6bit + extended 4bit */
184 .brp_inc = 1,
185 };
186
187 static const struct pci_device_id pch_pci_tbl[] = {
188 {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,},
189 {0,}
190 };
191 MODULE_DEVICE_TABLE(pci, pch_pci_tbl);
192
pch_can_bit_set(void __iomem * addr,u32 mask)193 static inline void pch_can_bit_set(void __iomem *addr, u32 mask)
194 {
195 iowrite32(ioread32(addr) | mask, addr);
196 }
197
pch_can_bit_clear(void __iomem * addr,u32 mask)198 static inline void pch_can_bit_clear(void __iomem *addr, u32 mask)
199 {
200 iowrite32(ioread32(addr) & ~mask, addr);
201 }
202
pch_can_set_run_mode(struct pch_can_priv * priv,enum pch_can_mode mode)203 static void pch_can_set_run_mode(struct pch_can_priv *priv,
204 enum pch_can_mode mode)
205 {
206 switch (mode) {
207 case PCH_CAN_RUN:
208 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT);
209 break;
210
211 case PCH_CAN_STOP:
212 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT);
213 break;
214
215 default:
216 netdev_err(priv->ndev, "%s -> Invalid Mode.\n", __func__);
217 break;
218 }
219 }
220
pch_can_set_optmode(struct pch_can_priv * priv)221 static void pch_can_set_optmode(struct pch_can_priv *priv)
222 {
223 u32 reg_val = ioread32(&priv->regs->opt);
224
225 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
226 reg_val |= PCH_OPT_SILENT;
227
228 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
229 reg_val |= PCH_OPT_LBACK;
230
231 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT);
232 iowrite32(reg_val, &priv->regs->opt);
233 }
234
pch_can_rw_msg_obj(void __iomem * creq_addr,u32 num)235 static void pch_can_rw_msg_obj(void __iomem *creq_addr, u32 num)
236 {
237 int counter = PCH_COUNTER_LIMIT;
238 u32 ifx_creq;
239
240 iowrite32(num, creq_addr);
241 while (counter) {
242 ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
243 if (!ifx_creq)
244 break;
245 counter--;
246 udelay(1);
247 }
248 if (!counter)
249 pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
250 }
251
pch_can_set_int_enables(struct pch_can_priv * priv,enum pch_can_mode interrupt_no)252 static void pch_can_set_int_enables(struct pch_can_priv *priv,
253 enum pch_can_mode interrupt_no)
254 {
255 switch (interrupt_no) {
256 case PCH_CAN_DISABLE:
257 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
258 break;
259
260 case PCH_CAN_ALL:
261 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
262 break;
263
264 case PCH_CAN_NONE:
265 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
266 break;
267
268 default:
269 netdev_err(priv->ndev, "Invalid interrupt number.\n");
270 break;
271 }
272 }
273
pch_can_set_rxtx(struct pch_can_priv * priv,u32 buff_num,int set,enum pch_ifreg dir)274 static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
275 int set, enum pch_ifreg dir)
276 {
277 u32 ie;
278
279 if (dir)
280 ie = PCH_IF_MCONT_TXIE;
281 else
282 ie = PCH_IF_MCONT_RXIE;
283
284 /* Reading the Msg buffer from Message RAM to IF1/2 registers. */
285 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
286 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
287
288 /* Setting the IF1/2MASK1 register to access MsgVal and RxIE bits */
289 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
290 &priv->regs->ifregs[dir].cmask);
291
292 if (set) {
293 /* Setting the MsgVal and RxIE/TxIE bits */
294 pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie);
295 pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
296 } else {
297 /* Clearing the MsgVal and RxIE/TxIE bits */
298 pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie);
299 pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
300 }
301
302 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
303 }
304
pch_can_set_rx_all(struct pch_can_priv * priv,int set)305 static void pch_can_set_rx_all(struct pch_can_priv *priv, int set)
306 {
307 int i;
308
309 /* Traversing to obtain the object configured as receivers. */
310 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++)
311 pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG);
312 }
313
pch_can_set_tx_all(struct pch_can_priv * priv,int set)314 static void pch_can_set_tx_all(struct pch_can_priv *priv, int set)
315 {
316 int i;
317
318 /* Traversing to obtain the object configured as transmit object. */
319 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
320 pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG);
321 }
322
pch_can_int_pending(struct pch_can_priv * priv)323 static u32 pch_can_int_pending(struct pch_can_priv *priv)
324 {
325 return ioread32(&priv->regs->intr) & 0xffff;
326 }
327
pch_can_clear_if_buffers(struct pch_can_priv * priv)328 static void pch_can_clear_if_buffers(struct pch_can_priv *priv)
329 {
330 int i; /* Msg Obj ID (1~32) */
331
332 for (i = PCH_RX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
333 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask);
334 iowrite32(0xffff, &priv->regs->ifregs[0].mask1);
335 iowrite32(0xffff, &priv->regs->ifregs[0].mask2);
336 iowrite32(0x0, &priv->regs->ifregs[0].id1);
337 iowrite32(0x0, &priv->regs->ifregs[0].id2);
338 iowrite32(0x0, &priv->regs->ifregs[0].mcont);
339 iowrite32(0x0, &priv->regs->ifregs[0].data[0]);
340 iowrite32(0x0, &priv->regs->ifregs[0].data[1]);
341 iowrite32(0x0, &priv->regs->ifregs[0].data[2]);
342 iowrite32(0x0, &priv->regs->ifregs[0].data[3]);
343 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
344 PCH_CMASK_ARB | PCH_CMASK_CTRL,
345 &priv->regs->ifregs[0].cmask);
346 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
347 }
348 }
349
pch_can_config_rx_tx_buffers(struct pch_can_priv * priv)350 static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
351 {
352 int i;
353
354 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
355 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
356 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
357
358 iowrite32(0x0, &priv->regs->ifregs[0].id1);
359 iowrite32(0x0, &priv->regs->ifregs[0].id2);
360
361 pch_can_bit_set(&priv->regs->ifregs[0].mcont,
362 PCH_IF_MCONT_UMASK);
363
364 /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
365 if (i == PCH_RX_OBJ_END)
366 pch_can_bit_set(&priv->regs->ifregs[0].mcont,
367 PCH_IF_MCONT_EOB);
368 else
369 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
370 PCH_IF_MCONT_EOB);
371
372 iowrite32(0, &priv->regs->ifregs[0].mask1);
373 pch_can_bit_clear(&priv->regs->ifregs[0].mask2,
374 0x1fff | PCH_MASK2_MDIR_MXTD);
375
376 /* Setting CMASK for writing */
377 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
378 PCH_CMASK_CTRL, &priv->regs->ifregs[0].cmask);
379
380 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
381 }
382
383 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
384 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
385 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
386
387 /* Resetting DIR bit for reception */
388 iowrite32(0x0, &priv->regs->ifregs[1].id1);
389 iowrite32(PCH_ID2_DIR, &priv->regs->ifregs[1].id2);
390
391 /* Setting EOB bit for transmitter */
392 iowrite32(PCH_IF_MCONT_EOB | PCH_IF_MCONT_UMASK,
393 &priv->regs->ifregs[1].mcont);
394
395 iowrite32(0, &priv->regs->ifregs[1].mask1);
396 pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff);
397
398 /* Setting CMASK for writing */
399 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
400 PCH_CMASK_CTRL, &priv->regs->ifregs[1].cmask);
401
402 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
403 }
404 }
405
pch_can_init(struct pch_can_priv * priv)406 static void pch_can_init(struct pch_can_priv *priv)
407 {
408 /* Stopping the Can device. */
409 pch_can_set_run_mode(priv, PCH_CAN_STOP);
410
411 /* Clearing all the message object buffers. */
412 pch_can_clear_if_buffers(priv);
413
414 /* Configuring the respective message object as either rx/tx object. */
415 pch_can_config_rx_tx_buffers(priv);
416
417 /* Enabling the interrupts. */
418 pch_can_set_int_enables(priv, PCH_CAN_ALL);
419 }
420
pch_can_release(struct pch_can_priv * priv)421 static void pch_can_release(struct pch_can_priv *priv)
422 {
423 /* Stooping the CAN device. */
424 pch_can_set_run_mode(priv, PCH_CAN_STOP);
425
426 /* Disabling the interrupts. */
427 pch_can_set_int_enables(priv, PCH_CAN_NONE);
428
429 /* Disabling all the receive object. */
430 pch_can_set_rx_all(priv, 0);
431
432 /* Disabling all the transmit object. */
433 pch_can_set_tx_all(priv, 0);
434 }
435
436 /* This function clears interrupt(s) from the CAN device. */
pch_can_int_clr(struct pch_can_priv * priv,u32 mask)437 static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
438 {
439 /* Clear interrupt for transmit object */
440 if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) {
441 /* Setting CMASK for clearing the reception interrupts. */
442 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
443 &priv->regs->ifregs[0].cmask);
444
445 /* Clearing the Dir bit. */
446 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
447
448 /* Clearing NewDat & IntPnd */
449 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
450 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
451
452 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask);
453 } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) {
454 /*
455 * Setting CMASK for clearing interrupts for frame transmission.
456 */
457 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
458 &priv->regs->ifregs[1].cmask);
459
460 /* Resetting the ID registers. */
461 pch_can_bit_set(&priv->regs->ifregs[1].id2,
462 PCH_ID2_DIR | (0x7ff << 2));
463 iowrite32(0x0, &priv->regs->ifregs[1].id1);
464
465 /* Clearing NewDat, TxRqst & IntPnd */
466 pch_can_bit_clear(&priv->regs->ifregs[1].mcont,
467 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
468 PCH_IF_MCONT_TXRQXT);
469 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, mask);
470 }
471 }
472
pch_can_reset(struct pch_can_priv * priv)473 static void pch_can_reset(struct pch_can_priv *priv)
474 {
475 /* write to sw reset register */
476 iowrite32(1, &priv->regs->srst);
477 iowrite32(0, &priv->regs->srst);
478 }
479
pch_can_error(struct net_device * ndev,u32 status)480 static void pch_can_error(struct net_device *ndev, u32 status)
481 {
482 struct sk_buff *skb;
483 struct pch_can_priv *priv = netdev_priv(ndev);
484 struct can_frame *cf;
485 u32 errc, lec;
486 struct net_device_stats *stats = &(priv->ndev->stats);
487 enum can_state state = priv->can.state;
488
489 skb = alloc_can_err_skb(ndev, &cf);
490 if (!skb)
491 return;
492
493 errc = ioread32(&priv->regs->errc);
494 if (status & PCH_BUS_OFF) {
495 pch_can_set_tx_all(priv, 0);
496 pch_can_set_rx_all(priv, 0);
497 state = CAN_STATE_BUS_OFF;
498 cf->can_id |= CAN_ERR_BUSOFF;
499 priv->can.can_stats.bus_off++;
500 can_bus_off(ndev);
501 } else {
502 cf->can_id |= CAN_ERR_CNT;
503 cf->data[6] = errc & PCH_TEC;
504 cf->data[7] = (errc & PCH_REC) >> 8;
505 }
506
507 /* Warning interrupt. */
508 if (status & PCH_EWARN) {
509 state = CAN_STATE_ERROR_WARNING;
510 priv->can.can_stats.error_warning++;
511 cf->can_id |= CAN_ERR_CRTL;
512 if (((errc & PCH_REC) >> 8) > 96)
513 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
514 if ((errc & PCH_TEC) > 96)
515 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
516 netdev_dbg(ndev,
517 "%s -> Error Counter is more than 96.\n", __func__);
518 }
519 /* Error passive interrupt. */
520 if (status & PCH_EPASSIV) {
521 priv->can.can_stats.error_passive++;
522 state = CAN_STATE_ERROR_PASSIVE;
523 cf->can_id |= CAN_ERR_CRTL;
524 if (errc & PCH_RP)
525 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
526 if ((errc & PCH_TEC) > 127)
527 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
528 netdev_dbg(ndev,
529 "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
530 }
531
532 lec = status & PCH_LEC_ALL;
533 switch (lec) {
534 case PCH_STUF_ERR:
535 cf->data[2] |= CAN_ERR_PROT_STUFF;
536 priv->can.can_stats.bus_error++;
537 stats->rx_errors++;
538 break;
539 case PCH_FORM_ERR:
540 cf->data[2] |= CAN_ERR_PROT_FORM;
541 priv->can.can_stats.bus_error++;
542 stats->rx_errors++;
543 break;
544 case PCH_ACK_ERR:
545 cf->can_id |= CAN_ERR_ACK;
546 priv->can.can_stats.bus_error++;
547 stats->rx_errors++;
548 break;
549 case PCH_BIT1_ERR:
550 case PCH_BIT0_ERR:
551 cf->data[2] |= CAN_ERR_PROT_BIT;
552 priv->can.can_stats.bus_error++;
553 stats->rx_errors++;
554 break;
555 case PCH_CRC_ERR:
556 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
557 priv->can.can_stats.bus_error++;
558 stats->rx_errors++;
559 break;
560 case PCH_LEC_ALL: /* Written by CPU. No error status */
561 break;
562 }
563
564 priv->can.state = state;
565 netif_receive_skb(skb);
566 }
567
pch_can_interrupt(int irq,void * dev_id)568 static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
569 {
570 struct net_device *ndev = (struct net_device *)dev_id;
571 struct pch_can_priv *priv = netdev_priv(ndev);
572
573 if (!pch_can_int_pending(priv))
574 return IRQ_NONE;
575
576 pch_can_set_int_enables(priv, PCH_CAN_NONE);
577 napi_schedule(&priv->napi);
578 return IRQ_HANDLED;
579 }
580
pch_fifo_thresh(struct pch_can_priv * priv,int obj_id)581 static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
582 {
583 if (obj_id < PCH_FIFO_THRESH) {
584 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
585 PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask);
586
587 /* Clearing the Dir bit. */
588 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
589
590 /* Clearing NewDat & IntPnd */
591 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
592 PCH_IF_MCONT_INTPND);
593 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
594 } else if (obj_id > PCH_FIFO_THRESH) {
595 pch_can_int_clr(priv, obj_id);
596 } else if (obj_id == PCH_FIFO_THRESH) {
597 int cnt;
598 for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
599 pch_can_int_clr(priv, cnt + 1);
600 }
601 }
602
pch_can_rx_msg_lost(struct net_device * ndev,int obj_id)603 static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
604 {
605 struct pch_can_priv *priv = netdev_priv(ndev);
606 struct net_device_stats *stats = &(priv->ndev->stats);
607 struct sk_buff *skb;
608 struct can_frame *cf;
609
610 netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n");
611 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
612 PCH_IF_MCONT_MSGLOST);
613 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
614 &priv->regs->ifregs[0].cmask);
615 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
616
617 skb = alloc_can_err_skb(ndev, &cf);
618 if (!skb)
619 return;
620
621 cf->can_id |= CAN_ERR_CRTL;
622 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
623 stats->rx_over_errors++;
624 stats->rx_errors++;
625
626 netif_receive_skb(skb);
627 }
628
pch_can_rx_normal(struct net_device * ndev,u32 obj_num,int quota)629 static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
630 {
631 u32 reg;
632 canid_t id;
633 int rcv_pkts = 0;
634 struct sk_buff *skb;
635 struct can_frame *cf;
636 struct pch_can_priv *priv = netdev_priv(ndev);
637 struct net_device_stats *stats = &(priv->ndev->stats);
638 int i;
639 u32 id2;
640 u16 data_reg;
641
642 do {
643 /* Reading the message object from the Message RAM */
644 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
645 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_num);
646
647 /* Reading the MCONT register. */
648 reg = ioread32(&priv->regs->ifregs[0].mcont);
649
650 if (reg & PCH_IF_MCONT_EOB)
651 break;
652
653 /* If MsgLost bit set. */
654 if (reg & PCH_IF_MCONT_MSGLOST) {
655 pch_can_rx_msg_lost(ndev, obj_num);
656 rcv_pkts++;
657 quota--;
658 obj_num++;
659 continue;
660 } else if (!(reg & PCH_IF_MCONT_NEWDAT)) {
661 obj_num++;
662 continue;
663 }
664
665 skb = alloc_can_skb(priv->ndev, &cf);
666 if (!skb) {
667 netdev_err(ndev, "alloc_can_skb Failed\n");
668 return rcv_pkts;
669 }
670
671 /* Get Received data */
672 id2 = ioread32(&priv->regs->ifregs[0].id2);
673 if (id2 & PCH_ID2_XTD) {
674 id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff);
675 id |= (((id2) & 0x1fff) << 16);
676 cf->can_id = id | CAN_EFF_FLAG;
677 } else {
678 id = (id2 >> 2) & CAN_SFF_MASK;
679 cf->can_id = id;
680 }
681
682 cf->len = can_cc_dlc2len((ioread32(&priv->regs->
683 ifregs[0].mcont)) & 0xF);
684
685 if (id2 & PCH_ID2_DIR) {
686 cf->can_id |= CAN_RTR_FLAG;
687 } else {
688 for (i = 0; i < cf->len; i += 2) {
689 data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]);
690 cf->data[i] = data_reg;
691 cf->data[i + 1] = data_reg >> 8;
692 }
693
694 stats->rx_bytes += cf->len;
695 }
696 stats->rx_packets++;
697 rcv_pkts++;
698 quota--;
699 netif_receive_skb(skb);
700
701 pch_fifo_thresh(priv, obj_num);
702 obj_num++;
703 } while (quota > 0);
704
705 return rcv_pkts;
706 }
707
pch_can_tx_complete(struct net_device * ndev,u32 int_stat)708 static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
709 {
710 struct pch_can_priv *priv = netdev_priv(ndev);
711 struct net_device_stats *stats = &(priv->ndev->stats);
712
713 stats->tx_bytes += can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1,
714 NULL);
715 stats->tx_packets++;
716 iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
717 &priv->regs->ifregs[1].cmask);
718 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, int_stat);
719 if (int_stat == PCH_TX_OBJ_END)
720 netif_wake_queue(ndev);
721 }
722
pch_can_poll(struct napi_struct * napi,int quota)723 static int pch_can_poll(struct napi_struct *napi, int quota)
724 {
725 struct net_device *ndev = napi->dev;
726 struct pch_can_priv *priv = netdev_priv(ndev);
727 u32 int_stat;
728 u32 reg_stat;
729 int quota_save = quota;
730
731 int_stat = pch_can_int_pending(priv);
732 if (!int_stat)
733 goto end;
734
735 if (int_stat == PCH_STATUS_INT) {
736 reg_stat = ioread32(&priv->regs->stat);
737
738 if ((reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) &&
739 ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL)) {
740 pch_can_error(ndev, reg_stat);
741 quota--;
742 }
743
744 if (reg_stat & (PCH_TX_OK | PCH_RX_OK))
745 pch_can_bit_clear(&priv->regs->stat,
746 reg_stat & (PCH_TX_OK | PCH_RX_OK));
747
748 int_stat = pch_can_int_pending(priv);
749 }
750
751 if (quota == 0)
752 goto end;
753
754 if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) {
755 quota -= pch_can_rx_normal(ndev, int_stat, quota);
756 } else if ((int_stat >= PCH_TX_OBJ_START) &&
757 (int_stat <= PCH_TX_OBJ_END)) {
758 /* Handle transmission interrupt */
759 pch_can_tx_complete(ndev, int_stat);
760 }
761
762 end:
763 napi_complete(napi);
764 pch_can_set_int_enables(priv, PCH_CAN_ALL);
765
766 return quota_save - quota;
767 }
768
pch_set_bittiming(struct net_device * ndev)769 static int pch_set_bittiming(struct net_device *ndev)
770 {
771 struct pch_can_priv *priv = netdev_priv(ndev);
772 const struct can_bittiming *bt = &priv->can.bittiming;
773 u32 canbit;
774 u32 bepe;
775
776 /* Setting the CCE bit for accessing the Can Timing register. */
777 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE);
778
779 canbit = (bt->brp - 1) & PCH_MSK_BITT_BRP;
780 canbit |= (bt->sjw - 1) << PCH_BIT_SJW_SHIFT;
781 canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1_SHIFT;
782 canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2_SHIFT;
783 bepe = ((bt->brp - 1) & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE_SHIFT;
784 iowrite32(canbit, &priv->regs->bitt);
785 iowrite32(bepe, &priv->regs->brpe);
786 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
787
788 return 0;
789 }
790
pch_can_start(struct net_device * ndev)791 static void pch_can_start(struct net_device *ndev)
792 {
793 struct pch_can_priv *priv = netdev_priv(ndev);
794
795 if (priv->can.state != CAN_STATE_STOPPED)
796 pch_can_reset(priv);
797
798 pch_set_bittiming(ndev);
799 pch_can_set_optmode(priv);
800
801 pch_can_set_tx_all(priv, 1);
802 pch_can_set_rx_all(priv, 1);
803
804 /* Setting the CAN to run mode. */
805 pch_can_set_run_mode(priv, PCH_CAN_RUN);
806
807 priv->can.state = CAN_STATE_ERROR_ACTIVE;
808
809 return;
810 }
811
pch_can_do_set_mode(struct net_device * ndev,enum can_mode mode)812 static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
813 {
814 int ret = 0;
815
816 switch (mode) {
817 case CAN_MODE_START:
818 pch_can_start(ndev);
819 netif_wake_queue(ndev);
820 break;
821 default:
822 ret = -EOPNOTSUPP;
823 break;
824 }
825
826 return ret;
827 }
828
pch_can_open(struct net_device * ndev)829 static int pch_can_open(struct net_device *ndev)
830 {
831 struct pch_can_priv *priv = netdev_priv(ndev);
832 int retval;
833
834 /* Registering the interrupt. */
835 retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
836 ndev->name, ndev);
837 if (retval) {
838 netdev_err(ndev, "request_irq failed.\n");
839 goto req_irq_err;
840 }
841
842 /* Open common can device */
843 retval = open_candev(ndev);
844 if (retval) {
845 netdev_err(ndev, "open_candev() failed %d\n", retval);
846 goto err_open_candev;
847 }
848
849 pch_can_init(priv);
850 pch_can_start(ndev);
851 napi_enable(&priv->napi);
852 netif_start_queue(ndev);
853
854 return 0;
855
856 err_open_candev:
857 free_irq(priv->dev->irq, ndev);
858 req_irq_err:
859 pch_can_release(priv);
860
861 return retval;
862 }
863
pch_close(struct net_device * ndev)864 static int pch_close(struct net_device *ndev)
865 {
866 struct pch_can_priv *priv = netdev_priv(ndev);
867
868 netif_stop_queue(ndev);
869 napi_disable(&priv->napi);
870 pch_can_release(priv);
871 free_irq(priv->dev->irq, ndev);
872 close_candev(ndev);
873 priv->can.state = CAN_STATE_STOPPED;
874 return 0;
875 }
876
pch_xmit(struct sk_buff * skb,struct net_device * ndev)877 static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
878 {
879 struct pch_can_priv *priv = netdev_priv(ndev);
880 struct can_frame *cf = (struct can_frame *)skb->data;
881 int tx_obj_no;
882 int i;
883 u32 id2;
884
885 if (can_dev_dropped_skb(ndev, skb))
886 return NETDEV_TX_OK;
887
888 tx_obj_no = priv->tx_obj;
889 if (priv->tx_obj == PCH_TX_OBJ_END) {
890 if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK)
891 netif_stop_queue(ndev);
892
893 priv->tx_obj = PCH_TX_OBJ_START;
894 } else {
895 priv->tx_obj++;
896 }
897
898 /* Setting the CMASK register. */
899 pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL);
900
901 /* If ID extended is set. */
902 if (cf->can_id & CAN_EFF_FLAG) {
903 iowrite32(cf->can_id & 0xffff, &priv->regs->ifregs[1].id1);
904 id2 = ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD;
905 } else {
906 iowrite32(0, &priv->regs->ifregs[1].id1);
907 id2 = (cf->can_id & CAN_SFF_MASK) << 2;
908 }
909
910 id2 |= PCH_ID_MSGVAL;
911
912 /* If remote frame has to be transmitted.. */
913 if (!(cf->can_id & CAN_RTR_FLAG))
914 id2 |= PCH_ID2_DIR;
915
916 iowrite32(id2, &priv->regs->ifregs[1].id2);
917
918 /* Copy data to register */
919 for (i = 0; i < cf->len; i += 2) {
920 iowrite16(cf->data[i] | (cf->data[i + 1] << 8),
921 &priv->regs->ifregs[1].data[i / 2]);
922 }
923
924 can_put_echo_skb(skb, ndev, tx_obj_no - PCH_RX_OBJ_END - 1, 0);
925
926 /* Set the size of the data. Update if2_mcont */
927 iowrite32(cf->len | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT |
928 PCH_IF_MCONT_TXIE, &priv->regs->ifregs[1].mcont);
929
930 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no);
931
932 return NETDEV_TX_OK;
933 }
934
935 static const struct net_device_ops pch_can_netdev_ops = {
936 .ndo_open = pch_can_open,
937 .ndo_stop = pch_close,
938 .ndo_start_xmit = pch_xmit,
939 .ndo_change_mtu = can_change_mtu,
940 };
941
942 static const struct ethtool_ops pch_can_ethtool_ops = {
943 .get_ts_info = ethtool_op_get_ts_info,
944 };
945
pch_can_remove(struct pci_dev * pdev)946 static void pch_can_remove(struct pci_dev *pdev)
947 {
948 struct net_device *ndev = pci_get_drvdata(pdev);
949 struct pch_can_priv *priv = netdev_priv(ndev);
950
951 unregister_candev(priv->ndev);
952 if (priv->use_msi)
953 pci_disable_msi(priv->dev);
954 pci_release_regions(pdev);
955 pci_disable_device(pdev);
956 pch_can_reset(priv);
957 pci_iounmap(pdev, priv->regs);
958 free_candev(priv->ndev);
959 }
960
pch_can_set_int_custom(struct pch_can_priv * priv)961 static void __maybe_unused pch_can_set_int_custom(struct pch_can_priv *priv)
962 {
963 /* Clearing the IE, SIE and EIE bits of Can control register. */
964 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
965
966 /* Appropriately setting them. */
967 pch_can_bit_set(&priv->regs->cont,
968 ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
969 }
970
971 /* This function retrieves interrupt enabled for the CAN device. */
pch_can_get_int_enables(struct pch_can_priv * priv)972 static u32 __maybe_unused pch_can_get_int_enables(struct pch_can_priv *priv)
973 {
974 /* Obtaining the status of IE, SIE and EIE interrupt bits. */
975 return (ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1;
976 }
977
pch_can_get_rxtx_ir(struct pch_can_priv * priv,u32 buff_num,enum pch_ifreg dir)978 static u32 __maybe_unused pch_can_get_rxtx_ir(struct pch_can_priv *priv,
979 u32 buff_num, enum pch_ifreg dir)
980 {
981 u32 ie, enable;
982
983 if (dir)
984 ie = PCH_IF_MCONT_RXIE;
985 else
986 ie = PCH_IF_MCONT_TXIE;
987
988 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
989 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
990
991 if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
992 ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie))
993 enable = 1;
994 else
995 enable = 0;
996
997 return enable;
998 }
999
pch_can_set_rx_buffer_link(struct pch_can_priv * priv,u32 buffer_num,int set)1000 static void __maybe_unused pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
1001 u32 buffer_num, int set)
1002 {
1003 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
1004 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
1005 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
1006 &priv->regs->ifregs[0].cmask);
1007 if (set)
1008 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
1009 PCH_IF_MCONT_EOB);
1010 else
1011 pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
1012
1013 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
1014 }
1015
pch_can_get_rx_buffer_link(struct pch_can_priv * priv,u32 buffer_num)1016 static u32 __maybe_unused pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
1017 u32 buffer_num)
1018 {
1019 u32 link;
1020
1021 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
1022 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
1023
1024 if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
1025 link = 0;
1026 else
1027 link = 1;
1028 return link;
1029 }
1030
pch_can_get_buffer_status(struct pch_can_priv * priv)1031 static int __maybe_unused pch_can_get_buffer_status(struct pch_can_priv *priv)
1032 {
1033 return (ioread32(&priv->regs->treq1) & 0xffff) |
1034 (ioread32(&priv->regs->treq2) << 16);
1035 }
1036
pch_can_suspend(struct device * dev_d)1037 static int __maybe_unused pch_can_suspend(struct device *dev_d)
1038 {
1039 int i;
1040 u32 buf_stat; /* Variable for reading the transmit buffer status. */
1041 int counter = PCH_COUNTER_LIMIT;
1042
1043 struct net_device *dev = dev_get_drvdata(dev_d);
1044 struct pch_can_priv *priv = netdev_priv(dev);
1045
1046 /* Stop the CAN controller */
1047 pch_can_set_run_mode(priv, PCH_CAN_STOP);
1048
1049 /* Indicate that we are aboutto/in suspend */
1050 priv->can.state = CAN_STATE_STOPPED;
1051
1052 /* Waiting for all transmission to complete. */
1053 while (counter) {
1054 buf_stat = pch_can_get_buffer_status(priv);
1055 if (!buf_stat)
1056 break;
1057 counter--;
1058 udelay(1);
1059 }
1060 if (!counter)
1061 dev_err(dev_d, "%s -> Transmission time out.\n", __func__);
1062
1063 /* Save interrupt configuration and then disable them */
1064 priv->int_enables = pch_can_get_int_enables(priv);
1065 pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1066
1067 /* Save Tx buffer enable state */
1068 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
1069 priv->tx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i,
1070 PCH_TX_IFREG);
1071
1072 /* Disable all Transmit buffers */
1073 pch_can_set_tx_all(priv, 0);
1074
1075 /* Save Rx buffer enable state */
1076 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
1077 priv->rx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i,
1078 PCH_RX_IFREG);
1079 priv->rx_link[i - 1] = pch_can_get_rx_buffer_link(priv, i);
1080 }
1081
1082 /* Disable all Receive buffers */
1083 pch_can_set_rx_all(priv, 0);
1084
1085 return 0;
1086 }
1087
pch_can_resume(struct device * dev_d)1088 static int __maybe_unused pch_can_resume(struct device *dev_d)
1089 {
1090 int i;
1091 struct net_device *dev = dev_get_drvdata(dev_d);
1092 struct pch_can_priv *priv = netdev_priv(dev);
1093
1094 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1095
1096 /* Disabling all interrupts. */
1097 pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1098
1099 /* Setting the CAN device in Stop Mode. */
1100 pch_can_set_run_mode(priv, PCH_CAN_STOP);
1101
1102 /* Configuring the transmit and receive buffers. */
1103 pch_can_config_rx_tx_buffers(priv);
1104
1105 /* Restore the CAN state */
1106 pch_set_bittiming(dev);
1107
1108 /* Listen/Active */
1109 pch_can_set_optmode(priv);
1110
1111 /* Enabling the transmit buffer. */
1112 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
1113 pch_can_set_rxtx(priv, i, priv->tx_enable[i - 1], PCH_TX_IFREG);
1114
1115 /* Configuring the receive buffer and enabling them. */
1116 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
1117 /* Restore buffer link */
1118 pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i - 1]);
1119
1120 /* Restore buffer enables */
1121 pch_can_set_rxtx(priv, i, priv->rx_enable[i - 1], PCH_RX_IFREG);
1122 }
1123
1124 /* Enable CAN Interrupts */
1125 pch_can_set_int_custom(priv);
1126
1127 /* Restore Run Mode */
1128 pch_can_set_run_mode(priv, PCH_CAN_RUN);
1129
1130 return 0;
1131 }
1132
pch_can_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)1133 static int pch_can_get_berr_counter(const struct net_device *dev,
1134 struct can_berr_counter *bec)
1135 {
1136 struct pch_can_priv *priv = netdev_priv(dev);
1137 u32 errc = ioread32(&priv->regs->errc);
1138
1139 bec->txerr = errc & PCH_TEC;
1140 bec->rxerr = (errc & PCH_REC) >> 8;
1141
1142 return 0;
1143 }
1144
pch_can_probe(struct pci_dev * pdev,const struct pci_device_id * id)1145 static int pch_can_probe(struct pci_dev *pdev,
1146 const struct pci_device_id *id)
1147 {
1148 struct net_device *ndev;
1149 struct pch_can_priv *priv;
1150 int rc;
1151 void __iomem *addr;
1152
1153 rc = pci_enable_device(pdev);
1154 if (rc) {
1155 dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc);
1156 goto probe_exit_endev;
1157 }
1158
1159 rc = pci_request_regions(pdev, KBUILD_MODNAME);
1160 if (rc) {
1161 dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc);
1162 goto probe_exit_pcireq;
1163 }
1164
1165 addr = pci_iomap(pdev, 1, 0);
1166 if (!addr) {
1167 rc = -EIO;
1168 dev_err(&pdev->dev, "Failed pci_iomap\n");
1169 goto probe_exit_ipmap;
1170 }
1171
1172 ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END);
1173 if (!ndev) {
1174 rc = -ENOMEM;
1175 dev_err(&pdev->dev, "Failed alloc_candev\n");
1176 goto probe_exit_alloc_candev;
1177 }
1178
1179 priv = netdev_priv(ndev);
1180 priv->ndev = ndev;
1181 priv->regs = addr;
1182 priv->dev = pdev;
1183 priv->can.bittiming_const = &pch_can_bittiming_const;
1184 priv->can.do_set_mode = pch_can_do_set_mode;
1185 priv->can.do_get_berr_counter = pch_can_get_berr_counter;
1186 priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
1187 CAN_CTRLMODE_LOOPBACK;
1188 priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */
1189
1190 ndev->irq = pdev->irq;
1191 ndev->flags |= IFF_ECHO;
1192
1193 pci_set_drvdata(pdev, ndev);
1194 SET_NETDEV_DEV(ndev, &pdev->dev);
1195 ndev->netdev_ops = &pch_can_netdev_ops;
1196 ndev->ethtool_ops = &pch_can_ethtool_ops;
1197 priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
1198
1199 netif_napi_add_weight(ndev, &priv->napi, pch_can_poll, PCH_RX_OBJ_END);
1200
1201 rc = pci_enable_msi(priv->dev);
1202 if (rc) {
1203 netdev_err(ndev, "PCH CAN opened without MSI\n");
1204 priv->use_msi = 0;
1205 } else {
1206 netdev_err(ndev, "PCH CAN opened with MSI\n");
1207 pci_set_master(pdev);
1208 priv->use_msi = 1;
1209 }
1210
1211 rc = register_candev(ndev);
1212 if (rc) {
1213 dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
1214 goto probe_exit_reg_candev;
1215 }
1216
1217 return 0;
1218
1219 probe_exit_reg_candev:
1220 if (priv->use_msi)
1221 pci_disable_msi(priv->dev);
1222 free_candev(ndev);
1223 probe_exit_alloc_candev:
1224 pci_iounmap(pdev, addr);
1225 probe_exit_ipmap:
1226 pci_release_regions(pdev);
1227 probe_exit_pcireq:
1228 pci_disable_device(pdev);
1229 probe_exit_endev:
1230 return rc;
1231 }
1232
1233 static SIMPLE_DEV_PM_OPS(pch_can_pm_ops,
1234 pch_can_suspend,
1235 pch_can_resume);
1236
1237 static struct pci_driver pch_can_pci_driver = {
1238 .name = "pch_can",
1239 .id_table = pch_pci_tbl,
1240 .probe = pch_can_probe,
1241 .remove = pch_can_remove,
1242 .driver.pm = &pch_can_pm_ops,
1243 };
1244
1245 module_pci_driver(pch_can_pci_driver);
1246
1247 MODULE_DESCRIPTION("Intel EG20T PCH CAN(Controller Area Network) Driver");
1248 MODULE_LICENSE("GPL v2");
1249 MODULE_VERSION("0.94");
1250
