1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * JZ47xx SoCs TCU clocks driver
4 * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/clockchips.h>
10 #include <linux/mfd/ingenic-tcu.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/regmap.h>
13 #include <linux/slab.h>
14 #include <linux/syscore_ops.h>
15
16 #include <dt-bindings/clock/ingenic,tcu.h>
17
18 /* 8 channels max + watchdog + OST */
19 #define TCU_CLK_COUNT 10
20
21 #undef pr_fmt
22 #define pr_fmt(fmt) "ingenic-tcu-clk: " fmt
23
24 enum tcu_clk_parent {
25 TCU_PARENT_PCLK,
26 TCU_PARENT_RTC,
27 TCU_PARENT_EXT,
28 };
29
30 struct ingenic_soc_info {
31 unsigned int num_channels;
32 bool has_ost;
33 bool has_tcu_clk;
34 bool allow_missing_tcu_clk;
35 };
36
37 struct ingenic_tcu_clk_info {
38 struct clk_init_data init_data;
39 u8 gate_bit;
40 u8 tcsr_reg;
41 };
42
43 struct ingenic_tcu_clk {
44 struct clk_hw hw;
45 unsigned int idx;
46 struct ingenic_tcu *tcu;
47 const struct ingenic_tcu_clk_info *info;
48 };
49
50 struct ingenic_tcu {
51 const struct ingenic_soc_info *soc_info;
52 struct regmap *map;
53 struct clk *clk;
54
55 struct clk_hw_onecell_data *clocks;
56 };
57
58 static struct ingenic_tcu *ingenic_tcu;
59
to_tcu_clk(struct clk_hw * hw)60 static inline struct ingenic_tcu_clk *to_tcu_clk(struct clk_hw *hw)
61 {
62 return container_of(hw, struct ingenic_tcu_clk, hw);
63 }
64
ingenic_tcu_enable(struct clk_hw * hw)65 static int ingenic_tcu_enable(struct clk_hw *hw)
66 {
67 struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
68 const struct ingenic_tcu_clk_info *info = tcu_clk->info;
69 struct ingenic_tcu *tcu = tcu_clk->tcu;
70
71 regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit));
72
73 return 0;
74 }
75
ingenic_tcu_disable(struct clk_hw * hw)76 static void ingenic_tcu_disable(struct clk_hw *hw)
77 {
78 struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
79 const struct ingenic_tcu_clk_info *info = tcu_clk->info;
80 struct ingenic_tcu *tcu = tcu_clk->tcu;
81
82 regmap_write(tcu->map, TCU_REG_TSSR, BIT(info->gate_bit));
83 }
84
ingenic_tcu_is_enabled(struct clk_hw * hw)85 static int ingenic_tcu_is_enabled(struct clk_hw *hw)
86 {
87 struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
88 const struct ingenic_tcu_clk_info *info = tcu_clk->info;
89 unsigned int value;
90
91 regmap_read(tcu_clk->tcu->map, TCU_REG_TSR, &value);
92
93 return !(value & BIT(info->gate_bit));
94 }
95
ingenic_tcu_enable_regs(struct clk_hw * hw)96 static bool ingenic_tcu_enable_regs(struct clk_hw *hw)
97 {
98 struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
99 const struct ingenic_tcu_clk_info *info = tcu_clk->info;
100 struct ingenic_tcu *tcu = tcu_clk->tcu;
101 bool enabled = false;
102
103 /*
104 * According to the programming manual, a timer channel's registers can
105 * only be accessed when the channel's stop bit is clear.
106 */
107 enabled = !!ingenic_tcu_is_enabled(hw);
108 regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit));
109
110 return enabled;
111 }
112
ingenic_tcu_disable_regs(struct clk_hw * hw)113 static void ingenic_tcu_disable_regs(struct clk_hw *hw)
114 {
115 struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
116 const struct ingenic_tcu_clk_info *info = tcu_clk->info;
117 struct ingenic_tcu *tcu = tcu_clk->tcu;
118
119 regmap_write(tcu->map, TCU_REG_TSSR, BIT(info->gate_bit));
120 }
121
ingenic_tcu_get_parent(struct clk_hw * hw)122 static u8 ingenic_tcu_get_parent(struct clk_hw *hw)
123 {
124 struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
125 const struct ingenic_tcu_clk_info *info = tcu_clk->info;
126 unsigned int val = 0;
127 int ret;
128
129 ret = regmap_read(tcu_clk->tcu->map, info->tcsr_reg, &val);
130 WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx);
131
132 return ffs(val & TCU_TCSR_PARENT_CLOCK_MASK) - 1;
133 }
134
ingenic_tcu_set_parent(struct clk_hw * hw,u8 idx)135 static int ingenic_tcu_set_parent(struct clk_hw *hw, u8 idx)
136 {
137 struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
138 const struct ingenic_tcu_clk_info *info = tcu_clk->info;
139 bool was_enabled;
140 int ret;
141
142 was_enabled = ingenic_tcu_enable_regs(hw);
143
144 ret = regmap_update_bits(tcu_clk->tcu->map, info->tcsr_reg,
145 TCU_TCSR_PARENT_CLOCK_MASK, BIT(idx));
146 WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx);
147
148 if (!was_enabled)
149 ingenic_tcu_disable_regs(hw);
150
151 return 0;
152 }
153
ingenic_tcu_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)154 static unsigned long ingenic_tcu_recalc_rate(struct clk_hw *hw,
155 unsigned long parent_rate)
156 {
157 struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
158 const struct ingenic_tcu_clk_info *info = tcu_clk->info;
159 unsigned int prescale;
160 int ret;
161
162 ret = regmap_read(tcu_clk->tcu->map, info->tcsr_reg, &prescale);
163 WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx);
164
165 prescale = (prescale & TCU_TCSR_PRESCALE_MASK) >> TCU_TCSR_PRESCALE_LSB;
166
167 return parent_rate >> (prescale * 2);
168 }
169
ingenic_tcu_get_prescale(unsigned long rate,unsigned long req_rate)170 static u8 ingenic_tcu_get_prescale(unsigned long rate, unsigned long req_rate)
171 {
172 u8 prescale;
173
174 for (prescale = 0; prescale < 5; prescale++)
175 if ((rate >> (prescale * 2)) <= req_rate)
176 return prescale;
177
178 return 5; /* /1024 divider */
179 }
180
ingenic_tcu_round_rate(struct clk_hw * hw,unsigned long req_rate,unsigned long * parent_rate)181 static long ingenic_tcu_round_rate(struct clk_hw *hw, unsigned long req_rate,
182 unsigned long *parent_rate)
183 {
184 unsigned long rate = *parent_rate;
185 u8 prescale;
186
187 if (req_rate > rate)
188 return rate;
189
190 prescale = ingenic_tcu_get_prescale(rate, req_rate);
191
192 return rate >> (prescale * 2);
193 }
194
ingenic_tcu_set_rate(struct clk_hw * hw,unsigned long req_rate,unsigned long parent_rate)195 static int ingenic_tcu_set_rate(struct clk_hw *hw, unsigned long req_rate,
196 unsigned long parent_rate)
197 {
198 struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
199 const struct ingenic_tcu_clk_info *info = tcu_clk->info;
200 u8 prescale = ingenic_tcu_get_prescale(parent_rate, req_rate);
201 bool was_enabled;
202 int ret;
203
204 was_enabled = ingenic_tcu_enable_regs(hw);
205
206 ret = regmap_update_bits(tcu_clk->tcu->map, info->tcsr_reg,
207 TCU_TCSR_PRESCALE_MASK,
208 prescale << TCU_TCSR_PRESCALE_LSB);
209 WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx);
210
211 if (!was_enabled)
212 ingenic_tcu_disable_regs(hw);
213
214 return 0;
215 }
216
217 static const struct clk_ops ingenic_tcu_clk_ops = {
218 .get_parent = ingenic_tcu_get_parent,
219 .set_parent = ingenic_tcu_set_parent,
220
221 .recalc_rate = ingenic_tcu_recalc_rate,
222 .round_rate = ingenic_tcu_round_rate,
223 .set_rate = ingenic_tcu_set_rate,
224
225 .enable = ingenic_tcu_enable,
226 .disable = ingenic_tcu_disable,
227 .is_enabled = ingenic_tcu_is_enabled,
228 };
229
230 static const char * const ingenic_tcu_timer_parents[] = {
231 [TCU_PARENT_PCLK] = "pclk",
232 [TCU_PARENT_RTC] = "rtc",
233 [TCU_PARENT_EXT] = "ext",
234 };
235
236 #define DEF_TIMER(_name, _gate_bit, _tcsr) \
237 { \
238 .init_data = { \
239 .name = _name, \
240 .parent_names = ingenic_tcu_timer_parents, \
241 .num_parents = ARRAY_SIZE(ingenic_tcu_timer_parents),\
242 .ops = &ingenic_tcu_clk_ops, \
243 .flags = CLK_SET_RATE_UNGATE, \
244 }, \
245 .gate_bit = _gate_bit, \
246 .tcsr_reg = _tcsr, \
247 }
248 static const struct ingenic_tcu_clk_info ingenic_tcu_clk_info[] = {
249 [TCU_CLK_TIMER0] = DEF_TIMER("timer0", 0, TCU_REG_TCSRc(0)),
250 [TCU_CLK_TIMER1] = DEF_TIMER("timer1", 1, TCU_REG_TCSRc(1)),
251 [TCU_CLK_TIMER2] = DEF_TIMER("timer2", 2, TCU_REG_TCSRc(2)),
252 [TCU_CLK_TIMER3] = DEF_TIMER("timer3", 3, TCU_REG_TCSRc(3)),
253 [TCU_CLK_TIMER4] = DEF_TIMER("timer4", 4, TCU_REG_TCSRc(4)),
254 [TCU_CLK_TIMER5] = DEF_TIMER("timer5", 5, TCU_REG_TCSRc(5)),
255 [TCU_CLK_TIMER6] = DEF_TIMER("timer6", 6, TCU_REG_TCSRc(6)),
256 [TCU_CLK_TIMER7] = DEF_TIMER("timer7", 7, TCU_REG_TCSRc(7)),
257 };
258
259 static const struct ingenic_tcu_clk_info ingenic_tcu_watchdog_clk_info =
260 DEF_TIMER("wdt", 16, TCU_REG_WDT_TCSR);
261 static const struct ingenic_tcu_clk_info ingenic_tcu_ost_clk_info =
262 DEF_TIMER("ost", 15, TCU_REG_OST_TCSR);
263 #undef DEF_TIMER
264
ingenic_tcu_register_clock(struct ingenic_tcu * tcu,unsigned int idx,enum tcu_clk_parent parent,const struct ingenic_tcu_clk_info * info,struct clk_hw_onecell_data * clocks)265 static int __init ingenic_tcu_register_clock(struct ingenic_tcu *tcu,
266 unsigned int idx, enum tcu_clk_parent parent,
267 const struct ingenic_tcu_clk_info *info,
268 struct clk_hw_onecell_data *clocks)
269 {
270 struct ingenic_tcu_clk *tcu_clk;
271 int err;
272
273 tcu_clk = kzalloc(sizeof(*tcu_clk), GFP_KERNEL);
274 if (!tcu_clk)
275 return -ENOMEM;
276
277 tcu_clk->hw.init = &info->init_data;
278 tcu_clk->idx = idx;
279 tcu_clk->info = info;
280 tcu_clk->tcu = tcu;
281
282 /* Reset channel and clock divider, set default parent */
283 ingenic_tcu_enable_regs(&tcu_clk->hw);
284 regmap_update_bits(tcu->map, info->tcsr_reg, 0xffff, BIT(parent));
285 ingenic_tcu_disable_regs(&tcu_clk->hw);
286
287 err = clk_hw_register(NULL, &tcu_clk->hw);
288 if (err) {
289 kfree(tcu_clk);
290 return err;
291 }
292
293 clocks->hws[idx] = &tcu_clk->hw;
294
295 return 0;
296 }
297
298 static const struct ingenic_soc_info jz4740_soc_info = {
299 .num_channels = 8,
300 .has_ost = false,
301 .has_tcu_clk = true,
302 };
303
304 static const struct ingenic_soc_info jz4725b_soc_info = {
305 .num_channels = 6,
306 .has_ost = true,
307 .has_tcu_clk = true,
308 };
309
310 static const struct ingenic_soc_info jz4770_soc_info = {
311 .num_channels = 8,
312 .has_ost = true,
313 .has_tcu_clk = false,
314 };
315
316 static const struct ingenic_soc_info x1000_soc_info = {
317 .num_channels = 8,
318 .has_ost = false, /* X1000 has OST, but it not belong TCU */
319 .has_tcu_clk = true,
320 .allow_missing_tcu_clk = true,
321 };
322
323 static const struct of_device_id __maybe_unused ingenic_tcu_of_match[] __initconst = {
324 { .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, },
325 { .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, },
326 { .compatible = "ingenic,jz4760-tcu", .data = &jz4770_soc_info, },
327 { .compatible = "ingenic,jz4770-tcu", .data = &jz4770_soc_info, },
328 { .compatible = "ingenic,x1000-tcu", .data = &x1000_soc_info, },
329 { /* sentinel */ }
330 };
331
ingenic_tcu_probe(struct device_node * np)332 static int __init ingenic_tcu_probe(struct device_node *np)
333 {
334 const struct of_device_id *id = of_match_node(ingenic_tcu_of_match, np);
335 struct ingenic_tcu *tcu;
336 struct regmap *map;
337 unsigned int i;
338 int ret;
339
340 map = device_node_to_regmap(np);
341 if (IS_ERR(map))
342 return PTR_ERR(map);
343
344 tcu = kzalloc(sizeof(*tcu), GFP_KERNEL);
345 if (!tcu)
346 return -ENOMEM;
347
348 tcu->map = map;
349 tcu->soc_info = id->data;
350
351 if (tcu->soc_info->has_tcu_clk) {
352 tcu->clk = of_clk_get_by_name(np, "tcu");
353 if (IS_ERR(tcu->clk)) {
354 ret = PTR_ERR(tcu->clk);
355
356 /*
357 * Old device trees for some SoCs did not include the
358 * TCU clock because this driver (incorrectly) didn't
359 * use it. In this case we complain loudly and attempt
360 * to continue without the clock, which might work if
361 * booting with workarounds like "clk_ignore_unused".
362 */
363 if (tcu->soc_info->allow_missing_tcu_clk && ret == -EINVAL) {
364 pr_warn("TCU clock missing from device tree, please update your device tree\n");
365 tcu->clk = NULL;
366 } else {
367 pr_crit("Cannot get TCU clock from device tree\n");
368 goto err_free_tcu;
369 }
370 } else {
371 ret = clk_prepare_enable(tcu->clk);
372 if (ret) {
373 pr_crit("Unable to enable TCU clock\n");
374 goto err_put_clk;
375 }
376 }
377 }
378
379 tcu->clocks = kzalloc(struct_size(tcu->clocks, hws, TCU_CLK_COUNT),
380 GFP_KERNEL);
381 if (!tcu->clocks) {
382 ret = -ENOMEM;
383 goto err_clk_disable;
384 }
385
386 tcu->clocks->num = TCU_CLK_COUNT;
387
388 for (i = 0; i < tcu->soc_info->num_channels; i++) {
389 ret = ingenic_tcu_register_clock(tcu, i, TCU_PARENT_EXT,
390 &ingenic_tcu_clk_info[i],
391 tcu->clocks);
392 if (ret) {
393 pr_crit("cannot register clock %d\n", i);
394 goto err_unregister_timer_clocks;
395 }
396 }
397
398 /*
399 * We set EXT as the default parent clock for all the TCU clocks
400 * except for the watchdog one, where we set the RTC clock as the
401 * parent. Since the EXT and PCLK are much faster than the RTC clock,
402 * the watchdog would kick after a maximum time of 5s, and we might
403 * want a slower kicking time.
404 */
405 ret = ingenic_tcu_register_clock(tcu, TCU_CLK_WDT, TCU_PARENT_RTC,
406 &ingenic_tcu_watchdog_clk_info,
407 tcu->clocks);
408 if (ret) {
409 pr_crit("cannot register watchdog clock\n");
410 goto err_unregister_timer_clocks;
411 }
412
413 if (tcu->soc_info->has_ost) {
414 ret = ingenic_tcu_register_clock(tcu, TCU_CLK_OST,
415 TCU_PARENT_EXT,
416 &ingenic_tcu_ost_clk_info,
417 tcu->clocks);
418 if (ret) {
419 pr_crit("cannot register ost clock\n");
420 goto err_unregister_watchdog_clock;
421 }
422 }
423
424 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, tcu->clocks);
425 if (ret) {
426 pr_crit("cannot add OF clock provider\n");
427 goto err_unregister_ost_clock;
428 }
429
430 ingenic_tcu = tcu;
431
432 return 0;
433
434 err_unregister_ost_clock:
435 if (tcu->soc_info->has_ost)
436 clk_hw_unregister(tcu->clocks->hws[i + 1]);
437 err_unregister_watchdog_clock:
438 clk_hw_unregister(tcu->clocks->hws[i]);
439 err_unregister_timer_clocks:
440 for (i = 0; i < tcu->clocks->num; i++)
441 if (tcu->clocks->hws[i])
442 clk_hw_unregister(tcu->clocks->hws[i]);
443 kfree(tcu->clocks);
444 err_clk_disable:
445 if (tcu->clk)
446 clk_disable_unprepare(tcu->clk);
447 err_put_clk:
448 if (tcu->clk)
449 clk_put(tcu->clk);
450 err_free_tcu:
451 kfree(tcu);
452 return ret;
453 }
454
tcu_pm_suspend(void)455 static int __maybe_unused tcu_pm_suspend(void)
456 {
457 struct ingenic_tcu *tcu = ingenic_tcu;
458
459 if (tcu->clk)
460 clk_disable(tcu->clk);
461
462 return 0;
463 }
464
tcu_pm_resume(void)465 static void __maybe_unused tcu_pm_resume(void)
466 {
467 struct ingenic_tcu *tcu = ingenic_tcu;
468
469 if (tcu->clk)
470 clk_enable(tcu->clk);
471 }
472
473 static struct syscore_ops __maybe_unused tcu_pm_ops = {
474 .suspend = tcu_pm_suspend,
475 .resume = tcu_pm_resume,
476 };
477
ingenic_tcu_init(struct device_node * np)478 static void __init ingenic_tcu_init(struct device_node *np)
479 {
480 int ret = ingenic_tcu_probe(np);
481
482 if (ret)
483 pr_crit("Failed to initialize TCU clocks: %d\n", ret);
484
485 if (IS_ENABLED(CONFIG_PM_SLEEP))
486 register_syscore_ops(&tcu_pm_ops);
487 }
488
489 CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-tcu", ingenic_tcu_init);
490 CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-tcu", ingenic_tcu_init);
491 CLK_OF_DECLARE_DRIVER(jz4760_cgu, "ingenic,jz4760-tcu", ingenic_tcu_init);
492 CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-tcu", ingenic_tcu_init);
493 CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-tcu", ingenic_tcu_init);
494
